CN105070727A - 一种薄膜晶体管阵列基板、其制作方法及显示装置 - Google Patents

一种薄膜晶体管阵列基板、其制作方法及显示装置 Download PDF

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CN105070727A
CN105070727A CN201510518773.3A CN201510518773A CN105070727A CN 105070727 A CN105070727 A CN 105070727A CN 201510518773 A CN201510518773 A CN 201510518773A CN 105070727 A CN105070727 A CN 105070727A
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film transistor
layer
thin
plate
transistor array
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CN105070727B (zh
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冯伟
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/513,172 priority patent/US10209594B2/en
Priority to PCT/CN2016/070257 priority patent/WO2017031924A1/zh
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Abstract

本发明公开了一种薄膜晶体管阵列基板、其制作方法及显示装置，包括：衬底基板，设置在衬底基板上的栅极，以及依次设置在栅极上的栅极绝缘层和有源层；还包括：设置在衬底基板上的像素电极、公共电极和透明电极层；其中，透明电极层和像素电极/公共电极同层同材质；透明电极层位于栅极绝缘层的下方；有源层在衬底基板上的正投影位于透明电极层的正投影所在区域内。由于薄膜晶体管中的有源层正下方设置有与像素电极或公共电极同层同材质的透明电极层，可以改善薄膜晶体管所在区域的电极层残沙，使有源层的表面平整，避免由残沙引起的画面不均的现象，实现方法简单，且对栅极电阻的影响较小，可以提升产品品质。

Description

一种薄膜晶体管阵列基板、其制作方法及显示装置
技术领域
本发明涉及显示技术领域，尤指一种薄膜晶体管阵列基板、其制作方法及显示装置。
背景技术
目前，高级超维场开关(AdvancedSuperDimensionSwitch，简称：ADS)薄膜晶体管液晶显示器是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间形成多维电场，使液晶盒内狭缝电极间、电极正上方的所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光率。因此ADS技术可以提高产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角等优点。
ADS技术是将两层氧化铟锡(IndiumTinOxide，简称：ITO)材料都制作在薄膜晶体管阵列基板上，分别作为公共电极和像素电极。现有ADS技术一般将公共电极制作在衬底基板的最底层，采用块状设计，而像素电极制作在最上层，采用狭缝设计，具有一定的ITO宽度间隔比。
ADS产品在生产过程中易发生污渍状画面不均，严重影响产品的良率。经分析，不良的发生机理为：与板状电极层(如公共电极)残沙相关，如图1a和图1b所示，残沙严重区域容易引起薄膜晶体管中的有源层01弯曲不平整，造成薄膜晶体管特性Ioff偏大，漏电严重，引起画面不均。
因此，如何解决板状电极层残沙引起的画面不均的问题，是本领域技术人员亟待解决的技术问题。
发明内容
有鉴于此，本发明实施例提供一种薄膜晶体管阵列基板、其制作方法及显示装置，可以改善薄膜晶体管所在区域的电极层残沙，避免由残沙引起的画面不均的现象。
因此，本发明实施例提供了一种薄膜晶体管阵列基板，包括：衬底基板，设置在所述衬底基板上的栅极，以及依次设置在所述栅极上的栅极绝缘层和有源层；
还包括：设置在所述衬底基板上的像素电极、公共电极和透明电极层；其中，
所述透明电极层和像素电极同层同材质；或，所述透明电极层和公共电极电极同层同材质；
所述透明电极层位于所述栅极绝缘层的正下方；
所述有源层在所述衬底基板上的正投影位于所述透明电极层的正投影所在区域内。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述透明电极层设置在所述衬底基板和所述栅极之间；或，
所述透明电极层设置在所述栅极和所述栅极绝缘层之间。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述衬底基板和所述栅极之间设置有缓冲层；
所述透明电极层设置在所述衬底基板和所述缓冲层之间。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管阵列基板中，还包括：设置在所述透明电极层上的多条栅线，每条所述栅线的一部分作为所述栅极。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述栅线在所述衬底基板上的正投影与所述透明电极层的正投影相互重叠。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述薄膜晶体管阵列基板中的像素电极位于公共电极的上方，其中，所述公共电极为板状电极。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述薄膜晶体管阵列基板中的像素电极位于公共电极的下方，其中，所述像素电极为板状电极。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述透明电极层的材料为氧化铟锡、氧化铟锌或氧化铟镓锌其中之一或组合。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述透明电极层为具有矩形形状的板状电极。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述透明电极层的厚度为300至1000
本发明实施例还提供了一种本发明实施例提供的上述薄膜晶体管阵列基板的制作方法，包括：
通过同一构图工艺在衬底基板上形成像素电极和透明电极层的图形；或，通过同一构图工艺在衬底基板上形成公共电极和透明电极层的图形；
在衬底基板上形成栅极的图形；
在形成有所述栅极图形的衬底基板上依次形成栅极绝缘层和有源层的图形；所述透明电极层图形位于所述栅极绝缘层图形的下方；所述有源层图形在所述衬底基板上的正投影位于所述透明电极层图形的正投影所在区域内。
本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述薄膜晶体管阵列基板。
本发明实施例的有益效果包括：
本发明实施例提供的一种薄膜晶体管阵列基板、其制作方法及显示装置，包括：衬底基板，设置在衬底基板上的栅极，以及依次设置在栅极上的栅极绝缘层和有源层；还包括：设置在衬底基板上的像素电极、公共电极和透明电极层；其中，透明电极层和像素电极/公共电极同层同材质；透明电极层位于栅极绝缘层的下方；有源层在衬底基板上的正投影位于透明电极层的正投影所在区域内。由于薄膜晶体管中的有源层正下方设置有与像素电极或公共电极同层同材质的透明电极层，可以改善薄膜晶体管所在区域的电极层残沙，使有源层的表面平整，避免由残沙引起的画面不均的现象，实现方法简单，且对栅极电阻的影响较小，可以提升产品品质。
附图说明
图1a为现有技术中薄膜晶体管阵列基板的俯视图；
图1b为图1a沿A-A’方向的剖面结构示意图；
图2a为本发明实施例提供的薄膜晶体管阵列基板的俯视图之一；
图2b和图2c分别为图2a沿B-B’方向的剖面结构示意图；
图3a为本发明实施例提供的薄膜晶体管阵列基板的俯视图之二；
图3b为图3a沿C-C’方向的剖面结构示意图；
图4为本发明实施例提供的薄膜晶体管阵列基板的制作方法流程图；
图5a至图5f分别为本发明实施例提供的薄膜晶体管阵列基板的制作方法在各步骤执行后的结构示意图。
附图标记说明：
1、衬底基板；2、栅线；3、透明电极层；4、有源层；5、源极；6、漏极；7、公共电极；8、公共电极线；9、数据扫描线；10、过孔；11、连接孔；12、像素电极；13、导电连接层。
具体实施方式
下面结合附图，对本发明实施例提供的薄膜晶体管阵列基板、其制作方法及显示装置的具体实施方式进行详细地说明。
其中，附图中各膜层的厚度和形状不反映薄膜晶体管阵列基板的真实比例，目的只是示意说明本发明内容。
本发明实施例提供了一种薄膜晶体管阵列基板，如图2a至图2c所示，包括：衬底基板1，设置在衬底基板1上的栅极，以及依次设置在栅极上的栅极绝缘层和有源层4；
还包括：设置在衬底基板1上的像素电极、公共电极和透明电极层3；其中，
透明电极层3和像素电极同层同材质；或，透明电极层3和公共电极电极同层同材质；
透明电极层3位于栅极绝缘层的下方；
该有源层4在衬底基板1上的正投影位于透明电极层3的正投影所在区域内。
在本发明实施例提供的上述薄膜晶体管阵列基板中，由于薄膜晶体管中的有源层正下方设置有与像素电极或公共电极同层同材质的透明电极层，可以改善薄膜晶体管所在区域的电极层残沙，使有源层的表面平整，避免由残沙引起的画面不均的现象，实现方法简单，且对栅极电阻的影响较小，可以提升产品品质。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，如图2b所示，透明电极层3可以设置在栅极和衬底基板1之间；或，如图2c所示，透明电极层3可以设置在栅极和栅极绝缘层之间。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，为了提高衬底基板与衬底基板上金属膜层的附着性，还可以在衬底基板与栅极之间设置缓冲层，此时，透明电极层也可以具体设置在衬底基板和缓冲层之间。在具体实现过程中，本发明实施例提供的透明电极层的位置不限于本发明附图中涉及到的位置，在此不作限定。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，如图2a至图2c所示，该薄膜晶体管阵列基板还包括：设置在透明电极层3上的多条栅线2，每条栅线2的一部分作为薄膜晶体管中的栅极，这样可以简化工艺，节省成本。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，当每条栅线的一部分作为薄膜晶体管中的栅极时，为了减少一次掩膜板进行构图工艺的使用，具体地，如图3a和图3b所示，可以将栅线在衬底基板上的正投影与透明电极层的正投影相互重叠，这样在制备薄膜晶体管阵列基板时不需要增加额外的制备工序，在衬底基板上沉积电极层薄膜和金属层薄膜之后，只需通过一次构图工艺(如半透膜掩膜工艺或单狭缝掩膜工艺)就可以形成透明电极层和栅线的图形，进而可以简化工艺，降低成本。为了不影响显示效果，如图3b所示，透明电极层3可以设置在栅线2和衬底基板1之间。
可选地，在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板可以应用于高级超维场开关(AdvancedSuperDimensionSwitch，ADS)型液晶面板中，在薄膜晶体管阵列基板中的公共电极作为板状电极位于下层(更靠近衬底基板)，像素电极作为狭缝电极位于上层(更靠近液晶层)，即像素电极位于公共电极的上方，在像素电极和公共电极之间设有绝缘层；此时，公共电极与透明电极层可以同层设置，这样，在制备薄膜晶体管阵列基板时不需要增加额外的制备工序，只需要通过同一构图工艺即可形成公共电极和透明电极层的图形，能够节省制备成本，提升产品附加值，并且可以改善薄膜晶体管所在区域的公共电极层残沙，避免由残沙引起的画面不均的现象。
可选地，在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板还可以应用于超高级超维场开关(HighAdvancedSuperDimensionSwitch，HADS)型液晶面板中，在薄膜晶体管阵列基板中的像素电极作为板状电极位于下层(更靠近衬底基板)，公共电极作为狭缝电极位于上层(更靠近液晶层)，即像素电极位于公共电极的下方，在像素电极和公共电极之间设有绝缘层；此时，像素电极与透明电极层可以同层设置，这样，在制备薄膜晶体管阵列基板时不需要增加额外的制备工序，只需要通过同一构图工艺即可形成像素电极和透明电极层的图形，能够节省制备成本，提升产品附加值，并且可以改善薄膜晶体管所在区域的像素电极层残沙，避免由残沙引起的画面不均的现象。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，优选地，透明电极层的材料可以为氧化铟锡、氧化铟锌或氧化铟镓锌其中之一或组合。合理选择上述透明电极层的材料，可以进一步实现薄膜晶体管所在区域不会产生电极层残沙的作用。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，优选地，透明电极层可以设置为具有矩形形状的板状电极，使刻蚀工艺简单化。对于透明电极层的形状也可以设置为其他规则图形，只需满足有源层在衬底基板上的正投影位于透明电极层的正投影所在区域内即可。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，优选地，透明电极层的厚度可以设置为300至1000进一步保证薄膜晶体管所在区域不会产生电极层残沙。
在具体实施时，本发明实施例提供的薄膜晶体管阵列基板中一般还会具有诸如栅绝缘层、欧姆接触层和钝化层等其他膜层结构，以及在衬底基板上还一般形成有公共电极线、数据线等结构，这些具体结构可以有多种实现方式，在此不做限定。
基于同一发明构思，本发明实施例还提供了一种本发明实施例提供的上述薄膜晶体管阵列基板的制作方法，由于该方法解决问题的原理与前述一种薄膜晶体管阵列基板相似，因此该方法的实施可以参见薄膜晶体管阵列基板的实施，重复之处不再赘述。
在具体实施时，本发明实施例提供的薄膜晶体管阵列基板的制作方法，如图4所示，具体包括以下步骤：
S401、通过同一构图工艺在衬底基板上形成像素电极和透明电极层的图形；或，通过同一构图工艺在衬底基板上形成公共电极和透明电极层的图形；
S402、在衬底基板上形成栅极的图形；
S403、在形成有栅极图形的衬底基板上依次形成栅极绝缘层和有源层的图形；透明电极层图形位于栅极绝缘层图形的下方；有源层图形在衬底基板上的正投影位于透明电极层图形的正投影所在区域内。
需要说明的是，步骤S401和步骤S402可以互换，当透明电极层位于栅极下方时，首先执行步骤S401，然后执行步骤S402；当透明电极层位于栅极和栅极绝缘层之间时，首先执行步骤S402，然后执行步骤S401。
在本发明实施例提供的上述薄膜晶体管阵列基板的制作方法中，由于薄膜晶体管中的有源层正下方设置有与像素电极或公共电极同层同材质的透明电极层，且有源层图形在衬底基板上的正投影位于透明电极层图形的正投影所在区域内，可以改善薄膜晶体管所在区域的电极层残沙，避免由残沙引起的画面不均的现象，实现方法简单，且对栅极电阻的影响较小，可以提升产品品质。
下面以一个具体的实例详细的说明本发明实施例提供的薄膜晶体管阵列基板的制作方法，具体步骤如下：
步骤一、通过同一构图工艺在衬底基板上形成包括公共电极和透明电极层的图形，如图5a所示；
在具体实施时，在衬底基板上通过溅射或热蒸发等方法沉积一层厚度约为300至1000的电极层薄膜，电极层薄膜的材质具体可以包括氧化铟锡ITO、或者氧化铟锌IZO、或者其它金属及金属氧化物；通过一次曝光、湿法刻蚀工艺，形成公共电极7和透明电极层3的图形，其中，薄膜晶体管对应的区域需保留电极层薄膜用来作为透明电极层3；
步骤二、在形成有公共电极和透明电极层图形的衬底基板上形成栅线的图形，如图5b所示；
在具体实施时，在上述衬底基板上通过溅射或热蒸发等方法，沉积一层缓冲层薄膜和金属层薄膜，缓冲层薄膜的厚度约为100至1000缓冲层薄膜的材质可以包括金属Ta、Cr、Mo、W、Nb等金属或者合金，或者透明导电薄膜；金属层薄膜的厚度约为1000至5000材质可以为铝或者铜，对金属层薄膜进行涂光刻胶、曝光、显影和湿法刻蚀及剥离工艺得到栅线2和公共电极线8(连接下层公共电极)等对应的图形；其中，每条栅线2图形的一部分作为薄膜晶体管中的栅极；
步骤三、在栅极图形上方依次形成栅极绝缘层和有源层的图形，如图5c所示；
在具体实施时，在完成步骤二的衬底基板上通过PECVD等方法依次沉积栅极绝缘层、有源层4、欧姆接触层的薄膜；栅绝缘层薄膜的厚度具体可为1000至4000材质具体可以包括氮化物SiNx或者氮氧化合物SiOxNx，或者是氮化物SiNx和氮氧化合物SiOxNx的复合物等；有源层4薄膜的厚度具体可为1000至4000欧姆接触层薄膜的厚度具体可为500至1000然后通过涂光刻胶、曝光、显影和干法刻蚀及剥离工艺形成薄膜晶体管的沟道；其中，有源层4在衬底基板上的正投影面积稍小于透明电极层3的正投影面积；
步骤四、在形成有源层图形的衬底基板上形成源极和漏极的图形，如图5d所示；
在具体实施时，在完成步骤三的衬底基板上通过溅射或热蒸发的方法依次沉积上厚度约为100至1000A的金属Ta、Cr、Mo、W、Nb等金属或合金、或者透明导电薄膜作为缓冲层；然后再沉积厚度约为1000～5000的金属层(材质可以为铝或者铜)，或由多层金属形成源漏极金属层；然后通过涂光刻胶、曝光、显影和湿法刻蚀及剥离工艺得到源极5、漏极6和数据扫描线9的图形；
步骤五、在形成包括源极和漏极图形的衬底基板上形成具有过孔的钝化层的图形，如图5e所示；
在具体实施时，在完成步骤四的衬底基板上通过PECVD等方法沉积厚度约为700～5000的钝化层，钝化层的材质具体可以包括氧化物、氮化物或者氧氮化合物等；然后通过涂光刻胶、曝光、显影和干法刻蚀及剥离工艺在钝化层形成像素区域的过孔10(去除钝化层)，以及形成连接上下公共电极7(公共电极线8)的连接孔11(去除钝化层和栅极绝缘层)；
步骤六、在形成钝化层图形的衬底基板上形成像素电极的图形，如图5f所示；
在具体实施时，在完成步骤五的衬底基板上通过溅射或热蒸发等方法沉积一层厚度约为300～1000的透明导电层，透明导电层的材质具体可以包括ITO、或者IZO、或者其它金属及金属氧化物；然后通过一次曝光、刻蚀工艺，形成像素电极12以及连接上下公共电极7(公共电极线8)的导电连接层13。
需要说明的是，上述制作工艺采用了六次曝光工艺形成的，此外还可以采用五次曝光工艺制作。即：执行步骤三时，通过形成PECVD等方法依次沉积栅绝缘层、有源层、欧姆接触层的薄膜之后，不进行曝光和刻蚀工艺，而是通过溅射或热蒸发的方法依次沉积缓冲层和金属层；后续，可采用半色调或灰色调掩模板曝光显影工艺，经过多步刻蚀之后形成栅绝缘层、半导体层、欧姆接触层以及源漏极金属层对应的图形，例如薄膜晶体管的沟道、源极、漏极和数据线。
至此，经过具体的实例提供的上述步骤一至六制作出了本发明实施例提供的上述薄膜晶体管阵列基板。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述薄膜晶体管阵列基板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。该显示装置的实施可以参见上述薄膜晶体管阵列基板的实施例，重复之处不再赘述。
本发明实施例提供的一种薄膜晶体管阵列基板、其制作方法及显示装置，包括：衬底基板，设置在衬底基板上的栅极，以及依次设置在栅极上的栅极绝缘层和有源层；还包括：设置在衬底基板上的像素电极、公共电极和透明电极层；其中，透明电极层和像素电极/公共电极同层同材质；透明电极层位于栅极绝缘层的下方；有源层在衬底基板上的正投影位于透明电极层的正投影所在区域内。由于薄膜晶体管中的有源层正下方设置有与像素电极或公共电极同层同材质的透明电极层，可以改善薄膜晶体管所在区域的电极层残沙，使有源层的表面平整，避免由残沙引起的画面不均的现象，实现方法简单，且对栅极电阻的影响较小，可以提升产品品质。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (12)

1.一种薄膜晶体管阵列基板，包括：衬底基板，设置在所述衬底基板上的栅极，以及依次设置在所述栅极上的栅极绝缘层和有源层；其特征在于，
还包括：设置在所述衬底基板上的像素电极、公共电极和透明电极层；其中，
所述透明电极层和像素电极同层同材质；或，所述透明电极层和公共电极电极同层同材质；
所述透明电极层位于所述栅极绝缘层的下方；
所述有源层在所述衬底基板上的正投影位于所述透明电极层的正投影所在区域内。
2.如权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述透明电极层设置在所述衬底基板和所述栅极之间；或，
所述透明电极层设置在所述栅极和所述栅极绝缘层之间。
3.如权利要求2所述的薄膜晶体管阵列基板，其特征在于，所述衬底基板和所述栅极之间设置有缓冲层；
所述透明电极层设置在所述衬底基板和所述缓冲层之间。
4.如权利要求1所述的薄膜晶体管阵列基板，其特征在于，还包括：设置在所述透明电极层上的多条栅线，每条所述栅线的一部分作为所述栅极。
5.如权利要求4所述的薄膜晶体管阵列基板，其特征在于，所述栅线在所述衬底基板上的正投影与所述透明电极层的正投影相互重叠。
6.如权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板中的像素电极位于公共电极的上方，其中，所述公共电极为板状电极。
7.如权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板中的像素电极位于公共电极的下方，其中，所述像素电极为板状电极。
8.如权利要求1-7任一项所述的薄膜晶体管阵列基板，其特征在于，所述透明电极层的材料为氧化铟锡、氧化铟锌或氧化铟镓锌其中之一或组合。
9.如权利要求1-7任一项所述的薄膜晶体管阵列基板，其特征在于，所述透明电极层为具有矩形形状的板状电极。
10.如权利要求1-7任一项所述的薄膜晶体管阵列基板，其特征在于，所述透明电极层的厚度为至
11.一种显示装置，其特征在于，包括如权利要求1-10任一项所述的薄膜晶体管阵列基板。
12.一种如权利要求1-10任一项所述薄膜晶体管阵列基板的制作方法，其特征在于，包括：
通过同一构图工艺在衬底基板上形成像素电极和透明电极层的图形；或，通过同一构图工艺在衬底基板上形成公共电极和透明电极层的图形；
在衬底基板上形成栅极的图形；
在形成有所述栅极图形的衬底基板上依次形成栅极绝缘层和有源层的图形；所述透明电极层图形位于所述栅极绝缘层图形的下方；所述有源层图形在所述衬底基板上的正投影位于所述透明电极层图形的正投影所在区域内。
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