WO2017008315A1 - 一种显示面板及其制造方法 - Google Patents

一种显示面板及其制造方法 Download PDF

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WO2017008315A1
WO2017008315A1 PCT/CN2015/084331 CN2015084331W WO2017008315A1 WO 2017008315 A1 WO2017008315 A1 WO 2017008315A1 CN 2015084331 W CN2015084331 W CN 2015084331W WO 2017008315 A1 WO2017008315 A1 WO 2017008315A1
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amorphous silicon
substrate
layer
film
silicon film
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French (fr)
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张旭东
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0227—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using structural arrangements to control crystal growth, e.g. placement of grain filters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/425—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer having different crystal properties in different TFTs or within an individual TFT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2922—Materials being non-crystalline insulating materials, e.g. glass or polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3238—Materials thereof being insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3248—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3454—Amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3808—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display panel and a method of fabricating the same.
  • Amorphous silicon thin film transistors are widely used because they can be formed at a low temperature of 200 ° C to 300 ° C, but the carrier mobility of amorphous silicon is low, making amorphous silicon thin film transistors unable to meet the needs of current high speed component applications.
  • the use of polysilicon thin film transistors is relatively high, and their relatively high carrier mobility and low temperature sensitivity make them more suitable for high speed components.
  • polycrystalline silicon is obtained by crystallizing amorphous silicon by a laser annealing process to obtain polycrystalline silicon.
  • a laser annealing process to obtain polycrystalline silicon.
  • more holes are formed after crystallization, resulting in more grain boundaries between grains and grains.
  • the mobility of the carriers is not high, and the performance of the corresponding display panel is poor.
  • the invention mainly solves the problem that the crystal grains of the polysilicon film of the prior art display panel are small, and the carrier mobility is small due to a large number of grain boundaries.
  • the present invention provides a method of manufacturing a display panel, the method comprising the steps of: forming an amorphous silicon film on a substrate by a vapor deposition method, the amorphous silicon film including crystal grains formed on the substrate a first amorphous silicon layer having a lower density, and a second amorphous silicon layer having a larger crystal grain density formed on the first amorphous silicon layer; converting the amorphous silicon film into a polysilicon film.
  • the step of converting the amorphous silicon film into a polysilicon film comprises: converting the amorphous silicon film into a polysilicon film by using a laser annealing process.
  • the present invention further provides a method of manufacturing a display panel, the method comprising the steps of: forming an amorphous silicon film on a substrate, the amorphous silicon film comprising at least two amorphous silicon layers, adjacent to each other The two amorphous silicon layers have different grain densities; the amorphous silicon film is converted into a polysilicon film.
  • the step of forming an amorphous silicon film on the substrate comprises: forming a first amorphous silicon layer having a small crystal grain density on the substrate; and forming a second non-density of the grain density on the first amorphous silicon layer Crystalline silicon layer.
  • the step of forming an amorphous silicon film on the substrate comprises: forming a first amorphous silicon layer having a larger crystal grain density on the substrate; and forming a second non-crystalline density on the first amorphous silicon layer Crystalline silicon layer.
  • the step of forming an amorphous silicon film on the substrate comprises: forming an amorphous silicon film on the substrate by a vapor deposition method.
  • the step of forming an amorphous silicon film on the substrate by using a vapor deposition method includes: forming a first amorphous silicon layer on the substrate; changing a parameter to form a second amorphous silicon layer on the first amorphous silicon layer, so that The grain density of the two amorphous silicon layers is different from the grain density of the first amorphous silicon layer.
  • parameters include air pressure, voltage and/or gas flow.
  • the step of converting the amorphous silicon film into a polysilicon film comprises: converting the amorphous silicon film into a polysilicon film by using a laser annealing process.
  • the step of forming an amorphous silicon film on the substrate includes: forming a buffer layer on the substrate; and forming an amorphous silicon film on the substrate comprises: forming an amorphous silicon film on the buffer layer.
  • the step of forming a buffer layer on the substrate includes: forming a silicon nitride layer on the substrate; and forming a silicon oxide layer on the silicon nitride layer.
  • the present invention further provides a display panel comprising a substrate and a polysilicon film disposed on the substrate, the polysilicon film being transformed from an amorphous silicon film including at least two amorphous silicon layers, The adjacent two amorphous silicon layers in the crystalline silicon film have different grain densities.
  • the amorphous silicon film includes a first amorphous silicon layer having a small crystal grain density formed on the substrate, and a second amorphous silicon layer having a large crystal density on the first amorphous silicon layer.
  • the amorphous silicon film includes a first amorphous silicon layer having a large crystal grain density formed on the substrate, and a second amorphous silicon layer having a small crystal density on the first amorphous silicon layer.
  • an amorphous silicon film is formed on the substrate by a vapor phase deposition method.
  • the amorphous silicon film comprises a first amorphous silicon layer formed on the substrate by a vapor phase deposition method, and a second amorphous layer formed on the first amorphous silicon layer by vapor deposition after changing parameters of the vapor deposition method
  • the grain density of the first amorphous silicon layer is different from the grain density of the second amorphous silicon layer.
  • parameters include air pressure, voltage and/or gas flow.
  • the polysilicon film is transformed from an amorphous silicon film by a laser annealing process.
  • the display panel further includes a buffer layer disposed between the substrate and the amorphous silicon film.
  • the buffer layer comprises a silicon nitride layer formed on the substrate, and a silicon oxide layer formed on the silicon nitride layer.
  • the invention has the beneficial effects that: prior to the prior art, the present invention firstly forms an amorphous silicon film on the substrate, the amorphous silicon film comprising at least two amorphous silicon layers, and two adjacent amorphous silicon layers.
  • the grain density is different; the amorphous silicon film is then converted into a polysilicon layer.
  • the combination of the two can reduce the grain boundaries and form larger grains. Thereby, the carrier mobility of the polysilicon film is increased, and the performance of the display panel is correspondingly improved.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method of manufacturing a display panel of the present invention
  • FIG. 2 is a schematic structural view of a substrate and a first amorphous silicon film in the first embodiment of the manufacturing method shown in FIG. 1;
  • FIG. 3 is a schematic structural view of a substrate and a second amorphous silicon film in the first embodiment of the manufacturing method shown in FIG. 1;
  • FIG. 4 is a schematic view showing the conversion of the first amorphous silicon film of FIG. 2 into a polysilicon film
  • FIG. 5 is a schematic flow chart of a second embodiment of a method for manufacturing a display panel of the present invention.
  • FIG. 6 is a schematic structural view showing formation of respective film layers on a substrate in the second embodiment of the manufacturing method shown in FIG. 5;
  • FIG. 7 is a schematic structural view of a first embodiment of a display panel of the present invention.
  • Figure 8 is a schematic view showing the structure of a second embodiment of the display panel of the present invention.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for manufacturing a display panel according to the present invention.
  • the manufacturing method in the present embodiment mainly includes the following steps:
  • S101 Forming an amorphous silicon film on the substrate.
  • the substrate may be selected from a quartz substrate or a glass substrate.
  • the quartz substrate can withstand a relatively high temperature relative to the glass substrate.
  • a temperature of 600 ° C or higher is required, and at this temperature, the glass substrate is required. It is easy to soften and deform, so a quartz substrate is generally used.
  • the price of the quartz substrate is much higher than that of the glass substrate.
  • the glass substrate must be used based on cost considerations, and at this time, a low temperature process is required.
  • a glass substrate is used.
  • the amorphous silicon film formed on the glass substrate includes at least two amorphous silicon layers in which adjacent two amorphous silicon layers have different grain densities.
  • FIG. 2 is a schematic structural view of a substrate and a first amorphous silicon film in the first embodiment of the manufacturing method of FIG. 1.
  • FIG. 3 is a first embodiment of the manufacturing method shown in FIG. Schematic diagram of the substrate and the second amorphous silicon film.
  • an amorphous silicon film 12 is formed on the glass substrate 11, and the amorphous silicon film 12 includes a first amorphous silicon layer 121 and a second amorphous silicon layer 122, and in FIG. 2, a-Si is amorphous silicon. Also in other figures, a-Si also represents amorphous silicon.
  • a first amorphous silicon layer 121 having a small crystal grain density is formed on the substrate 11 by a chemical vapor deposition method; and then parameters of the chemical vapor deposition method, such as gas pressure, voltage, and/or gas flow rate, are continuously continued.
  • a second amorphous silicon layer 122 having a large crystal grain density is formed on the first amorphous silicon layer 121.
  • the amorphous silicon film 12 is formed at one time in the chemical vapor deposition equipment. Specifically, the substrate 11 is placed in a chemical vapor deposition apparatus, and a first amorphous silicon layer 121 is deposited on the surface of the substrate 11; after the first amorphous silicon layer 121 is solidified in the vacuum chamber of the chemical vapor deposition apparatus The chemical vapor deposition apparatus parameters are adjusted, and then a second amorphous silicon layer 122 is deposited on the first amorphous silicon layer 121.
  • the second method specifically includes: placing the substrate 11 in a chemical vapor deposition apparatus, depositing a first amorphous silicon layer 121 on the surface of the substrate 11, and removing the substrate 11 on which the first amorphous silicon layer 121 is deposited from the device. And drying the first amorphous silicon layer 121 in an atmospheric environment, then adjusting the parameters of the chemical vapor deposition apparatus, placing the substrate 11 in the device, and forming a second surface on the surface of the first amorphous silicon layer 121. Amorphous silicon layer 122.
  • the first one takes longer than the second one; in the first mode, the amorphous silicon layer is solidified in the vacuum chamber, and the second mode is the amorphous silicon layer in the atmospheric environment. Under the drying, in comparison, drying in the atmosphere is prone to oxidation and the like, so the polysilicon film formed by the conversion of the amorphous silicon film in the first mode is better than the second one.
  • a second amorphous silicon layer 122 having a small crystal density is formed on the first amorphous silicon layer 121.
  • an amorphous silicon film 22 is formed on the glass substrate 21, and the amorphous silicon film 22 includes a first amorphous silicon layer 221, a second amorphous silicon layer 222, and a third amorphous silicon layer 223.
  • the amorphous silicon layer in FIG. 3 is formed in the same manner as in FIG. 2, and in FIG. 3, the first amorphous silicon layer 221 has a smaller crystal grain density, and the second amorphous silicon layer 222 has a larger crystal grain density.
  • the grain density of the three amorphous silicon layer 223 is small; the crystal grain density combination of the three amorphous silicon layers may be larger-smaller-larger; when the amorphous silicon film includes 4, 5 or
  • a combination of different grain densities may be performed, for example, larger-smaller-larger-small, and the grain density of the adjacent two amorphous silicon layers may be different.
  • the amorphous silicon film is converted into the polysilicon film by a laser annealing process, and the laser annealing process can convert the amorphous silicon film into the polysilicon film at about 400 ° C.
  • the temperature is the temperature that the glass substrate can withstand. In other embodiments, other low temperature processes can be used to form a polysilicon film at a lower temperature.
  • FIG. 4 is a schematic diagram of the first amorphous silicon film of FIG. 2 converted into a polysilicon film, and in FIG. 4, Poly-Si is polysilicon, and in other drawings, Poly-Si is also polysilicon.
  • the amorphous silicon film 12 is converted into the polysilicon film 13 by a laser annealing process.
  • the first amorphous silicon layer 121 has a small crystal grain density, and the structure thereof is relatively loose, and the volume is reduced in the process of converting into polycrystalline silicon; and the second amorphous silicon layer 122 has a relatively large grain density, and the structure thereof is relatively dense.
  • the volume is enlarged; the combination of the two can reduce the formation of holes, reduce the number of grain boundaries, and can form larger crystal grains, corresponding carrier mobility increases, and the display panel is improved. Performance.
  • FIG. 5 is a schematic flow chart of a second embodiment of a method for manufacturing a display panel according to the present invention
  • FIG. 6 is a structure for forming respective film layers on a substrate in the second embodiment of the manufacturing method shown in FIG. schematic diagram.
  • the manufacturing method in this embodiment mainly includes the following steps:
  • the silicon nitride layer 32 formed on the substrate 31 and the silicon oxide layer 33 formed on the silicon nitride layer 32 in step S201 and step S202 serve as a buffer layer between the substrate 31 and the amorphous silicon film 34, also by chemistry A deposition method is formed for blocking impurities in the glass substrate 31 from entering the amorphous silicon film 34. Further to Fig. 6, it is necessary to further explain that SiOx represents silicon oxide and SiNx represents silicon nitride.
  • the buffer layer includes a silicon nitride layer 32 and a silicon oxide layer 33, and is oxidized.
  • a silicon layer 33 is disposed on the silicon nitride layer 32 such that the amorphous silicon film 34 can be formed on the silicon oxide layer 33, wherein the silicon oxide layer 33 can also be used in a subsequent doping process.
  • Step S203 and step S204 are similar to step S101 and step S102 in the first embodiment of the manufacturing method, and details are not described herein again.
  • the amorphous silicon film formed in the present invention comprises at least two amorphous silicon layers, and the adjacent two amorphous silicon layers have different crystal grain densities, and the polycrystalline silicon film obtained by converting the amorphous silicon film is crystallized.
  • the particles are larger and the grain boundaries are smaller, so the carrier mobility is larger, and the performance of the corresponding display panel is better.
  • FIG. 7 is a schematic structural view of a first embodiment of a display panel according to the present invention.
  • the display panel 400 includes a substrate 41 and a polysilicon film 42 formed on the substrate 41.
  • the polysilicon film 42 is formed by converting an amorphous silicon film including at least two amorphous silicon layers, and the adjacent two amorphous silicon layers have different crystal densities.
  • the polysilicon film 42 formed in the present embodiment has fewer grain boundaries, larger crystal grains, and larger carrier mobility, and the corresponding display panel 400 has better performance.
  • the display panel 400 of the present embodiment is produced by the first embodiment of the above manufacturing method.
  • FIG. 8 is a schematic structural view of a second embodiment of the display panel of the present invention.
  • the display panel 500 includes a substrate 51, a polysilicon film 52, and a buffer layer 53 between the substrate 51 and the polysilicon film 52.
  • the polysilicon film 52 is formed by converting an amorphous silicon film including at least two amorphous silicon layers, and the adjacent two amorphous silicon layers have different crystal densities.
  • the polysilicon film 52 formed in the present embodiment has fewer grain boundaries, larger crystal grains, and larger carrier mobility, and the corresponding display panel 500 has better performance.
  • the buffer layer 53 includes a silicon nitride layer 531 disposed above the substrate 51 and a silicon oxide layer 532 disposed above the silicon nitride layer 531.
  • the display panel 500 of the present embodiment is produced by the second embodiment of the above manufacturing method.
  • the carrier mobility of the polysilicon film in the display panel of the invention is large, and the performance of the display panel is good.

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  • Recrystallisation Techniques (AREA)
  • Liquid Crystal (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

一种显示面板及其制造方法，显示面板的制造方法包括步骤：在基板（11）上形成一非晶硅膜（12），该非晶硅膜（12）包括至少两非晶硅层（121，122），相邻的两非晶硅层（121，122）的晶粒密度不同；将非晶硅膜（12）转化为一多晶硅膜（13）。该制造方法中得到晶粒较大，晶界较少的多晶硅膜（13），因此该多晶硅膜（13）的载流子迁移率较大，相应显示面板的性能较好。

Description

一种显示面板及其制造方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种显示面板及其制造方法。
【背景技术】
当前，液晶显示技术发展迅速，薄膜晶体管的应用，使得液晶显示器成为了平面显示器的主流，应用于个人电脑、监视器、游戏机等产品。非晶硅薄膜晶体管由于可在200℃-300℃的低温生成，因此得到广泛使用，但非晶硅的载流子迁移率低，使得非晶硅薄膜晶体管不能满足目前高速组件应用的需求，因此当前较多的使用多晶硅薄膜晶体管，其相对较高的载流子迁移率和低温敏感性使其更适用于高速组件。
当前得到多晶硅的方式是：利用激光退火工艺使非晶硅晶化得到多晶硅。然而在非晶硅晶化的过程中，由于多晶硅与非晶硅晶粒密度的不同，在晶化后容易形成较多空穴，造成晶粒和晶粒之间的晶界比较多，因此载流子迁移率不高，相应显示面板的性能较差。
【发明内容】
本发明主要解决现有技术显示面板的多晶硅膜中晶粒较小，晶界较多造成的载流子迁移率较小的问题。
为解决上述技术问题，本发明提供一种显示面板的制造方法，所述制造方法包括步骤：利用气相沉积法在基板上形成一非晶硅膜，非晶硅膜包括形成在基板上的晶粒密度较小的第一非晶硅层，以及形成在第一非晶硅层上的晶粒密度较大的第二非晶硅层；将非晶硅膜转化为一多晶硅膜。
其中，将非晶硅膜转化为一多晶硅膜的步骤包括：利用激光退火工艺将非晶硅膜转化为多晶硅膜。
为解决上述技术问题，本发明又提供一种显示面板的制造方法，该制造方法包括步骤：在基板上形成一非晶硅膜，该非晶硅膜包括至少两非晶硅层，相邻的两非晶硅层的晶粒密度不同；将非晶硅膜转化为一多晶硅膜。
其中，在基板上形成一非晶硅膜的步骤包括：在基板上形成晶粒密度较小的第一非晶硅层；在第一非晶硅层上形成晶粒密度较大的第二非晶硅层。
其中，在基板上形成一非晶硅膜的步骤包括：在基板上形成晶粒密度较大的第一非晶硅层；在第一非晶硅层上形成晶粒密度较小的第二非晶硅层。
其中，在基板上形成一非晶硅膜的步骤包括：利用气相沉积法在基板上形成非晶硅膜。
其中，利用气相沉积法在基板上形成非晶硅膜的步骤包括：在基板上形成第一非晶硅层；改变参数，在第一非晶硅层上形成第二非晶硅层，使得第二非晶硅层的晶粒密度不同于第一非晶硅层的晶粒密度。
其中，参数包括气压、电压和/或气体流量。
其中，将非晶硅膜转化为一多晶硅膜的步骤包括：利用激光退火工艺将非晶硅膜转化为多晶硅膜。
其中，在基板上形成一非晶硅膜的步骤之前包括：在基板上形成缓冲层；在基板上形成一非晶硅膜的步骤包括：在缓冲层上形成一非晶硅膜。
其中，在基板上形成缓冲层的步骤包括：在基板上形成一氮化硅层；在氮化硅层上形成一氧化硅层。
为解决上述技术问题，本发明还提供一种显示面板，该显示面板包括基板以及设置于基板上的一多晶硅膜，多晶硅膜由包括至少两非晶硅层的非晶硅膜转化而成，非晶硅膜中相邻两非晶硅层的晶粒密度不同。
其中，非晶硅膜包括形成在基板上晶粒密度较小的第一非晶硅层，以及形成在第一非晶硅层上晶粒密度较大的第二非晶硅层。
其中，非晶硅膜包括形成在基板上晶粒密度较大的第一非晶硅层，以及形成在第一非晶硅层上晶粒密度较小的第二非晶硅层。
其中，非晶硅膜由气相沉积法形成在所述基板上。
其中，非晶硅膜包括由气相沉积法形成在基板上的第一非晶硅层，以及改变气相沉积法的参数后，由气相沉积法形成在第一非晶硅层上的第二非晶硅层，第一非晶硅层的晶粒密度与第二非晶硅层的晶粒密度不同。
其中，参数包括气压、电压和/或气体流量。
其中，多晶硅膜由非晶硅膜通过激光退火工艺转化而成。
其中，显示面板进一步包括缓冲层，缓冲层设置在基板与非晶硅膜之间。
其中，缓冲层包括形成在基板上的氮化硅层，以及形成在氮化硅层上的氧化硅层。
本发明的有益效果是：区别于现有技术，本发明首先在基板上形成一非晶硅膜，该非晶硅膜包括至少两非晶硅层，相邻的两所述非晶硅层的晶粒密度不同；然后将该非晶硅膜转化为一多晶硅层。晶粒密度不同的两非晶硅层在转化为多晶硅膜时，密度较大的在晶化过程中体积缩小、密度较小的体积扩大，两者结合能够减少晶界，形成较大的晶粒，从而提高多晶硅膜的载流子迁移率，相应的提高显示面板的性能。
【附图说明】
图1是本发明显示面板的制造方法第一实施方式的流程示意图；
图2是图1所示制造方法第一实施方式中基板及第一种非晶硅膜的结构示意图；
图3是图1所示制造方法第一实施方式中基板及第二种非晶硅膜的结构示意图；
图4是图2中第一种非晶硅膜转化为多晶硅膜的示意图；
图5是本发明显示面板的制造方法第二实施方式的流程示意图；
图6是图5所示制造方法第二实施方式中基板上形成各个膜层的结构示意图；
图7是本发明显示面板第一实施方式的结构示意图；
图8是本发明显示面板第二实施方式的结构示意图。
【具体实施方式】
参阅图1，图1是本发明显示面板的制造方法第一实施方式的流程示意图，本实施方式中的制造方法主要包括以下步骤：
S101：在基板上形成一非晶硅膜。
基板可选择石英基板或玻璃基板，石英基板相对于玻璃基板可承受的温度更大，在传统工艺中，将非晶硅转变为多晶硅时，需要600℃以上的温度，在这个温度下，玻璃基板容易软化变形，因此一般使用石英基板。然而石英基板相对玻璃基板的价格高很多，当显示面板的尺寸越来越大，即需要的基板也越来越大时，基于成本的考虑，必须使用玻璃基板，此时则需要的采用低温工艺来将非晶硅转化为多晶硅。本实施方式中采用玻璃基板。
在玻璃基板上形成的非晶硅膜包括至少两非晶硅层，其中相邻的两非晶硅层的晶粒密度不同。具体请参阅图2和图3，图2是图1所述制造方法第一实施方式中基板及第一种非晶硅膜的结构示意图；图3是图1所示制造方法第一实施方式中基板及第二种非晶硅膜的结构示意图。
图2中，玻璃基板11上形成非晶硅膜12，该非晶硅膜12包括第一非晶硅层121和第二非晶硅层122，且图2中a-Si为非晶硅，同样在其他附图中a-Si也表示非晶硅。
具体的，通过化学气相沉积法，在基板11上形成晶粒密度较小的第一非晶硅层121；然后改变化学气相沉积法的参数，比如：气压、电压和/或气体流量，继续在第一非晶硅层121上形成晶粒密度较大的第二非晶硅层122。
在实际的生产过程中，有专门的化学气相沉积设备来实现这一过程，相应的有两种方式：第一种，在化学气相沉积设备中一次形成非晶硅膜12。具体地，将基板11放入化学气相沉积设备中，在基板11的表面上沉积形成第一非晶硅层121；待第一非晶硅层121在化学气相沉积设备的真空腔体中凝固后，调节化学气相沉积设备参数，然后在第一非晶硅层121上沉积形成第二非晶硅层122。第二种方法具体包括，将基板11放入化学气相沉积设备中，在基板11的表面沉积形成第一非晶硅层121，将沉积了第一非晶硅层121的基板11自设备中取出，并在大气环境中对第一非晶硅层121进行干燥处理，然后调节化学气相沉积设备的参数，再将基板11放入设备中，并在第一非晶硅层121的表面形成第二非晶硅层122。以上两种方式相比较，第一种比第二种花费的时间更长；而第一种方式中非晶硅层是在真空腔体中凝固，第二种方式中非晶硅层在大气环境下干燥，相比来说，大气环境下干燥容易出现氧化等问题，因此第一种方式中非晶硅膜转化形成的多晶硅膜相较于第二种性能更好。
同理可知，也可在基板11上形成晶粒密度较大的第一非晶硅层121后，然后在第一非晶硅层121上形成晶粒密度较小的第二非晶硅层122。
图3中，玻璃基板21上形成有非晶硅膜22，该非晶硅膜22包括第一非晶硅层221、第二非晶硅层222以及第三非晶硅层223。
图3中非晶硅层的形成方式与图2中的相同，而在图3中，第一非晶硅层221晶粒密度较小、第二非晶硅层222晶粒密度较大、第三非晶硅层223晶粒密度较小；同理三个非晶硅层的晶粒密度组合也可为较大-较小-较大；当非晶硅膜中包括4个、5个或多个非晶硅层时，可进行不同晶粒密度的组合，例如：较大-较小-较大-较小，保证相邻的两非晶硅层晶粒密度不同即可。层数越多，后续形成的多晶硅膜性能越好，然而层数越多，相应的化学气相沉积所需要的时间也越长。因此，可对时间成本及产品质量进行综合考量，设置合适层数的非晶硅层。
S102：将非晶硅膜转化为多晶硅膜。
本实施方式中在玻璃基板上形成非晶硅膜后，利用激光退火工艺将非晶硅膜转化多晶硅膜，激光退火工艺能够在大概400℃的条件下使非晶硅膜转化为多晶硅膜，该温度是玻璃基板所能承受的温度。在其他实施方式中，也可使用其他的低温工艺，在更低的温度下形成多晶硅膜。
具体请参阅图4，图4是图2中第一种非晶硅膜转化为多晶硅膜的示意图，且图4中Poly-Si为多晶硅，同样其他附图中Poly-Si也为多晶硅，本实施方式中非晶硅膜12经激光退火工艺转化为多晶硅膜13。
其中，第一非晶硅层121的晶粒密度较小，其结构较为疏松，在转化为多晶硅的过程中体积缩小；而第二非晶硅层122的晶粒密度较大，其结构较为致密，在转化为多晶硅的过程中体积扩大；两者相结合，能够减少空穴的形成，减少晶界数量，且能够形成较大的晶粒，相应的载流子迁移率增大，提高显示面板的性能。
请参阅图5和图6，图5是本发明本发明显示面板的制造方法第二实施方式的流程示意图，图6是图5所示制造方法第二实施方式中基板上形成各个膜层的结构示意图。本实施方式中的制造方法主要包括以下步骤：
S201：在基板上形成一氮化硅层。
S202：在氮化硅层上形成一氧化硅层。
在步骤S201和步骤S202中基板31上形成的氮化硅层32、以及氮化硅层32上形成的氧化硅层33，作为基板31与非晶硅膜34之间的缓冲层，也是由化学沉积法制成，用于阻挡玻璃基板31中的杂质进入非晶硅膜34。对图6需要进一步说明的是，其中SiOx表示氧化硅，SiNx表示氮化硅。
在其他实施方式中也可只用一氧化硅层，然而由于氮化硅层的隔离效果更好，因此在本实施方式中缓冲层包括一氮化硅层32和一氧化硅层33，并且氧化硅层33设置在氮化硅层32上，以使得非晶硅膜34能够形成在氧化硅层33上，其中氧化硅层33还可用于后续的掺杂工艺中。
S203：在氧化硅层上形成非晶硅膜。
S204：将非晶硅膜转化为多晶硅膜。
步骤S203和步骤S204类似于制造方法第一实施方式中的步骤S101和步骤S102，具体不再赘述。
区别于现有技术，本发明中形成的非晶硅膜包括至少两非晶硅层，且相邻的两非晶硅层的晶粒密度不同，将非晶硅膜转化得到的多晶硅膜中晶粒较大，晶界较小，因此载流子迁移率较大，相应的显示面板的性能较好。
本发明进一步保护一种显示面板。请参阅图7，图7是本发明显示面板第一实施方式的结构示意图，其中显示面板400包括基板41和形成于基板41上的多晶硅膜42。
其中多晶硅膜42由非晶硅膜转化而成，该非晶硅膜包括至少两非晶硅层，且相邻两非晶硅层的晶粒密度不同。本实施方式中所形成的多晶硅膜42中晶界较少、晶粒较大，载流子迁移率也较大，相应的显示面板400性能较好。
本实施方式显示面板400由上述制造方法第一实施方式制得。
请参阅图8，图8是本发明显示面板第二实施方式的结构示意图，其中显示面板500包括基板51、多晶硅膜52、以及基板51与多晶硅膜52之间的缓冲层53。
其中，多晶硅膜52由非晶硅膜转化而成，该非晶硅膜包括至少两非晶硅层，且相邻两非晶硅层的晶粒密度不同。本实施方式中所形成的多晶硅膜52中晶界较少、晶粒较大，载流子迁移率也较大，相应的显示面板500性能较好。缓冲层53则包括氮化硅层531和氧化硅层532，其中氮化硅层531设置在基板51上方，氧化硅层532设置在氮化硅层531上方。
本实施方式显示面板500由上述制造方法第二实施方式制得。
区别于现有技术，本发明显示面板中多晶硅膜的载流子迁移率较大，且显示面板的性能较好。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种显示面板的制造方法，其中，所述制造方法包括步骤：
    利用气相沉积法在基板上形成一非晶硅膜，所述非晶硅膜包括形成在所述基板上的晶粒密度较小的第一非晶硅层，以及形成在所述第一非晶硅层上的晶粒密度较大的第二非晶硅层；
    将所述非晶硅膜转化为一多晶硅膜。
  2. 根据权利要求1所述的制造方法，其中，所述将所述非晶硅膜转化为一多晶硅膜的步骤包括：
    利用激光退火工艺将所述非晶硅膜转化为所述多晶硅膜。
  3. 一种显示面板的制造方法，其中，所述制造方法包括步骤：
    在基板上形成一非晶硅膜，所述非晶硅膜包括至少两非晶硅层，相邻的两所述非晶硅层的晶粒密度不同；
    将所述非晶硅膜转化为一多晶硅膜。
  4. 根据权利要求3所述的制造方法，其中，所述在基板上形成一非晶硅膜的步骤包括：
    在所述基板上形成晶粒密度较小的第一非晶硅层；
    在所述第一非晶硅层上形成晶粒密度较大的第二非晶硅层。
  5. 根据权利要求3所述的制造方法，其中，所述在基板上形成一非晶硅膜的步骤包括：
    在所述基板上形成晶粒密度较大的第一非晶硅层；
    在所述第一非晶硅层上形成晶粒密度较小的第二非晶硅层。
  6. 根据权利要求3所述的制造方法，其中，所述在基板上形成一非晶硅膜的步骤包括：
    利用气相沉积法在所述基板上形成所述非晶硅膜。
  7. 根据权利要求6所述的制造方法，其中，所述利用气相沉积法在所述基板上形成所述非晶硅膜的步骤包括：
    在所述基板上形成第一非晶硅层；
    改变参数，在所述第一非晶硅层上形成第二非晶硅层，使得所述第二非晶硅层的晶粒密度不同于所述第一非晶硅层的晶粒密度。
  8. 根据权利要求7所述的制造方法，其中，所述参数包括气压、电压和/或气体流量。
  9. 根据权利要求3所述的制造方法，其中，所述将所述非晶硅膜转化为一多晶硅膜的步骤包括：
    利用激光退火工艺将所述非晶硅膜转化为所述多晶硅膜。
  10. 根据权利要求3所述的制造方法，其中，所述在基板上形成一非晶硅膜的步骤之前包括：
    在所述基板上形成缓冲层；
    所述在基板上形成一非晶硅膜的步骤包括：
    在所述缓冲层上形成一非晶硅膜。
  11. 根据权利要求10所述的制造方法，其中，所述在所述基板上形成缓冲层的步骤包括：
    在所述基板上形成一氮化硅层；
    在所述氮化硅层上形成一氧化硅层。
  12. 一种显示面板，其中，所述显示面板包括基板以及设置于所述基板上的一多晶硅膜，所述多晶硅膜由包括至少两非晶硅层的非晶硅膜转化而成，所述非晶硅膜中相邻两所述非晶硅层的晶粒密度不同。
  13. 根据权利要求12所述的显示面板，其中，所述非晶硅膜包括形成在所述基板上晶粒密度较小的第一非晶硅层，以及形成在所述第一非晶硅层上晶粒密度较大的第二非晶硅层。
  14. 根据权利要求12所述的显示面板，其中，所述非晶硅膜包括形成在所述基板上晶粒密度较大的第一非晶硅层，以及形成在所述第一非晶硅层上晶粒密度较小的第二非晶硅层。
  15. 根据权利要求12所述的显示面板，其中，所述非晶硅膜由气相沉积法形成在所述基板上。
  16. 根据权利要求15所述的显示面板，其中，所述非晶硅膜包括由气相沉积法形成在所述基板上的第一非晶硅层，以及改变所述气相沉积法的参数后，由气相沉积法形成在所述第一非晶硅层上的第二非晶硅层，所述第一非晶硅层的晶粒密度与所述第二非晶硅层的晶粒密度不同。
  17. 根据权利要求16所述的显示面板，其中，所述参数包括气压、电压和/或气体流量。
  18. 根据权利要求12所述的显示面板，其中，所述多晶硅膜由非晶硅膜通过激光退火工艺转化而成。
  19. 根据权利要求12所述的显示面板，其中，所述显示面板进一步包括缓冲层，所述缓冲层设置在所述基板与所述非晶硅膜之间。
  20. 根据权利要求19所述的显示面板，其中，所述缓冲层包括形成在所述基板上的氮化硅层，以及形成在所述氮化硅层上的氧化硅层。
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