WO2016206449A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2016206449A1
WO2016206449A1 PCT/CN2016/079266 CN2016079266W WO2016206449A1 WO 2016206449 A1 WO2016206449 A1 WO 2016206449A1 CN 2016079266 W CN2016079266 W CN 2016079266W WO 2016206449 A1 WO2016206449 A1 WO 2016206449A1
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Prior art keywords
common electrode
pixel
display panel
line
thin film
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Ceased
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PCT/CN2016/079266
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English (en)
French (fr)
Inventor
江鹏
贾纬华
杨海鹏
金在光
尹傛俊
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/511,057 priority Critical patent/US9964823B2/en
Publication of WO2016206449A1 publication Critical patent/WO2016206449A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a display panel and a display device.
  • the number of Chip On Flex or Chip On Film is a twisted nematic (TN) type or a vertical alignment (VA) type liquid crystal display (Liquid Crystal Display, LCD) devices are commonly used to reduce costs.
  • TN twisted nematic
  • VA vertical alignment
  • LCD liquid crystal display
  • the frame of the LCD device tends to decrease. Therefore, the Dual Gate Lines have been designed to reduce the data COF.
  • AD-SDS Super Dimension Switch
  • ADS Advanced Super Dimension Switch
  • the technical problem to be solved by the present invention is to provide a display panel and a display device having the advantages of good common electrode voltage uniformity and small common electrode line resistance, in view of the above-mentioned deficiencies in the prior art.
  • a display panel including an array substrate having a plurality of pixel regions of a plurality of rows and columns, each of the plurality of pixel regions being provided with a gate, a source, and a drain Thin film transistors of the pole and active layers.
  • Two gate lines are disposed between adjacent two rows of pixel regions, and gates of thin film transistors of adjacent two pixel regions in the same row are respectively connected to one of two gate lines adjacent to the row of pixel regions .
  • Two adjacent columns of pixel regions constitute one pixel column group, one data line is disposed between two columns of pixel regions of the same pixel column group, and no data lines are disposed between the respective pixel column groups.
  • the source of the thin film transistor of the prime region is connected to the data line disposed in the pixel column group.
  • the array substrate further includes a pixel electrode, a common electrode, and a common electrode line.
  • the common electrode line includes a lateral common electrode line disposed in parallel with the gate line, wherein the lateral common electrode line and the drain of each thin film transistor do not overlap in a direction perpendicular to the display panel.
  • the lateral common electrode line may include a lateral common electrode line body disposed in parallel with the gate line and a lateral common electrode line connecting body surrounding the drains of the respective thin film transistors.
  • a gap may be formed between the lateral common electrode line connector and the drain of the thin film transistor in the corresponding pixel region.
  • the shape of the portion of the lateral common electrode line connecting body surrounding the drain of the thin film transistor may be a right angle shape, a diagonal line shape, or a circular shape.
  • the common electrode line may further include a longitudinal common electrode line disposed between the respective pixel column groups.
  • an insulating layer may be disposed between the common electrode line and the pixel electrode connected to the common electrode, and the vertical common electrode line may pass through a connection via penetrating the insulating layer and disposed in the same layer as the pixel electrode
  • the connection electrode is electrically connected.
  • the common electrode lines, the gates of the respective thin film transistors, and the respective gate lines may be disposed in the same layer.
  • the common electrode and the pixel electrode may both be disposed in the pixel region, the common electrode line may be connected to the common electrode, and the pixel electrode may be connected to the drain of the thin film transistor of the corresponding pixel region.
  • the common electrode may be a plate electrode, the pixel electrode may be a slit electrode, and the pixel electrode and the common electrode may overlap in a direction perpendicular to the display panel.
  • each of the thin film transistors may be a bottom gate type thin film transistor, and the common electrode may be disposed under the common electrode line.
  • the display panel may further include a color filter substrate including a black matrix.
  • the common electrode line and the black matrix may overlap in a direction perpendicular to the display panel.
  • a display device comprising a display panel according to the present invention.
  • the display panel of the present invention not only the common electrode can be lifted in the display panel
  • the uniformity of the voltage, the reduction of the resistance of the common electrode line, and the reduction of the voltage difference between the pixel electrode and the common electrode can also avoid electrostatic discharge due to the formation process of the gate insulating layer. Therefore, the display device using the display panel has good display quality and low cost.
  • FIG. 1 is a top plan view of a display panel in accordance with an embodiment of the present invention.
  • FIG. 2 is a partial schematic view of the display panel shown in FIG. 1;
  • FIG. 3 is a cross-sectional view of a display panel in accordance with an embodiment of the present invention.
  • FIG. 4 is a partial schematic view of a display panel in accordance with another embodiment of the present invention.
  • the technical idea of the present invention is to provide a lateral common electrode line extending in the row direction of the pixel region, which does not overlap with the drain of the thin film transistor of each pixel region in a direction perpendicular to the display panel, thereby realizing double in the ADS type display panel Grid line design. Since the lateral common electrode lines and the drains of the respective thin film transistors do not overlap in a direction perpendicular to the display panel, Electro-Static Discharge (ESD) due to the formation process of the gate insulating layer can be avoided. In addition, it is also possible to increase the uniformity of the common electrode voltage in the display panel, reduce the resistance of the common electrode line, and reduce the voltage difference between the pixel electrode and the common electrode.
  • ESD Electro-Static Discharge
  • FIG. 1 is a plan view of a display panel according to an embodiment of the present invention
  • FIG. 2 is a partial schematic view of the display panel illustrated in FIG. 1
  • FIG. 3 is a cross-sectional view of the display panel according to an embodiment of the present invention.
  • a display panel may include an array substrate and a color filter substrate. As shown in FIG. 1, the array substrate is divided into a plurality of pixel regions 7 of a plurality of rows and columns. Each of the pixel regions 7 may be provided with a thin film transistor including a gate electrode, a source electrode 4, an active layer 5, and a drain electrode 6.
  • the gate of the film transistor may be formed as a portion extending from the first gate line 1 and the second gate line 2 toward the corresponding pixel region 7, the extended portion being perpendicular to the display panel
  • the active layer 5, the source 4, and the drain 6 of the thin film transistor partially overlap in the direction.
  • two gate lines that is, a first gate line 1 and a second gate line 2 are disposed between adjacent two rows of pixel regions. Further, gates of thin film transistors of adjacent two pixel regions in the same row are respectively connected to one of two gate lines adjacent to the row of pixel regions.
  • the gate of the thin film transistor of the first pixel region in the first row of pixel regions shown in FIG. 1 is connected to the gate line 1 adjacent to the row of pixel regions, and the second of the row of pixel regions The gate of the thin film transistor of the pixel region is connected to the gate line 2 adjacent to the row of pixel regions.
  • the gate of the thin film transistor of the first pixel region in one row of pixel regions may be connected to the gate line 2 adjacent to the row of pixel regions, and the second pixel in one row of pixel regions
  • the gate of the thin film transistor of the region may be connected to the gate line 1 adjacent to the row of pixel regions below.
  • two adjacent columns of pixel regions may constitute a pixel column group.
  • the first column of pixel regions and the second column of pixel regions may constitute a first group of pixel columns
  • the third column of pixel regions and the fourth column of pixel regions may constitute a second group of pixel columns.
  • a data line 8 is disposed between two columns of pixel regions of the same pixel column group, and no data lines are provided between the respective pixel column groups.
  • the source 4 of the thin film transistor of the pixel region of the same pixel column group is connected to the data line 8 disposed in the pixel column group. Further, as shown in FIG.
  • the array substrate according to the present embodiment may further include a pixel electrode 12, a common electrode 11, and a common electrode line 3.
  • the common electrode line 3 may include a lateral common electrode line 31 disposed in parallel with the gate line 1 and the gate line 2, and a longitudinal common electrode line 32 disposed between the respective pixel column groups, as shown in FIG.
  • the lateral common electrode line 31 and the drain 6 of each thin film transistor do not overlap in a direction perpendicular to the display panel.
  • the present invention is not limited thereto, and the longitudinal common electrode line 32 may not be provided.
  • the above structure provides an ADS type double gate line type array substrate. Same phase The adjacent two pixels are controlled by one data line and two gate lines. Since the driving IC of the data line is more expensive than the driving IC of the gate line, the display panel having the structure can have the advantages of the ADS type display panel, and at the same time, the number of the data flip chip is reduced by half by the double gate line design, and the production cost is effectively reduced. .
  • the lateral common electrode line 31 may include a lateral common electrode line body disposed in parallel with the gate line and a lateral common electrode line connecting body 310 surrounding the drain electrode 6 of each thin film transistor.
  • a gap may be formed between the lateral common electrode line connecting body 310 and the drain electrode 6 of the thin film transistor in the corresponding pixel region 7.
  • the shape of the portion of the lateral common electrode line connecting body 310 surrounding the drain electrode 6 of the thin film transistor may be a right angle shape.
  • the shape of the portion of the lateral common electrode line connecting body 310 surrounding the drain electrode 6 of the thin film transistor may be obliquely shaped.
  • the present invention is not limited thereto, and the shape of the portion of the lateral common electrode line connecting body 310 surrounding the drain electrode 6 of the thin film transistor may also be other shapes, for example, a circular shape.
  • the lower limit of the width of the gap formed between the lateral common electrode line connecting body 310 and the drain electrode 6 should satisfy the alignment accuracy of the preparation process of the array, and the upper limit should be as large as possible without affecting the aperture ratio.
  • the gap formed between the lateral common electrode line connecting body 310 and the drain electrode 6 has a width ranging from 1.5 ⁇ m to 4 ⁇ m.
  • the lateral common electrode line 31 bypasses the drain 6 of each thin film transistor in its extending direction without overlapping it in a direction perpendicular to the display panel. Since the drain pad is small, the effect on the pixel aperture ratio is small.
  • the lateral common electrode line disposed in this manner can reduce the resistance of the common electrode line without affecting the aperture ratio, thereby avoiding the poor greening of the screen due to the large resistance of the common electrode line or the large coupling capacitance. . Since the lateral common electrode line 31 does not pass under the drain 6 of each thin film transistor, the data line signal and the common electrode signal are short-circuited due to the voltage difference between the common electrode 3 and the drain 6.
  • the thin film transistor may be a bottom gate type thin film transistor, and the common electrode 11 may be disposed under the common electrode line 3 as shown in FIG.
  • the common electrode 11 is disposed on the substrate 13, and the common electrode line 3 is disposed on the common electrode 11.
  • the gate line 1 and the gate line 2 may be disposed in the same layer as the common electrode line 3.
  • a gate insulating layer 9, an active layer 5, a source 4 and a drain 6, a passivation layer 10, and a pixel electrode 12 are sequentially formed on the substrate 13 on which the gate line 1, the gate line 2, and the common electrode line 3 are formed.
  • the color filter substrate may include a color film layer 15 and a black matrix 14 which are sequentially disposed on the substrate 13.
  • the common electrode 11 and the pixel electrode 12 are both disposed in the pixel region 7.
  • the common electrode line 3 is connected to the common electrode 11, and the pixel electrode 12 is connected to the drain 6 of the thin film transistor of the corresponding pixel region 7.
  • the common electrode is a plate electrode
  • the pixel electrode is a slit electrode
  • the pixel electrode 12 and the common electrode 11 overlap in a direction perpendicular to the display panel.
  • the present invention is not limited thereto as long as one of the common electrode and the pixel electrode is a slit electrode and the other is a plate electrode. Further, it suffices that the slit electrode is at a position opposite to the upper layer (that is, closer to the color filter substrate).
  • the longitudinal common electrode line 32 disposed between the respective pixel column groups is disconnected in the longitudinal direction to avoid the gate line 1 disposed in the same layer. Crosses the grid line 2.
  • an insulating layer 9 may be disposed between the common electrode line 3 connected to the common electrode 11 and the pixel electrode 12.
  • Each of the longitudinal common electrode lines 32 may be electrically connected through a connection via 16 penetrating the insulating layer 9 and a connection electrode provided in the same layer as the pixel electrode 12.
  • the lateral common electrode line 31, the longitudinal common electrode line 32, and the connection electrode connecting the respective longitudinal common electrode lines 32 may constitute a mesh-shaped common electrode line 3, thereby reducing the resistance of the common electrode line 3 and increasing the voltage of the common electrode. Uniformity.
  • the common electrode line 3 of the array substrate may overlap with the black matrix 14 of the color filter substrate in a direction perpendicular to the display panel.
  • a display device comprising a display panel substantially of the present invention.
  • the display device may include, but is not limited to, a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板，包括具有多行多列的多个像素区（7）的阵列基板，所述多个像素区（7）中的每一个均设置有包括栅极、源极（4）、漏极（6）和有源层（5）的薄膜晶体管。在相邻两行像素区（7）之间设置有两条栅线（1，2）。相邻两列像素区（7）构成一个像素列组，在同一像素列组的两列像素区（7）之间设置有一条数据线（8）。阵列基板还包括像素电极（12）、公共电极（11）和公共电极线（3），公共电极线（3）包括与栅线（1，2）平行设置的横向公共电极线（31），其中，横向公共电极线（31）与各个薄膜晶体管的漏极（6）在垂直于显示面板的方向上不重叠。

Description

显示面板和显示装置 技术领域
本发明属于显示技术领域，具体涉及一种显示面板和显示装置。
背景技术
在平板显示装置中，减少覆晶薄膜(Chip On Flex或Chip On Film，COF)数量是扭曲向列(twisted nematic，TN)型或垂直配向(vertical alignment，VA)型液晶显示(Liquid Crystal Display，LCD)装置降低成本的常用方案。此外，LCD装置的边框呈不断减小的趋势。因此，出现了双栅线(Dual Gate Lines)设计，以达到减少一半数据覆晶薄膜(Data COF)的目的。
随着显示技术的发展，出现了高级超维场转换技术(ADvanced Super Dimension Switch，AD-SDS，简称ADS)型LCD装置，其具有较好的显示品质，具备高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(push Mura)等优点。然而，迄今为止还未出现将双栅线设计应用于ADS型LCD装置的技术方案，因此ADS型LCD装置的性能和成本还存在改善空间。
发明内容
本发明所要解决的技术问题是针对现有技术中存在的上述不足，提供一种显示面板和显示装置，其具有公共电极电压均一性好，且公共电极线电阻小的优点。
根据本发明的一个方面，提供一种显示面板，其包括具有多行多列的多个像素区的阵列基板，所述多个像素区中的每一个均设置有包括栅极、源极、漏极和有源层的薄膜晶体管。在相邻两行像素区之间设置有两条栅线，同一行中相邻两个像素区的薄膜晶体管的栅极分别连接至与该行像素区邻近的两条栅线中的一条栅线。相邻两列像素区构成一个像素列组，在同一像素列组的两列像素区之间设置有一条数据线，并且在各个像素列组之间不设置数据线。同一像素列组的像 素区的薄膜晶体管的源极连接至设置在该像素列组中的数据线。阵列基板还包括像素电极、公共电极和公共电极线。公共电极线包括与栅线平行设置的横向公共电极线，其中，横向公共电极线与各个薄膜晶体管的漏极在垂直于显示面板的方向上不重叠。
根据本发明的实施例，横向公共电极线可以包括与栅线平行设置的横向公共电极线主体以及围绕各个薄膜晶体管的漏极的横向公共电极线连接体。横向公共电极线连接体与对应的像素区内的薄膜晶体管的漏极之间可以形成间隙。
根据本发明的实施例，横向公共电极线连接体围绕薄膜晶体管的漏极的部分的形状可以为直角形状、斜线形状或圆形形状。
根据本发明的实施例，公共电极线还可以包括设置在各个像素列组之间的纵向公共电极线。
根据本发明的实施例，在连接至公共电极的公共电极线与像素电极之间可以设置有绝缘层，并且纵向公共电极线可以通过穿透绝缘层的连接过孔以及与像素电极同层设置的连接电极电连接。
根据本发明的实施例，公共电极线、各个薄膜晶体管的栅极和各条栅线可以设置在同一层。
根据本发明的实施例，公共电极和像素电极可以均设置在像素区内，公共电极线可以与公共电极连接，并且像素电极可以与相应的像素区的薄膜晶体管的漏极连接。公共电极可以为板状电极，像素电极可以为狭缝状电极，并且像素电极和公共电极可以在垂直于显示面板的方向上重叠。
根据本发明的实施例，各个薄膜晶体管可以为底栅型薄膜晶体管，并且公共电极可以设置在公共电极线下方。
根据本发明多少岁了，显示面板还可以包括彩膜基板，所述彩膜基板包括黑矩阵。公共电极线与黑矩阵可以在垂直于显示面板的方向上重叠。
根据本发明的另一个方面，提供一种显示装置，其包括根据本发明的显示面板。
根据本发明的显示面板，不仅能够在显示面板内提升公共电极 电压的均一性、降低公共电极线的电阻、减小像素电极和公共电极之间的电压差，还能避免因栅绝缘层的形成工艺所带来的静电释放。因此，采用该显示面板的显示装置显示质量好且成本低。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将结合附图对本发明的各实施例进行详细描述。应当认识到，下面的描述仅用于说明本发明的实施例，而非限制本发明的范围。对于本领域普通技术人员来讲，在不脱离本发明的范围的情况下，可以对各实施例进行各种修改和改变。在所示的附图中：
图1为根据本发明的实施例的显示面板的俯视图；
图2为图1所示的显示面板的局部示意图；
图3为根据本发明的实施例的显示面板的剖视图；以及
图4为根据本发明的另一实施例的显示面板的局部示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明显示面板和显示装置作进一步详细描述。
本发明的技术构思在于：设置沿像素区行方向延伸的横向公共电极线，其与各个像素区的薄膜晶体管的漏极在垂直于显示面板的方向上不重叠，从而ADS型显示面板中实现双栅线设计。由于横向公共电极线与各个薄膜晶体管的漏极在垂直于显示面板的方向上不重叠，因此能避免因栅绝缘层的形成工艺所带来的静电释放(Electro-Static Discharge，简称ESD)。此外，还能够在显示面板内提升公共电极电压的均一性、降低公共电极线的电阻、并减小像素电极和公共电极之间的电压差。
图1为根据本发明的实施例的显示面板的俯视图，图2为图1所示的显示面板的局部示意图，并且图3为根据本发明的实施例的显示面板的剖视图。
参见图1至图3，根据本发明的实施例的显示面板可以包括阵列基板和彩膜基板。如图1所示，阵列基板划分为多行多列的多个像素区7。每一个像素区7可以设置有包括栅极、源极4、有源层5和漏极6的薄膜晶体管。在图1示出的显示面板中，膜晶体管的栅极可以形成为从第一栅线1和第二栅线2向相应的像素区7延伸的一部分，该延伸的部分在垂直于显示面板的方向上薄膜晶体管的有源层5、源极4和漏极6部分地/全部地重叠。
参见图1，在相邻两行像素区之间设置有两条栅线，即，第一栅线1和第二栅线2。此外，同一行中相邻两个像素区的薄膜晶体管的栅极分别连接至与该行像素区邻近的两条栅线中的一条栅线。例如，在图1所示的第一行像素区中的第一个像素区的薄膜晶体管的栅极连接至在下方与该行像素区邻近的栅线1，该行像素区中的第二个像素区的薄膜晶体管的栅极连接至在上方与该行像素区邻近的栅线2。然而，本发明不限于此，一行像素区中的第一个像素区的薄膜晶体管的栅极可以连接至在上方与该行像素区邻近的栅线2，而一行像素区中的第二个像素区的薄膜晶体管的栅极可以连接至在下方与该行像素区邻近的栅线1。
参见图1，相邻两列像素区可以构成一个像素列组。例如，如图1所述，第一列像素区和第二列像素区可以构成第一像素列组，第三列像素区和第四列像素区可以构成第二像素列组。在同一像素列组的两列像素区之间设置有一条数据线8，并且在各个像素列组之间不设置数据线。同一像素列组的像素区的薄膜晶体管的源极4连接至设置在该像素列组中的数据线8。此外，如图3所示，根据本实施例的阵列基板还可以包括像素电极12、公共电极11和公共电极线3。公共电极线3可以包括与栅线1和栅线2平行设置的横向公共电极线31和设置在各个像素列组之间的纵向公共电极线32，如图1所示。横向公共电极线31与各个薄膜晶体管的漏极6在垂直于显示面板的方向上不重叠。然而，本发明不限于此，也可以不设置纵向公共电极线32。
上述结构提供了一种ADS型的双栅线型阵列基板。同一行中相 邻两个像素由一条数据线和两条栅线控制。由于数据线的驱动IC比栅线的驱动IC成本高，因此具备该结构的显示面板能够具有ADS型显示面板的优点，同时通过双栅线设计减少一半数据覆晶薄膜数量，并有效降低生产成本。
参见图2，根据本实施例，横向公共电极线31可以包括与栅线平行设置的横向公共电极线主体以及围绕各个薄膜晶体管的漏极6的横向公共电极线连接体310。横向公共电极线连接体310与对应的像素区7内的薄膜晶体管的漏极6之间可以形成间隙。
如图2所述，横向公共电极线连接体310围绕薄膜晶体管的漏极6的部分的形状可以为直角形状。
图4为根据本发明的另一实施例的显示面板的局部示意图。如图4所述，横向公共电极线连接体310围绕薄膜晶体管的漏极6的部分的形状可以斜线形状。然而，本发明不限于此，横向公共电极线连接体310围绕薄膜晶体管的漏极6的部分的形状还可以是其他形状，例如，圆形形状。
通常情况下，横向公共电极线连接体310与漏极6之间成的间隙的宽度的下限应当满足阵列的制备工艺的对位精度，而上限以不影响开口率的条件下越大越好。根据本发明的实施例，横向公共电极线连接体310与漏极6之间形成的间隙的宽度范围为1.5μm-4μm。
根据本发明的实施例，横向公共电极线31在其延伸方向上绕开各个薄膜晶体管的漏极6而不与之在垂直于显示面板的方向上重叠。由于漏极焊盘较小，因此对像素开口率影响较小。以此方式设置的横向公共电极线能够在不影响开口率前提下降低公共电极线的电阻，从而避免因公共电极线的电阻较大或耦合电容较大而在特定画面下出现的画面泛绿不良。由于横向公共电极线31没有从各个薄膜晶体管的漏极6下方穿过，因此避免了由于公共电极3与漏极6之间的电压差所导致的数据线信号与公共电极信号短路。
根据本发明的实施例，薄膜晶体管可以为底栅型薄膜晶体管，并且公共电极11可以设置在公共电极线3下方，如图3所示。在图3所示的实施例中，在衬底13上设置公共电极11，并且公共电极线 3设置在公共电极11上。栅线1和栅线2可以与公共电极线3设置在同一层。在形成有栅线1、栅线2和公共电极线3的衬底13上依次形成栅绝缘层9、有源层5、源极4和漏极6、钝化层10和像素电极12。彩膜基板可以包括依次设置在衬底13上的彩膜层15和黑矩阵14。
公共电极11和像素电极12均设置于像素区7内。公共电极线3与公共电极11连接，并且像素电极12与相应的像素区7的薄膜晶体管的漏极6连接。在图3所示的实施例中，公共电极为板状电极，而像素电极为狭缝状电极，并且像素电极12和公共电极11在垂直于显示面板的方向上重叠。然而，本发明不限于此，只要公共电极和像素电极中的一个为狭缝状电极、另一个为板状电极即可。此外，只要狭缝状电极处于相对上层(即，更靠近彩膜基板)的位置即可。
再次参考图1，在公共电极线3包括纵向公共电极线32的情况下，设置在各个像素列组之间的纵向公共电极线32在纵向上断开，以避免与同层设置的栅线1和栅线2交叉。
根据本发明的实施例，在连接至公共电极11的公共电极线3与像素电极12之间可以设置有绝缘层9(如图3所示)。各个纵向公共电极线32可以通过穿透绝缘层9的连接过孔16以及与像素电极12同层设置的连接电极电连接。这里，横向公共电极线31、纵向公共电极线32以及连接各个纵向公共电极线32的连接电极可以构成网状的公共电极线3，从而减低了公共电极线3的电阻并提高了公共电极电压的均一性。
根据本发明的实施例，阵列基板的公共电极线3可以与彩膜基板的黑矩阵14在垂直于显示面板的方向上重叠。
根据本发明的另一个方面，提供一种显示装置，其包括根本本发明的显示面板。所述显示装置可以包括(但不限于)：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的 普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

  1. 一种显示面板，包括具有多行多列的多个像素区的阵列基板，所述多个像素区中的每一个均设置有包括栅极、源极、漏极和有源层的薄膜晶体管，其中，在相邻两行像素区之间设置有两条栅线，同一行中相邻两个像素区的薄膜晶体管的栅极分别连接至与该行像素区邻近的两条栅线中的一条栅线，相邻两列像素区构成一个像素列组，在同一像素列组的两列像素区之间设置有一条数据线，并且在各个像素列组之间不设置数据线，同一像素列组的像素区的薄膜晶体管的源极连接至设置在该像素列组中的数据线，
    阵列基板还包括像素电极、公共电极和公共电极线，公共电极线包括与栅线平行设置的横向公共电极线，其中，横向公共电极线与各个薄膜晶体管的漏极在垂直于显示面板的方向上不重叠。
  2. 根据权利要求1所述的显示面板，其中，横向公共电极线包括与栅线平行设置的横向公共电极线主体以及围绕各个薄膜晶体管的漏极的横向公共电极线连接体，横向公共电极线连接体与对应的像素区内的薄膜晶体管的漏极之间形成间隙。
  3. 根据权利要求2所述的显示面板，其中，横向公共电极线连接体围绕薄膜晶体管的漏极的部分的形状为直角形状、斜线形状或圆形形状。
  4. 根据权利要求1所述的显示面板，其中，公共电极线还包括设置在各个像素列组之间的纵向公共电极线。
  5. 根据权利要求4所述的显示面板，其中，在连接至公共电极的公共电极线与像素电极之间设置有绝缘层，并且纵向公共电极线通过穿透绝缘层的连接过孔以及与像素电极同层设置的连接电极电连接。
  6. 根据权利要求1所述的显示面板，其中，公共电极线、各个薄膜晶体管的栅极和各条栅线设置在同一层。
  7. 根据权利要求1所述的显示面板，其中，公共电极和像素电极均设置在像素区内，公共电极线与公共电极连接，并且像素电极与相应的像素区的薄膜晶体管的漏极连接，
    其中，公共电极为板状电极，像素电极为狭缝状电极，并且像素电极和公共电极在垂直于显示面板的方向上重叠。
  8. 根据权利要求1所述的显示面板，其中，各个薄膜晶体管为底栅型薄膜晶体管，并且公共电极设置在公共电极线下方。
  9. 根据权利要求1-8任一项所述的显示面板，还包括彩膜基板，所述彩膜基板包括黑矩阵，公共电极线与黑矩阵在垂直于显示面板的方向上重叠。
  10. 一种显示装置，包括权利要求1-9任一项所述的显示面板。
PCT/CN2016/079266 2015-06-23 2016-04-14 显示面板和显示装置 Ceased WO2016206449A1 (zh)

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WO2023184426A1 (zh) * 2022-03-31 2023-10-05 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
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