WO2016202050A1 - 薄膜晶体管及其制作方法、显示基板、显示装置 - Google Patents

薄膜晶体管及其制作方法、显示基板、显示装置 Download PDF

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WO2016202050A1
WO2016202050A1 PCT/CN2016/078424 CN2016078424W WO2016202050A1 WO 2016202050 A1 WO2016202050 A1 WO 2016202050A1 CN 2016078424 W CN2016078424 W CN 2016078424W WO 2016202050 A1 WO2016202050 A1 WO 2016202050A1
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layer
pattern
thin film
film transistor
heat dissipation
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PCT/CN2016/078424
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English (en)
French (fr)
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黄维
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京东方科技集团股份有限公司
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Priority to US15/511,653 priority Critical patent/US10170717B2/en
Publication of WO2016202050A1 publication Critical patent/WO2016202050A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
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    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/474—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/125—Active-matrix OLED [AMOLED] displays including organic TFTs [OTFT]

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor, a method of fabricating the same, a display substrate, and a display device.
  • OLEDs organic light-emitting diodes
  • OLEDs Organic Light-Emitting Diodes
  • the flexible OLED display has high requirements on the threshold voltage (Vth) uniformity and Vth reliability of the flexible thin film transistor (TFT), that is, the electric biased threshold voltage shift (Bias stress) characteristic.
  • the floating value ( ⁇ Vth) of the threshold voltage is generally required to be less than 0.3V. Therefore, the suppression of the electrically biased threshold voltage drift and the improvement of the structure of the flexible thin film transistor/process improvement have become the development trend of the technology of the flexible thin film transistor to drive the OLED display.
  • the self-heating effect is a major cause of the electrical biased threshold voltage drift of thin film transistors.
  • the effect is more pronounced, and the leakage current (Id) of the thin film transistor can vary by 4-5 times with the self-heating effect.
  • the present disclosure provides a thin film transistor, a method for fabricating the same, a display substrate, and a display device, which can effectively reduce the influence of the self-heating effect of the thin film transistor.
  • an embodiment of the present disclosure provides a thin film transistor including a source electrode pattern and a drain electrode pattern disposed in a same layer, the thin film transistor further comprising:
  • a heat dissipation layer disposed between the source electrode pattern and the drain electrode pattern.
  • the heat dissipation layer is a polymer carbon nanotube composite material.
  • the polymer carbon nanotube composite material is an insulating material.
  • the top surface of the heat dissipation layer is coated with a hydrophobic organic film layer;
  • the top surface of the heat dissipation layer is subjected to plasma treatment.
  • the thin film transistor further includes:
  • the source electrode pattern, the drain electrode pattern, and the heat dissipation layer are located above the buffer layer.
  • the thin film transistor further includes:
  • An organic semiconductor layer located on the source electrode pattern, the drain electrode pattern, and the heat dissipation layer;
  • a gate electrode layer over the first organic dielectric insulating layer.
  • the thin film transistor further includes:
  • the polymer carbon nanotube composite material is a material formed by filling carbon nanotubes aggregated by phase separation in a non-uniform or uniformly distributed pore in an insulating polymer matrix.
  • an embodiment of the present disclosure further provides a method of fabricating a thin film transistor including a source electrode pattern and a drain electrode pattern disposed in the same layer;
  • the method includes:
  • a heat dissipation layer pattern having a predetermined conductivity is formed between the source electrode pattern and the drain electrode pattern.
  • the heat dissipation layer is a polymer carbon nanotube composite material.
  • the polymer carbon nanotube composite material is a material formed by filling carbon nanotubes aggregated by phase separation in a non-uniform or uniformly distributed pore in an insulating polymer matrix.
  • the method further includes:
  • the top surface of the heat dissipation layer is plasma treated.
  • the method further includes: before the heat dissipation layer pattern is formed:
  • a source electrode pattern and a drain electrode pattern are formed over the buffer layer pattern.
  • the method further includes:
  • a gate electrode layer pattern is formed over the first organic dielectric insulating layer pattern.
  • the method further includes:
  • the gate electrode layer pattern is formed over the second organic dielectric insulating layer.
  • an embodiment of the present disclosure further provides a display substrate, which may specifically include the thin film transistor provided by the embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a display device, which may specifically include the display substrate provided by the embodiment of the present disclosure.
  • the display substrate, and the display device provided by the present disclosure a predetermined conductivity is set between the source electrode pattern and the drain electrode pattern disposed in the same layer of the thin film transistor.
  • the heat dissipation layer can effectively reduce the influence of the self-heating effect of the thin film transistor and ensure the image display quality of the display device.
  • FIG. 1 is a schematic structural view of a thin film transistor provided in some embodiments of the present disclosure.
  • FIG. 2 is a schematic structural view of a thin film transistor provided in some embodiments of the present disclosure.
  • FIG. 3 is a schematic structural view of a thin film transistor provided in some embodiments of the present disclosure.
  • FIG. 4 is a schematic structural view of a thin film transistor provided in some embodiments of the present disclosure.
  • FIG. 5 is a schematic structural view of a thin film transistor provided in some embodiments of the present disclosure.
  • FIG. 6 is a schematic structural view of a thin film transistor provided in some embodiments of the present disclosure.
  • the self-heating effect is mainly concentrated on the interface between the gate electrode and the gate insulating layer (GI), the substrate having poor thermal conductivity (for example, a plastic substrate), and the channel region in the TFT structure.
  • the self-heating effect at the interface can be effectively improved by adding a heat conductive layer such as a thin layer of Cu at a position close to the gate point or the like.
  • a self-heating effect can be effectively improved by adding an insulating layer between the gate electrode and the plastic substrate, such as a buffer commonly used in TFT backplane technology.
  • the efficiency of heat conduction is further affected by the interval of a film layer such as an active layer, a buffer layer, a planarization layer, or the like. A certain negative impact.
  • the embodiment of the present disclosure provides a thin film transistor.
  • the thin film transistor may specifically include a source electrode 1 pattern and a drain electrode 2 pattern disposed in the same layer.
  • the thin film transistor may further include a heat dissipation layer 3 having a predetermined conductivity between the source electrode 1 pattern and the drain electrode 2 pattern.
  • the heat dissipation layer 3 in the communication region of the thin film transistor with relatively good self-heating effect, the heat dissipation and transmission in the channel region can be accelerated, the effect of the self-heating effect of the thin film transistor is effectively improved, and the display device is ensured. Image display quality.
  • the material of the heat dissipation layer 3 may be a material having good heat transfer property, that is, thermal conductivity; at the same time, the material also needs to have a lower conductivity to control the source electrode 1 at both ends of the heat dissipation layer 3 and Leakage current between the drain electrodes 2.
  • the inventors measured the thermal conductivity and electrical conductivity of several substances. The specific results are shown in Table 1:
  • the thermal conductivity and electrical conductivity characteristics of the carbon nanotubes are in conformity with the requirements of the heat dissipation layer 3 of the embodiments of the present disclosure.
  • carbon nanotubes have the advantages of solution processing, excellent mechanical properties, and good thermal conductivity. Therefore, in a specific embodiment, the heat dissipation layer 3 according to the embodiment of the present disclosure may specifically be a polymer carbon nanotube composite material.
  • the heat dissipation layer 3 can be prepared by preparing one or several layers of the polymer carbon nanotube composite material film layer.
  • the polymer carbon nanotube composite material may specifically fill the non-uniform or uniformly distributed pores in the insulating polymer matrix with carbon nanotubes aggregated by phase separation, so that the heat dissipation layer 3 has high thermal conductivity. Low conductivity and flexural resistance. Therefore, the effect of the self-heating effect of the thin film transistor can be effectively reduced, and the bias voltage characteristic of the bias voltage of the thin film transistor can be improved. At the same time, the material has the advantages of simple process and mass production. The existence of the above advantages makes the thin film transistor through which the embodiment of the present disclosure has a large application potential in display panels (flexible display panels), printable semiconductor electronic devices, sensing components, and the like.
  • inkjet printing A solution processing method such as cast) or spin coating is sequentially performed by depositing an organic semiconductor solution or an organic polymer dielectric material solution at a position where the heat dissipation layer 3 is located, that is, a thin film transistor communication region, and performing pattern formation.
  • the surface of the heat dissipation layer 3 of the polymer carbon nanotube composite material may be subjected to certain treatment, for example, at the top of the heat dissipation layer 3.
  • the surface is coated with a hydrophobic organic film layer; or the top surface of the heat dissipation layer 3 is subjected to plasma treatment or the like.
  • the thin film transistor provided by the embodiment of the present disclosure may specifically include the following layers in addition to the source electrode 1 , the drain electrode 2 , and the heat dissipation layer 3 :
  • the source electrode 1 pattern, the drain electrode 2 pattern, and the heat dissipation layer 3 are located on the buffer layer 5;
  • An organic semiconductor layer (OSC) 6 located on the source electrode 1 pattern, the drain electrode 2 pattern, and the heat dissipation layer 3;
  • the technical solution provided by the embodiment of the present disclosure is described by using an organic thin film transistor that is in contact with the top of the top gate.
  • the thin film transistor provided by the embodiment of the present disclosure may also be Other types of thin film transistors, such as bottom gate type thin film transistors, have been of the thin film transistor type. That is, in the embodiment of the present disclosure, the layers other than the heat dissipation layer 3, the source electrode 1, and the drain electrode 2 may be disposed as needed.
  • the semiconductor layer of the TFT structure in order to improve image display quality and reduce leakage of the array backplane for the top TFT bottom contact organic TFT flexible backplane, it is generally required to pattern the semiconductor layer of the TFT structure.
  • OSC organic semiconductor layer
  • OPI organic dielectric insulating layer
  • photolithography, laser, plasma etching, etc. may also be employed for the organic semiconductor layer 6 and the first organic
  • the dielectric insulating layer 7 is patterned to reduce leakage (Ids) of the non-channel region, then the second organic dielectric insulating layer 9 is deposited, and the gate electrode 8 is formed over the second organic dielectric insulating layer 9 and is flat. Layers (not shown).
  • the structure of the thin film transistor can be as shown in FIG.
  • a second organic dielectric insulating layer 9 is disposed over the first organic dielectric insulating layer 7, and a gate electrode 8 is formed over the second organic dielectric insulating layer 9.
  • the embodiment of the present disclosure further provides a method for fabricating a thin film transistor including a source electrode 1 pattern and a drain electrode 2 pattern disposed in the same layer.
  • the method further includes: forming a pattern of the heat dissipation layer 3 between the pattern of the source electrode 1 and the pattern of the drain electrode 2, the heat dissipation layer 3 having a predetermined conductivity.
  • the method further includes: before the pattern of the heat dissipation layer 3 is formed:
  • a source electrode 1 pattern and a drain electrode 2 pattern are formed over the buffer layer 5 pattern.
  • the method further includes:
  • the top surface of the heat dissipation layer 3 is subjected to plasma treatment.
  • the method further includes:
  • a pattern of the gate electrode layer 8 is formed over the first organic dielectric insulating layer pattern 7.
  • a low stress, insulating buffer layer 5 pattern is deposited on the flexible or rigid substrate substrate 4.
  • the preparation process of the buffer layer 5 pattern is not limited, and the buffer layer 5 pattern may be prepared by any mature fabrication process, for example, but not limited to photolithography, printing, printing, and metal mask. (shadow mask) One or more of methods such as vapor deposition.
  • the structure diagram of the thin film transistor at this time can be as shown in FIG.
  • the structural schematic diagram of the thin film transistor at this time can be as shown in FIG.
  • solution processing methods such as inkjet, drop cast, spincoat, etc., to uniformly mix carbon nanotubes, monomers or oligomers, initiators, a solution of a dopant or the like (or other substance capable of forming a polymer carbon nanotube composite), deposited on The channel region of the thin film transistor, that is, between the source electrode 1 and the drain electrode 2 pattern.
  • the solution is irradiated with ultraviolet light or other heat source to initiate polymerization phase separation (ie, separation stage), and finally a polymer carbon nanotube composite material layer composed of an insulating polymer and a thermally conductive carbon nanotube is formed, that is, heat dissipation Layer 3.
  • the structure diagram of the thin film transistor at this time can be as shown in FIG. 6.
  • the organic semiconductor layer 6 (OSC) and the first organic dielectric insulating layer pattern 7 (OGI) are sequentially formed.
  • a pattern of the gate electrode layer 8 is formed.
  • the thin film transistor fabrication method provided by the embodiment of the present disclosure may also be on the existing thin film transistor structure (for example, the organic semiconductor layer 6 and the first layer) before the gate electrode layer 8 pattern is formed.
  • the embodiment of the present disclosure further provides a display substrate, which may specifically include the thin film transistor provided by the embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a display device, which may specifically include the display substrate provided by the embodiment of the present disclosure.

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Abstract

提供一种薄膜晶体管及其制作方法、显示基板、显示装置。薄膜晶体管包括同层设置的源电极（1）图案和漏电极（2）图案，以及设置于源电极（1）图案和漏电极（2）图案之间的散热层（3）。

Description

薄膜晶体管及其制作方法、显示基板、显示装置
相关申请的交叉引用
本申请主张在2015年6月15日在中国提交的中国专利申请号No.201510329297.0的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，具体可以涉及一种薄膜晶体管及其制作方法、显示基板、显示装置。
背景技术
近年来，有机发光二极管又称为有机电激光显示(Organic Light-Emitting Diode，OLED)因种种优势成为柔性显示的主要显示类型。
柔性OLED显示对柔性薄膜晶体管(TFT)的阈值电压(Vth)均匀性、Vth信赖性，即电偏置式阈值电压漂移(Bias stress)特性要求很高。一般要求阈值电压的浮动值(ΔVth)小于0.3V。因此，电偏置式阈值电压漂移的抑制和柔性薄膜晶体管结构的改进/工艺提高等成为柔性薄膜晶体管驱动OLED显示的技术开发趋势。
自发热效应是导致薄膜晶体管产生电偏置式阈值电压漂移的一大原因。对于高分辨率、短沟道的薄膜晶体管来说，其影响更加显著，薄膜晶体管的漏电流(Id)变化可随着自加热效应相差4-5倍。
如何避免自发热效应是本领域需要解决的技术问题之一。
发明内容
本公开提供一种薄膜晶体管及其制作方法、显示基板、显示装置，可有效降低薄膜晶体管自发热效应的影响。
一方面，本公开实施例提供了一种薄膜晶体管，包括同层设置的源电极图案和漏电极图案，所述薄膜晶体管还包括：
设置于所述源电极图案和漏电极图案之间的散热层。
可选的，所述散热层为高分子碳纳米管复合材料。
可选的，所述高分子碳纳米管复合材料为绝缘材料。
可选的，所述散热层顶部表面涂覆有疏水性有机膜层；或者
所述散热层顶部表面经过等离子体处理。
可选的，所述薄膜晶体管还包括：
衬底基板；
形成于衬底基板之上的缓冲层；
所述源电极图案、漏电极图案以及散热层位于所述缓冲层之上。
可选的，所述薄膜晶体管还包括：
位于所述源电极图案、漏电极图案以及散热层之上的有机半导体层；
位于所述有机半导体层之上的第一有机介电绝缘层；
位于所述第一有机介电绝缘层之上的栅电极层。
可选的，所述薄膜晶体管还包括：
位于所述第一有机介电绝缘层与所述栅电极层之间的第二有机介电绝缘层。
可选的，所述高分子碳纳米管复合材料为在绝缘的高分子基体中不均匀或者均匀分布的孔道内填充由相分离作用而聚集的碳纳米管所形成的材料。
另一方面，本公开实施例还提供了一种薄膜晶体管制作方法，所述薄膜晶体管包括同层设置的源电极图案和漏电极图案；
所述方法包括：
在所述源电极图案和漏电极图案之间制作具有预设导电率散热层图案。
可选的，所述散热层为高分子碳纳米管复合材料。
可选的，所述高分子碳纳米管复合材料为在绝缘的高分子基体中不均匀或者均匀分布的孔道内填充由相分离作用而聚集的碳纳米管所形成的材料。
可选的，所述方法还包括：
在所述散热层顶部表面涂覆疏水性有机膜层；或者
对散热层顶部表面进行等离子体处理。
可选的，所述方法在制作散热层图案之前还包括：
在衬底基板之上制作缓冲层图案；
在所述缓冲层图案之上制作源电极图案和漏电极图案。
可选的，所述方法还包括：
在所述源电极图案、漏电极图案以及散热层图案之上制作有机半导体层 图案；
在所述有机半导体层图案之上制作第一有机介电绝缘层图案；
在所述第一有机介电绝缘层图案之上制作栅电极层图案。
可选的，在制作所述栅电极层之前，所述方法还包括：
在所述第一有机介电绝缘层图案之上制作第二有机介电绝缘层图案；
所述栅电极层图案形成于所述第二有机介电绝缘层之上。
另一方面，本公开实施例还提供了一种显示基板，该显示基板具体可以包括上述本公开实施例提供的薄膜晶体管。
另一方面，本公开实施例还提供了一种显示装置，该显示装置具体可以包括上述本公开实施例提供的显示基板。
从以上所述可以看出，在本公开提供的薄膜晶体管及其制作方法、显示基板、显示装置中，通过在薄膜晶体管同层设置的源电极图案和漏电极图案之间设置具有预设导电率的散热层，可有效降低薄膜晶体管自发热效应的影响，确保显示装置图像显示质量。
附图说明
图1为本公开一些实施例中提供的薄膜晶体管结构示意图；
图2为本公开一些实施例中提供的薄膜晶体管结构示意图；
图3为本公开一些实施例中提供的薄膜晶体管结构示意图；
图4为本公开一些实施例中提供的薄膜晶体管结构示意图；
图5为本公开一些实施例中提供的薄膜晶体管结构示意图；并且
图6为本公开一些实施例中提供的薄膜晶体管结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权 利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
经过发明人的研究发现，自发热效应的产生主要集中于栅电极与栅绝缘层(GI)之间的界面、热导率较差的基底(例如塑料基底)以及TFT结构中沟道区内。针对栅电极与栅绝缘层之间的自发热效应，可通过在栅点极等邻近位置增加导热层，如Cu薄层等，来有效改善该界面处的自发热效应。而对于热导率较差的塑料基底，可通过在栅电极和塑料基底之间增加绝缘层，如TFT背板技术中常用的缓冲层(buffer)，也可有效改善自发热效应。而对于沟道区内电流产生的自发热热效应，目前没有有效的技术手段实现热量有效地导出。特别地，对于顶栅型TFT器件(尤其是有机TFT器件)，经过半导体层(active)、缓冲层(buffer)、平坦化层(planarization)等膜层的间隔后，热量传导的效率更是受到了一定的负面影响。
本公开实施例提供了一种薄膜晶体管，如图1所示，该薄膜晶体管具体可以包括同层设置的源电极1图案和漏电极2图案。
如图1所示，该薄膜晶体管具体还可以包括设置于所述源电极1图案和漏电极2图案之间的、具有预设导电率的散热层3。
本公开实施例所提供的薄膜晶体管，通过在自发热效应比较显著的薄膜晶体管沟通区域设置散热层3，可加快沟道区内热量的散发和传递，有效改善薄膜晶体管自发热效应的影响，确保显示装置图像显示质量。
本公开实施例所涉及的散热层3的材质可为具有良好热传递性即热导率的材质；同时，该材质还需要具有较低的电导率，以控制散热层3两端的源电极1与漏电极2之间的漏电流。
发明人测得了几种物质的热导率、电导率，具体结果如表1所示：
表1
Figure PCTCN2016078424-appb-000001
通过对上表中物质的特性的分析对比可知，碳纳米管(绝缘体)所具有的热导率和电导率特性比较符合本公开实施例对于散热层3的要求。此外，碳纳米管还具备可溶液加工、力学性能优异、导热性好等优点。因此，在一具体实施例中，本公开实施例所涉及的散热层3具体可为高分子碳纳米管复合材料。
本公开实施例中，可通过制备一层或若干层的高分子碳纳米管复合材料薄膜层，以制备散热层3。
所述高分子碳纳米管复合材料具体可以为在绝缘的高分子基体中不均匀或者均匀分布的孔道内填充由相分离作用而聚集的碳纳米管，从而可使散热层3具备导热率高、电导率低、耐挠曲的性质。因此，可有效降低薄膜晶体管自发热效应的影响，改善薄膜晶体管的电偏置式阈值电压漂移(bias stress)特性。同时采用该材料还具有工艺简单、可批量生产等优点。上述优点的存在，可使本公开实施例通过的薄膜晶体管在显示面板(柔性显示面板)、可印刷半导体电子器件、传感元器件等方面具有较大的应用潜力。
本公开实施例中，可通过使用但不局限于喷墨印刷(inkjet)、甩涂(drop  cast)、旋涂(spincoat)等的溶液加工方法，依次将有机半导体溶液、有机高分子介电材料溶液沉积于散热层3所在位置处即薄膜晶体管沟通区域，并完成图形化的制作。
本公开实施例中，为了优化散热层3表面能分布以增加有机半导体膜层的生长质量，还可对高分子碳纳米管复合材料的散热层3表面进行一定的处理，例如在散热层3顶部表面涂覆有疏水性有机膜层；或者对散热层3顶部表面进行等离子体处理等。
如图2所示，本公开实施例所提供的薄膜晶体管，除源电极1、漏电极2以及散热层3之外、具体还可以包括以下图层：
衬底基板4；
形成于衬底4基板之上的缓冲层5，源电极1图案、漏电极2图案以及散热层3位于缓冲层5之上；
位于源电极1图案、漏电极2图案以及散热层3之上的有机半导体层(OSC)6；
位于有机半导体层6之上的第一有机介电绝缘层(OGI)7；
位于第二有机介电绝缘层7之上的栅电极层8。
在上述图2所示薄膜晶体管中，通过顶栅底接触的有机薄膜晶体管为例对本公开实施例提供的技术方案进行说明，但在实际应用中，本公开实施例所提供的薄膜晶体管还可为其他类型的薄膜晶体管，例如底栅型薄膜晶体管等已有薄膜晶体管类型。即，本公开实施例中，除散热层3、源电极1、漏电极2之外的图层，可基于需要进行设置。
另一具体实施例中，对于顶栅底接触的有机TFT柔性背板，为了提升图像显示质量、减少阵列背板漏电，一般需要对TFT结构的半导体层进行图形化。举例来说，对于沉积好的有机半导体层(OSC)6和第一有机介电绝缘层(OGI)7，还可采用光刻、激光、等离子刻蚀等手段对有机半导体层6和第一有机介电绝缘层7进行图形化，减少非沟道区域的漏电(Ids)，然后再沉积第二有机介电绝缘层9，并在第二有机介电绝缘层9之上形成栅电极8、平坦层等图层(未示出)。该薄膜晶体管的结构图可如图3所示。
本公开实施例所提供的薄膜晶体管，具体还可以包括：
位于第一有机介电绝缘层7之上的第二有机介电绝缘层9，栅电极8形成于所述第二有机介电绝缘层9之上。
本公开实施例还提供了一种薄膜晶体管制作方法，该薄膜晶体管包括同层设置的源电极1图案和漏电极2图案。
该方法还包括：在源电极1图案和漏电极2图案之间制作散热层3图案，散热层3具有预设导电率。
在一具体实施例中，所述方法在制作散热层3图案之前还包括：
在衬底基板4之上制作缓冲层5图案；
在缓冲层5图案之上制作源电极1图案和漏电极2图案。
在一具体实施例中，所述方法还包括：
在散热层3顶部表面涂覆疏水性有机膜层；或者
对散热层3顶部表面进行等离子体处理。
在一具体实施例中，所述方法还包括：
在源电极1图案、漏电极2图案以及散热层3图案之上制作有机半导体层6图案；
在有机半导体层图案6之上制作第一有机介电绝缘层图案7；
在第一有机介电绝缘层图案7之上制作栅电极层8图案。
下面，以顶栅底接触型薄膜晶体管为例，对本公开实施例提供的薄膜晶体管制作方法的一个具体实施例进行详细的描述。
1、在柔性或者硬性的衬底基板4上沉积低应力、绝缘的缓冲层5图案。
本公开实施例中，并不限制该缓冲层5图案的制备过程，具体可采用任意成熟的制作工艺制备该缓冲层5图案，例如，使用但不局限于光刻、印刷、打印、金属掩模板(shadow mask)蒸镀等方法中的某一种或几种。
此时薄膜晶体管的结构示意图可如图4所示。
2、制备图形化的源电极1以及漏电极2图案。
此时薄膜晶体管的结构示意图可如附图5所示。
3、使用但不局限于喷墨印刷(inkjet)、甩涂(drop cast)、旋涂(spincoat)等的溶液加工方法，将混合均匀的碳纳米管、单体或低聚物、引发剂、掺杂剂等(或者其他可以形成高分子碳纳米管复合材料的物质)的溶液，沉积于 薄膜晶体管的沟道区内，即源电极1与漏电极2图案之间。使用紫外光或者其他热源对溶液进行照射，引发聚合相分离(即分离阶段)，最终形成由绝缘的高分子以及导热的碳纳米管复合而成的高分子碳纳米管复合材料膜层，即散热层3。
此时薄膜晶体管的结构示意图可如图6所示。
4、依次制作有机半导体层6(OSC)以及第一有机介电绝缘层图案7(OGI)。
5、制作栅电极层8图案。
最终形成如图2所示的薄膜晶体管。
另外，在另一具体实施例中，本公开实施例所提供的薄膜晶体管制作方法，还可以在制作栅电极层8图案之前，在已有的薄膜晶体管结构之上(例如有机半导体层6以及第一有机介电绝缘层图案7，制作第二有机介电绝缘层图案9，然后在制作栅电极层8图案，最终形成如图3所示的薄膜晶体管结构。
本公开实施例还提供了一种显示基板，该显示基板具体可以包括上述本公开实施例提供的薄膜晶体管。
本公开实施例还提供了一种显示装置，该显示装置具体可以包括上述本公开实施例提供的显示基板。
以上所述仅是本公开的实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (17)

  1. 一种薄膜晶体管，包括同层设置的源电极图案和漏电极图案，其中，所述薄膜晶体管还包括：
    设置于所述源电极图案和漏电极图案之间的散热层。
  2. 如权利要求1所述的薄膜晶体管，其中，所述散热层为高分子碳纳米管复合材料。
  3. 如权利要求2所述的薄膜晶体管，其中，所述高分子碳纳米管复合材料为绝缘材料。
  4. 如权利要求1所述的薄膜晶体管，其中，所述散热层顶部表面涂覆有疏水性有机膜层；或者
    所述散热层顶部表面经过等离子体处理。
  5. 如权利要求1所述的薄膜晶体管，还包括：
    衬底基板；
    形成于衬底基板之上的缓冲层；其中
    所述源电极图案、漏电极图案以及散热层位于所述缓冲层之上。
  6. 如权利要求1所述的薄膜晶体管，还包括：
    位于所述源电极图案、漏电极图案以及散热层之上的有机半导体层；
    位于所述有机半导体层之上的第一有机介电绝缘层；
    位于所述第一有机介电绝缘层之上的栅电极层。
  7. 如权利要求6所述的薄膜晶体管，还包括：
    位于所述第一有机介电绝缘层与所述栅电极层之间的第二有机介电绝缘层。
  8. 如权利要求2所述的薄膜晶体管，其中，
    所述高分子碳纳米管复合材料为在绝缘的高分子基体中不均匀或者均匀分布的孔道内填充由相分离作用而聚集的碳纳米管所形成的材料。
  9. 一种薄膜晶体管制作方法，所述薄膜晶体管包括同层设置的源电极图案和漏电极图案，其中，所述方法包括：
    在所述源电极图案和漏电极图案之间制作具有预设导电率散热层图案。
  10. 如权利要求9所述的方法，其中，所述散热层为高分子碳纳米管复合材料。
  11. 如权利要求10所述的方法，其中，
    所述高分子碳纳米管复合材料为在绝缘的高分子基体中不均匀或者均匀分布的孔道内填充由相分离作用而聚集的碳纳米管所形成的材料。
  12. 如权利要求9所述的方法，还包括：
    在所述散热层顶部表面涂覆疏水性有机膜层；或者
    对散热层顶部表面进行等离子体处理。
  13. 如权利要求9所述的方法，其中，所述方法在制作散热层图案之前还包括：
    在衬底基板之上制作缓冲层图案；
    在所述缓冲层图案之上制作源电极图案和漏电极图案。
  14. 如权利要求9所述的方法，还包括：
    在所述源电极图案、漏电极图案以及散热层图案之上制作有机半导体层图案；
    在所述有机半导体层图案之上制作第一有机介电绝缘层图案；
    在所述第一有机介电绝缘层图案之上制作栅电极层图案。
  15. 如权利要求14所述的方法，其中，在制作所述栅电极层之前，所述方法还包括：
    在所述第一有机介电绝缘层图案之上制作第二有机介电绝缘层图案；其中，所述栅电极层图案形成于所述第二有机介电绝缘层之上。
  16. 一种显示基板，其中，包括权利要求1至8任一项所述薄膜晶体管。
  17. 一种显示装置，其中，包括权利要求16所述的显示基板。
PCT/CN2016/078424 2015-06-15 2016-04-05 薄膜晶体管及其制作方法、显示基板、显示装置 WO2016202050A1 (zh)

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