WO2016197502A1 - 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 - Google Patents

薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 Download PDF

Info

Publication number
WO2016197502A1
WO2016197502A1 PCT/CN2015/092206 CN2015092206W WO2016197502A1 WO 2016197502 A1 WO2016197502 A1 WO 2016197502A1 CN 2015092206 W CN2015092206 W CN 2015092206W WO 2016197502 A1 WO2016197502 A1 WO 2016197502A1
Authority
WO
WIPO (PCT)
Prior art keywords
active layer
drain
gate
source
patterning process
Prior art date
Application number
PCT/CN2015/092206
Other languages
English (en)
French (fr)
Inventor
杨维
刘翔
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP15885770.6A priority Critical patent/EP3306648B1/en
Priority to US15/300,362 priority patent/US10483296B2/en
Publication of WO2016197502A1 publication Critical patent/WO2016197502A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • At least one embodiment of the present invention is directed to a thin film transistor and a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device.
  • liquid crystal display devices and OLED (Organic Light Emitting Diode) display devices are two mainstream display products.
  • the liquid crystal display device controls the deflection of the liquid crystal molecules by utilizing the electric field between the pixel electrode and the common electrode, thereby controlling the light passing through the liquid crystal panel.
  • the pixel electrode and the common electrode may be disposed on the array substrate in the display device, or the pixel electrode may be disposed on the array substrate, and the common electrode may be disposed on the opposite substrate disposed opposite to the array substrate.
  • the OLED display device is displayed by controlling the light emission of the light-emitting layer between the anode and the cathode, and the anode, the cathode, and the light-emitting layer are located on the array substrate in the display device.
  • a plurality of thin film transistors are disposed on the array substrate, and the thin film transistor may include an amorphous silicon thin film transistor, a polysilicon thin film transistor, an oxide thin film transistor, or the like.
  • Embodiments of the present invention provide a thin film transistor, a method for fabricating the same, an array substrate, a method for fabricating the same, and a display device for reducing the number of masks used in the fabrication process of a thin film transistor or an array substrate, saving process flow, increasing throughput, and reducing Cost of production.
  • At least one embodiment of the present invention provides an array substrate including a thin film transistor on a substrate substrate, the thin film transistor including an active layer, a gate, and a source electrically connected to the active layer, respectively a drain, and a gate insulating layer between the gate and the active layer, the gate, the source, and the drain being formed in a same patterning process.
  • At least one embodiment of the present invention also provides a display device including the above array substrate.
  • At least one embodiment of the present invention also provides a thin film transistor including an active layer and a gate a source, a drain and a drain respectively electrically connected to the active layer, and a gate insulating layer between the gate and the active layer, the gate, the source, and the The drain is formed in the same patterning process.
  • At least one embodiment of the present invention also provides a method of fabricating a thin film transistor, the method comprising: forming an active layer, a gate, a source and a drain electrically connected to the active layer, respectively, and A gate insulating layer between the gate and the active layer such that the gate, the source, and the drain are formed in the same patterning process.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, the method comprising: forming a thin film transistor on a substrate; the thin film transistor being fabricated by the method of fabricating the thin film transistor.
  • 1a is a cross-sectional structural view of an array substrate having a bottom gate type thin film transistor
  • 1b is a schematic cross-sectional view of an array substrate having a top gate type thin film transistor
  • FIG. 2a and FIG. 2b are schematic cross-sectional structural views of an array substrate including a bottom gate type thin film transistor according to Embodiment 1 of the present invention
  • FIG. 3a is a cross-sectional structural view of a first signal line and a second signal line in Embodiment 1 of the present invention
  • 3b is a schematic top plan view of a first signal line and a second signal line according to Embodiment 1 of the present invention
  • FIG. 4 is a cross-sectional structural view of an array substrate having a top gate thin film transistor according to Embodiment 2 of the present invention.
  • FIG. 5 is a cross-sectional structural view of an array substrate having a top gate type thin film transistor according to Embodiment 3 of the present invention.
  • FIG. 6 is a cross-sectional view of an array substrate having a top gate thin film transistor according to Embodiment 4 of the present invention.
  • FIG. 7 is a cross-sectional structural view of a display device according to Embodiment 5 of the present invention.
  • FIG. 8a to FIG. 8c are schematic cross-sectional structural views of a substrate processed by each step in a first patterning process using a halftone mask according to Embodiment 8 of the present invention.
  • FIG. 8d is a schematic structural view showing ion implantation or plasma treatment of a substrate subjected to a first patterning process according to Embodiment 8 of the present invention.
  • Embodiment 8e is a cross-sectional structural view of a substrate subjected to a second patterning process in Embodiment 8 of the present invention.
  • Embodiment 8f is a cross-sectional structural view of a substrate subjected to a third patterning process in Embodiment 8 of the present invention.
  • FIG. 1a is a cross-sectional structural view of a pixel unit in an array substrate.
  • a thin film transistor 100, a first passivation layer 150, and a pixel electrode 160 are sequentially disposed on a base substrate 101.
  • the first passivation layer 150 covers the thin film transistor 100.
  • the thin film transistor 100 adopts a bottom gate structure, and includes a gate electrode 110, a gate insulating layer 120, an active layer 140, and a source electrode 131 and a drain electrode 132 respectively overlapping the active layer 140.
  • the thin film transistor 100 may be an oxide thin film transistor, and the active layer 110 included may be made of a metal oxide material such as IGZO (Indium Gallium Zinc Oxide).
  • the manufacturing process of the array substrate includes, for example, the following steps 1 to 6.
  • Step 1 forming a gate 110 and a plurality of gate lines on the base substrate 101 by a first patterning process (also referred to as a mask process, for example, including exposure, development, etching, etc.) (not shown in FIG. 1a) Out).
  • a first patterning process also referred to as a mask process, for example, including exposure, development, etching, etc.
  • Step 2 Through the second patterning process, the gate insulating layer 120 and the lead holes (not shown in FIG. 1a) are formed in the gate insulating layer 120.
  • the lead holes are used to realize the connection between the electrode driving lines and the driving IC, for example, the gate lines (i.e., the driving lines of the gate electrodes 110) are led to the driving ICs in the Pad (contact pad) region through their corresponding lead holes.
  • Step 3 An active layer 140 is formed on the gate insulating layer 120 by a third patterning process.
  • Step 4 Through the fourth patterning process, source 131 and drain 132 respectively overlapping the active layer 140, and a plurality of data lines (not shown in FIG. 1a) are formed.
  • Step 5 The first passivation layer 150 is formed by the fifth patterning process, and via holes exposing the drain electrode 132 and lead holes (not shown in FIG. 1a) are formed in the first passivation layer 150.
  • the lead holes are used to realize the connection between the electrode driving lines and the driving ICs, for example, the source driving lines and the drain driving lines are led to the corresponding driving ICs through the corresponding lead holes.
  • Step 6 The pixel electrode 160 is formed on the first passivation layer 150 by the sixth patterning process, and the pixel electrode 160 is connected to the drain electrode 132 through the via hole formed in the step 5.
  • FIG. 1b shows a pixel unit of an array substrate using an ADS (Advanced Superdimensional Field Switch) mode, and the thin film transistor 100 in the array substrate adopts a top gate structure as compared with the case shown in FIG. 1a, and
  • the array substrate further includes a second passivation layer 170 and a common electrode 180.
  • the first six patterning processes of the method for fabricating the array substrate shown in FIG. 1b are similar to the above steps 1 to 6, except that the order in which the gate insulating layer 120 and the gate electrode 110 are formed is in accordance with the structure of the top gate type thin film transistor. Adjust accordingly. Based on this, the method for fabricating the array substrate further includes the following steps.
  • Step 7 The second passivation layer 170 is formed by the seventh patterning process.
  • Step 8 Through the eighth patterning process, the common electrode 180 and the common electrode line connected thereto (not shown in Fig. 1b) are formed.
  • an array substrate including a transparent electrode for example, a pixel electrode
  • the patterning process ie, 6 masks are required
  • the fabrication of an array substrate comprising two transparent electrodes eg, pixel electrodes and common electrodes
  • the fabrication of an array substrate comprising two transparent electrodes generally requires at least eight patterning processes as described above (ie, eight masks are required) Board), which will greatly limit the production capacity of the production line.
  • Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device, which are formed by forming a gate, a source, and a drain of a thin film transistor in a patterning process, and FIG. 1a and FIG.
  • the number of masks used in the fabrication of the thin film transistor or the array substrate can be reduced, the process flow can be saved, the throughput can be increased, and the production cost can be reduced.
  • At least one embodiment of the present invention provides a thin film transistor including an active layer, a gate, a source and a drain electrically connected to the active layer, respectively, and a gate and an active layer
  • the gate insulating layer, the gate, the source and the drain are formed in the same patterning process.
  • At least one embodiment of the present invention provides an array substrate including a thin film transistor disposed on a base substrate, the thin film transistor including an active layer, a gate, and a source and a drain electrically connected to the active layer, respectively And a gate insulating layer between the gate and the active layer, the gate, the source and the drain are formed in the same patterning process.
  • the patterning process includes a process of forming a set pattern by using a mask, for example, including photoresist coating, photoresist exposure, photoresist development, etching a thin film layer by using a photoresist pattern, and the like. Steps; however, the embodiment is not limited thereto, and the patterning process may be other processes capable of forming a set pattern, for example, a set pattern may be formed by a 3D printing process.
  • the gate insulating layer may be disposed on the active layer, and the gate, the source and the drain are disposed on the gate insulating layer, that is, the top gate structure is adopted; or
  • the gate insulating layer may be disposed on the gate, the source and the drain, and the active layer is disposed on the gate insulating layer, that is, the bottom gate structure is adopted.
  • the array substrate provided by the embodiment of the invention is suitable for a liquid crystal display device, such as a liquid crystal display device of a display mode such as TN, VA, FFS, IPS, ADS, HADS, SADS. That is, the array substrate provided by the embodiment of the present invention may include a transparent electrode or two transparent electrodes, and the two transparent electrodes may be disposed in the same layer or in different layers. Of course, the array substrate provided by the embodiment of the present invention is also applicable to other types of display devices such as an OLED display device and an electronic paper display device.
  • the present embodiment provides a thin film transistor 200 and an array substrate 20, the array substrate 20 including a thin film transistor 200 and a cover film disposed on the base substrate 201.
  • the thin film transistor 200 includes an active layer 210, a gate 232, a source 231 and a drain 233 electrically connected to the active layer 210, respectively, and a gate insulating layer 220 between the gate 232 and the active layer 210.
  • the pole 232, the source 231 and the drain 233 are formed side by side in the same layering process (on the base substrate 201 as shown in FIGS.
  • the gate 232, the source 231, and the drain 233 is not limited to the case shown in FIGS. 2a and 2b, as long as the three can be formed by the same patterning process.
  • the array substrate provided in this embodiment can be used for a liquid crystal display device or an electronic paper display device.
  • the transparent electrode 243 can be a pixel electrode and electrically connected to the drain 233 of the thin film transistor 200, as shown in FIG. 2a and FIG. 2b.
  • the array substrate can be used for an OLED display device, and in this case, the transparent electrode 243 can be a cathode or an anode, and can be electrically connected to one of a source and a drain of the thin film transistor.
  • the transparent electrode 243 can be made of a material such as transparent metal oxide ITO (indium tin oxide), IGZO (indium gallium zinc oxide), or IZO (indium zinc oxide).
  • the array substrate is further provided with a plurality of gate lines and a plurality of data lines.
  • the gate, the source and the drain are formed in the same patterning process, in order to save the process, In the patterning process, gate lines and data lines can also be formed.
  • one of the gate line and the data line may be set As a continuous structure, the other is provided as a segment structure including a plurality of line portions, and a connection portion is provided at a position where the gate lines and the data lines intersect to connect adjacent line portions.
  • the array substrate further includes a plurality of first signal lines 235 extending in the first direction and a plurality of second signal lines 234 extending in the second direction.
  • the first signal line 235 includes a plurality of intermittently disposed linear portions 2351 and a connecting portion 2352 connecting adjacent linear portions 2351.
  • the linear portions 2351 and the connecting portion 2352 are disposed in different layers (the connecting portion 2352 may also be disposed in a line shape)
  • the portion 2351 and the second signal line 234 are below), and the linear portion 2351 and the second signal line 234 are disposed in the same layer.
  • the first signal line 235 may be a gate line, and the second signal line 234 is a data line; or, the first signal line 235 may be a data line, and the second signal line 234 may be a gate line.
  • the linear portion 2351 of the first signal line 235 and the second signal line 234 An insulating layer 270 is disposed thereon, and a connecting portion 2352 corresponding to the intersection of the first signal line 235 and the second signal line 234 is disposed on the insulating layer 270, and the connecting portion 2352 is connected to the adjacent line through the via hole in the insulating layer 270.
  • the insulating layer 270 may include one or more insulating layers depending on the film layer in which the connecting portion 2352 is located.
  • connection portion 2352 may be formed in the same patterning process as the transparent electrode 243, in which case the insulating layer 270 may include the gate insulating layer 220 and passivation as shown in FIGS. 2a and 2b. Layer 250.
  • the connecting portion 2352 can also be formed in the same patterning process as other conductive structures on the array substrate.
  • the transparent electrode 243 is a pixel electrode
  • the connection portion 2352 may also be formed in the same patterning process as the common electrode.
  • FIGS. 3a and 3b only a partial structure of the array substrate is shown in FIGS. 3a and 3b, and structures such as a gate, a source, a drain, and an active layer are not shown.
  • the source 231 and the drain 233 of the thin film transistor may be in contact with the active layer 210, respectively.
  • via holes 224 respectively corresponding to the source and drain electrodes 231 and 233 are disposed in the gate insulating layer 220, so that the active layer 210 formed on the gate insulating layer 220 can be formed.
  • the vias 224 are electrically connected to the source 231 and the drain 233, respectively.
  • the active layer 210 may also be directly overlapped on the source 231 and the drain 233, that is, the electrical connection between the active layer 210 and the source 231 and the drain 233 does not need to pass through the gate insulating layer 220. Hole, as shown in Figure 2b.
  • the gate electrode 232, the source electrode 231, and the drain electrode 233 of the thin film transistor may be made of a metal such as aluminum, molybdenum, titanium, copper, or the like, or an alloy thereof, and may have a single layer or a multilayer structure.
  • the active layer 210 of the thin film transistor 200 is in contact with the source 231 and the drain 233, respectively, and the source 231 and the drain 233 are made of a metal material, the active layer 210 may be made of amorphous silicon, polysilicon or metal oxide. And other semiconductor materials.
  • the gate insulating layer 220 and the passivation layer 250 may be formed using one or more of an insulating material such as an oxide of silicon, a nitride of silicon, an oxynitride of silicon, an oxide of aluminum, or an oxide of germanium.
  • an insulating material such as an oxide of silicon, a nitride of silicon, an oxynitride of silicon, an oxide of aluminum, or an oxide of germanium.
  • the thin film transistor 200 adopts a bottom gate structure, that is, the gate insulating layer 220 is disposed on the gate 232, the source 231 and the drain 233, and the active layer 210 is disposed on the gate insulating layer 220.
  • the gate electrode 232, the source electrode 231 and the drain electrode 233 are formed in the same patterning process, compared with the array substrate formed by at least six patterning processes (for example, the above steps 1 to 6) shown in FIG. 1a, A mask can be saved to increase productivity and reduce production costs.
  • the present embodiment provides a thin film transistor 200 and an array substrate 20.
  • the thin film transistor 200 adopts a top gate structure. That is, the gate insulating layer 220 is disposed on the active layer 210, and the gate 232, the source 231, and the drain 233 are disposed on the gate insulating layer 220.
  • lead holes corresponding to the driving lines of the gate electrode 232, the source electrode 231 and the drain electrode 233 may be disposed in the passivation layer 250. As shown in FIG. 4, the inner surface of the lead hole may be deposited. For example, the material of the pixel electrode is convenient for the lead. Of course, the lead holes corresponding to the driving lines of the gate 232 may also be disposed in the gate insulating layer 220.
  • the thin film transistor 200 and the array substrate 20 provided in FIG. 4 are described by taking only a top gate structure and the source 231 and the drain 233 are respectively in contact with the active layer 210 through the via 224.
  • Embodiments of the invention include but are not limited thereto.
  • the source and the drain may also overlap with the active layer, for example, the orthographic projection of the gate insulating layer on the surface of the active layer may be located by providing a pattern of the gate insulating layer. A portion of the surface of the active layer is exposed in the active layer to expose the active layer to the source and drain.
  • FIG. 2b which is not shown in the drawing.
  • the gate, the source and the drain are formed in the same patterning process, and the gate and the source/drain are respectively formed by different patterning processes (ie, the array substrate is formed by at least six patterning processes). Compared with the method, it can save one patterning process, which saves a mask, increases productivity and reduces production costs.
  • the present embodiment provides a thin film transistor 200 and an array substrate 20.
  • the difference between this embodiment and the second embodiment is that in the array substrate 20, the gate insulating layer 220 and the gate 232, the source The electrode 231 and the drain 233 are formed in the same patterning process; and the array substrate 20 is an ADS type array substrate, that is, two transparent electrodes including different layers, and one of the two transparent electrodes is a pixel electrode. The other layer is a common electrode.
  • the pixel electrode may be located in the lower layer and the common electrode is located in the upper layer, or the pixel electrode may be located in the upper layer and the common electrode may be located in the lower layer.
  • only the pixel electrode 243 is disposed between the common electrode 280 and the base substrate 201 (ie, the pixel electrode is located in the lower layer and the common electrode is located
  • the upper layer is explained as an example.
  • the gate insulating layer 220 is formed in the same patterning process as the gate 232, the source 231, and the drain 233, the gate is in a direction substantially parallel to the plane of the substrate 201. 232.
  • the source 231 and the drain 233 may be substantially equal in width to their corresponding gate insulating layers, respectively.
  • the gate insulating layer 220 may include a first insulating portion 221 , a second insulating portion 222 , and a third insulating portion 223 disposed at intervals; the first insulating portion 221 is located at the source 231 and the active layer 210 The second insulating portion 222 is located between the gate 232 and the active layer 210; the third insulating portion 223 is located between the drain 233 and the active layer 210.
  • the gate insulating layer 220 is formed in the same patterning process as the gate 232, the source 231, and the drain 233, the source 231 and the drain 233 cannot pass through the via holes in the gate insulating layer 220 and the active layer 210, respectively.
  • the electrical connection cannot be directly overlapped on the active layer 210. Therefore, in this case, the source 231 and the drain can be made by providing a conductive structure after forming the gate 232, the source 231, and the drain 233.
  • the poles 233 are electrically connected to the active layer 210, respectively.
  • the source electrode 231 and the active layer 210 may be electrically connected through the first conductive structure 241, for example, the first conductive structure 241 may be on the upper surface 231a of the source 231 and the portion of the active layer 210.
  • the surface 210a is in contact;
  • the drain electrode 233 is electrically connected to the active layer 210 through the second conductive structure 242.
  • the second conductive structure 242 may be in contact with the upper surface 233a of the drain electrode 233 and the other portion upper surface 210b of the active layer 210.
  • a first opening 321 is disposed between the first insulating portion 221 and the second insulating portion 222, and a second opening 322 is disposed between the second insulating portion 222 and the third insulating portion 223.
  • the first conductive structure 241 is disposed.
  • the second conductive structure 242 may be in contact with the upper surface of the corresponding first opening 321 of the active layer 210, and the second conductive structure 242 may be in contact with the upper surface of the corresponding second opening 322 of the active layer 210.
  • embodiments of the invention are not limited thereto.
  • the first conductive structure 241 and the second conductive structure 242 are along a thickness substantially perpendicular to the direction of the substrate 201. It is smaller than the film thickness of the gate insulating layer 220 (for example, the second insulating portion 222).
  • the first conductive structure 241 and the second conductive structure 242 may be formed in the same patterning process as the original conductive structure on the array substrate to save the process.
  • the first conductive structure 241, the second conductive structure 242, and the pixel electrode 243 may be disposed in the same layer and the materials are the same (ie, formed using materials of the same film layer), so that they may be formed in the same patterning process.
  • the second conductive structure 242 and the pixel electrode 243 are both connected to the drain 233 of the thin film transistor 200, the second conductive structure 242 and the pixel electrode 243 may be integrally formed.
  • the material of the active layer 210 may be a metal oxide semiconductor material
  • the material of the active layer 210 Before forming the first conductive structure 241 and the second conductive structure 242, at a position of the active layer 210 to be in contact with the first conductive structure 241 and the second conductive structure 242 (for example, the first opening 321 shown in FIG. 5 and An ion implantation or a plasma process is performed at a position corresponding to the second opening 322 to form an ohmic contact between the active layer 210 and the first conductive structure 241 and the second conductive structure 242, respectively. Good electrical connection.
  • the lead holes corresponding to the driving lines of the gate electrode 232, the source electrode 231, and the drain electrode 233 may be formed in the passivation layer 250 between the pixel electrode 243 and the common electrode 280, respectively.
  • the arrangement of the gate lines and the data lines on the array substrate can also be adopted in the first embodiment, that is, one of the gate lines and the data lines is continuously disposed, and the other portion is disposed and connected to the respective segments through the connection portion.
  • the first signal line includes a plurality of spaced apart linear portions and a connecting portion connecting the adjacent linear portions, and the linear portions of the first signal lines are disposed in the same layer as the second signal lines; the connection portion of the first signal lines It may be formed in the same patterning process as the common electrode 280 shown in FIG. 5, and the adjacent linear portions are connected through via holes in the passivation layer 250.
  • the first signal line may be a gate line, and the second signal line is a data line; or, the first signal line may be a data line, and the second signal line may be a gate line.
  • connection portion of the first signal line may also be formed in the same patterning process as other conductive structures on the array substrate. I will not repeat them here.
  • the gate insulating layer, the gate electrode, the source electrode and the drain electrode are simultaneously formed by one patterning process, and at least two masks can be reduced compared with the case where the array substrate shown in FIG. 1b requires three patterning processes to form the above structure. Board to further increase production capacity and reduce production costs.
  • the drain electrode 233 is disposed between the active layer 210 and the metal/semiconductor under the source/drain electrodes to form an electron layer when the source/drain respectively have signal input, thereby effectively opening the thin film transistor. State current, improving the performance of thin film transistors.
  • the first conductive structure 241 connecting the source electrode 231 and the active layer 210 and the connection between the drain electrode 233 and the active layer 210 may be formed by a separate patterning process.
  • the thin film transistor can be reduced once more than the thin film transistor 100 included in the array substrate shown in FIG. 1b.
  • the patterning process saves a mask.
  • the present embodiment provides a thin film transistor 200 and an array substrate 20 .
  • the difference between this embodiment and the third embodiment is that the active layer 210 , the gate insulating layer 220 , the gate 232 , and the source 231 .
  • the drain 233 is formed by the same patterning process (for example, using a halftone mask).
  • the gate insulating layer 220 is formed in the same patterning process as the gate 232, the source 231, and the drain 233, the gate is in a direction substantially parallel to the plane of the substrate 201. 232.
  • the source 231 and the drain 233 are respectively substantially equal in width to their corresponding gate insulating layers (see Embodiment 3, and details are not described herein again).
  • the width of the gate insulating layer 220 and the width of the active layer 210 are substantially parallel to the direction of the substrate 201. Almost equal.
  • the gate insulating layer 220 may include a first insulating portion 221 , a second insulating portion 222 , and a third insulating portion 223 .
  • the first insulating portion 221 and the second insulating portion 222 are disposed with a first opening 321 .
  • a second opening 322 is disposed between the second insulating portion 222 and the third insulating portion 223; in a direction parallel to the base substrate 201, the width of the active layer 210 is substantially equal to the first insulating portion 221, the first opening 321, The sum of the widths of the second insulating portion 222, the second opening 322, and the third insulating portion 223.
  • the active layer, the gate insulating layer, the gate, the source and the drain in this embodiment are formed by one patterning process, and the patterning process shown in FIG. 1b can be reduced by at least three times, that is, at least three times.
  • the mask is used to effectively increase productivity and reduce production costs.
  • first insulating portion 221 is disposed between the source electrode 231 and the active layer 210
  • a third insulating portion 223 is disposed between the drain electrode 233 and the active layer 210, and when the source/drain respectively have signal input , The metal oxide semiconductor under the source/drain can form an electron layer, thereby effectively increasing the on-state current of the thin film transistor.
  • the first conductive structure 241 connecting the source electrode 231 and the active layer 210 and the connection between the drain electrode 233 and the active layer 210 may be formed by a separate patterning process.
  • the thin film transistor is in phase with the thin film transistor 100 included in the array substrate shown in FIG. 1b. Compared, it is still possible to reduce the number of two patterning processes, thereby saving two masks.
  • This embodiment provides a display device including the array substrate provided by any of the above embodiments.
  • the display device may include an array substrate 20 and a counter substrate 30 , and the array substrate 20 and the opposite substrate 30 are opposed to each other and pass the frame sealant. 35 to form a liquid crystal cell in which the liquid crystal material 40 is filled.
  • the counter substrate 30 is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate 20 is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the display device further includes a backlight 50 that provides backlighting for the array substrate 20.
  • the display device provided in this embodiment may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • At least one embodiment of the present invention also provides a method of fabricating a thin film transistor, the method comprising: forming an active layer, a gate, a source and a drain electrically connected to the active layer, and a gate and A gate insulating layer between the source layers such that the gate, source and drain are formed in the same patterning process.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, the method comprising: forming a thin film transistor on a substrate, the thin film transistor being fabricated by using the thin film transistor provided in the above embodiment.
  • the present embodiment provides a method for fabricating a corresponding array substrate. Taking the situation shown in FIG. 4 as an example, the method may include the following steps S41-S45, which are described one by one below.
  • Step S41 The active layer 210 is formed on the base substrate 201 by a first patterning process (also referred to as a mask process, for example, including exposure, development, etching, etc.).
  • a first patterning process also referred to as a mask process, for example, including exposure, development, etching, etc.
  • Step S42 forming a gate insulating layer 220 on the active layer 210 by a second patterning process, and forming an exposed portion at a position of the gate insulating layer 220 corresponding to the source 231 and the drain 233 to be formed, respectively. Via 224 of source layer 210.
  • Step S43 forming a source 231, a gate 232, a drain 233, a line portion of the first signal line, and a second signal line on the gate insulating layer 220 through the third patterning process, so that the source 231 and the drain
  • the poles 233 are electrically connected to the active layer 210 through via holes formed in step S42, respectively.
  • one of the first signal line and the second signal line is a gate line, and the other is a data line, and the first signal line and the second signal line are not shown in FIG.
  • Step S44 forming a passivation layer 250 by a fourth patterning process, and forming a first via hole exposing the drain electrode 233 and a second via hole exposing the line portion of the first signal line in the passivation layer 250 (not shown in Figure 4), and lead holes.
  • the lead holes are used to realize the connection between the electrode driving lines and the corresponding driving ICs.
  • the above-mentioned lead holes may include driving lines corresponding to the gate electrodes 232, driving lines of the source electrodes 231, and driving of the drain electrodes 233, respectively.
  • the lead hole of the wire may include driving lines corresponding to the gate electrodes 232, driving lines of the source electrodes 231, and driving of the drain electrodes 233, respectively.
  • the lead holes in FIG. 4 are only illustrative examples of the embodiment.
  • the lead holes are disposed in the Pad region of the array substrate, and the thin film transistors of the pixel regions do not correspond to the lead holes.
  • Step S45 forming a transparent electrode 243 and a connection portion of the first signal line on the passivation layer 250 through the fifth patterning process, so that the transparent electrode 243 is electrically connected to the drain electrode 233 through the first via hole formed in step S44. And the connection portion of the first signal line is connected to the adjacent linear portion through the second via hole formed in step S44.
  • the material of the transparent electrode 243 can also cover the inner surface of the lead hole as shown in FIG. 4, which facilitates the setting of the lead.
  • the present embodiment provides a thin film transistor.
  • the method shown in FIG. 4 may include the above steps S41 and S42 in the embodiment, and the source 231 and the gate are formed on the gate insulating layer 220 by the third patterning process.
  • the pole 232 and the drain 233 are such that the source 231 and the drain 233 are electrically connected to the active layer 210 through the via 224 formed in step S42, respectively.
  • the active layer 210 is formed by the first patterning process; the gate insulating layer 220 is formed on the active layer 210 by the second patterning process, and the corresponding source 231 and the drain of the gate insulating layer 220 are respectively A via 224 exposing the active layer 210 is formed at a position of the pole 233; and a source 231, a gate 232, and a drain 233 are formed on the gate insulating layer 220 by a third patterning process, so that the source 231 and The drain electrodes 233 are electrically connected to the active layer through via holes, respectively.
  • the pattern of the gate insulating layer may be disposed to expose the source.
  • the surface of the drain and drain so that the source and drain overlap the active layer. I will not repeat them here.
  • the method for fabricating the array substrate and the method for fabricating the thin film transistor provided by the embodiment can reduce the patterning process once.
  • the fabrication method of the array substrate 20/thin film transistor 200 shown in FIG. 2a provided in the first embodiment is similar to the fabrication method provided in this embodiment, except that the steps of forming the active layer are in forming the source, the gate and the drain.
  • the step of the pole and the step of forming the gate insulating layer That is, the method for fabricating the array substrate 20/thin film transistor 200 as shown in FIG.
  • the second patterning process Forming a gate insulating layer 220, and forming via holes 224 exposing the source 231 and the drain 233, respectively, at positions corresponding to the source 231 and the drain 233 of the gate insulating layer 220; through the third patterning process,
  • the active layer 210 is formed on the gate insulating layer 220, and the active layer 220 is electrically connected to the source 231 and the drain 233 through the via 224, respectively.
  • the array substrate 20/thin film transistor 200 shown in FIG. 2b provided in the first embodiment is different from the method of fabricating the array substrate/thin film transistor 200 shown in FIG. 2a in that the step of forming the gate insulating layer 220 is not A via 224 is formed in the gate insulating layer 220, but a pattern of the gate insulating layer 220 is disposed to expose the surfaces of the source 231 and the drain 233 to facilitate electrical connection with the active layer 210.
  • the embodiment provides a method for fabricating an array substrate, which comprises: forming a gate insulating layer and a gate of a thin film transistor by using one patterning process; a source and a drain; and a pixel electrode electrically connected to the drain and a common electrode disposed in a different layer from the pixel electrode.
  • Forming a first conductive structure electrically connecting the source and the active layer, and a second conductive structure electrically connecting the drain and the active layer for example, forming an upper surface with the source while forming the pixel electrode or the common electrode a first conductive structure in contact with an upper surface of the active layer, and a second conductive structure in contact with an upper surface of the drain and an upper surface of the active layer.
  • the upper surface of the active layer to be in contact with the first conductive structure and the second conductive structure is subjected to ion implantation or plasma treatment before forming the first conductive structure and the second conductive structure.
  • the array substrate 20 includes a pixel electrode 243 and a common electrode 280.
  • the first conductive structure 241 and the second conductive structure 242 shown in FIG. 5 are disposed in the same layer as the pixel electrode 243.
  • the method for fabricating the provided array substrate may include the following steps S51-S55, which are described one by one below.
  • Step S51 The active layer 210 is formed on the base substrate 201 by the first patterning process.
  • Step S52 forming a gate insulating layer 220 on the active layer 210 and a gate 232, a source 231, a drain 233, and a line of the first signal line disposed on the gate insulating layer 220 by a second patterning process. And a second signal line; and a surface of the active layer 210 to be in contact with the first conductive structure 241 and the second conductive structure 242 (eg, a portion of the upper surfaces 210a and 210b of the active layer 210 in FIG. 5) Ion implantation or plasma treatment is performed to improve the electrical conductivity of the surface.
  • the gate insulating layer 220 includes a first insulating portion 221 corresponding to the source electrode 231, a second insulating portion 222 corresponding to the gate electrode 232, and a third insulating portion 223 corresponding to the drain electrode 233; and, along substantially parallel to In the direction of the base substrate, each electrode has the same width as its corresponding insulating portion.
  • one of the first signal line and the second signal line is a gate line, and the other is a data line, and the line portion and the second signal line of the first signal line are not shown in FIG.
  • Step S53 forming a pixel electrode 243, a first conductive structure 241 connecting the source electrode 231 and the active layer 210, and a second conductive structure 242 connecting the drain electrode 233 and the active layer 210 by a third patterning process.
  • a part of the pixel electrode material is etched away to insulate each of the wires (for example, the linear portion of the first signal line and the second signal line) from each other.
  • the pixel electrode material at the intersection of the first signal line and the second signal line is etched away to insulate between the linear portions of the first signal line and between the linear portion and the second signal line. Since the etching rate of the etching liquid for etching the pixel electrode material is very slow to the metal material, the line portion and the first portion of the etching to the first signal line can be ignored in the normal process. The influence of the two signal lines.
  • the pixel electrode 243 and the second conductive structure 242 may be integrally formed and located on both sides of the drain 233, respectively.
  • Step S54 forming a passivation layer 250 by a fourth patterning process, and forming a via hole and a lead hole exposing the linear portion of the first signal line in the passivation layer 250 (as described in Embodiment 6, here) No longer).
  • Step S55 forming a common electrode 280 and a common electrode line connected thereto and a connection portion of the first signal line on the passivation layer 250 by the fifth patterning process, so that the connection portion of the first signal line is formed in step S54.
  • the vias connect adjacent linear portions.
  • the material forming the common electrode 280 may also cover the inner surface of the lead hole formed in step S54 to facilitate the provision of the lead.
  • the embodiment further provides a method for fabricating the thin film transistor 200 as shown in FIG. 5, the method comprising: forming the active layer 210 by a first patterning process; and the active layer 210 by a second patterning process.
  • the surface in contact with the first conductive structure 241 and the second conductive structure 242 is subjected to ion implantation or plasma treatment to improve electrical conductivity at the place; and the third connection patterning process is performed to form the electrical connection source 231 and the active layer 210
  • the first conductive structure 241 and the second conductive structure 242 electrically connecting the drain 233 and the active layer 210.
  • the first conductive structure and the second conductive structure may be fabricated by separately forming a conductive layer (for example, a metal layer).
  • the embodiment provides a method for fabricating an array substrate, which comprises: forming an active layer, a gate insulating layer, a gate, a source, and a drain of a thin film transistor by using one patterning process. And forming a pixel electrode electrically connected to the drain and a common electrode disposed in a different layer from the pixel electrode.
  • first conductive structure electrically connecting the source and the active layer, and a second conductive structure electrically connecting the drain and the active layer for example, forming an upper surface with the source while forming the pixel electrode or the common electrode a first conductive structure in contact with an upper surface of the active layer, and a second conductive structure in contact with an upper surface of the drain and an upper surface of the active layer.
  • the array substrate 20 includes a pixel electrode 243 and a common electrode 280.
  • the first conductive structure 241 and the second conductive structure 242 shown in FIG. 6 are disposed in the same layer as the pixel electrode 243.
  • the method for fabricating the provided array substrate may include the following steps S61-S64, which are described one by one below.
  • Step S61 forming an active layer 210, a gate insulating layer 220, a gate electrode 232, a source electrode 231, a drain electrode 233, a line portion of the first signal line, and a portion on the base substrate 201 by a first patterning process. And two surfaces of the active layer 210 to be in contact with the first conductive structure 241 and the second conductive structure 242 are ion-implanted or plasma-treated to improve the conductive properties of the surface.
  • the first patterning process may employ a halftone mask, as described in the following steps S611 to S614, which will be described below in connection with Figs. 8a to 8c.
  • Step S611 sequentially depositing a metal oxide semiconductor film, a gate insulating layer film, and a metal film on the base substrate 201, and coating a metal film on the metal film.
  • Step S612 performing exposure using a half-tone mask, then performing development, and etching the metal film, the gate insulating layer film, and the metal oxide semiconductor film without photoresist protection to obtain The substrate shown in Figure 8a.
  • the halftone mask includes a non-exposed area, a partially exposed area, and a fully exposed area, as shown in Figure 8a, with the fully exposed areas (not shown in Figure 8a) on either side of the non-exposed areas.
  • the non-exposed area corresponds to a gate, a source, a drain, a line portion of the first signal line, and a second signal line to be formed;
  • the partially exposed area corresponds to the first opening and the second opening to be formed; the remaining part is Fully exposed area.
  • the photoresist in the fully exposed region is removed, and the portions of the metal film, the gate insulating film, and the corresponding fully exposed regions of the metal oxide semiconductor film are etched away without photoresist protection, and the rest Some are retained.
  • the active layer 210, the etched gate insulating film 220', the etched metal film 230, and the photoresist 300 covering the metal film 230 may be formed.
  • Step S613 The photoresist 300 is subjected to ashing treatment to obtain a substrate as shown in Fig. 8b. At this time, the ashed photoresist 300' covers a part of the metal thin film 230.
  • Step S614 etching away the metal film 230 and the gate insulating layer which are not protected by the photoresist 300'
  • the film 220' retains the portion of the active layer 210 that is not protected by the photoresist 300', thereby obtaining a substrate as shown in Fig. 8c.
  • the gate 232, the source 231 and the drain 233 are coplanar, the first signal line and the second signal line;
  • the gate insulating film 220' is formed to include the first insulating portion 221, a second insulating portion 222 and a gate insulating layer of the third insulating portion 223; and a first opening 321 and a second opening 322 exposing the active layer 210 are formed in the gate insulating layer.
  • step S615 is performed: as shown in FIG. 8d, ion implantation or plasma treatment is performed on the surfaces of the corresponding first opening 321 and the second opening 322 of the active layer to reduce the Contact resistance.
  • the source 231, the gate 232, and the drain 233 are respectively substantially equal in width to the corresponding insulating portion in a direction substantially parallel to the substrate; in a direction substantially parallel to the substrate 201,
  • the width of the gate insulating layer is substantially equal to the width of the active layer 210, that is, the sum of the widths of the first insulating portion 221, the first opening 321, the second insulating portion 222, the second opening 322, and the third insulating portion 223
  • the width of the source layers is approximately equal.
  • one of the first signal line and the second signal line is a gate line, and the other is a data line, and the line portion of the first signal line and the second signal line are not shown in FIGS. 8a to 8d.
  • Step S62 forming a pixel electrode 243 by a second patterning process, connecting the source electrode 231 and the active layer 210 through the first conductive structure 241, and connecting the drain electrode 233 and the active layer 210 through the second conductive structure 242 to form a conductive
  • the channel for example, results in a substrate as shown in Figure 8e.
  • a part of the pixel electrode material is etched away to insulate each of the wires (for example, the linear portion of the first signal line and the second signal line) from each other.
  • the pixel electrode material at the intersection of the first signal line and the second signal line is etched away to insulate between the linear portions of the first signal line and between the linear portion and the second signal line. Since the etching rate of the etching liquid for etching the pixel electrode material to the metal material is very slow, the influence of the etching on the linear portion and the second signal line of the first signal line can be ignored.
  • the pixel electrode 243 and the second conductive structure 242 may be integrally formed and located on both sides of the drain 233, respectively.
  • Step S63 forming a passivation layer 250 by a third patterning process, and forming a via hole exposing the linear portion of the first signal line and a lead hole in the passivation layer 250 (as described in Embodiment 6 No further details are given), for example, a substrate as shown in Fig. 8f is obtained.
  • Step S64 forming a common electrode 280 and a common electrode line connected thereto and a connection portion of the first signal line on the passivation layer 250 through the fourth patterning process, so that the connection portion of the first signal line
  • the adjacent linear portions are connected by the via holes formed in step S63 to obtain a substrate as shown in FIG.
  • the material of the common electrode 280 may also cover the inner surface of the lead hole formed in step S63, which facilitates the setting of the lead.
  • the active layer, the gate insulating layer, the gate, and the source/drain of the thin film transistor are formed by using one patterning process, and the source/drain and the active layer are connected by a material forming the pixel electrode to form a conductive
  • the channel can reduce the number of masking processes by three times compared with the case shown in FIG. 1b, thereby effectively reducing the number of masks, increasing productivity, and saving cost; and, when the source/drain have signal input, the source
  • the metal oxide semiconductor material under the drain can also form an electron layer, which can effectively increase the on-state current of the thin film transistor, thereby improving the performance of the thin film transistor.
  • the embodiment further provides a method for fabricating the thin film transistor 200 as shown in FIG. 6, which may include: forming an active through a first patterning process (for example, using a halftone mask, see step S61 above) a layer 210, a gate insulating layer 220, a gate 232, a source 231 and a drain 233; a surface of the active layer 210 not covered by the gate insulating layer 220 (ie, to be with the first conductive structure 241 and the second conductive
  • the surface to which the structures 242 are respectively contacted is subjected to ion implantation or plasma treatment to improve the electrical conductivity at the place; and, by the second patterning process, the first conductive structures 241 electrically connecting the source 231 and the active layer 210 are formed, and The drain 233 and the second conductive structure 242 of the active layer 210 are electrically connected.
  • the first conductive structure and the second conductive structure may be fabricated by separately forming a conductive layer (for example, a metal layer).
  • a metal common electrode line may be formed by using a material for forming a gate line, and the common electrode passes through A via hole in the insulating layer below it is electrically connected to the metal common electrode line, which can reduce the resistance of the common electrode. I will not repeat them here.
  • structures formed using the same film layer may be side by side on the same layer, as shown in Figures 2a, 2b, 4, 5, and 6 side by side.
  • the structure formed by the same film layer may also have a high and low undulating shape, such as the first conductive structure 241 and the second in FIGS. 5 and 6.
  • the conductive structure 242 and the pixel electrode 243 are shown.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种薄膜晶体管及其制作方法、阵列基板及其制作方法以及显示装置，该薄膜晶体管(200)的制作方法包括：形成有源层(210)、栅极(232)、分别与所述有源层(210)电连接的源极(231)和漏极(233)、以及位于所述栅极(232)和所述有源层(210)之间的栅极绝缘层(220)，使得所述栅极(232)、所述源极(231)和所述漏极(233)在同一次构图工艺中形成。该方法可以减少薄膜晶体管(200)或阵列基板(20)制作过程中掩膜板的使用数量，节省工艺流程，提高产能，降低生产成本。

Description

薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 技术领域
本发明的至少一个实施例涉及一种薄膜晶体管及其制作方法、阵列基板及其制作方法以及显示装置。
背景技术
在显示技术领域，液晶显示装置和OLED(有机发光二极管，Organic Light Emitting Diode)显示装置是两种主流的显示产品。
液晶显示装置通过利用像素电极和公共电极之间的电场控制液晶分子的偏转，进而控制通过液晶面板的光线。像素电极和公共电极可以都设置于显示装置中的阵列基板上，也可以是像素电极设置于阵列基板上，且公共电极设置于与阵列基板相对设置的对置基板上。
OLED显示装置通过控制阳极和阴极之间的发光层的发光进行显示，阳极、阴极和发光层位于显示装置中的阵列基板上。
无论是在液晶显示装置还是在OLED显示装置中，阵列基板上都设置有多个薄膜晶体管，该薄膜晶体管可以包括非晶硅薄膜晶体管、多晶硅薄膜晶体管或氧化物薄膜晶体管等。
发明内容
本发明实施例提供了一种薄膜晶体管及其制作方法、阵列基板及其制作方法以及显示装置，以减少薄膜晶体管或阵列基板制作过程中掩膜板的使用数量，节省工艺流程，提高产能，降低生产成本。
本发明的至少一个实施例提供了一种阵列基板，其包括位于衬底基板上的薄膜晶体管，所述薄膜晶体管包括有源层、栅极、分别与所述有源层电连接的源极和漏极、以及位于所述栅极和所述有源层之间的栅极绝缘层，所述栅极、所述源极和所述漏极在同一次构图工艺中形成。
本发明的至少一个实施例还提供了一种显示装置，其包括上述阵列基板。
本发明的至少一个实施例还提供了一种薄膜晶体管，其包括有源层、栅 极、分别与所述有源层电连接的源极和漏极、以及位于所述栅极和所述有源层之间的栅极绝缘层，所述栅极、所述源极和所述漏极在同一次构图工艺中形成。
本发明的至少一个实施例还提供了一种薄膜晶体管的制作方法，该方法包括：形成有源层、栅极、分别与所述有源层电连接的源极和漏极、以及位于所述栅极和所述有源层之间的栅极绝缘层，使得所述栅极、所述源极和所述漏极在同一次构图工艺中形成。
本发明的至少一个实施例提供了一种阵列基板的制作方法，该方法包括：在衬底基板上形成薄膜晶体管；所述薄膜晶体管采用上述薄膜晶体管的制作方法制作。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a为一种具有底栅型薄膜晶体管的阵列基板的剖视结构示意图；
图1b为一种具有顶栅型薄膜晶体管的阵列基板的剖视示意图；
图2a和图2b为本发明实施例一提供的包括底栅型薄膜晶体管的阵列基板的剖视结构示意图；
图3a为本发明实施例一中第一信号线和第二信号线的剖视结构示意图；
图3b为本发明实施例一中第一信号线和第二信号线的俯视示意图；
图4为本发明实施例二提供的具有顶栅型薄膜晶体管的阵列基板的剖视结构示意图；
图5为本发明实施例三提供的具有顶栅型薄膜晶体管的阵列基板的剖视结构示意图；
图6为本发明实施例四提供的具有顶栅型薄膜晶体管的阵列基板的剖视示意图；
图7为本发明实施例五提供的显示装置的剖视结构示意图；
图8a至图8c为本发明实施例八中采用半色调掩膜板进行第一次构图工艺过程中经过各步骤处理后的基板的剖视结构示意图；
图8d为本发明实施例八中对经过第一次构图工艺的基板进行离子注入或等离子体处理的结构示意图；
图8e为本发明实施例八中经过第二次构图工艺的基板的剖视结构示意图；
图8f为本发明实施例八中经过第三次构图工艺的基板的剖视结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1a为一种阵列基板中的一个像素单元的剖视结构示意图。如图1a所示，在衬底基板101上依次设置有薄膜晶体管100、第一钝化层150和像素电极160。第一钝化层150覆盖薄膜晶体管100。该薄膜晶体管100采用底栅结构，包括栅极110、栅极绝缘层120、有源层140以及分别与有源层140搭接的源极131和漏极132。薄膜晶体管100可以为氧化物薄膜晶体管，其包括的有源层110可以采用金属氧化物材料制作，例如IGZO(氧化铟镓锌)， 此时，该阵列基板的制作过程例如包括以下步骤1～步骤6。
步骤1：通过第一次构图工艺(也称为掩膜工艺，例如包括曝光、显影、刻蚀等步骤)，在衬底基板101上形成栅极110、多条栅线(图1a中未示出)。
步骤2：通过第二次构图工艺，形成栅极绝缘层120及位于栅极绝缘层120中的引线孔(图1a中未示出)。引线孔用于实现电极驱动线与驱动IC之间的连接，例如，栅线(即栅极110的驱动线)通过其对应的引线孔被引至Pad(接触垫)区域中的驱动IC上。
步骤3：通过第三次构图工艺，在栅极绝缘层120上形成有源层140。
步骤4：通过第四次构图工艺，形成分别与有源层140搭接的源极131和漏极132，以及多条数据线(图1a中未示出)。
步骤5：通过第五次构图工艺，形成第一钝化层150，并在第一钝化层150中形成暴露出漏极132的过孔以及引线孔(图1a中未示出)。引线孔用于实现电极驱动线与驱动IC之间的连接，例如，源极驱动线和漏极驱动线通过相应的引线孔被引至相应的驱动IC。
步骤6：通过第六次构图工艺，在第一钝化层150上形成像素电极160，使像素电极160通过步骤5中形成的过孔与漏极132连接。
图1b示出了一种采用ADS(高级超维场开关)模式的阵列基板的一个像素单元，与图1a所示的情形相比，该阵列基板中的薄膜晶体管100采用顶栅结构，并且该阵列基板还包括第二钝化层170以及公共电极180。图1b所示的阵列基板的制作方法的前六次构图工艺与上述步骤1至步骤6类似，不同之处在于栅极绝缘层120、栅极110的形成顺序根据顶栅型薄膜晶体管的结构进行相应调整。在此基础上，该阵列基板的制作方法还包括如下的步骤。
步骤7：通过第七次构图工艺，形成第二钝化层170。
步骤8：通过第八次构图工艺，形成公共电极180和与其连接的公共电极线(图1b中未示出)。
在研究中，本申请的发明人注意到，上述阵列基板的制作工艺较为复杂，制作如图1a所示的包括一层透明电极(例如像素电极)的阵列基板一般需要如上所述的至少六次构图工艺(即需要使用6张掩膜板)，而制作包括两层透明电极(例如像素电极和公共电极)的阵列基板一般需要如上所述的至少八次构图工艺(即需要使用8张掩膜板)，这会极大限制生产线的产能。
本发明实施例提供了一种薄膜晶体管及其制作方法、阵列基板及其制作方法以及显示装置，通过在一次构图工艺中形成薄膜晶体管的栅极、源极和漏极，与图1a和图1b中栅极和源/漏极通过不同的构图工艺形成的情形相比，可以减少薄膜晶体管或阵列基板制作过程中掩膜板的使用数量，节省工艺流程，提高产能，降低生产成本。
本发明的至少一个实施例提供了一种薄膜晶体管，该薄膜晶体管包括有源层、栅极、分别与有源层电连接的源极和漏极、以及位于栅极和有源层之间的栅极绝缘层，栅极、源极和漏极在同一次构图工艺中形成。
本发明的至少一个实施例提供了一种阵列基板，其包括设置于衬底基板上的薄膜晶体管，该薄膜晶体管包括有源层、栅极、分别与有源层电连接的源极和漏极、以及位于栅极和有源层之间的栅极绝缘层，栅极、源极和漏极在同一次构图工艺中形成。
在本发明实施例中，构图工艺包括通过利用掩膜板形成设定图案的工艺，例如包括光刻胶涂敷、光刻胶曝光、光刻胶显影、利用光刻胶图案刻蚀薄膜层等步骤；但实施方式不限于此，构图工艺还可以是其他的能够形成设定图案的工艺，例如可以通过3D打印工艺形成设定图案。
本发明实施例提供的薄膜晶体管和阵列基板中，栅极绝缘层可以设置于有源层上，并且栅极、源极和漏极设置于栅极绝缘层上，即采用顶栅结构；或者，栅极绝缘层可以设置于栅极、源极和漏极上，有源层设置于栅极绝缘层上，即采用底栅结构。
本发明实施例提供的阵列基板适用于液晶显示装置，例如TN、VA、FFS、IPS、ADS、HADS、SADS等显示模式的液晶显示装置。也就是说，本发明实施例提供的阵列基板可以包括一层透明电极，或者包括两层透明电极，并且，这两层透明电极可以同层设置或异层设置。当然，本发明实施例提供的阵列基板也适用于OLED显示装置、电子纸显示装置等其他类型显示装置。
下面结合实施例一至实施例四对本发明上述实施例提供的阵列基板以及薄膜晶体管进行详细说明。
实施例一
如图2a和图2b所示，本实施例提供了一种薄膜晶体管200和阵列基板20，该阵列基板20包括设置于衬底基板201上的薄膜晶体管200、覆盖薄膜 晶体管200的钝化层250以及设置于钝化层250上的透明电极243。薄膜晶体管200包括有源层210、栅极232、分别与有源层210电连接的源极231和漏极233、以及位于栅极232和有源层210之间的栅极绝缘层220，栅极232、源极231和漏极233因在同一次构图工艺中形成而并排位于同一层(如图2a和图2b所示的衬底基板201)上且材料相同，透明电极243与源极231和漏极233中的一个电连接。当然，栅极232、源极231和漏极233的设置方式并不限于图2a和图2b所示的情形，只要这三者可以通过同一次构图工艺形成即可。
本实施例提供的阵列基板可以用于液晶显示装置或电子纸显示装置，此时，透明电极243可以为像素电极，并且与薄膜晶体管200的漏极233电连接，如图2a和图2b所示；或者，该阵列基板可以用于OLED显示装置，此时，透明电极243可以为阴极或阳极，并且可以与薄膜晶体管的源极和漏极中的一个电连接。透明电极243可以采用透明的金属氧化物ITO(氧化铟锡)、IGZO(氧化铟镓锌)、IZO(氧化铟锌)等材料制作。
阵列基板上还设置有多条栅线和多条数据线，在本发明的一个实施例提供的阵列基板中，栅极、源极和漏极在同一次构图工艺中形成，为节省工艺，在该构图工艺中，还可以形成栅线和数据线。并且，由于栅线的延伸方向和数据线的延伸方向相交，例如，栅线横向延伸且数据线纵向延伸，所以为了使栅线和数据线彼此绝缘，可以将栅线和数据线中的一个设置为连续结构，另一个设置为包括多个线状部的分段结构，并在栅线和数据线相交的位置处设置连接部以连接相邻的线状部。
也就是说，在至少一个示例中，如图3a和图3b所示，阵列基板还包括多条沿第一方向延伸的第一信号线235和多条沿第二方向延伸的第二信号线234，第一信号线235包括多个间断设置的线状部2351以及连接相邻的线状部2351的连接部2352，线状部2351与连接部2352异层设置(连接部2352也可以设置在线状部2351和第二信号线234的下方)，并且线状部2351和第二信号线234同层设置。第一信号线235可以为栅线，并且第二信号线234为数据线；或者，第一信号线235可以为数据线，并且第二信号线234为栅线。
在图3a所示的情形中，第一信号线235的线状部2351和第二信号线234 上设置有绝缘层270，在绝缘层270上设置有对应第一信号线235和第二信号线234交叉处的连接部2352，连接部2352通过绝缘层270中的过孔连接相邻的线状部2351。根据连接部2352所在膜层的不同，绝缘层270可以包括一层或多层绝缘层。例如，为节省工艺，连接部2352可以与透明电极243在同一次构图工艺中形成，在这种情况下，绝缘层270可以包括如图2a和图2b所示的栅极绝缘层220和钝化层250。
当然，连接部2352也可以与阵列基板上的其他导电结构在同一次构图工艺中形成。例如，当阵列基板包括不同层设置的像素电极和公共电极时，上述透明电极243为像素电极，连接部2352还可以与公共电极在同一次构图工艺中形成。
需要说明的是，图3a和图3b中仅示出了阵列基板的部分结构，未示出栅极、源极、漏极和有源层等结构。
例如，薄膜晶体管的源极231和漏极233可以分别与有源层210接触。例如，如图2a所示，在栅极绝缘层220中设置有分别对应源极231和漏极233的过孔224，从而形成在栅极绝缘层220上的有源层210可以通过所形成的过孔224分别与源极231和漏极233电连接。此外，有源层210也可以直接搭接在源极231和漏极233上，即，有源层210与源极231和漏极233之间的电连接不需要通过栅绝缘层220中的过孔，如图2b所示。
在本实施例中，薄膜晶体管的栅极232、源极231和漏极233可以采用铝、钼、钛、铜等金属或其合金制作，并且可以为单层或多层结构。
由于薄膜晶体管200的有源层210分别与源极231和漏极233接触，并且源极231和漏极233采用金属材料制作，因而，有源层210可以采用非晶硅、多晶硅或金属氧化物等半导体材料制作。
栅极绝缘层220和钝化层250可以采用硅的氧化物、硅的氮化物、硅的氮氧化物、铝的氧化物、铪的氧化物等绝缘材料中的一种或多种制作。
本实施例提供的阵列基板20中，薄膜晶体管200采用底栅结构，即栅极绝缘层220设置于栅极232、源极231和漏极233上，有源层210设置于栅极绝缘层220上，由于栅极232、源极231和漏极233在同一次构图工艺中形成，与图1a所示的通过至少六次构图工艺(例如上述步骤1至步骤6)形成的阵列基板相比，可以节省一张掩膜板，从而提高产能，降低生产成本。
实施例二
如图4所示，本实施例提供了一种薄膜晶体管200和阵列基板20，本实施例与实施例一中的图2a所示的情形相比，区别在于：薄膜晶体管200采用顶栅结构，即栅极绝缘层220设置于有源层210上，栅极232、源极231和漏极233设置于栅极绝缘层220上。
由于薄膜晶体管200采用顶栅结构，栅极232、源极231和漏极233的驱动线分别对应的引线孔可以设置于钝化层250中，如图4所示，引线孔的内表面可沉积例如像素电极的材料以便于引线。当然，栅极232的驱动线对应的引线孔也可以设置在栅极绝缘层220中。
在本实施例中，栅线、数据线、透明电极、有源层等结构的设置可以参考实施例一中的相关描述，此处不再赘述。此外，图4提供的薄膜晶体管200和阵列基板20仅以采用顶栅结构且源极231和漏极233分别通过过孔224与有源层210接触为例进行说明。本发明实施例包括但不限于此。例如，采用顶栅结构时，源极和漏极还可以分别与有源层搭接，例如，可以通过设置栅极绝缘层的图案使栅极绝缘层在有源层所在面上的正投影位于有源层所在区域内且暴露出有源层的部分表面，以实现有源层与源极和漏极的搭接，对此，可参考图2b，附图中未示出。
在本实施例中，栅极、源极和漏极在同一次构图工艺中形成，与栅极与源/漏极分别通过不同的构图工艺形成的方式(即阵列基板至少通过六次构图工艺形成的方式)相比，可以节省一次构图工艺，从而节省一张掩膜板、提高产能并降低生产成本。
实施例三
如图5所示，本实施例提供了一种薄膜晶体管200和阵列基板20，本实施例与实施例二的区别在于：在该阵列基板20中，栅极绝缘层220与栅极232、源极231和漏极233在同一次构图工艺中形成；并且，该阵列基板20为ADS型阵列基板，即包括不同层设置的两层透明电极，这两层透明电极中的一层为像素电极，另一层为公共电极。
在本实施例中，可以是像素电极位于下层且公共电极位于上层，也可以是像素电极位于上层且公共电极位于下层。本实施例仅以像素电极243设置于公共电极280与衬底基板201之间(即像素电极位于下层且公共电极位于 上层)为例进行说明。
在本实施例中，由于栅极绝缘层220与栅极232、源极231和漏极233在同一次构图工艺中形成，因此，沿大致平行于衬底基板201所在平面的方向上，栅极232、源极231和漏极233可以分别与其对应的栅极绝缘层的宽度大致相等。
例如，如图5所示，栅极绝缘层220可以包括间隔设置的第一绝缘部221、第二绝缘部222以及第三绝缘部223；第一绝缘部221位于源极231和有源层210之间；第二绝缘部222位于栅极232与有源层210之间；第三绝缘部223位于漏极233与有源层210之间。
由于栅极绝缘层220与栅极232、源极231和漏极233在同一次构图工艺中形成，源极231和漏极233无法通过栅极绝缘层220中的过孔分别与有源层210电连接，也无法直接搭接在有源层210上，因此，在这种情况下，可以通过在形成栅极232、源极231和漏极233之后设置导电结构的方式使源极231和漏极233分别与有源层210电连接。
例如，如图5所示，源极231与有源层210可以通过第一导电结构241电连接，例如，第一导电结构241可以与源极231的上表面231a和有源层210的部分上表面210a接触；漏极233与有源层210通过第二导电结构242电连接，例如，第二导电结构242可以与漏极233的上表面233a和有源层210的另一部分上表面210b接触。图5仅以有源层210的与第一导电结构241接触的上表面位于源极231和栅极232之间且有源层210的与第二导电结构242接触的上表面位于栅极232和漏极233之间为例进行说明。本实施例包括，但不限于此，只要可以实现将源极231和漏极233分别与有源层210电连接即可。
在图5中，第一绝缘部221与第二绝缘部222之间设置有第一开口321，第二绝缘部222与第三绝缘部223之间设置有第二开口322，第一导电结构241可以与有源层210的对应第一开口321的上表面接触，第二导电结构242可以与有源层210的对应第二开口322的上表面接触。但本发明实施例不限于此。
为了避免第一导电结构241和第二导电结构242与栅极电连接，第一导电结构241和第二导电结构242沿大致垂直于衬底基板201方向的膜层厚度 小于栅极绝缘层220(例如第二绝缘部222)的膜层厚度。
第一导电结构241和第二导电结构242可以与阵列基板上原有的导电结构在同一次构图工艺中形成，以节省工艺。例如，第一导电结构241、第二导电结构242以及像素电极243可以同层设置且材料相同(即利用同一膜层的材料形成)，从而可以在同一次构图工艺中形成。
由于第二导电结构242和像素电极243都与薄膜晶体管200的漏极233连接，因此，第二导电结构242和像素电极243可以一体形成。
由于像素电极243通常采用金属氧化物材料制作，当第一导电结构241和第二导电结构242与像素电极243的材料相同时，有源层210的材料可以为金属氧化物半导体材料，并且，在形成第一导电结构241和第二导电结构242之前，可以在有源层210的待与第一导电结构241和第二导电结构242接触的位置处(例如图5所示的第一开口321和第二开口322对应的位置处)进行离子注入(ion implantation)或等离子体(Plasma)处理，以使有源层210分别与第一导电结构241和第二导电结构242之间形成欧姆接触从而实现良好的电连接。
在本实施例中，可以在像素电极243和公共电极280之间的钝化层250中形成栅极232、源极231和漏极233的驱动线分别对应的引线孔。
此外，阵列基板上的栅线和数据线的设置也可以采用实施例一中的方式，即，栅线和数据线中的一个连续设置，另一个分段设置并且通过连接部连接各段。例如，第一信号线包括多个间隔设置的线状部以及连接相邻线状部的连接部，第一信号线的线状部与第二信号线同层设置；第一信号线的连接部可以与图5所示的公共电极280在同一次构图工艺中形成，并通过钝化层250中的过孔连接相邻的线状部。第一信号线可以为栅线，并且第二信号线为数据线；或者，第一信号线可以为数据线，并且第二信号线为栅线。
当然，根据实际需要，第一信号线的连接部也可以与阵列基板上的其他导电结构在同一次构图工艺中形成。此处不做赘述。
本实施例通过一次构图工艺同时形成栅极绝缘层、栅极、源极和漏极，与图1b所示的阵列基板需要三次构图工艺形成上述结构的情形相比，可以至少减少两张掩膜板，从而进一步提高产能并降低生产成本。
此外，由于源极231和有源层210之间设置有第一绝缘部221，漏极233 和有源层210之间设置有第三绝缘部223，当源/漏极分别有信号输入的时候，源/漏极下方的金属氧化物半导体能形成电子层，从而能有效提升薄膜晶体管的开态电流，提高薄膜晶体管的性能。
本实施例提供的薄膜晶体管200脱离阵列基板20单独提供时，可通过单独的构图工艺形成连接源极231和有源层210的第一导电结构241以及连接漏极233和有源层210的第二导电结构242。在这种情况下，由于栅极232、源极231和漏极233在同一次构图工艺中形成，该薄膜晶体管与图1b所示的阵列基板中包括的薄膜晶体管100相比，仍然可以减少一次构图工艺，从而节省一张掩膜板。
实施例四
如图6所示，本实施例提供了一种薄膜晶体管200和阵列基板20，本实施例与实施例三的区别在于：有源层210、栅极绝缘层220、栅极232、源极231和漏极233通过同一次构图工艺(例如采用半色调掩膜板)形成。
在本实施例中，由于栅极绝缘层220与栅极232、源极231和漏极233在同一次构图工艺中形成，因此，沿大致平行于衬底基板201所在平面的方向上，栅极232、源极231和漏极233可以分别与其对应的栅极绝缘层的宽度大致相等(参见实施例三，此处不再赘述)。在此基础上，由于有源层210与栅极绝缘层220在该构图工艺中形成，因此，沿大致平行于衬底基板201的方向，栅极绝缘层220的宽度与有源层210的宽度大致相等。
例如，栅极绝缘层220可以包括间隔设置的第一绝缘部221、第二绝缘部222以及第三绝缘部223，第一绝缘部221和第二绝缘部222之间设置有第一开口321，第二绝缘部222和第三绝缘部223之间设置有第二开口322；沿平行于衬底基板201的方向上，有源层210的宽度大致等于第一绝缘部221、第一开口321、第二绝缘部222、第二开口322和第三绝缘部223的宽度之和。
本实施例中的有源层、栅极绝缘层、栅极、源极和漏极通过一次构图工艺形成，与图1b所示的阵列基板相比，可以至少减少三次构图工艺，即至少减少三张掩膜板，从而可以有效地提高产能并降低生产成本。
此外，由于源极231和有源层210之间设置有第一绝缘部221，漏极233和有源层210之间设置有第三绝缘部223，当源/漏极分别有信号输入的时候， 源/漏极下方的金属氧化物半导体能形成电子层，从而能有效提升薄膜晶体管的开态电流。
本实施例提供的薄膜晶体管200脱离阵列基板20单独提供时，可通过单独的构图工艺形成连接源极231和有源层210的第一导电结构241以及连接漏极233和有源层210的第二导电结构242。在这种情况下，由于栅极绝缘层220、栅极232、源极231和漏极233在同一次构图工艺中形成，该薄膜晶体管与图1b所示的阵列基板中包括的薄膜晶体管100相比，仍然可以减少两次构图工艺，从而节省两张掩膜板。
本实施例中的栅线、数据线、薄膜晶体管、像素电极、公共电极以及引线孔等结构的设置，可以参考实施例三中的相关描述，此处不再赘述。
实施例五
本实施例提供了一种显示装置，其包括上述任一实施例提供的阵列基板。
以液晶显示装置为例，如图7所示，本实施例的一个示例提供的显示装置可以包括阵列基板20与对置基板30，阵列基板20与对置基板30彼此对置且通过封框胶35以形成液晶盒，在液晶盒中填充有液晶材料40。该对置基板30例如为彩膜基板。阵列基板20的每个像素单元的像素电极用于施加电场以对液晶材料的旋转程度进行控制从而进行显示操作。在一些实施例中，该显示装置还包括为阵列基板20提供背光的背光源50。
本实施例提供的显示装置可以为：液晶面板、电子纸、OLED面板、手机、电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明的至少一个实施例还提供了一种薄膜晶体管的制作方法，该方法包括：形成有源层、栅极、分别与有源层电连接的源极和漏极、以及位于栅极和有源层之间的栅极绝缘层，使得栅极、源极和漏极在同一次构图工艺中形成。
本发明的至少一个实施例还提供了一种阵列基板的制作方法，该方法包括：在衬底基板上形成薄膜晶体管，所述薄膜晶体管采用上述实施例提供的薄膜晶体管的制作方法制作。
下面结合实施例六至实施例八对本发明上述实施例提供的阵列基板的制作方法以及薄膜晶体管的制作方法进行详细说明。
实施例六
针对实施例二提供的阵列基板20，本实施例提供一种相应的阵列基板的制作方法，以图4所示的情形为例，该方法可以包括以下步骤S41-S45，下面逐一介绍这些步骤。
步骤S41：通过第一次构图工艺(也称为掩膜工艺，例如包括曝光、显影、刻蚀等步骤)，在衬底基板201上形成有源层210。
步骤S42：通过第二次构图工艺，在有源层210上形成栅极绝缘层220，并在栅极绝缘层220的分别对应待形成的源极231和漏极233的位置处形成暴露出有源层210的过孔224。
步骤S43：通过第三次构图工艺，在栅极绝缘层220上形成源极231、栅极232、漏极233、第一信号线的线状部和第二信号线，使源极231和漏极233分别通过步骤S42中形成的过孔与有源层210电连接。
在该步骤中，第一信号线和第二信号线中的一个为栅线，另一个为数据线，并且，第一信号线和第二信号线在图4中未示出。
步骤S44：通过第四次构图工艺，形成钝化层250，并在钝化层250中形成暴露出漏极233的第一过孔、暴露出第一信号线的线状部的第二过孔(图4中未示出)、以及引线孔。
如上所述，引线孔用于实现电极驱动线与相应的驱动IC之间的连接，例如，上述引线孔可以包括分别对应栅极232的驱动线、源极231的驱动线和漏极233的驱动线的引线孔。
需要说明的是，图4中的引线孔仅是示例性地说明本实施例，在具体实施时，通常，引线孔设置于阵列基板的Pad区域，而像素区域的薄膜晶体管并不对应引线孔。
步骤S45：通过第五次构图工艺，在钝化层250上形成透明电极243以及第一信号线的连接部，使透明电极243通过步骤S44中形成的第一过孔与漏极233电连接，并且使第一信号线的连接部通过步骤S44中形成的第二过孔连接相邻的线状部。
在该步骤中，透明电极243的材料还可以覆盖引线孔的内表面，如图4所示，这样可以便于设置引线。
针对实施例二所述的薄膜晶体管200，本实施例提供了一种薄膜晶体管 的制作方法，以图4所示的情形为例，该方法可包括本实施例中的上述步骤S41和S42，以及通过第三次构图工艺，在栅极绝缘层220上形成源极231、栅极232和漏极233，使源极231和漏极233分别通过步骤S42中形成的过孔224与有源层210电连接。即：通过第一次构图工艺，形成有源层210；通过第二次构图工艺，在有源层210上形成栅极绝缘层220，并在栅极绝缘层220的分别对应源极231和漏极233的位置处形成暴露出有源层210的过孔224；以及通过第三次构图工艺，在栅极绝缘层220上形成源极231、栅极232和漏极233，使源极231和漏极233分别通过过孔与有源层电连接。
在本实施例提供的阵列基板或薄膜晶体管中，当源极和漏极与有源层搭接时，在形成栅极绝缘层的步骤中，可通过设置栅极绝缘层的图案以暴露出源极和漏极的表面，以便于源极和漏极与有源层搭接。此处不再赘述。
与图1a所示的情形相比，本实施例提供的阵列基板的制作方法以及薄膜晶体管的制作方法都可以减少一次构图工艺。
实施例一提供的如图2a所示的阵列基板20/薄膜晶体管200的制作方法与本实施例提供的制作方法类似，不同之处在于形成有源层的步骤在形成源极、栅极和漏极的步骤以及形成栅极绝缘层的步骤之后。即实施例一提供的如图2a所示的阵列基板20/薄膜晶体管200的制作方法包括：通过第一次构图工艺，形成源极231、栅极232和漏极；通过第二次构图工艺，形成栅极绝缘层220，并在栅极绝缘层220的分别对应源极231和漏极233的位置处形成分别暴露出源极231和漏极233的过孔224；通过第三次构图工艺，在栅极绝缘层220上形成有源层210，使有源层220通过过孔224分别与源极231和漏极233电连接。相应步骤可参考本实施例中的相关描述，重复之处不再赘述。
实施例一提供的如图2b所示的阵列基板20/薄膜晶体管200，其与图2a所示的阵列基板/薄膜晶体管200的制作方法的区别在于：在形成栅极绝缘层220的步骤中未在栅极绝缘层220中形成过孔224，而是通过设置栅极绝缘层220的图案以暴露出源极231和漏极233的表面以便于与有源层210电连接。
实施例七
针对实施例三提供的阵列基板，本实施例提供一种阵列基板的制作方法，该制作方法包括：利用一次构图工艺形成薄膜晶体管的栅极绝缘层、栅极、 源极和漏极；以及形成与漏极电连接的像素电极以及与像素电极不同层设置的公共电极。在形成像素电极或公共电极的同时，还形成电连接源极和有源层的第一导电结构、以及电连接漏极和有源层的第二导电结构，例如，形成与源极的上表面和有源层的上表面接触的第一导电结构，以及与漏极的上表面和有源层的上表面接触的第二导电结构。在形成第一导电结构和第二导电结构之前，对有源层的待与第一导电结构和第二导电结构接触的上表面进行离子注入或等离子体处理。
如图5所示，阵列基板20包括像素电极243和公共电极280，以图5所示的第一导电结构241和第二导电结构242与像素电极243同层设置的情形为例，本实施例提供的阵列基板的制作方法可以包括以下步骤S51-S55，下面逐一介绍这些步骤。
步骤S51：通过第一次构图工艺，在衬底基板201上形成有源层210。
步骤S52：通过第二次构图工艺，在有源层210上形成栅极绝缘层220以及设置于栅极绝缘层220上的栅极232、源极231、漏极233、第一信号线的线状部以及第二信号线；并且，对有源层210的待与第一导电结构241和第二导电结构242接触的表面(例如，图5中有源层210的部分上表面210a和210b)进行离子注入或等离子体处理以提高该表面的导电性能。
在该步骤中，栅极绝缘层220包括对应源极231的第一绝缘部221、对应栅极232的第二绝缘部222以及对应漏极233的第三绝缘部223；并且，沿大致平行于衬底基板的方向上，各电极与其对应的绝缘部的宽度相等。
此外，第一信号线和第二信号线中的一个为栅线，另一个为数据线，第一信号线的线状部和第二信号线在图5中未示出。
步骤S53：通过第三次构图工艺，形成像素电极243、连接源极231和有源层210的第一导电结构241、以及连接漏极233和有源层210的第二导电结构242。
在该步骤中，需刻蚀掉部分像素电极材料以使各导线(例如，第一信号线的线状部和第二信号线)彼此绝缘。例如，刻蚀掉第一信号线和第二信号线交叉处的像素电极材料，以使第一信号线的线状部之间以及线状部与第二信号线之间彼此绝缘。由于刻蚀像素电极材料的刻蚀药液对金属材料的刻蚀速率非常慢，因而在正常的工艺中可以忽略刻蚀对第一信号线的线状部和第 二信号线的影响。
此外，像素电极243和第二导电结构242可以一体形成，并且分别位于漏极233的两侧。
步骤S54：通过第四次构图工艺，形成钝化层250，并在钝化层250中形成暴露出第一信号线的线状部的过孔以及引线孔(如实施例六所述，此处不再赘述)。
步骤S55：通过第五次构图工艺，在钝化层250上形成公共电极280和与其连接的公共电极线、以及第一信号线的连接部，使第一信号线的连接部通过步骤S54中形成的过孔连接相邻的线状部。
在该步骤中，形成公共电极280的材料还可以覆盖步骤S54中形成的引线孔的内表面，以便于设置引线。
本实施例还提供了一种如图5所示的薄膜晶体管200的制作方法，该方法包括：通过第一次构图工艺，形成有源层210；通过第二次构图工艺，在有源层210上形成栅极绝缘层220以及设置于栅极绝缘层220上的栅极232、源极231和漏极233；对有源层210的未被栅极绝缘层220覆盖的至少部分表面(即待与第一导电结构241和第二导电结构242接触的表面)进行离子注入或等离子体处理以提高该处的导电性能；以及通过第三次构图工艺，形成电连接源极231和有源层210的第一导电结构241、以及电连接漏极233和有源层210的第二导电结构242。
在本实施例提供的薄膜晶体管的制作方法中，第一导电结构和第二导电结构可以通过单独形成导电层(例如金属层)的方式制作。
实施例八
针对实施例四提供的阵列基板，本实施例提供一种阵列基板的制作方法，该制作方法包括：利用一次构图工艺形成薄膜晶体管的有源层、栅极绝缘层、栅极、源极和漏极；以及形成与漏极电连接的像素电极以及与像素电极不同层设置的公共电极。在形成像素电极或公共电极的同时，还形成电连接源极和有源层的第一导电结构、以及电连接漏极和有源层的第二导电结构，例如，形成与源极的上表面和有源层的上表面接触的第一导电结构，以及与漏极的上表面和有源层的上表面接触的第二导电结构。在形成第一导电结构和第二导电结构之前，在有源层的待与第一导电结构和第二导电结构接触的位置处 进行离子注入或等离子体处理。
如图6所示，阵列基板20包括像素电极243和公共电极280，以图6所示的第一导电结构241和第二导电结构242与像素电极243同层设置的情形为例，本实施例提供的阵列基板的制作方法可以包括以下步骤S61-S64，下面逐一介绍这些步骤。
步骤S61：通过第一次构图工艺，在衬底基板201上形成有源层210、栅极绝缘层220、栅极232、源极231、漏极233、第一信号线的线状部以及第二信号线；并且，对有源层210的待与第一导电结构241和第二导电结构242接触的表面进行离子注入或等离子体处理以提高该表面的导电性能。
例如，该第一次构图工艺可以采用半色调掩膜板，如以下步骤S611～S614所述，下面结合图8a至图8c进行描述。
步骤S611：在衬底基板201上依次沉积金属氧化物半导体薄膜、栅极绝缘层薄膜以及金属薄膜，并在金属薄膜上涂覆一层光刻胶。
步骤S612：利用半色调掩膜板(Half-tone mask)进行曝光，之后进行显影，并将没有光刻胶保护的金属薄膜、栅极绝缘层薄膜以及金属氧化物半导体薄膜刻蚀掉，得到如图8a所示的基板。
半色调掩膜板包括非曝光区域、部分曝光区域以及完全曝光区域，如图8a所示，完全曝光区域(图8a中未示出)位于非曝光区域两侧。非曝光区域对应待形成的栅极、源极、漏极、第一信号线的线状部以及第二信号线等结构；部分曝光区域对应待形成的第一开口和第二开口；其余部分为完全曝光区域。
经过显影处理之后，位于完全曝光区域的光刻胶被去除，金属薄膜、栅极绝缘层薄膜以及金属氧化物半导体薄膜的对应完全曝光区域的部分因没有光刻胶保护而被刻蚀掉，其余部分则被保留。
如图8a所示，经过步骤S612处理后可以形成：有源层210、刻蚀后的栅极绝缘层薄膜220’、刻蚀后的金属薄膜230、以及覆盖金属薄膜230的光刻胶300。
步骤S613：对光刻胶300进行灰化处理，得到如图8b所示的基板，此时，灰化后的光刻胶300’覆盖金属薄膜230的一部分。
步骤S614：刻蚀掉没有光刻胶300’保护的金属薄膜230和栅极绝缘层薄 膜220’，并保留有源层210的没有光刻胶300’保护的部分，从而得到如图8c所示的基板。如此，可以形成栅极232、源极231和漏极233共面的结构、第一信号线的线状部以及第二信号线；栅极绝缘层薄膜220’形成包括第一绝缘部221、第二绝缘部222以及第三绝缘部223的栅极绝缘层；并且，栅极绝缘层中形成暴露出有源层210的第一开口321和第二开口322。
在完成上述第一次构图工艺后，进行步骤S615：如图8d所示，对有源层的对应第一开口321和第二开口322的表面进行离子注入或等离子体处理，来降低此处的接触电阻。
经过上述步骤处理，沿大致平行于衬底基板的方向上，源极231、栅极232以及漏极233分别与其对应的绝缘部的宽度大致相等；沿大致平行于衬底基板201的方向上，栅极绝缘层的宽度与有源层210的宽度大致相等，即第一绝缘部221、第一开口321、第二绝缘部222、第二开口322以及第三绝缘部223的宽度之和与有源层的宽度大致相等。
此外，第一信号线和第二信号线中的一个为栅线，另一个为数据线，第一信号线的线状部以及第二信号线在图8a～8d中未示出。
步骤S62：通过第二次构图工艺，形成像素电极243，使源极231和有源层210通过第一导电结构241连接、漏极233和有源层210通过第二导电结构242连接以形成导电沟道，例如，得到如图8e所示的基板。
在该步骤中，需刻蚀掉部分像素电极材料以使各导线(例如，第一信号线的线状部和第二信号线)彼此绝缘。例如，刻蚀掉第一信号线和第二信号线交叉处的像素电极材料，以使第一信号线的线状部之间以及线状部与第二信号线之间彼此绝缘。由于刻蚀像素电极材料的刻蚀药液对金属材料的刻蚀速率非常慢，因而可以忽略刻蚀对第一信号线的线状部和第二信号线的影响。
此外，像素电极243和第二导电结构242可以一体形成，并且分别位于漏极233的两侧。
步骤S63：通过第三次构图工艺，形成钝化层250，并在钝化层250中形成暴露出第一信号线的线状部的过孔、以及引线孔(如实施例六所述，此处不再赘述)，例如，得到如图8f所示的基板。
步骤S64：通过第四次构图工艺，在钝化层250上形成公共电极280和与其连接的公共电极线、以及第一信号线的连接部，使第一信号线的连接部 通过步骤S63中形成的过孔连接相邻的线状部，得到如图6所示的基板。
在该步骤中，公共电极280的材料还可以覆盖步骤S63中形成的引线孔的内表面，这样可以便于设置引线。
本实施例使用一次构图工艺形成了薄膜晶体管的有源层、栅极绝缘层、栅极以及源/漏极，再通过形成像素电极的材料将源/漏极和有源层连接起来以形成导电沟道，与图1b所示的情形相比，可以减少三次构图工艺，从而可以有效地减少掩膜板的数量、提高产能并节省成本；而且，当源/漏极有信号输入的时候，源/漏极下方的金属氧化物半导体材料也能形成电子层，这样能有效提升薄膜晶体管的开态电流，从而提升薄膜晶体管的性能。
本实施例还提供了一种如图6所示的薄膜晶体管200的制作方法，该方法可以包括：通过第一次构图工艺(例如利用半色调掩膜板，参见上述步骤S61)，形成有源层210、栅极绝缘层220、栅极232、源极231和漏极233；对有源层210的未被栅极绝缘层220覆盖的表面(即待与第一导电结构241和第二导电结构242分别接触的表面)进行离子注入或等离子体处理以提高该处的导电性能；以及，通过第二次构图工艺，形成电连接源极231和有源层210的第一导电结构241、以及电连接漏极233和有源层210的第二导电结构242。
在本实施例提供的薄膜晶体管的制作方法中，第一导电结构和第二导电结构可以通过单独形成导电层(例如金属层)的方式制作。
需要说明的是，对于大尺寸的显示装置，在包括两层透明电极(如图5和图6所示)的阵列基板中，还可以利用形成栅线的材料形成金属公共电极线，公共电极通过其下方的绝缘层中的过孔与该金属公共电极线电连接，这样可以减小公共电极的电阻。此处不做赘述。
在本发明的上述实施例中，利用同一膜层形成的结构(即同层设置或位于同一层的不同结构)可以并排位于同一层上，如图2a、2b、4、5、6中的并排位于同一层上的栅极232、源极231和漏极233所示，利用同一膜层形成的结构也可以具有高低起伏的形状，如图5和图6中的第一导电结构241、第二导电结构242和像素电极243所示。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年6月8日递交的中国专利申请第201510308890.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (26)

  1. 一种阵列基板，包括位于衬底基板上的薄膜晶体管，其中，
    所述薄膜晶体管包括有源层、栅极、分别与所述有源层电连接的源极和漏极、以及位于所述栅极和所述有源层之间的栅极绝缘层，所述栅极、所述源极和所述漏极在同一次构图工艺中形成。
  2. 如权利要求1所述的阵列基板，还包括多条沿第一方向延伸的第一信号线和多条沿第二方向延伸且与所述第一信号线相绝缘的第二信号线，其中，每条所述第一信号线包括多个间断设置的线状部以及连接相邻的所述线状部的连接部，所述连接部与所述线状部异层设置，所述线状部和所述第二信号线同层设置；并且
    所述第一信号线为栅线，并且所述第二信号线为数据线；或者，所述第一信号线为数据线，并且所述第二信号线为栅线。
  3. 如权利要求1或2所述的阵列基板，其中，所述栅极绝缘层设置于所述有源层上，所述栅极、所述源极和所述漏极设置于所述栅极绝缘层上。
  4. 如权利要求3所述的阵列基板，其中，所述栅极绝缘层包括间隔设置的第一绝缘部、第二绝缘部以及第三绝缘部；
    所述第一绝缘部位于所述源极和所述有源层之间；
    所述第二绝缘部位于所述栅极和所述有源层之间；
    所述第三绝缘部位于所述漏极和所述有源层之间。
  5. 如权利要求4所述的阵列基板，其中，所述第一绝缘部和所述第二绝缘部之间设置有第一开口，所述第二绝缘部和所述第三绝缘部之间设置有第二开口；
    沿平行于所述衬底基板的方向上，所述有源层的宽度等于所述第一绝缘部、所述第一开口、所述第二绝缘部、所述第二开口和所述第三绝缘部的宽度之和。
  6. 如权利要求4或5所述的阵列基板，其中，
    所述源极与所述有源层通过第一导电结构电连接，所述第一导电结构与所述源极的上表面和所述有源层的部分上表面接触；
    所述漏极与所述有源层通过第二导电结构电连接，所述第二导电结构与 所述漏极的上表面和所述有源层的另一部分上表面接触。
  7. 如权利要求6所述的阵列基板，还包括：与所述漏极电连接的像素电极以及与所述像素电极不同层设置的公共电极，其中，
    所述第一导电结构、所述第二导电结构和所述像素电极同步形成且材料相同，或者，所述第一导电结构、所述第二导电结构和所述公共电极同步形成且材料相同。
  8. 如权利要求7所述的阵列基板，其中，所述有源层的材料包括金属氧化物半导体材料。
  9. 如权利要求1或2所述的阵列基板，其中，所述栅极绝缘层设置于所述栅极、所述源极和所述漏极上，所述有源层设置于所述栅极绝缘层上。
  10. 如权利要求1-3，9中任一项所述的阵列基板，其中，所述源极和所述漏极分别与所述有源层接触。
  11. 如权利要求10所述的阵列基板，其中，所述有源层的材料包括金属氧化物半导体材料、非晶硅材料或多晶硅材料。
  12. 如权利要求10或11所述的阵列基板，其中，所述栅极绝缘层中设置有分别对应所述源极和所述漏极的过孔，所述源极和所述漏极分别通过所述栅绝缘层中的过孔与所述有源层接触；或者
    所述源极和所述漏极搭接在所述有源层上。
  13. 一种显示装置，包括如权利要求1-12中任一项所述的阵列基板。
  14. 一种薄膜晶体管，包括有源层、栅极、分别与所述有源层电连接的源极和漏极、以及位于所述栅极和所述有源层之间的栅极绝缘层，其中，
    所述栅极、所述源极和所述漏极在同一次构图工艺中形成。
  15. 一种薄膜晶体管的制作方法，包括：形成有源层、栅极、分别与所述有源层电连接的源极和漏极、以及位于所述栅极和所述有源层之间的栅极绝缘层，其中，
    所述栅极、所述源极和所述漏极在同一次构图工艺中形成。
  16. 如权利要求15所述的方法，其中，所述栅极绝缘层、所述栅极、所述源极和所述漏极在所述同一次构图工艺中形成。
  17. 如权利要求15或16所述的方法，其中，采用半色调掩膜板在所述同一次构图工艺中形成所述有源层、所述栅极绝缘层、所述栅极、所述源极 和所述漏极。
  18. 如权利要求15所述的方法，其中，
    通过第一次构图工艺，形成所述有源层；通过第二次构图工艺，在所述有源层上形成所述栅极绝缘层，并在所述栅极绝缘层的分别对应所述源极和漏极的位置处形成暴露出所述有源层的过孔；以及通过第三次构图工艺，在所述栅极绝缘层上形成所述源极、所述栅极和所述漏极，使所述源极和所述漏极分别通过所述过孔与所述有源层电连接；
    或者
    通过第一次构图工艺，形成所述源极、所述栅极和所述漏极；通过第二次构图工艺，形成所述栅极绝缘层，并在所述栅极绝缘层的分别对应所述源极和所述漏极的位置处形成分别暴露出所述源极和所述漏极的过孔；以及通过第三次构图工艺，在所述栅极绝缘层上形成所述有源层，使所述有源层通过所述过孔分别与所述源极和所述漏极电连接。
  19. 如权利要求16所述的方法，其中，
    通过第一次构图工艺，形成所述有源层；
    通过第二次构图工艺，在所述有源层上形成所述栅极绝缘层以及设置于所述栅极绝缘层上的所述栅极、源极和漏极；
    对所述有源层的未被所述栅极绝缘层覆盖的至少部分表面进行离子注入或等离子体处理；以及
    通过第三次构图工艺，形成电连接所述源极和所述有源层的第一导电结构、以及连接所述漏极和所述有源层的第二导电结构。
  20. 如权利要求17所述的方法，其中，
    通过第一次构图工艺，形成所述有源层、所述栅极绝缘层、所述栅极、所述源极和所述漏极；
    对所述有源层的未被所述栅极绝缘层覆盖的表面进行离子注入或等离子体处理；以及，
    通过第二次构图工艺，形成电连接所述源极和所述有源层的第一导电结构、以及电连接所述漏极和所述有源层的第二导电结构。
  21. 一种阵列基板的制作方法，包括：在衬底基板上形成薄膜晶体管，其中，
    所述薄膜晶体管采用如权利要求15所述的方法制作。
  22. 如权利要求21所述的方法，其中，所述栅极绝缘层、所述栅极、所述源极和所述漏极在所述同一次构图工艺中形成。
  23. 如权利要求20或21所述的方法，其中，采用半色调掩膜板在所述同一次构图工艺中形成所述有源层、所述栅极绝缘层、所述栅极、所述源极和所述漏极。
  24. 如权利要求21所述的方法，其中，
    通过第一次构图工艺，形成所述有源层；通过第二次构图工艺，在所述有源层上形成所述栅极绝缘层，并在所述栅极绝缘层的分别对应所述源极和漏极的位置处形成暴露出所述有源层的过孔；以及通过第三次构图工艺，在所述栅极绝缘层上形成所述源极、所述栅极和所述漏极，使所述源极和所述漏极分别通过所述过孔与所述有源层电连接；
    或者
    通过第一次构图工艺，形成所述源极、所述栅极和所述漏极；通过第二次构图工艺，形成所述栅极绝缘层，并在所述栅极绝缘层的分别对应所述源极和所述漏极的位置处形成分别暴露出所述源极和所述漏极的过孔；以及通过第三次构图工艺，在所述栅极绝缘层上形成所述有源层，使所述有源层通过所述过孔分别与所述源极和所述漏极电连接。
  25. 如权利要求21所述的方法，还包括：形成与所述漏极电连接的像素电极以及与所述像素电极不同层设置的公共电极，其中，
    通过第一次构图工艺，形成所述有源层；
    通过第二次构图工艺，在所述有源层上形成所述栅极绝缘层以及设置于所述栅极绝缘层上的所述栅极、源极和漏极；
    对所述有源层的未被所述栅极绝缘层覆盖的至少部分表面进行离子注入或等离子体处理；以及
    通过第三次构图工艺，形成所述像素电极或所述公共电极、以及连接所述源极和所述有源层的第一导电结构、以及电连接所述漏极和所述有源层的第二导电结构。
  26. 如权利要求21所述的方法，还包括：形成与所述漏极电连接的像素电极以及与所述像素电极不同层设置的公共电极，其中，
    通过第一次构图工艺，形成所述有源层、所述栅极绝缘层、所述栅极、所述源极和所述漏极；
    对所述有源层的未被所述栅极绝缘层覆盖的表面进行离子注入或等离子体处理；以及，
    通过第二次构图工艺，形成所述像素电极或所述公共电极、以及电连接所述源极和所述有源层的第一导电结构、以及连接所述漏极和所述有源层的第二导电结构。
PCT/CN2015/092206 2015-06-08 2015-10-19 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 WO2016197502A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP15885770.6A EP3306648B1 (en) 2015-06-08 2015-10-19 Film transistor and manufacturing method therefor, array substrate and manufacturing method therefor, and display apparatus
US15/300,362 US10483296B2 (en) 2015-06-08 2015-10-19 TFT and manufacturing method thereof, array substrate and manufacturing method thereof, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510308890.7A CN104851789B (zh) 2015-06-08 2015-06-08 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置
CN201510308890.7 2015-06-08

Publications (1)

Publication Number Publication Date
WO2016197502A1 true WO2016197502A1 (zh) 2016-12-15

Family

ID=53851346

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/092206 WO2016197502A1 (zh) 2015-06-08 2015-10-19 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置

Country Status (4)

Country Link
US (1) US10483296B2 (zh)
EP (1) EP3306648B1 (zh)
CN (1) CN104851789B (zh)
WO (1) WO2016197502A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104851789B (zh) 2015-06-08 2018-05-01 京东方科技集团股份有限公司 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置
CN204964955U (zh) * 2015-07-28 2016-01-13 合肥鑫晟光电科技有限公司 电连接结构、阵列基板和显示装置
JP6671155B2 (ja) * 2015-11-26 2020-03-25 三菱電機株式会社 薄膜トランジスタ基板
CN105957812B (zh) * 2016-06-06 2019-02-22 京东方科技集团股份有限公司 场效应晶体管及其制造方法、阵列基板及其制造方法以及显示面板
CN106531692A (zh) * 2016-12-01 2017-03-22 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板及显示装置
CN108666437B (zh) * 2017-04-01 2020-05-26 上海和辉光电有限公司 显示面板及其制作方法
CN107863373A (zh) * 2017-10-31 2018-03-30 昆山国显光电有限公司 显示面板及终端
EP4130858A4 (en) * 2020-04-01 2023-05-31 BOE Technology Group Co., Ltd. NETWORK SUBSTRATE AND DISPLAY DEVICE
CN113867043B (zh) * 2020-06-30 2023-01-10 京东方科技集团股份有限公司 发光基板及其制备方法、显示装置
WO2024124571A1 (zh) * 2022-12-16 2024-06-20 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080002081A1 (en) * 2006-06-30 2008-01-03 Lg Philips Lcd Co., Ltd. Liquid crystal display device and method of fabricating the same
CN103715094A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN104681630A (zh) * 2015-03-24 2015-06-03 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示面板
CN104851789A (zh) * 2015-06-08 2015-08-19 京东方科技集团股份有限公司 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101192073B1 (ko) * 2005-06-28 2012-10-17 엘지디스플레이 주식회사 프린지 필드 스위칭 모드 액정표시장치 및 그 제조방법
KR20140032155A (ko) * 2012-09-06 2014-03-14 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조방법
KR102105485B1 (ko) * 2012-11-23 2020-04-29 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
US9023683B2 (en) * 2013-05-13 2015-05-05 Sharp Laboratories Of America, Inc. Organic semiconductor transistor with epoxy-based organic resin planarization layer
CN104022077B (zh) * 2014-05-27 2017-01-25 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104022076B (zh) 2014-05-27 2017-01-25 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104253159B (zh) 2014-08-19 2017-06-13 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
CN104637955B (zh) * 2015-01-30 2017-10-24 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN104681627B (zh) * 2015-03-10 2019-09-06 京东方科技集团股份有限公司 阵列基板、薄膜晶体管及制作方法、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080002081A1 (en) * 2006-06-30 2008-01-03 Lg Philips Lcd Co., Ltd. Liquid crystal display device and method of fabricating the same
CN103715094A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN104681630A (zh) * 2015-03-24 2015-06-03 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示面板
CN104851789A (zh) * 2015-06-08 2015-08-19 京东方科技集团股份有限公司 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3306648A4 *

Also Published As

Publication number Publication date
EP3306648B1 (en) 2021-05-19
EP3306648A1 (en) 2018-04-11
CN104851789A (zh) 2015-08-19
EP3306648A4 (en) 2019-03-06
CN104851789B (zh) 2018-05-01
US20170186784A1 (en) 2017-06-29
US10483296B2 (en) 2019-11-19

Similar Documents

Publication Publication Date Title
WO2016197502A1 (zh) 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置
WO2018018893A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
WO2016141709A1 (zh) 阵列基板及其制作方法、显示装置
WO2015096355A1 (zh) 阵列基板及其制作方法、显示装置
JP6382496B2 (ja) 薄膜トランジスタアレイ基板及びその製造方法
WO2019007228A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
US9893098B2 (en) Array substrate and fabrication method thereof, and display device
KR101344980B1 (ko) 박막 트랜지스터 및 어레이 기판의 제조 방법, 및 마스크
US11397359B2 (en) Thin film transistor array substrate, manufacturing method thereof, and display panel
WO2017024640A1 (zh) 阵列基板及其制造方法
US9450103B2 (en) Thin film transistor, method for manufacturing the same, display device and electronic product
EP3236499B1 (en) Array substrate and manufacturing method therefor, and display device
KR20130098709A (ko) 박막트랜지스터 기판 및 이의 제조 방법
US9741861B2 (en) Display device and method for manufacturing the same
WO2015096374A1 (zh) 阵列基板及其制作方法、显示装置和薄膜晶体管
WO2015096309A1 (zh) 薄膜晶体管及其制造方法、阵列基板、显示装置
WO2015010404A1 (zh) 薄膜晶体管及其制作方法、阵列基板及显示装置
US20200295054A1 (en) Thin film transistor and manufacturing method therefor, array substrate and display device
TW201642478A (zh) 薄膜電晶體的製造方法
WO2018090496A1 (zh) 一种阵列基板及其制备方法、液晶显示面板
WO2014172970A1 (zh) 阵列基板及其制造方法和显示装置
US9502446B2 (en) Poly-silicon TFT, poly-silicon array substrate and preparing method thereof, display device
WO2015096369A1 (zh) 阵列基板及其制造方法、显示装置
CN106856199B (zh) 显示面板及其制造方法
CN106298951B (zh) 薄膜晶体管的制作方法

Legal Events

Date Code Title Description
REEP Request for entry into the european phase

Ref document number: 2015885770

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 15300362

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15885770

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2015885770

Country of ref document: EP