WO2016188448A2 - 一种碳化硅mosfet器件及其制备方法 - Google Patents

一种碳化硅mosfet器件及其制备方法 Download PDF

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WO2016188448A2
WO2016188448A2 PCT/CN2016/083450 CN2016083450W WO2016188448A2 WO 2016188448 A2 WO2016188448 A2 WO 2016188448A2 CN 2016083450 W CN2016083450 W CN 2016083450W WO 2016188448 A2 WO2016188448 A2 WO 2016188448A2
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gate oxide
oxide layer
region
thickness
silicon carbide
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French (fr)
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WO2016188448A3 (zh
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高云斌
李诚瞻
刘国友
吴煜东
史晶晶
赵艳黎
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株洲中车时代电气股份有限公司
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Priority to US15/576,652 priority Critical patent/US10475896B2/en
Publication of WO2016188448A2 publication Critical patent/WO2016188448A2/zh
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Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a power device, and more particularly to a silicon carbide MOSFET device and a method for fabricating the same.
  • the silicon carbide (SiC) material represented by the third-generation semiconductor has a larger forbidden band width and a critical breakdown electric field. Therefore, it is suitable for manufacturing high voltage and high power semiconductor devices.
  • SiC silicon carbide
  • the silicon carbide MOSFET has a significantly lower on-resistance and switching loss, which is suitable for higher operating frequencies, and because of its high-temperature operating characteristics, Improve high temperature stability.
  • the critical breakdown electric field strength of silicon carbide MOSFETs can reach 2-3 MV/cm. According to the principle of continuity of electric flux at the interface of the oxide layer, when the device is under pressure, the electric field strength of the gate oxide layer above the JFET region easily exceeds 4 MV/cm, which seriously affects the reliability of the gate oxide layer.
  • the JFET region width is too narrow, the on-resistance is too large. When the width is too wide, the electric field curvature concentration effect is significant, and the device breakdown voltage is lowered.
  • the on-resistance characteristics are usually sacrificed, and the narrow JFET region width, high p-well doping concentration and Larger p-well junction depth design.
  • the improved methods in the prior art tend to increase the on-resistance of the device on the one hand, and high-energy and high-dose aluminum ion implantation on the other hand, which increases the process difficulty and is not conducive to lowering the work. Loss.
  • the electric field strength of the gate oxide layer in the silicon carbide MOSFET device provided by the present invention is weakened while maintaining the threshold voltage.
  • the on-resistance can be further reduced by increasing the width of the JFET region.
  • the present invention also provides a method of fabricating the silicon carbide MOSFET device, particularly a method of fabricating a gate oxide layer.
  • a silicon carbide MOSFET device includes a gate oxide layer composed of a first gate oxide layer and a second gate oxide layer, wherein a thickness of the second gate oxide layer is greater than the first The thickness of a gate oxide layer.
  • the threshold voltage of the device and the electric field strength of the gate oxide layer are adjusted by disposing the gate oxide layer in two portions having different thicknesses, that is, the gate oxide layer is stepped.
  • the silicon carbide MOSFET device is a Vertical Double-diffused MOSFET (VDMOS). That is, in this embodiment, the silicon carbide MOSFET device has the basic construction and basic operating principles of a vertical double diffused MOSFET known to those skilled in the art. On this basis, the silicon carbide MOSFET device of the present application has further improved construction and performance.
  • VDMOS Vertical Double-diffused MOSFET
  • the thickness of the second gate oxide layer is 1.5-4 times, preferably 2-4 times, more preferably 2-3 times the thickness of the first gate oxide layer.
  • the first gate oxide layer has a thickness of 40-80 nm, preferably 40-60 nm.
  • the second gate oxide layer has a thickness of 60-320 nm, preferably 80-240 nm, more preferably 80-180 nm, such as 80 nm, 100 nm, 120 nm, 140 nm, 160 nm or 180 nm.
  • the silicon carbide MOSFET device provided by the present invention includes a parallel P + doped region (also referred to as a P + ohmic contact region), an N + source region (also referred to as an N + doped region), a channel, and a JFET (Junction Field Effect). Transistor) area.
  • the first gate oxide layer corresponds to a channel of the device, a portion of the N + source region, and optionally a portion of the JFET region, the second gate oxide layer and the device At least a portion of the JFET regions correspond, and the first gate oxide layer is in contact with the second gate oxide layer.
  • the first gate oxide layer covers the entire channel region and a portion of the N + source region, and optionally covers a portion of the JFET region; the second gate oxide layer is adjacent to the first gate oxide layer. Covering at least a portion of the JFET region, preferably covering the entire JFET region.
  • the thickness of the gate oxide layer above the channel is designed to be thin, which ensures that the threshold voltage of the device is moderate and the gate control characteristics are good; and the gate oxide layer above the JFET region is designed to be thicker, which can be effective.
  • the electric field strength of the gate oxide layer is reduced when the device withstands voltage, thereby improving the reliability of the gate oxide layer. After adopting this scheme, it can be designed
  • the relatively wide JFET region ensures low on-resistance of the device.
  • the width ratio of the second gate oxide layer to the JFET region of the device is in the range of 2:3 to 1:1, preferably 3:4 to 1:1, more preferably 1: 1.
  • One side of the second gate oxide layer is aligned with one side of the device, and when the width ratio of the second gate oxide layer to the JFET region of the device is less than 1, the second gate oxide layer is The interface of the first gate oxide layer falls on the JFET region.
  • the width of the first gate oxide layer covering the N + source region is determined by specific process parameters, preferably covering from 20% to 60% of the width of the N + source region.
  • the covering portion has a width of 0.5 to 2 ⁇ m.
  • the JFET region of the MOSFET device is a region of the N-type epitaxial layer (also referred to as "N - drift layer") of the device juxtaposed and adjacent to the P-well, specifically after forming a P-well on the N - drift region. A region of natural inclusion between two adjacent P-well regions.
  • the device has a JFET region width of 2-6 ⁇ m, preferably 3-5.5 ⁇ m, more preferably 3.2-5 ⁇ m, for example 3.5 ⁇ m, or 3.8 ⁇ m, or 4.0 ⁇ m, or 4.5. Mm, or 5.0 ⁇ m, or 5.5 ⁇ m.
  • the JFET region of a conventional silicon carbide MOSFET device is set to be narrow, typically 2-3.5 ⁇ m.
  • the width of the JFET region can be increased correspondingly, for example, can be increased to 4.0 ⁇ m or more. The on-resistance of the device while avoiding breakdown of the device in advance.
  • the width of the second gate oxide layer is 2-6 ⁇ m, preferably 3.2-5.5 ⁇ m, more preferably 3.2-5 ⁇ m, and the width ratio of the second gate oxide layer to the JFET region is 2 : a range of 3 to 1:1, preferably in the range of 3:4 to 1:1, more preferably 1:1.
  • the first gate oxide layer and the second gate oxide layer may have the same physical properties, or there may be a difference in the appropriate range, for example, the first gate oxide layer has higher density than the second gate oxide layer.
  • the medium of the first gate oxide layer and the second gate oxide layer are both SiO 2 .
  • the device comprises the following components:
  • a silicon carbide substrate preferably an N-type silicon carbide substrate, more preferably a highly doped N-type silicon carbide substrate;
  • JFET region which is an area on the N-type epitaxial layer juxtaposed with the P-well;
  • the first gate oxide layer and the second gate oxide layer are both a first gate oxide layer on the channel and a portion of the N + source region and a second gate oxide layer on the JFET region SiO 2 ;
  • a polysilicon gate deposited on the first gate oxide layer and the second gate oxide layer.
  • the device further includes
  • an N-type buffer layer is further included between the silicon carbide substrate and the N-type epitaxial layer.
  • the P-well has a junction depth of 0.5-1.0 ⁇ m, preferably 0.6-0.8 ⁇ m, such as 0.6-0.65 ⁇ m, or 0.65-0.70 ⁇ m, or 0.70-0.75 ⁇ m, or 0.75-0.80. Mm, or 0.80-0.90 ⁇ m, or 0.90-1.0 ⁇ m;
  • the peak doping concentration of aluminum ions is 1 ⁇ 10 18 cm -3 -1 ⁇ 10 19 cm -3 , preferably 1 ⁇ 10 18 cm -3 - 5 ⁇ 10 18 Cm -3 , more preferably 2 ⁇ 10 18 cm -3 - 4.5 ⁇ 10 18 cm -3 .
  • the aluminum ion peak doping concentration is the maximum aluminum ion concentration incorporated in the P well.
  • the P + doped region has a junction depth of 0.2 to 0.3 ⁇ m and an aluminum ion doping concentration of 1 ⁇ 10 19 cm -3 to 5 ⁇ 10 19 cm -3 .
  • the N + source region has a junction depth of 0.2-0.3 ⁇ m and a nitrogen ion doping concentration of 1 ⁇ 10 19 cm ⁇ 3 ⁇ 1 ⁇ 10 20 cm ⁇ 3 , preferably 5 ⁇ 10 19 cm -3 -1 ⁇ 10 20 cm -3 .
  • the respective width and width ratios of the P + doped region, the N + source region, and the channel region can be conventionally set by those skilled in the art.
  • the N-type epitaxial layer has a thickness of 10-13 ⁇ m and a nitrogen ion doping concentration of 1 ⁇ 10 15 cm -3 -9 ⁇ 10 15 cm -3 .
  • the polysilicon gate has a thickness of from 0.4 ⁇ m to 1 ⁇ m, preferably from 0.4 to 0.6 ⁇ m, and a phosphorus ion doping concentration of from 1 ⁇ 10 20 cm -3 to 3 ⁇ 10 20 cm -3 .
  • the N-type buffer layer has a thickness of 1-2 ⁇ m and a nitrogen ion doping concentration of the order of 1 ⁇ 10 18 cm -3 .
  • the metal and thickness deposited on the source and drain can be determined by those skilled in the art as desired.
  • the metal is preferably at least one of Ni, Ti, and Al, and more preferably a Ni/Al alloy.
  • the source covers Ni having a thickness of 30-100 nm and Al having a thickness of 1-3 ⁇ m.
  • the drain covers Ni having a thickness of 30-100 nm and Al having a thickness of 1-3 ⁇ m.
  • the silicon carbide MOSFET device provided in accordance with the present invention has a lower on-resistance than a conventional silicon carbide MOSFET device having the same withstand voltage rating (for example, 600V to 3300V), for example, as low as 8m ⁇ cm 2 or less, or even It is as low as 6 m ⁇ cm 2 or less, for example, in the range of 3-6 m ⁇ cm 2 .
  • the silicon carbide MOSFET device provided by the present invention is particularly suitable as a cell of an active region of a planar power device.
  • the silicon carbide MOSFET device as shown in Figure 1 herein is only half of the cells of the active region of the power device, and the other half is in a mirror conformation with the structure shown in Figure 1.
  • the silicon carbide MOSFET device cell provided by the present invention includes, for example, the configuration shown in Figure 1 and a configuration that is mirrored therewith. It should be noted that among the dimensions of the components given herein, the P well region width, the JFET region width, the P + doped region width, the second gate oxide width, the polysilicon gate width, and the source width dimension are all based on the entire cell. That is, twice the size of the corresponding component shown in Figure 1, the other width dimensions are based on the half cell meter shown in Figure 1.
  • a method of fabricating a silicon carbide MOSFET device comprising: fabricating a second gate oxide layer and a first gate oxide layer during formation of a gate oxide layer of the device, And making the thickness of the second gate oxide layer larger than the thickness of the first gate oxide layer; preferably, the thickness of the second gate oxide layer is 1.5-4 times, preferably 2-4, of the thickness of the first gate oxide layer Times, more preferably 2-3 times.
  • the thickness of the first gate oxide layer is preferably 40-80 nm, preferably 40-60 nm; and/or the thickness of the second gate oxide layer is preferably 60-320 nm, preferably 80-240 nm, It is preferably 80-180 nm.
  • the second gate oxide layer and the first gate oxide layer may be separately fabricated or fabricated together, as the manufacturing method allows, and the order of construction of the second gate oxide layer and the first gate oxide layer is not limited.
  • the second gate oxide layer and the first gate oxide layer are successively fabricated from the viewpoint of process difficulty.
  • the method comprises:
  • a gate oxide dielectric and a polysilicon of the P + doped region and a portion of the N + source region are etched to form the first gate oxide layer, and a polysilicon gate covering the first gate oxide layer and the second gate oxide layer.
  • the first generated gate oxide dielectric has a thickness of 40-80 nm, preferably 40-60 nm; and/or the second generated gate oxide dielectric has a thickness of 60-320 nm, preferably 80-320 nm. More preferably, it is 80-180 nm.
  • the gate oxide medium may be selected from a medium conventionally used in the art, preferably SiO 2 .
  • the formation of the sequentially adjacent JFET regions, channels, N + source regions, and P + doped regions is as follows:
  • Performing aluminum ion implantation on the N-type epitaxial layer may be performed multiple times, such as 3-4 injections) to form a P well, wherein the width of the P well is smaller than the width of the silicon carbide substrate,
  • the N-type epitaxial layer and the P-well The juxtaposed area is the JFET area;
  • Aluminum ion implantation and nitrogen ion implantation are respectively performed on the P well to form adjacent P + doped regions and N + source regions, and a channel is formed between the N + source regions and the JFET regions.
  • the preparation method according to the present invention further comprises depositing an interlayer dielectric, mainly SiO 2 , and etching to form an ohmic contact hole.
  • an interlayer dielectric mainly SiO 2
  • etching to form an ohmic contact hole.
  • the deposition of the interlayer dielectric can be routinely operated by those skilled in the art.
  • the preparation method according to the present invention further comprising: sputtering an ohmic contact metal, preferably Ni and Al, on a portion of the surface of the P + doped region and the adjacent N + source region to form a source; on the back side of the silicon carbide substrate
  • the ohmic contact metal preferably Ni and Al, is sputtered to form a drain.
  • the sputtered alloy acts as an ohmic contact metal for the source and drain.
  • the device is annealed in a nitrogen atmosphere at 800 ° C - 1000 ° C, for example 2-5 minutes.
  • the junction depth of the P well is set to 0.5-1.0 ⁇ m, preferably 0.6-0.9 ⁇ m, and the peak doping concentration of aluminum ions is 1 ⁇ 10 18 cm -3 -1 . ⁇ 10 19 cm -3 , preferably 1 ⁇ 10 18 cm -3 - 5 ⁇ 10 18 cm -3 .
  • the P + doped region has a junction depth of 0.2-0.3 ⁇ m and an aluminum ion doping concentration of 1 ⁇ 10 19 cm -3 -5 ⁇ 10 19 cm. -3 .
  • the junction depth of the N + source region is set to 0.2-0.3 ⁇ m, and the nitrogen ion doping concentration is 1 ⁇ 10 19 cm ⁇ 3 ⁇ 1 ⁇ 10 20 cm ⁇ 3 , preferably 5 ⁇ 10 19 cm -3 - 5 ⁇ 10 19 cm -3 .
  • the thickness of the N-type epitaxial layer is set to 10-13 ⁇ m, and the nitrogen ion doping concentration is 1 ⁇ 10 15 cm -3 -9 ⁇ 10 15 cm -3 .
  • the thickness of the polysilicon gate is set to be 0.4 ⁇ m to 1.0 ⁇ m, preferably 0.4 to 0.6 ⁇ m, and the phosphorus ion doping concentration is 1 ⁇ 10 20 cm ⁇ 3 ⁇ 3 ⁇ . 10 20 cm -3 .
  • a portion of the first gate oxide medium generated first is removed by etching so that the width ratio of the second gate oxide layer to the JFET region of the device is 2: A range of 3 to 1:1, preferably 3:4 to 1:1, more preferably 1:1.
  • the configuration of the width of the JFET region of the device is 2-6 ⁇ m, preferably 3-5.5 ⁇ m, preferably 3.2-5 ⁇ m.
  • the first generation uses a low pressure chemical vapor deposition, a wet oxygen thermal oxidation technique or a dry oxygen thermal oxidation technique.
  • the second generation is carried out using a dry oxythermal oxidation technique and is preferably carried out at a temperature of from 1,200 to 1,350 ° C in a high temperature oxidation furnace.
  • the second generation uses dry oxygen thermal oxidation techniques, while the first generation may select low pressure chemical vapor deposition or wet oxygen thermal oxidation techniques.
  • the first gate oxide layer thus formed has higher density than the second gate oxide layer, which is advantageous for threshold voltage and stability of the gate oxide layer, and device operational reliability, and for forming the first
  • the first generation of the second gate oxide layer does not require dry oxygen thermal oxidation technology, which not only reduces the process difficulty, but also saves technical cost and time cost.
  • the method for preparing a silicon carbide MOSFET device provided by the invention adopts selective etching and secondary thermal oxidation growth of a gate oxide layer to construct a gate oxide layer having a step shape, thereby improving the withstand voltage of the silicon carbide MOSFET device. And performance such as on-resistance.
  • a method of fabricating a silicon carbide MOSFET device comprising the steps of:
  • S2 growing an N-type buffer layer on the silicon carbide substrate, preferably having a thickness of 1-2 ⁇ m and a nitrogen ion doping concentration of the order of 1 ⁇ 10 18 cm ⁇ 3 ;
  • S3 epitaxially growing an N-type epitaxial layer on the N-type buffer layer, preferably having a thickness of 10-13 ⁇ m, and a nitrogen ion doping concentration of 1 ⁇ 10 15 cm -3 -9 ⁇ 10 15 cm -3 ;
  • S4 implanting aluminum ions on the N-type epitaxial layer to form a P well, preferably having a junction depth of 0.5-1.0 ⁇ m, preferably 0.6-0.8 ⁇ m, and an aluminum ion peak doping concentration of 1 ⁇ 10 18 cm ⁇ 3 -5 ⁇ 10 18 cm -3 ; the width of the P well is smaller than the width of the silicon carbide substrate, and a region juxtaposed with the P well on the N type epitaxial layer is a JFET region;
  • S5 implanting aluminum ions on the P well to form a P + doped region, preferably having a junction depth of 0.2-0.3 ⁇ m, and an aluminum ion doping concentration of 1 ⁇ 10 19 cm ⁇ 3 ⁇ 5 ⁇ 10 19 cm ⁇ 3 ;
  • N + source region implanting nitrogen ions in a region adjacent to the P + doped region on the P well to form an N + source region, preferably having a junction depth of 0.2-0.3 ⁇ m and a nitrogen ion doping concentration of 1 ⁇ 10 19 Cm -3 - 5 ⁇ 10 19 cm -3 ; a channel is formed between the N + source region and the JFET region;
  • SiO 2 is first formed on the JFET region, the channel, the N + source region, and the P + doped region, and has a thickness of 80-240 nm, preferably 80-180 nm, and the first generation preferably uses low pressure chemistry Vapor deposition, wet oxygen thermal oxidation technology or dry oxygen thermal oxidation technology;
  • the second generation preferably uses dry oxygen thermal oxidation technology, the temperature is 1200-1350 ° C;
  • S10 depositing polycrystalline silicon on the formed SiO 2 , preferably having a thickness of 0.4-0.6 ⁇ m, and a phosphorus ion doping concentration of 1 ⁇ 10 20 cm -3 -3 ⁇ 10 20 cm -3 ;
  • S11 etching removes SiO 2 and polysilicon on the P + doped region and a portion of the N + source region to form a polysilicon gate electrode pattern;
  • S13 sputtering Ni on the P + doped region and a portion of the N + source region and on the back side of the silicon carbide substrate, and annealing in an inert atmosphere at 800-1000 ° C for, for example, 2-5 minutes, preferably forming a Ni layer having a thickness of 30-100 nm. ;
  • Al is sputtered on the Ni layer, and the Al layer preferably formed has a thickness of 1-3 ⁇ m.
  • a suitable silicon carbide substrate is a silicon carbide substrate which is conventionally used in the art, and a highly doped N-type (N + -type) silicon carbide substrate is preferred in the present invention.
  • the etching is preferably dry etching, and is preferably reactive ion etching (RIE).
  • RIE reactive ion etching
  • the RIE principle is that when a high-frequency voltage of 10-100 MHZ is applied between the plate electrodes, an ion layer of several hundred micrometers thick is generated, and a sample is placed therein, and the ion strikes the sample at a high speed to complete the chemical reaction etching.
  • orientations such as “upper”, “upper”, “above” or “below” refer to the relative positional relationship of the regions or components or the like in the normal use state of the device.
  • the unit "cm -3” means "pieces / cm -3 ".
  • the silicon carbide MOSFET device provided by the present invention has a gate oxide layer with a modified specific structure, that is, a stepped gate oxide structure.
  • the gate oxide layer above the JFET region is thicker, and the gate oxide layer above the channel region is thinner. While effectively reducing the electric field strength of the gate oxide layer, it does not affect the threshold voltage and gate control characteristics of the device. That is, without increasing the threshold voltage and on-resistance of the device, the voltage resistance and reliability of the gate oxide layer can be enhanced, and then the design margin can be fully expanded, and the device guide can be further reduced by adopting a wider JFET region structure. resistance, for example, can be reduced to 2 or less 8m ⁇ ⁇ cm, or even 2 or less 6m ⁇ ⁇ cm.
  • FIG. 1 is a schematic structural view of a silicon carbide MOSFET device having a stepped gate oxide layer according to an embodiment of the present invention.
  • FIG. 2 is a flow chart showing the preparation of a silicon carbide MOSFET device having a stepped gate oxide layer of the present invention in accordance with an embodiment of the present invention.
  • FIGS. 3a-3j is a flow chart showing the fabrication of a silicon carbide MOSFET device having a stepped gate oxide layer of the present invention in accordance with an embodiment of the present invention.
  • the silicon carbide MOSFET device provided by the present invention includes a gate oxide layer composed of a first gate oxide layer 9-1 and a second gate oxide layer 9-2, wherein The thickness of the second gate oxide layer 9-2 is greater than the thickness of the first gate oxide layer 9-1, that is, the gate oxide layer has a stepped structure.
  • the thickness of the second gate oxide layer 9-2 is 1.5-4 times, preferably 2-4 times, more preferably 2-3 times the thickness of the first gate oxide layer 9-1.
  • the first gate oxide layer 9-1 may have a thickness of 40 to 80 nm, preferably 40 to 60 nm.
  • the second gate oxide layer 9-2 may have a thickness of 60 to 320 nm, preferably 80 to 240 nm, more preferably 80 to 180 nm.
  • the silicon carbide MOSFET device specifically includes: a silicon carbide substrate 1, an N-type buffer layer 2 formed on the silicon carbide substrate, and an N-type epitaxially epitaxially grown on the N-type buffer layer 2.
  • Layer 3 a P well 4 formed by implanting aluminum ions in the N-type epitaxial layer 3, a JFET region 5 juxtaposed with the P well 4 on the N-type epitaxial layer 3, and P formed by aluminum ion implantation on the P well 4 + doped region 7 and N + source region 8 formed by nitrogen ion implantation, and channel region 6 formed between N + source region 8 and JFET region 5.
  • the first gate oxide layer 9-1 covers the channel region 6 and a portion of the N + source region 8
  • the second gate oxide layer 9-2 covers the JFET region 5 at the first gate.
  • the polysilicon gate 10 is covered on the oxide layer 9-1 and the second gate oxide layer 9-2.
  • the second gate oxide layer 9-2 may cover only a portion of the JFET region 5, for example, covering 2/3 to 1 of the JFET region 5, while the remaining portion of the JFET region 5 is Covered by a gate oxide layer 9-1.
  • the width of the JFET region is in the range of 2-6 ⁇ m; the first gate oxide layer covers 20% to 60% of the width of the N + source region.
  • the silicon carbide MOSFET device further includes a P + doped region 7 and a source 11 on a portion of the N + source region 8 and a drain 12 under the silicon carbide substrate 1.
  • the source 11 and the drain 12 may be composed of Ni and Al, for example, a Ni layer of 30-100 nm and an Al layer of 1-3 ⁇ m thick.
  • An interlevel dielectric exists between the source and the gate oxide and the polysilicon gate and can be constructed in a conventional manner.
  • Features such as thickness or junction depth, ion doping amount, and the like of each member can be selected in the range described above.
  • the silicon carbide MOSFET device provided by the present invention can be used to constitute an active region of a power device, which is a cell constituting the active region.
  • FIG. 1 only schematically shows half of the cells, that is, the complete silicon carbide MOSFET device provided by the present invention includes the configuration described in FIG. 1 and the other half configuration mirrored in FIG. Of course, the half cells as shown in Figure 1 are also within the scope of the invention.
  • a voltage bias higher than a threshold voltage is applied to the gate electrode of the device, an inversion layer is formed on the surface of the channel region, and a vertical conductive path is formed inside the device, and the current is gated.
  • the voltage changes, and the voltage drop between the drain and the source is small, and the device enters a conducting state, exhibiting a low gate-controlled resistance characteristic.
  • a zero or negative bias is applied to the gate electrode of the device, the channel is closed, the internal vertical conduction path of the device is turned off, and the device's high resistance drift region is subjected to a high drain-source voltage, and the device enters a blocking state.
  • the silicon carbide MOSFET device can be fabricated by a process flow as shown in FIG.
  • the process includes epitaxially growing an N-type epitaxial layer on a silicon carbide substrate, ion implantation to form a P well, ion implantation to form a P + ohmic contact region, ion implantation to form an N + source region, deposition or thermal oxidation to grow the SiO 2 medium, Etching removes SiO 2 dielectric other than above the JFET region, dry oxidative thermal oxidation grows SiO 2 gate dielectric, forms gate polysilicon, etches away part of dry oxythermally grown SiO 2 gate dielectric to form polysilicon gate pattern, and forms ohmic The step of contacting the electrodes.
  • the preparation method provided by the present invention comprises a process of depositing SiO 2 dielectric-selective etching-secondary SiO 2 dielectric to form a first gate oxide layer and a second gate oxide layer, respectively.
  • the method for preparing the provided silicon carbide MOSFET device will be exemplarily described in detail below with reference to FIG. 3 through a specific embodiment of the present invention.
  • the preparation method of the silicon carbide MOSFET device specifically includes the following steps.
  • N-type buffer layer 2 is grown to have a thickness of 10-13 ⁇ m and a nitrogen ion doping concentration of 1 ⁇ 10 15 cm -3 to 9 ⁇ 10 15 cm -3 as shown in Fig. 3a.
  • N + source region 8 having a junction depth of 0.2-0.3 ⁇ m and a nitrogen ion doping concentration of 5 ⁇ 10 19 cm -3 -1 ⁇ 10 20 cm -3 ; a channel region 6 is formed between the N + source region 7 and the JFET region 5, as shown in Fig. 3d.
  • the reaction is 10 min - 50 min, in the JFET region 5, the channel 6, the N + source region 8 and the P + doped region 7 generate a first SiO 2 gate dielectric 9, a thickness of 80-320nm, preferably 80-180nm a SiO 2 gate dielectric 9, as shown in FIG. 3e.
  • SiO 2 and polysilicon on the P + doped region 7 and a portion of the N + source region 8 are etched away by RIE to form a first gate oxide layer 9-1 and a polysilicon gate 10, as shown in Fig. 3i.
  • a silicon carbide MOSFET device a with a withstand voltage rating of 1200 V was prepared by the above method, and the specific feature was that the N-type buffer layer on the silicon carbide substrate was 1 ⁇ m; the N-type epitaxial layer was 12 ⁇ m thick, and the nitrogen ion doping concentration was 8.5 ⁇ 10 15 .
  • P well junction depth is 0.9 ⁇ m, aluminum ion doping concentration is 1 ⁇ 10 18 cm -3 ;
  • P + doped region has a junction depth of 0.3 ⁇ m and aluminum ion doping concentration is 1 ⁇ 10 19 cm - 3 ;
  • N + source region has a junction depth of 0.3 ⁇ m, a nitrogen ion doping concentration of 1 ⁇ 10 19 cm -3 ;
  • the width is 3 ⁇ m and 10 ⁇ m, respectively, the thickness is 120nm and 60nm; the thickness of the polysilicon gate is 0.6 ⁇ m, the phosphorus ion doping concentration is 1 ⁇ 10 20 cm -3 ; the source and the drain are sputtered by 30nm Ni and 3 ⁇ m Al.
  • a silicon carbide MOSFET device b having a withstand voltage rating of 1200 V is prepared by a similar method, which differs from device a in that the width of the JFET region is 5 ⁇ m; the widths of the second gate oxide layer and the first gate oxide layer are 5 ⁇ m and 10 ⁇ m, respectively.
  • the thicknesses were 120 nm and 60 nm, respectively.
  • the electrical characteristics of the device b were simulated in the same manner as in the first embodiment.
  • device b operates at a blocking voltage of 1200 V
  • the peak electric field intensity at the gate oxide layer above the JFET region is 1.5 MV/cm, and electric field concentration is effectively suppressed.
  • the on-resistance at a forward voltage drop of 1.6V is 5.3m ⁇ cm 2 , which is superior to device a.
  • a silicon carbide MOSFET device c with a withstand voltage rating of 1200 V is fabricated in a similar manner, having an N-type buffer layer of 1 ⁇ m on a silicon carbide substrate, an N-type epitaxial layer having a thickness of 10 ⁇ m, and a nitrogen ion doping concentration of 6 ⁇ 10 15 .
  • P well junction depth is 0.9 ⁇ m, aluminum ion doping concentration is 1 ⁇ 10 18 cm -3 ;
  • P + doped region has a junction depth of 0.3 ⁇ m and aluminum ion doping concentration is 1 ⁇ 10 19 cm - 3 ;
  • N + source region has a junction depth of 0.3 ⁇ m, a nitrogen ion doping concentration of 1 ⁇ 10 19 cm -3 ;
  • the width is 2 ⁇ m and 10 ⁇ m, respectively, the thickness is 150nm and 50nm;
  • the polysilicon gate is 0.6 ⁇ m, the phosphorus ion doping concentration is 1 ⁇ 10 20 cm -3 ;
  • the source and drain are 30nm Ni and 3 ⁇ m Al.
  • the electrical characteristics of the device c were simulated in the same manner as in the first embodiment.
  • the device c operates at a blocking voltage of 1200 V
  • the peak electric field intensity at the gate oxide layer above the JFET region is 1.7 MV/cm, and the electric field concentration is effectively suppressed.
  • the device d was prepared in a similar manner to the preparation of the device a, except that the above steps 6) and 7) were omitted, and the obtained device d was different from the device a in that the device d had a single gate oxide layer of 60 nm. .
  • the electrical characteristics of the device d were simulated in the same manner as in the first embodiment.
  • device d operates at a blocking voltage of 1200V
  • the peak electric field at the gate oxide layer above the JFET region is 3.6 MV/cm, and the electric field concentration phenomenon is more serious. In this case, if the quality of the oxide layer is not high, failure is more likely to occur.
  • the on-resistance at a forward voltage drop of 1.6V is 5.9m ⁇ cm 2 .
  • the electric field intensity of the gate oxide layer above the JFET region of the device can be effectively attenuated, from 3.6 MV/cm of the conventional structure to 1.2. MV/cm.
  • Example 2 Comparative Example 1 embodiment the simulation results, an appropriate width increasing the JFET region on the basis of Example 1, can reduce the on-resistance of 5.6m ⁇ ⁇ cm 2 to 5.3m ⁇ ⁇ cm 2, while the region above the gate JFET The electric field strength of the oxide layer was maintained at 1.5 MV/cm, which was still much lower than that of Comparative Example 1. Comparing the simulation results of Embodiment 3 and Embodiment 1, when the ratio of the width of the second gate oxide layer to the width of the JFET region is 1:1, the electric field intensity suppression effect is better, reaching 1.2 MV/cm, which is better than 1.7 MV/cm at 2:3. .
  • the wet oxygen thermal oxidation technique, the RIE dry etching, the dry oxygen thermal oxidation technique, and the low pressure chemical vapor deposition method used in the present invention are all known and commonly used in the art, and for the sake of brevity, the present invention does not Specific introduction.

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Abstract

本发明提供了一种碳化硅MOSFET器件，包括由第一栅氧化层和第二栅氧化层构成的栅氧化层，其中，所述第二栅氧化层的厚度大于所述第一栅氧化层的厚度。通过将栅氧化层设置成厚度不同的两部分，即所述栅氧化层呈阶梯状，在有效减小栅氧化层电场强度的同时，不影响器件阈值电压和栅控特性，且可通过增大JFET区宽度减小器件的导通电阻。本发明还提供了所述碳化硅MOSFET器件的制造方法。

Description

一种碳化硅MOSFET器件及其制备方法
关联申请的交叉引用
本申请要求申请日为2015年5月26日、名称为“一种碳化硅MOSFET器件及其制备方法”的中国专利申请CN 201510274919.4的优先权，其全部内容通过引用并入本申请中。
技术领域
本发明涉及半导体技术领域，具体涉及一种功率器件，尤其是涉及一种碳化硅MOSFET器件以及其制备方法。
背景技术
相对于以硅为代表的第一代半导体和以砷化镓为代表的第二代半导体，作为第三代半导体代表的碳化硅(SiC)材料具有更大的禁带宽度和临界击穿电场，从而适合制造高压大功率半导体器件。作为国际上功率电子和新型材料领域研究的热点，碳化硅一直以来受到学术界的高度重视，并已在Cree、Rohm、Infineon等公司的推动下，进入商业化阶段。
对于一种高性能、高可靠性的功率器件，需要有足够高的耐压能力，承受高压主电路通断；同时，需要有尽量低的导通电阻，以降低器件工作损耗，达到高效、环保和节能的要求。与相同功率等级的硅基MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)相比，碳化硅MOSFET导通电阻、开关损耗大幅降低，适用于更高的工作频率，另由于其高温工作特性，大大提高了高温稳定性。
但是，值得关注的是，不同于硅基MOSFET器件，碳化硅MOSFET的临界击穿电场强度可达到2-3MV/cm。根据氧化层界面处电通量连续性原理，器件耐压工作时，JFET区上方栅氧化层电场强度很容易超过4MV/cm，严重影响栅氧化层的可靠性。对于碳化硅功率MOSFET器件，JFET区宽度过窄则导通电阻过大，过宽则电场曲率集中效应显著，器件击穿电压下降。因此，在碳化硅MOSFET器件设计中，为抑制栅氧化层电场集中，保证栅氧化层可靠性，通常不惜牺牲导通电阻特性，采用较窄的JFET区宽度、较高的p阱掺杂浓度和较大的p阱结深设计。但是，现有技术中的改进方法往往一方面会增大器件的导通电阻，另一方面需采用高能高剂量铝离子注入，增大了工艺难度，也不利于降低工 作损耗。
发明内容
本发明的目的在于提供一种具有新型结构的碳化硅MOSFET器件，其具有阶梯形栅氧化层结构。在不需要缩小JFET区宽度或增大p阱掺杂浓度和p阱结深的情况下，本发明所提供的碳化硅MOSFET器件中栅氧化层的电场强度被削弱，在保持阈值电压不变的同时，可通过增大JFET区宽度进一步降低导通电阻。
本发明还提供了所述碳化硅MOSFET器件的制备方法，尤其是栅氧化层的制造方法。
根据本发明的一个方面，提供了一种碳化硅MOSFET器件，包括由第一栅氧化层和第二栅氧化层构成的栅氧化层，其中，所述第二栅氧化层的厚度大于所述第一栅氧化层的厚度。通过将栅氧化层设置成厚度不同的两部分，即所述栅氧化层呈阶梯状，调节器件的阈值电压和栅氧化层的电场强度。
在本发明的优选实施方式中，所述碳化硅MOSFET器件为垂直双扩散MOSFET(Vertical Double-diffused MOSFET，VDMOS)。即在此实施方式中，所述碳化硅MOSFET器件具有本领域技术人员公知的垂直双扩散MOSFET的基本构造和基本工作原理。在此基础上，本申请的碳化硅MOSFET器件具有进一步改进的构造和性能。
在本发明的优选实施方式中，所述第二栅氧化层的厚度是所述第一栅氧化层的厚度的1.5-4倍，优选2-4倍，更优选2-3倍。
根据本发明的优选实施方式，所述第一栅氧化层的厚度为40-80nm，优选40-60nm。
根据本发明的优选实施方式，所述第二栅氧化层的厚度60-320nm，优选为80-240nm，更优选80-180nm，例如80nm、100nm、120nm、140nm、160nm或180nm。
本发明提供的碳化硅MOSFET器件包括并列的P+掺杂区(也称为P+欧姆接触区)、N+源区(也称为N+掺杂区)、沟道和JFET(Junction Field Effect Transistor)区。在本发明的优选实施方式中，所述第一栅氧化层与所述器件的沟道、部分N+源区和任选地一部分JFET区相对应，所述第二栅氧化层与所述器件的至少一部分JFET区相对应，且所述第一栅氧化层与所述第二栅氧化层相接触。具体而言，所述第一栅氧化层覆盖整个沟道区域和一部分N+源区，还任选地覆盖一部分JFET区；所述第二栅氧化层与所述第一栅氧化层相邻，覆盖至少一部分JFET区，优选覆盖整个JFET区。
根据本发明的优选实施方式，将沟道上方的栅氧化层厚度设计得较薄，保证了器件的阈值电压适中，栅控特性良好；而将JFET区上方栅氧化层设计得较厚，可以有效减小器件耐压时该栅氧化层的电场强度，从而提高栅氧化层的可靠性。采用这一方案后，可设计 相对较宽的JFET区，保证器件低的导通电阻。
根据本发明的优选实施方式，所述第二栅氧化层与所述器件的JFET区的宽度比在2:3至1:1的范围，优选3:4至1:1，更优选在1:1。所述第二栅氧化层的一侧与所述器件的一侧对齐，当所述第二栅氧化层与所述器件的JFET区的宽度比在1以下时，所述第二栅氧化层与第一栅氧化层的分界面落在所述JFET区上。
第一栅氧化层覆盖N+源区的宽度由具体工艺参数决定，优选覆盖所述N+源区宽度的20％至60％。优选地，覆盖部分的宽度为0.5-2μm。
MOSFET器件的JFET区，是器件的N型外延层(也称为“N-漂移层”)上与所述P阱并列且相邻的区域，具体是在N-漂移区上形成P阱后，两个相邻P阱区域之间天然夹杂的区域。在本发明的优选实施方式中，所述器件的JFET区宽度为2-6μm，优选3-5.5μm，更优选3.2-5μm，例如可以设置为3.5μm，或3.8μm，或4.0μm，或4.5μm，或5.0μm，或5.5μm。为了抑制器件的栅氧化层的电场集中，常规碳化硅MOSFET器件的JFET区被设置得较窄，通常为2-3.5μm。然而，在本发明提供的碳化硅MOSFET器件中，由于分别设置了沟道区和JFET区上方的栅氧化层厚度，因而可相应地增加JFET区的宽度，例如可以增加到4.0μm以上，减小器件的导通电阻，同时避免器件提前被击穿。
在本发明的优选实施方式中，所述第二栅氧化层的宽度为2-6μm，优选3.2-5.5μm更优选3.2-5μm，且所述第二栅氧化层与JFET区的宽度比在2:3至1:1的范围，优选在3:4至1:1的范围，更优选1:1。
根据本发明，所述第一栅氧化层和第二栅氧化层可以具有相同的物理性能，也可以存在适当范围的差异，例如第一栅氧化层具有比第二栅氧化层更高的致密性。优选第一栅氧化层和第二栅氧化层的介质均为SiO2。
在本发明的一些优选实施方式中，所述器件包括以下部件：
碳化硅衬底，优选N型碳化硅衬底，更优选高掺杂的N型碳化硅衬底；
在所述碳化硅衬底上外延生长的N型外延层；
在所述N型外延层上经铝离子注入形成的P阱，所述P阱的宽度小于所述碳化硅衬底宽度；
JFET区，为N型外延层上与所述P阱并列的区域；
在所述P阱上进行铝离子注入形成的P+掺杂区，以及进行氮离子注入形成的N+源区，且所述P+掺杂区和N+源区相邻，所述N+源区和所述JFET区之间间隔沟道；
在所述沟道和部分N+源区上的第一栅氧化层和在所述JFET区上的第二栅氧化层，优选所述第一栅氧化层和所述第二栅氧化层均为SiO2；以及
所述第一栅氧化层和所述第二栅氧化层上淀积的多晶硅栅。
进一步地，所述器件还包括
源极，覆盖在P+掺杂区和相邻的N+源区的部分表面；
漏极，覆盖在N+衬底背面；
且所述碳化硅衬底和所述N型外延层之间还包括N型缓冲层。
在本发明的优选实施方式中，所述P阱的结深为0.5-1.0μm，优选0.6-0.8μm，例如0.6-0.65μm，或0.65-0.70μm，或0.70-0.75μm，或0.75-0.80μm，或0.80-0.90μm，或0.90-1.0μm；铝离子峰值掺杂浓度为1×1018cm-3-1×1019cm-3，优选1×1018cm-3-5×1018cm-3，更优选2×1018cm-3-4.5×1018cm-3。所述铝离子峰值掺杂浓度是在所述P阱中掺入的最大铝离子浓度。
在本发明的优选实施方式中，所述P+掺杂区的结深为0.2-0.3μm，铝离子掺杂浓度为1×1019cm-3-5×1019cm-3。
在本发明的优选实施方式中，所述N+源区的结深为0.2-0.3μm，氮离子掺杂浓度为1×1019cm-3-1×1020cm-3，优选5×1019cm-3-1×1020cm-3。
根据本发明提供的碳化硅MOSFET器件，P+掺杂区、所述N+源区和沟道区各自的宽度和宽度比例可由本领域技术人员常规设定。
在本发明的优选实施方式中，所述N型外延层的厚度为10-13μm，氮离子掺杂浓度为1×1015cm-3-9×1015cm-3。
在本发明的优选实施方式中，所述多晶硅栅的厚度为0.4μm-1μm，优选0.4-0.6μm，磷离子掺杂浓度为1×1020cm-3-3×1020cm-3。
在本发明的优选实施方式中，N型缓冲层的厚度为1-2μm，氮离子掺杂浓度为1×1018cm-3量级。
根据本发明，在源极和漏极上淀积的金属以及厚度均可由本领域技术人员根据需要来确定。在本发明中，所述金属优选为Ni、Ti和Al中的至少一种，更优选为Ni/Al合金。在本发明的优选实施方式中，源极覆盖厚度为30-100nm的Ni和厚度为1-3μm的Al。在本发明的优选实施方式中，漏极覆盖厚度为30-100nm的Ni和厚度为1-3μm的Al。
根据本发明提供的碳化硅MOSFET器件的导通电阻比具有相同耐压等级(例如600V-3300V)的常规碳化硅MOSFET器件具有更低的导通电阻，例如可低至8mΩ·cm2以下，甚至低至6mΩ·cm2以下，例如在3-6mΩ·cm2的范围。
本发明提供的碳化硅MOSFET器件尤其适合作为平面型功率器件的有源区的元胞。如本文附图1显示的碳化硅MOSFET器件仅为功率器件的有源区的元胞的一半，另一半 与图1所示的结构成镜面构象。本发明提供的碳化硅MOSFET器件元胞包括例如图1所示的构造和与其成镜面构象的构造。需注意，本文中给出的各部件的尺寸中，P阱区宽度、JFET区宽度、P+掺杂区宽度、第二栅氧化层宽度、多晶硅栅宽度、源极宽度尺寸均基于整个元胞计，即为图1所显示的相应部件的尺寸的两倍，其他宽度尺寸基于图1所示的半个元胞计。
根据本发明的另一方面，提供了一种如上的碳化硅MOSFET器件的制备方法，该方法包括在形成所述器件的栅氧化层的过程中制造第二栅氧化层和第一栅氧化层，且使第二栅氧化层的厚度大于所述第一栅氧化层的厚度；优选所述第二栅氧化层的厚度是所述第一栅氧化层的厚度的1.5-4倍，优选2-4倍，更优选2-3倍。如上所述，所述第一栅氧化层的厚度优选为40-80nm，优选40-60nm；和/或，所述第二栅氧化层的厚度优选为60-320nm，优选为80-240nm，更优选80-180nm。
在制造方法允许的情况下，可以分别制造或一起构造第二栅氧化层和第一栅氧化层，且第二栅氧化层和第一栅氧化层的构造顺序不限。在本发明的优选实施方式中，如下文所述，从工艺难易的角度考虑，先后制造第二栅氧化层和第一栅氧化层。
在本发明的优选实施方式中，所述方法包括：
依次相邻的JFET区、沟道、N+源区和P+掺杂区的形成，然后在其上第一次生成栅氧化层介质，刻蚀除去部分栅氧化层介质，以在JFET区上形成所述第二栅氧化层；
在被刻蚀除去部分栅氧化层介质的区域上进行第二次生成栅氧化层介质，且第二次生成的栅氧化层介质的厚度比第一次生成的栅氧化层介质的厚度小；
接着在形成的所述第二栅氧化层和第二次生成的栅氧化层介质上进一步淀积多晶硅；
刻蚀P+掺杂区和部分N+源区的栅氧化层介质和多晶硅，形成所述第一栅氧化层，以及覆盖所述第一栅氧化层和第二栅氧化层的多晶硅栅。
优选地，第一次生成的栅氧化层介质的厚度为40-80nm，优选40-60nm；和/或，所述第二次生成的栅氧化层介质的厚度为60-320nm，优选80-320nm，更优选80-180nm。所述栅氧化层介质可选自本领域常规应用的介质，优选为SiO2。
在本发明的优选实施方式中，所述依次相邻的JFET区、沟道、N+源区和P+掺杂区的形成的过程如下：
提供碳化硅衬底；
在所述碳化硅衬底上外延生长N型外延层；
在所述N型外延层上进行铝离子注入(可进行多次，如3-4次的注入)，以形成P阱，其中，所述P阱的宽度小于所述碳化硅衬底宽度，在所述N型外延层上与所述P阱 并列的区域为JFET区；
在所述P阱上分别进行铝离子注入和氮离子注入，以形成相邻的P+掺杂区和N+源区，且所述N+源区和所述JFET区之间形成沟道。
根据本发明的制备方法，还包括淀积层间介质，主要是SiO2，刻蚀形成欧姆接触孔。层间介质的淀积可由本领域技术人员来常规操作。
根据本发明的制备方法，还包括：在P+掺杂区和相邻的N+源区的部分表面上溅射欧姆接触金属，优选是Ni和Al，形成源极；在碳化硅衬底背面溅射欧姆接触金属，优选是Ni和Al，形成漏极。
溅射的合金作为源极和漏极的欧姆接触金属。在溅射金属层后，将器件在800℃-1000℃氮气氛围中进行退火，例如2-5分钟。
在本发明提供的制备方法的优选实施方式中，将所述P阱的结深设置为0.5-1.0μm，优选0.6-0.9μm，铝离子峰值掺杂浓度为1×1018cm-3-1×1019cm-3，优选1×1018cm-3-5×1018cm-3。
在本发明提供的制备方法的优选实施方式中，将所述P+掺杂区的结深设置为0.2-0.3μm，铝离子掺杂浓度为1×1019cm-3-5×1019cm-3。
在本发明提供的制备方法的优选实施方式中，将所述N+源区的结深设置为0.2-0.3μm，氮离子掺杂浓度为1×1019cm-3-1×1020cm-3，优选5×1019cm-3-5×1019cm-3。
在本发明提供的制备方法的优选实施方式中，将所述N型外延层的厚度设置为10-13μm，氮离子掺杂浓度为1×1015cm-3-9×1015cm-3。
在本发明提供的制备方法的优选实施方式中，将所述多晶硅栅的厚度设置为0.4μm-1.0μm，优选0.4-0.6μm，磷离子掺杂浓度为1×1020cm-3-3×1020cm-3。
在本发明提供的制备方法的优选实施方式中，通过刻蚀除去一部分第一次生成的第二栅氧化介质，使所述第二栅氧化层与所述器件的JFET区的宽度比在2:3至1:1的范围，优选3:4至1:1，更优选在1:1。
在本发明提供的制备方法的优选实施方式中，将所述器件的JFET区的宽度的构造为2-6μm，优选3-5.5μm，优选3.2-5μm。
根据本发明的优选实施方式，所述第一次生成采用低压化学气相淀积、湿氧热氧化技术或干氧热氧化技术。进一步优选地，所述第二次生成采用干氧热氧化技术，并优选在高温氧化炉中在1200-1350℃下进行。
在本发明的优选实施方式中，第二次生成采用干氧热氧化技术，而第一次生成则可以选择低压化学气相淀积或湿氧热氧化技术。这样形成的第一栅氧化层具有比第二栅氧化层更高的致密性，有利于阈值电压和栅氧化层的稳定性，及器件工作可靠性，而对于形成第 二栅氧化层的第一次生成，不需要采用干氧热氧化技术来进行，不仅降低了工艺难度，还节约技术成本和时间成本。
本发明提供的碳化硅MOSFET器件的制备方法采用了栅氧化层的选择性刻蚀与二次热氧化生长，构造出了具有阶梯形的栅氧化层，从而改善了碳化硅MOSFET器件的耐压性和导通电阻等的性能。
在本发明的一个具体实施方式中，提供了一种碳化硅MOSFET器件的制备方法，包括以下步骤：
S1：提供碳化硅衬底；
S2：在碳化硅衬底上生长N型缓冲层，优选厚度为为1-2μm，氮离子掺杂浓度为1×1018cm-3量级；
S3：在所述N型缓冲层上外延生长N型外延层，优选其厚度为10-13μm，氮离子掺杂浓度为1×1015cm-3-9×1015cm-3；
S4：在所述N型外延层上注入铝离子，形成P阱，优选其结深为0.5-1.0μm，优选0.6-0.8μm，铝离子峰值掺杂浓度为1×1018cm-3-5×1018cm-3；所述P阱的宽度小于所述碳化硅衬底宽度，在所述N型外延层上与所述P阱并列的区域为JFET区；
S5：在所述P阱上注入铝离子，形成P+掺杂区，优选其结深为0.2-0.3μm，铝离子掺杂浓度为1×1019cm-3-5×1019cm-3；
S6：在所述P阱上与所述P+掺杂区相邻的区域注入氮离子，形成N+源区，优选其结深为0.2-0.3μm，氮离子掺杂浓度为1×1019cm-3-5×1019cm-3；所述N+源区和所述JFET区之间形成沟道；
S7：在所述JFET区、沟道、N+源区和P+掺杂区上第一次生成SiO2，厚度为80-240nm，优选80-180nm，所述第一次生成优选采用低压化学气相淀积、湿氧热氧化技术或干氧热氧化技术；
S8：刻蚀除去部分SiO2，以形成第二栅氧化层，所述第二栅氧化层覆盖所述器件的JFET区上方的至少部分区域，且所述第二栅氧化层与JFET区的宽度比在2:3至1:1的范围；
S9：在所述JFET区、沟道、N+源区和P+掺杂区上除去所述第二栅氧化层区域之外的区域第二次生成SiO2，厚度为40-80nm，所述第二次生成优选采用干氧热氧化技术，温度为1200-1350℃；
S10：在所形成的SiO2上淀积多晶硅，优选厚度为0.4-0.6μm，磷离子掺杂浓度为1×1020cm-3-3×1020cm-3；
S11：刻蚀除去所述P+掺杂区和部分N+源区上的SiO2和多晶硅，形成多晶硅栅电极图 形；
S12：淀积层间介质，然后经刻蚀形成欧姆接触孔；
S13：在P+掺杂区和部分N+源区上以及碳化硅衬底背面溅射Ni，在800-1000℃惰性气氛下退火例如2-5分钟，优选形成的Ni层厚度为30-100nm；
S14：在Ni层上溅射Al，优选形成的Al层厚度为1-3μm。
在本发明中，适用的碳化硅衬底为本领域常规应用的碳化硅衬底，在本发明中优选高掺杂的N型(N+型)碳化硅衬底。
在本发明中，所述刻蚀优选干法刻蚀，并优选反应离子刻蚀(Reactive Ion Etching，RIE)。RIE原理是当在平板电极之间施加10-100MHZ的高频电压时会产生数百微米厚的离子层，在其中放入试样，离子高速撞击试样而完成化学反应蚀刻。
在本发明中，例如“上”、“上方”、“之上”或“下方”等方位是指器件在正常使用状态下各区域或各部件等的相对位置关系。
在本发明中，单位“cm-3”是指“个/cm-3”。
本发明提供的碳化硅MOSFET器件，具有经过改进的特定结构的栅氧化层，即具有阶梯形栅氧化层结构。尤其是JFET区上方的栅氧化层较厚，而沟道区域上方的栅氧化层厚度较薄。在有效减小栅氧化层电场强度的同时，不致影响器件阈值电压和栅控特性。即在不增大器件阈值电压和导通电阻的前提下，能够增强栅氧化层耐压能力与可靠性，继而可充分扩展设计余量，通过采用较宽的JFET区结构，进一步减小器件导通电阻，例如可减小至8mΩ·cm2以下，甚至6mΩ·cm2以下。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。
图1为根据本发明一个具体实施方式提供的具有阶梯型栅氧化层的碳化硅MOSFET器件的结构示意图。
图2为根据本发明一个具体实施方式制备本发明具有阶梯型栅氧化层的碳化硅MOSFET器件的流程框图。
图3，包括图3a-图3j，为根据本发明一个具体实施方式制备本发明具有阶梯型栅氧化层的碳化硅MOSFET器件的图示流程图。
其中，1为碳化硅N型衬底；2为N型缓冲层；3为N型外延层；4为P阱；5为JFET区；6为沟道区；7为P+掺杂区；8为N+源区；9和9’为栅氧化层介质，其中9-1为第一 栅氧化层，9-2为第二栅氧化层；10为多晶硅栅；11为源极；12为漏极。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。
在本发明的一个具体实施方式中，本发明提供的碳化硅MOSFET器件如图1所示，包括由第一栅氧化层9-1和第二栅氧化层9-2构成的栅氧化层，其中，所述第二栅氧化层9-2的厚度大于所述第一栅氧化层9-1的厚度，即所述栅氧化层呈阶梯状结构。
如前文所述，所述第二栅氧化层9-2的厚度是所述第一栅氧化层9-1的厚度的1.5-4倍，优选2-4倍，更优选2-3倍。所述第一栅氧化层9-1的厚度可以为40-80nm，优选40-60nm。所述第二栅氧化层9-2的厚度可以为60-320nm，优选为80-240nm，更优选80-180nm。
如图1所显示的，该碳化硅MOSFET器件具体包括：碳化硅衬底1，在所述碳化硅衬底上形成的N型缓冲层2，在N型缓冲层2上外延生长的N型外延层3，在N型外延层3经铝离子注入形成的P阱4，在N型外延层3上与P阱4并列的JFET区5，在所述P阱4上进行铝离子注入形成的P+掺杂区7和进行氮离子注入形成的N+源区8，以及N+源区8和JFET区5之间形成的沟道区6。
如图所示，在此具体实施方式中，第一栅氧化层9-1覆盖沟道区6和部分N+源区8，第二栅氧化层9-2覆盖JFET区5，在第一栅氧化层9-1和第二栅氧化层9-2上面覆盖多晶硅栅10。如前文所述，在其他实施方式中，第二栅氧化层9-2可以仅覆盖JFET区5的一部分，例如覆盖JFET区5的2/3至1，同时，JFET区5的剩余部分被第一栅氧化层9-1所覆盖。其中，JFET区宽度在2-6μm的范围；第一栅氧化层覆盖N+源区的宽度的20％至60％。
进一步地，该碳化硅MOSFET器件还包括P+掺杂区7和部分N+源区8上的源极11和碳化硅衬底1下的漏极12。源极11和漏极12可以由Ni和Al构成，例如包括30-100nm的Ni层和厚度为1-3μm的Al层。源极与栅氧化层和多晶硅栅之间存在层间介质，可通过常规方式来构造。各部件的厚度或结深、离子掺杂量等特征可在前文所述的范围进行选择。
本发明提供的碳化硅MOSFET器件可用于构成功率器件有源区，为构成所述有源区的元胞。需要注意的是，图1仅示意性地示出元胞的一半，即本发明所提供的完整的碳化硅MOSFET器件包括图1所述的构造和与图1成镜像的另一半构造。当然，如图1所显示的半元胞也在本发明的范围内。
在启用本发明提供的碳化硅MOSFET器件时，在所述器件的栅电极上施加高于阈值电压的电压偏置，沟道区域表面形成反型层，器件内部纵向导电通路形成，其电流随栅电压变化，且漏极-源极间压降很小，器件进入导通状态，呈现低的栅控电阻特性。在器件栅电极上施加零偏置或负偏置，沟道闭合，器件内部纵向导电通路关断，器件高阻漂移区承受高的漏极-源极电压，器件进入阻断状态。
在本发明的一个具体实施方式中，可以通过如图2所示的工艺流程来制备所述碳化硅MOSFET器件。该工艺流程包括在碳化硅衬底上外延生长N型外延层，离子注入形成P阱，离子注入形成P+欧姆接触区，离子注入形成N+源区，淀积或热氧化生长SiO2介质，刻蚀除去JFET区上方以外的SiO2介质，干氧热氧化生长SiO2栅介质，形成栅极多晶硅，刻蚀除去部分干氧热氧化生长的SiO2栅介质以形成多晶硅栅图形，以及形成欧姆接触电极的步骤。可见，本发明提供的制备方法包括淀积SiO2介质-选择性刻蚀-二次生成SiO2介质的过程，以分别形成第一栅氧化层和第二栅氧化层。
下面结合图3，通过本发明的一个具体实施方式对所提供的碳化硅MOSFET器件的制备方法做示例性的具体说明。
碳化硅MOSFET器件的制备方法具体包括以下步骤。
1)在所提供碳化硅衬底1上生成N型缓冲层2，其厚度为1-2μm、氮离子掺杂浓度为1×1018cm-3；然后在所述N型缓冲层2上外延生长N型外延层3，其厚度为10-13μm，氮离子掺杂浓度为1×1015cm-3-9×1015cm-3，如图3a所示。
2)在所述N型外延层3上注入铝离子，形成P阱4，其结深为0.5-1.0μm，铝离子峰值掺杂浓度为1×1018cm-3-1×1019cm-3；所述P阱4的宽度小于所述碳化硅衬底1宽度，在所述N型外延层3上与所述P阱4并列的区域为JFET区5，所述JFET区5的宽度为2-6μm，如图3b所示。
3)在所述P阱4上注入铝离子，形成P+掺杂区7，其结深为0.2-0.3μm，铝离子掺杂浓度为1×1019cm-3-5×1019cm-3，如图3c所示。
4)在所述P阱4上与所述P+掺杂区7相邻的区域注入氮离子，形成N+源区8，其结深为0.2-0.3μm，氮离子掺杂浓度为5×1019cm-3-1×1020cm-3；所述N+源区7和所述JFET区5之间形成沟道区6，如图3d所示。
5)采用湿氧热氧化技术，在高温氧化炉中1000℃-1300℃的温度下，反应 10min-50min，在所述JFET区5、沟道6、N+源区8和P+掺杂区7上第一次生成SiO2栅介质9，厚度为80-320nm，优选80-180nm的SiO2栅介质9，如图3e所示。
6)采用RIE法刻蚀除去所述JFET区上方以外的SiO2栅介质9，以形成第二栅氧化层9-2，所述第二栅氧化层9-2与JFET区5的宽度比在2:3至1:1的范围，如图3f所示。
7)采用干氧热氧化技术，在高温氧化炉中，1000℃-1350℃温度下，反应20min-100min，以在所述JFET区5、沟道区6、N+源区8和P+掺杂区7上除去所述第二栅氧化层9-2区域之外的区域第二次生成SiO2栅介质9’，厚度为40-80nm，如图3g所示。
8)采用低压化学气相淀积法，在栅介质9’和第二栅氧化层9-2上淀积多晶硅，其厚度为0.4-1.0μm，磷离子掺杂浓度为1×1020cm-3-3×1020cm-3，如图3h所示。
9)采用RIE法刻蚀除去所述P+掺杂区7和部分N+源区8上的SiO2和多晶硅，形成第一栅氧化层9-1和多晶硅栅10，如图3i所示。
10)淀积层间介质，主要是SiO2，刻蚀形成欧姆接触孔。
11)在P+掺杂区和部分N+源区上以及碳化硅衬底背面溅射30-100nm的Ni，在800℃-1000℃氮气氛围中退火2-5min，继续溅射1-3μm的Al，腐蚀形成源极11和漏极12，并形成欧姆接触区，如图3j所示。
实施例1
采用上述方法制备得到耐压等级为1200V的碳化硅MOSFET器件a，具体特征：在碳化硅衬底上的N型缓冲层为1μm；N型外延层厚度12μm，氮离子掺杂浓度8.5×1015cm-3；P阱结深为0.9μm，铝离子掺杂浓度为1×1018cm-3；P+掺杂区的结深为0.3μm，铝离子掺杂浓度为1×1019cm-3；N+源区的结深为0.3μm，氮离子掺杂浓度为1×1019cm-3；JFET区宽度为3μm；沟道宽度为1μm；第二栅氧化层和第一栅氧化层的宽度分别为3μm和10μm，厚度分别为120nm和60nm；多晶硅栅的厚度为0.6μm，磷离子掺杂浓度为1×1020cm-3；源极和漏极溅射30nm的Ni和3μm的Al。
通过Silvaco TCAD仿真软件，器件a在阻断电压1200V下工作时，JFET区上方栅氧化层(第一栅氧化层和第二栅氧化层)处峰值电场强度为1.2MV/cm，电场集中得到有效抑制。在导通状态下工作时，1.6V正向压降下导通电阻为5.6mΩ·cm2。
实施例2
通过类似方法制备得到耐压等级为1200V的碳化硅MOSFET器件b，与器件a的区别在于：JFET区宽度为5μm；第二栅氧化层和第一栅氧化层的宽度分别为5μm和10μm， 厚度分别为120nm和60nm。
采用与实施例1中相同的方式，对器件b进行电学特性仿真。器件b在阻断电压1200V下工作时，JFET区上方栅氧化层处峰值电场强度为1.5MV/cm，电场集中得到有效抑制。而在导通状态下工作时，1.6V正向压降下导通电阻为5.3mΩ·cm2，优于器件a。
实施例3
采用类似方法制造耐压等级为1200V的碳化硅MOSFET器件c，具有以下特征：在碳化硅衬底上的N型缓冲层为1μm；N型外延层厚度10μm，氮离子掺杂浓度6×1015cm-3；P阱结深为0.9μm，铝离子掺杂浓度为1×1018cm-3；P+掺杂区的结深为0.3μm，铝离子掺杂浓度为1×1019cm-3；N+源区的结深为0.3μm，氮离子掺杂浓度为1×1019cm-3；JFET区宽度为3μm；沟道宽度为1μm；第二栅氧化层和第一栅氧化层的宽度分别为2μm和10μm，厚度分别为150nm和50nm；多晶硅栅的厚度为0.6μm，磷离子掺杂浓度为1×1020cm-3；源极和漏极溅射30nm的Ni和3μm的Al。
采用与实施例1中相同的方式，对器件c进行电学特性仿真。器件c在阻断电压1200V下工作时，JFET区上方栅氧化层处峰值电场强度为1.7MV/cm，电场集中得到有效抑制。
对比例1
采用与制备器件a类似的步骤制备器件d，不同之处在于，省去上述步骤6)和7)，得到的器件d与器件a的区别在于：器件d具有厚度单一的栅氧化层，为60nm。
采用与实施例1相同的方法对器件d进行电学特性仿真。器件d在阻断电压1200V下工作时，JFET区上方栅氧化层处峰值电场为3.6MV/cm，电场集中现象较为严重。在这种情况下，若氧化层质量不高，较易发生失效。在导通状态下工作时，1.6V正向压降下导通电阻为5.9mΩ·cm2。
由以上仿真结果显示了，通过采用本发明的阶梯形栅氧化层结构，能够有效削弱器件JFET区上方栅氧化层的电场强度，由此可采用较宽的JFET区设计，实现更低的导通电阻。
例如，对比实施例1与对比例1仿真结果，通过采用本发明的阶梯形栅氧化层结构，能够有效削弱器件JFET区上方栅氧化层的电场强度，由传统结构的3.6MV/cm下降至1.2MV/cm。
此外，对比实施例2与实施例1仿真结果，在实施例1基础上适度增大JFET区宽度， 可使导通电阻由5.6mΩ·cm2降低至5.3mΩ·cm2，同时JFET区上方栅氧化层的电场强度维持在1.5MV/cm，仍远低于对比例1。对比实施例3与实施例1仿真结果，第二栅氧化层与JFET区宽度比值1：1时，电场强度抑制效果更佳，达到1.2MV/cm，优于2：3时的1.7MV/cm。
本发明所采用的湿氧热氧化技术、RIE干法刻蚀、干氧热氧化技术和低压化学气相淀积法等均为本领域已知并常用的技术，为简要起见，本发明中不做具体介绍。
虽然本发明已作了详细描述，但对本领域技术人员来说，在本发明精神和范围内的修改将是显而易见的。此外，应当理解的是，本发明记载的各方面、不同具体实施方式的各部分、和列举的各种特征可被组合或全部或部分互换。在上述的各个具体实施方式中，那些参考另一个具体实施方式的实施方式可适当地与其它实施方式组合，这是将由本领域技术人员所能理解的。此外，本领域技术人员将会理解，前面的描述仅是示例的方式，并不旨在限制本发明。

Claims (21)

  1. 一种碳化硅MOSFET器件，包括由第一栅氧化层和第二栅氧化层构成的栅氧化层，其中，所述第二栅氧化层的厚度大于所述第一栅氧化层的厚度。
  2. 根据权利要求1所述的器件，其特征在于，所述第二栅氧化层的厚度是所述第一栅氧化层的厚度的1.5-4倍，优选2-4倍，更优选2-3倍。
  3. 根据权利要求1或2所述的器件，其特征在于，所述第一栅氧化层的厚度为40-80nm，优选40-60nm；和/或，所述第二栅氧化层的厚度为60-320nm，优选80-240nm。
  4. 根据权利要求1-3中任一项所述的器件，其特征在于，所述第一栅氧化层与所述器件的沟道、部分N+源区和任选地一部分JFET区相对应，所述第二栅氧化层与所述器件的至少一部分JFET区相对应；优选所述第一栅氧化层覆盖所述N+源区宽度的20％至60％。
  5. 根据权利要求1-4中任一项所述的器件，其特征在于，所述第二栅氧化层与所述器件的JFET区的宽度比在2:3至1:1的范围，优选3:4至1:1，更优选在1:1。
  6. 根据权利要求1-5中任一项所述的器件，其特征在于，所述器件的JFET区宽度为2-6μm，优选3.2-5.5μm。
  7. 根据权利要求1-6中任一项所述的器件，其特征在于，所述器件包括：
    碳化硅衬底；
    在所述碳化硅衬底上外延生长的N型外延层；
    在所述N型外延层上经铝离子注入形成的P阱，所述P阱的宽度小于所述碳化硅衬底宽度；
    JFET区，为N型外延层上与所述P阱并列的区域；
    在所述P阱上进行铝离子注入形成的P+掺杂区，以及进行氮离子注入形成的N+源区，且所述P+掺杂区和N+源区相邻，所述N+源区和所述JFET区之间间隔沟道；
    在所述沟道和部分N+源区上的第一栅氧化层和在所述JFET区上的第二栅氧化层，优选所述第一栅氧化层和所述第二栅氧化层均为SiO2；以及
    所述第一栅氧化层和所述第二栅氧化层上淀积的多晶硅栅。
  8. 根据权利要求1-7中任一项所述的器件，其特征在于，所述器件还包括：
    源极，覆盖在P+掺杂区和相邻的N+源区的部分表面；
    漏极，覆盖在N+衬底背面；
    且所述碳化硅衬底和所述N型外延层之间还设有N型缓冲层。
  9. 根据权利要求7或8所述的器件，其特征在于，所述P阱的结深为0.5-1.0μm，优选0.6-0.8μm；铝离子峰值掺杂浓度为1×1018cm-3-1×1019cm-3，优选1×1018cm-3-5×1018cm-3。
  10. 根据权利要求7-9中任一项所述的器件，其特征在于，
    所述P+掺杂区的结深为0.2-0.3μm，铝离子掺杂浓度为1×1019cm-3-5×1019cm-3；和/或
    所述N+源区的结深为0.2-0.3μm，氮离子掺杂浓度为1×1019cm-3-1×1020cm-3。
  11. 根据权利要求7-10中任一项所述的器件，其特征在于，所述N型外延层的厚度为10-13μm，氮离子掺杂浓度为1×1015cm-3-9×1015cm-3；和/或
    所述多晶硅栅的厚度为0.4-0.6μm，磷离子掺杂浓度为1×1020cm-3-3×1020cm-3。
  12. 根据权利要求1-11中任一项所述的器件，其特征在于，所述器件的导通电阻在6mΩ·cm2以下，优选1-5.5mΩ·cm2。
  13. 一种根据权利要求1-12中任一项所述的碳化硅MOSFET器件的制备方法，包括在形成所述器件的栅氧化层的过程中制造第二栅氧化层和第一栅氧化层，且使第二栅氧化层的厚度大于所述第一栅氧化层的厚度；优选所述第二栅氧化层的厚度是所述第一栅氧化层的厚度的1.5-4倍，优选2-4倍。
  14. 根据权利要求13所述的制备方法，其特征在于，所述方法包括依次相邻的JFET区、沟道、N+源区和P+掺杂区的形成，然后在其上第一次生成栅氧化层介质，刻蚀除去部分栅氧化层介质，以在JFET区上形成所述第二栅氧化层；
    在被刻蚀除去部分栅氧化层介质的区域上进行第二次生成栅氧化层介质，且第二次生成的栅氧化层介质的厚度比第一次生成的栅氧化层介质的厚度小；
    接着在形成的所述第二栅氧化层和第二次生成的栅氧化层介质上进一步淀积多晶硅；
    刻蚀P+掺杂区和部分N+源区的栅氧化层介质和多晶硅，形成所述第一栅氧化层以及覆盖所述第一栅氧化层和第二栅氧化层的多晶硅栅。
  15. 根据权利要求14所述的制备方法，其特征在于，第一次生成的栅氧化层介质的厚度为40-80nm，优选40-60nm；和/或，所述第二次生成的栅氧化层介质的厚度为60-320nm，优选80-240nm。
  16. 根据权利要求15所述的制备方法，其特征在于，所述依次相邻的JFET区、沟道、N+源区和P+掺杂区的形成的过程如下：
    提供碳化硅衬底；
    在所述碳化硅衬底上外延生长N型外延层；
    在所述N型外延层上进行铝离子注入，以形成的P阱，其中，所述P阱的宽度小于 所述碳化硅衬底宽度，在所述N型外延层上与所述P阱并列的区域为JFET区；
    在所述P阱上分别进行铝离子注入和氮离子注入，以形成相邻的P+掺杂区和N+源区，且所述N+源区和所述JFET区之间形成沟道。
  17. 根据权利要求16所述的制备方法，其特征在于，所述方法还包括在P+掺杂区和相邻的N+源区的部分表面上溅射欧姆接触金属，优选Ni和Al，形成源极；在碳化硅衬底背面溅射欧姆接触金属，优选Ni和Al，形成漏极。
  18. 根据权利要求16或17所述的制备方法，其特征在于，
    所述P阱的结深为0.5-1.0μm，铝离子峰值掺杂浓度为1×1018cm-3-1×1019cm-3；
    所述P+掺杂区的结深为0.2-0.3μm，铝离子掺杂浓度为1×1019cm-3-5×1019cm-3；
    所述N+源区的结深为0.2-0.3μm，氮离子掺杂浓度为1×1019cm-3-1×1020cm-3；
    所述N型外延层的厚度为10-13μm，氮离子掺杂浓度为1×1015cm-3-9×1015cm-3；和/或
    所述多晶硅栅的厚度为0.4-0.6μm，磷离子掺杂浓度为1×1020cm-3-3×1020cm-3。
  19. 根据权利要求15-17中任一项所述的制备方法，其特征在于，所述第二栅氧化层与所述器件的JFET区的宽度比在2:3至1:1的范围，优选在1:1；
    优选所述器件的JFET区宽度为2-6μm，优选3.2-5μm。
  20. 根据权利要求15所述的制备方法，其特征在于，所述第一次生成采用低压化学气相淀积、湿氧热氧化技术或干氧热氧化技术；所述第二次生成采用干氧热氧化技术，优选在1200-1350℃下进行。
  21. 一种碳化硅MOSFET器件的制备方法，包括以下步骤：
    S1：提供碳化硅衬底；
    S2：在碳化硅衬底上生长N型缓冲层，优选厚度为为1-2μm，氮离子掺杂浓度为1×1018cm-3量级；
    S3：在所述N型缓冲层上外延生长N型外延层，优选其厚度为10-13μm，氮离子掺杂浓度为1×1015cm-3-9×1015cm-3；
    S4：在所述N型外延层上注入铝离子，形成P阱，优选其结深为0.5-1.0μm，铝离子峰值掺杂浓度为1×1018cm-3-5×1018cm-3；所述P阱的宽度小于所述碳化硅衬底宽度，在所述N型外延层上与所述P阱并列的区域为JFET区；
    S5：在所述P阱上注入铝离子，形成P+掺杂区，优选其结深为0.2-0.3μm，铝离子掺杂浓度为1×1019cm-3-5×1019cm-3；
    S6：在所述P阱上与所述P+掺杂区相邻的区域注入氮离子，形成N+源区，优选其结深 为0.2-0.3μm，氮离子掺杂浓度为1×1019cm-3-5×1019cm-3；所述N+源区和所述JFET区之间形成沟道；
    S7：在所述JFET区、沟道、N+源区和P+掺杂区上第一次生成SiO2，厚度为80-240nm，所述第一次生成优选采用低压化学气相淀积、湿氧热氧化技术或干氧热氧化技术；
    S8：刻蚀除去部分SiO2，以形成第二栅氧化层，所述第二栅氧化层与所述器件的JFET区的宽度比在2:3至1:1的范围；
    S9：在所述JFET区、沟道、N+源区和P+掺杂区上除去所述第二栅氧化层区域之外的区域第二次生成SiO2，厚度为40-80nm，所述第二次生成优选采用干氧热氧化技术，温度为1200-1350℃；
    S10：在所形成的SiO2上淀积多晶硅，优选厚度为0.4-0.6μm，磷离子掺杂浓度为1×1020cm-3-3×1020cm-3；
    S11：刻蚀除去所述P+掺杂区和部分N+源区上的SiO2和多晶硅，形成多晶硅栅电极图形；
    S12：淀积层间介质，然后经刻蚀形成欧姆接触孔；
    S13：在P+掺杂区和部分N+源区上以及碳化硅衬底背面淀积Ni，在800-1000℃惰性气氛下退火，优选形成的Ni层厚度为30-100nm；
    S14：在Ni层上淀积Al，优选形成的Al层厚度为1-3μm。
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