WO2016185802A1 - 駆動回路 - Google Patents
駆動回路 Download PDFInfo
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- WO2016185802A1 WO2016185802A1 PCT/JP2016/059959 JP2016059959W WO2016185802A1 WO 2016185802 A1 WO2016185802 A1 WO 2016185802A1 JP 2016059959 W JP2016059959 W JP 2016059959W WO 2016185802 A1 WO2016185802 A1 WO 2016185802A1
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- drive circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
- H03K17/163—Soft switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/18—Modifications for indicating state of switch
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/033—Monostable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K2017/0806—Modifications for protecting switching circuit against overcurrent or overvoltage against excessive temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
Definitions
- the present invention relates to a drive circuit.
- a level shift circuit in the drive circuit converts a low voltage signal into a high voltage signal, and a switch element such as a transistor is controlled based on this signal. When the switch element is turned off, a hard shutdown is performed (see, for example, Patent Documents 1 and 2).
- Patent Document 1 Japanese Patent Application Laid-Open No. 9-200017
- Patent Document 2 US Pat. No. 5,919,359
- a drive circuit may include a level shift circuit and a control unit.
- the level shift circuit may convert the input signal from the preceding circuit into a signal having a higher voltage than the input signal.
- the control unit may output a signal for softly shutting down the first switch element based on the output signal of the level shift circuit.
- the drive circuit may drive the first switch element.
- the pre-stage circuit may include an abnormality detection circuit.
- the control unit may determine whether to soft-shut down the first switch based on the output signal of the abnormality detection circuit.
- the first switch element may be switched on and off according to the input control signal.
- the drive circuit may further include a latch circuit.
- the latch circuit may generate a control signal corresponding to a set signal and a reset signal input from the previous stage circuit to the level shift circuit.
- the control unit may determine whether to soft-shut down the first switch element based on the output of the latch circuit and a state signal generated based on the output signal of the abnormality detection circuit.
- the control unit may soft-shut down the first switch element when the output signal of the latch circuit indicates that the first switch element should be turned on and the status signal indicates that an abnormality is detected in the preceding circuit. .
- the set signal may indicate a predetermined logical value when the first switch element is to be turned on.
- the reset signal may indicate a predetermined logic value when the first switch element is to be hard shut down.
- the status signal may indicate a predetermined logical value when an abnormality is detected in the preceding circuit. A malfunction that maintains ON or OFF of the first switch element when two or more of the set signal, the reset signal, and the status signal have predetermined logic values, except when the first switch element is softly shut down.
- the drive circuit may further include a protection circuit.
- the level shift circuit may include a status signal input circuit, a set signal input circuit, and a reset signal input circuit.
- the state signal input circuit may shift the level of the state signal.
- the set signal input circuit may shift the level of the set signal.
- the reset signal input circuit may shift the level of the reset signal.
- Each of the state signal input circuit, the set signal input circuit, and the reset signal input circuit may include a resistance element connected to the high potential side and a transistor having a drain connected to the low potential side of the resistance element.
- the high potential sides of the resistance elements are connected to each other, and the resistance value of the resistance elements and the characteristics of the transistors may be the same.
- the pre-stage circuit may determine whether to soft-shut down the first switch element based on the signal for controlling the first switch element input from the outside and the output signal of the abnormality detection circuit.
- the first switch The pre-stage circuit may output a state signal for softly shutting down the element to the level shift circuit.
- the control unit may shift to a hard shutdown of the first switch element after a predetermined period has elapsed after starting the soft shutdown of the first switch element.
- the control unit may determine a predetermined period according to the type of abnormality detected in the preceding circuit.
- the control unit may determine a time constant for soft shutdown according to the type of abnormality detected in the previous circuit.
- the pre-stage circuit may include a low side control circuit.
- the low side control circuit may control on and off of the second switch element connected in series to the low potential side of the first switch element.
- the abnormality detection circuit may include a circuit that detects the state of the second switch element.
- FIG. 3 is a diagram illustrating a drive circuit 100, a load 80, a power supply 82, a transistor 34, and a transistor 74.
- FIG. 3 is a diagram showing a part of a low-side control circuit 130. It is a figure which shows the example of the rising differential pulse generation circuit 241 and 247.
- FIG. 6 is a diagram illustrating an example of a falling differential pulse generation circuit 245.
- FIG. It is a figure which shows the operation
- 3 is a diagram illustrating a specific example of a high side control circuit 120.
- FIG. 4 is a diagram illustrating a first operation example of the drive circuit 100.
- FIG. 4 is a diagram illustrating a first operation example of the drive circuit 100.
- FIG. 7 is a diagram illustrating a second operation example of the drive circuit 100.
- FIG. 3 is a diagram showing a high-side control circuit 120.
- FIG. 3 is a diagram showing a high-side control circuit 120.
- FIG. 3 is a diagram showing a high-side control circuit 120.
- FIG. 10 is a diagram illustrating a first modification of the pre-stage circuit 200.
- FIG. 10 is a diagram illustrating a second modification of the pre-stage circuit 200.
- FIG. 10 is a diagram illustrating a third modification of the pre-stage circuit 200.
- FIG. 1 is a diagram showing a drive circuit 100, a load 80, a power source 82, a transistor 34 as a first switch element, and a transistor 74 as a second switch element.
- the drive circuit 100 includes a level shift circuit 70, a high side control circuit 120, and a low side control circuit 130 as a pre-stage circuit.
- the drive circuit 100 of this example is formed by being integrated on one semiconductor chip. However, the high side control circuit 120 and the pre-stage circuit may be formed on separate semiconductor chips as described in other examples.
- the level shift circuit 70 converts the input signal from the preceding circuit into an output signal having a voltage higher than that of the input signal.
- the high side control circuit 120 receives an input from the level shift circuit 70 and outputs a control signal HO to the transistor 34.
- the pre-stage circuit in this example is a low-side control circuit 130.
- the low side control circuit 130 inputs input signals to the set signal input terminal 12, the reset signal input terminal 14, and the state signal input terminal 16 of the level shift circuit 70.
- the drive circuit 100 drives the transistor 34 and the transistor 74.
- Transistor 34 and transistor 74 are connected in series to constitute an inverter circuit.
- the drive circuit 100 inputs / outputs a control signal to the gates of the transistor 34 and the transistor 74 to turn on / off the transistor 34 and the transistor 74.
- the transistor 34 is on, the load 80 and the high potential side of the power source 82 are connected.
- the transistor 74 is on, the load 80 is connected to a reference potential (ground potential).
- the transistor 34 and the transistor 74 in this example are NMOS transistors.
- the transistor 34 is provided between the load 80 and the positive electrode of the power source 82.
- the power source 82 is a power source having a voltage of 400 [V], for example.
- the drive circuit 100 drives the load 80 with a voltage of 0 [V] to 400 [V] by turning on and off the transistors 34 and 74 in a complementary manner. Note that in this specification, for the sake of brevity, the voltage drop due to the on-resistance of the transistor and the forward voltage of the diode are omitted. The voltage drop due to the on-resistance of the transistor and the forward voltage of the diode may be considered sufficiently smaller than the voltage value of the power supply 82.
- the potential of the negative electrode of the power source 35 connected to the drive circuit 100 is Vs.
- Vs may vary in the range of 0 [V] to 400 [V] depending on on / off of the transistor 34 and the transistor 74.
- the potential of the positive electrode of the power source 35 connected to the drive circuit 100 is Vb.
- the potential Vb is referred to as a high potential side of the driving circuit 100.
- Vb may vary in a range from E1 to (E1 + 400 [V]).
- E1 is, for example, 15 [V].
- the low side control circuit 130 includes a low side driver 72, a power source 76, a drive control circuit 131, and an abnormality detection circuit 210.
- the microcomputer 140 is provided outside or inside the drive circuit 100.
- the microcomputer 140 sends an input signal LIN to the drive control circuit 131.
- the drive control circuit 131 sends the input signal LIN to the low side driver 72.
- the low side driver 72 is driven by an input signal LIN of the microcomputer 140, outputs a control signal LO, and drives a transistor 74 as a switch element.
- the low side driver 72 turns on / off the transistor 74 by inputting the high potential side voltage or the low potential side voltage of the power source 76 to the gate of the transistor 74.
- the positive and negative electrodes of the power source 76 are connected to the low-side driver 72, the drive control circuit 131, and the abnormality detection circuit 210, respectively.
- the abnormality detection circuit 210 detects a voltage abnormality of the power supply 76 and outputs a signal to the drive control circuit 131.
- the drive control circuit 131 receives the input signal HIN from the microcomputer 140 and generates a set signal (set) and a reset signal (reset). set is input to the set signal input terminal 12, and reset is input to the reset signal input terminal 14. Further, the drive control circuit 131 generates a status signal (LER) based on the signal received from the abnormality detection circuit 210. LER is input to the status signal input terminal 16.
- the drive circuit 100 includes a state signal input circuit 40, a set signal input circuit 50, and a reset signal input circuit 60.
- the state signal input circuit 40, the set signal input circuit 50, and the reset signal input circuit 60 are collectively referred to as a level shift circuit 70.
- the state signal input circuit 40 includes a resistance element 42 connected to the high potential side of the drive circuit 100 and a transistor 46 having a drain 47 connected to the low potential side of the resistance element 42.
- the low potential side of the resistance element 42 means an end portion side of the resistance element 42 having two ends that is not connected to the high potential side.
- the set signal input circuit 50 also includes a resistance element 52 connected to the high potential side and a transistor 56 connected to the drain 57 on the low potential side of the resistance element 52.
- the reset signal input circuit 60 includes a resistance element 62 connected to the high potential side and a transistor 66 connected to the drain 67 on the low potential side of the resistance element 62.
- the high potential sides of the resistance elements 42, 52, and 62 are connected to each other.
- the resistance values of the resistance elements 42, 52 and 62 and the characteristics of the transistors 46, 56 and 66 are the same.
- the transistors 46, 56 and 66 in this example are NMOS transistors.
- the pre-stage circuit (drive control circuit 131) inputs a state signal (LER) to the state signal input terminal 16 which is the gate terminal of the transistor 46.
- the status signal input circuit 40 shifts the LER level.
- the state signal input circuit 40 shifts the voltage value of LER to LERdrn having a voltage value higher than LER.
- LER indicates a predetermined logical value when the transistor 34 is softly shut down to separate the high potential side of the power supply 82 and the load 80.
- the pre-stage circuit of this example inputs a high level LER to the state signal input terminal 16 when an abnormality is detected. Further, the pre-stage circuit of this example inputs a low-level LER to the state signal input terminal 16 when no abnormality is detected. Therefore, when the pre-stage circuit detects an abnormality, the transistor 34 is soft shut down.
- the transistor 46 When the transistor 46 is turned on by a high level LER, a voltage drop occurs in the resistance element 42. On the other hand, when the transistor 46 is turned off by the low level LER, no voltage drop occurs in the resistance element 42. Therefore, when a high-level LER is input, the LERdrn that is the potential of the drain 47 is lower than when a low-level LER is input. In summary, when LER is at a high level, LERdrn, which is the potential of the drain 47, is at a low level. On the other hand, when the LER is at a low level, the LERdrn that is the potential of the drain 47 is at a high level.
- the pre-stage circuit inputs a set signal (set) to the set signal input terminal 12 of the transistor 56.
- the set signal input circuit 50 shifts the set level.
- the set signal input circuit 50 shifts the voltage value of set to setdrn, which is a signal having a voltage value higher than set.
- “Set” indicates a predetermined logic value when the transistor 34 is turned on and the high potential side of the power source 82 and the load 80 are to be connected.
- the pre-stage circuit of this example may output a high level set to the set signal input circuit 50 when the transistor 34 is turned on.
- the pre-stage circuit inputs a reset signal (reset) to the reset signal input terminal 14 of the transistor 66.
- the reset signal input circuit 60 shifts the reset level.
- the reset signal input circuit 60 shifts the voltage value of reset to resdrn, which is a signal having a voltage value higher than reset.
- “Reset” indicates a predetermined logical value when the transistor 34 is turned off and the high potential side of the power source 82 and the load 80 should be separated.
- the pre-stage circuit of this example may output a low level reset to the drive circuit 100 when the transistor 34 is turned on. Note that the transistor 34 is turned on when the set is at a high level and the reset is at a low level.
- the functions of the resistance elements 52 and 62 are the same as those of the resistance element 42.
- the potential setdrn of the drain 57 is at a low level.
- the potential setdrn of the drain 47 is at a high level.
- the potential resdrn of the drain 67 is at a low level.
- the potential resdrn of the drain 47 is at a high level.
- the source 49 of the transistor 46 is grounded.
- a parasitic capacitance 48 is formed between the drain 47 and the source 49.
- the source 59 of transistor 46 and the source 69 of transistor 56 are similarly grounded.
- a parasitic capacitance 58 is formed between the drain 57 and the source 59, and a parasitic capacitance 68 is formed between the drain 67 and the source 69.
- the capacitances of the parasitic capacitors 48, 58 and 68 are the same.
- the status signal input circuit 40, the set signal input circuit 50, and the reset signal input circuit 60 have the same characteristics.
- Surge voltage is an instantaneous voltage change. Due to the switching operation of the transistor 34, current associated with the surge voltage flows from the line at the potential Vs through the diodes 45, 55 and 65 to the sources 49, 59 and 69. The current is represented by the product of the time variation (dv / dt) of the surge voltage and the capacitances (C) of the parasitic capacitors 48, 58 and 68. The current can cause a voltage drop in the resistance elements 42, 52 and 62.
- LERdrrn, resdrn and setdrn which are output signals of the drains 47, 57 and 67 can be at a low level. That is, the same situation can occur as when high-level LER, reset, and set are input to the transistors 46, 56, and 66, respectively. This is noise due to the surge voltage. The noise causes a malfunction of the drive circuit 100.
- the status signal input circuit 40, the set signal input circuit 50, and the reset signal input circuit 60 have the same characteristics. Therefore, noise is applied in the same manner in the state signal input circuit 40, the set signal input circuit 50, and the reset signal input circuit 60. Thereby, when noise occurs in the level shift circuit 70, the noise can be determined in a malfunction protection circuit 90 described later.
- the state signal input circuit 40 includes a diode 44 having a cathode connected to the high potential side of the drive circuit 100 and an anode connected to the low potential side of the resistance element 42.
- the set signal input circuit 50 includes a diode 54 having a cathode connected to the high potential side of the drive circuit 100 and an anode connected to the low potential side of the resistance element 52.
- the reset signal input circuit 60 includes a diode 64 having a cathode connected to the high potential side of the drive circuit 100 and an anode connected to the low potential side of the resistance element 62.
- the diodes 44, 54 and 64 clamp the potential of each anode to the potential of the positive electrode of the power supply 35 (ie, Vb).
- the drive circuit 100 includes a diode 45, a diode 55, and a diode 65.
- the anodes of the diodes 45, 55 and 65 are connected to the negative electrode of the power supply 35.
- the cathode of the diode 45 is connected to the drain 47 of the transistor 46.
- the cathode of the diode 55 is connected to the drain 57 of the transistor 56, and the cathode of the diode 65 is connected to the drain 67 of the transistor 66.
- the diodes 45, 55 and 65 clamp the potential of each cathode to the potential of the negative electrode of the power supply 35 (that is, Vs).
- FIG. 2 is a diagram showing a part of the low-side control circuit 130.
- 2 is a circuit example of the abnormality detection circuit 210 and the drive control circuit 131 excluding the low side driver 72 in the low side control circuit 130 in FIG.
- the pre-stage circuit 200 in FIG. 2 may be provided outside the drive circuit 100.
- the pre-stage circuit 200 inputs the state signal LER, the reset signal reset, and the set signal set to the level shift circuit 70.
- the pre-stage circuit 200 includes an abnormality detection circuit 210, an input buffer circuit 220, an AND logic circuit 230, and a pulse generation circuit 240.
- the abnormality detection circuit 210 includes a comparator 211, a reference power supply 212, and a noise filter 213.
- An abnormality detection signal is input to the abnormality detection circuit 210.
- the abnormality detection signal is a signal indicating whether or not an abnormality has occurred in another part of the pre-stage circuit 200.
- the abnormality detection signal is at a high level, it is assumed that an abnormality is detected in another part of the pre-stage circuit 200.
- the abnormality detection signal is at a low level, it is assumed that no abnormality is detected in other parts of the pre-stage circuit 200.
- a high level logical value is represented by H
- a low level logical value is represented by L.
- the comparator 211 compares the voltage value of the abnormality detection signal at the non-inverting input terminal with the reference voltage of the reference power supply 212 at the inverting input terminal.
- the comparator 211 outputs an H signal to the noise filter 213 when the voltage value of the abnormality detection signal is larger than the reference voltage of the reference power supply 212.
- the comparator 211 outputs an L signal to the noise filter 213 when the voltage value of the abnormality detection signal is smaller than the reference voltage of the reference power supply 212.
- the noise filter 213 removes noise from the output signal of the comparator 211.
- the input buffer circuit 220 has the same configuration as the abnormality detection circuit 210. However, in the input buffer circuit 220, the input signal HIN is input to the non-inverting input terminal of the comparator 211 instead of the abnormality detection signal.
- the comparator 221 outputs an H signal to the noise filter 223 when the voltage value of the input signal HIN is larger than the reference voltage of the reference power supply 222.
- the comparator 221 outputs an L signal to the noise filter 223 when the voltage value of the input signal HIN is smaller than the reference voltage of the reference power supply 222.
- the input signal HIN is a drive set signal for driving a high side driver 32 described later in the drive circuit 100.
- the control signal HO of the high side driver 32 of the drive circuit 100 is H.
- the control signal HO of the high side driver 32 of the drive circuit 100 is L.
- the output signal of the abnormality detection circuit 210 and the output signal of the input buffer circuit 220 are input to the AND logic circuit 230.
- both the abnormality detection circuit 210 and the input buffer circuit 220 output H to the AND logic circuit 230. Therefore, in this case, the AND logic circuit 230 outputs an H output signal to the pulse generation circuit 240. Therefore, the AND logic circuit 230 is a circuit that determines whether or not the transistor 34 is softly shut down.
- the pulse generation circuit 240 includes a rising differential pulse generation circuit 241, a falling differential pulse generation circuit 245, and a rising differential pulse generation circuit 247.
- the rising differential pulse generation circuits 241 and 247 are circuits that generate a pulse signal at the rising time of the input signal.
- the falling differential pulse generation circuit 245 is a circuit that generates a pulse signal at the falling time of the input signal.
- the output signal of the AND logic circuit 230 is input to the rising differential pulse generation circuit 241.
- the rising differential pulse generation circuit 241 generates a pulse signal.
- the pulse signal is input to the state signal input terminal 16 of the level shift circuit 70 as the state signal LER.
- the LER is also input to the subsequent OR logic circuit 248 as an input signal.
- the output signal of the input buffer circuit 220 is input to the falling differential pulse generation circuit 245.
- the falling differential pulse generation circuit 245 detects the falling of the input signal HIN. That is, the falling differential pulse generation circuit 245 generates a pulse signal at the falling time of the input signal HIN.
- the pulse signal is input to the OR logic circuit 248 in the subsequent stage.
- the OR logic circuit 248 receives the state signal (LER) and the pulse signal output from the falling differential pulse generation circuit 245.
- LER is a pulse signal that is generated when an abnormality is detected in the pre-stage circuit 200 and the high-side driver 32 is driven.
- the pulse signal output from the falling differential pulse generation circuit 245 is generated when the input signal HIN changes from H to L. That is, the pulse signal output from the falling differential pulse generation circuit 245 is a pulse signal generated when driving of the high side driver 32 is stopped.
- the OR logic circuit 248 outputs H when an abnormality is detected in the pre-stage circuit 200, when an abnormality is detected in the pre-stage circuit 200 and the high-side driver 32 is driven, or when driving of the high-side driver 32 is stopped. To do.
- the output signal of the OR logic circuit 248 is a reset signal (reset).
- the output signal of the input buffer circuit 220 is input to the rising differential pulse generation circuit 247.
- the rising differential pulse generation circuit 247 detects the rising edge of the input signal HIN. That is, the rising differential pulse generation circuit 247 generates a pulse signal at the time when the drive of the high side driver 32 is driven. That is, the output of the rising differential pulse generation circuit 247 is a set signal (set).
- the set, reset, and LER are input to the set signal input terminal 12, the reset signal input terminal 14, and the state signal input terminal 16 of the drive circuit 100, respectively.
- FIG. 3 is a diagram illustrating an example of the rising differential pulse generation circuit 241.
- the rising differential pulse generation circuit 241 is an example of a rising differential pulse generation circuit, and the configuration of another rising differential pulse generation circuit may be applied.
- the rising differential pulse generation circuit 241 of this example includes a delay circuit 242 and an AND logic circuit 243.
- the AND logic circuit 243 has two input terminals. The same input signal is input to one terminal of the delay circuit 242 and the AND logic circuit 243. A signal obtained by inverting the logic of the output signal DO of the delay circuit 242 is input to the other terminal of the AND logic circuit 243.
- the AND logic circuit 243 outputs a logical product of the input signal and a signal obtained by inverting the logic of DO as an output signal RISE.
- the output signal RISE becomes LER in the rising differential pulse generation circuit 241 and becomes set in the rising differential pulse generation circuit 247.
- FIG. 4 is a diagram illustrating an example of the falling differential pulse generation circuit 245.
- the falling differential pulse generation circuit 245 is an example of a falling differential pulse generation circuit, and the configuration of another falling differential pulse generation circuit may be applied.
- the falling differential pulse generation circuit 245 of this example includes a delay circuit 242 and an AND logic circuit 244.
- An input signal is input to the delay circuit 242.
- the AND logic circuit 244 has two input terminals. A signal obtained by inverting the logic of the input signal is input to one terminal of the AND logic circuit 244.
- the output signal DO of the delay circuit 242 is input to the other terminal of the AND logic circuit 243.
- the AND logic circuit 244 outputs a logical product of a signal obtained by inverting the logic of the input signal and the output signal DO as the output signal FALL.
- the output signal FALL is reset.
- FIG. 5 is a diagram showing an operation time chart of RISE and FALL.
- the vertical axis indicates the voltage values of the input signal, DO, RISE, and FALL in order from the top.
- the horizontal axis is time. On the horizontal axis, the time on the right is newer than the time on the left.
- the voltage value of any signal is L at time t0.
- the input signal transitions from L to H.
- the delay circuit 242 transitions from L to H with a delay at time t2.
- the AND logic circuit 243 generates an output signal that is H only during a period when the input signal is H and DO is L. That is, RISE is a pulse signal that is H only between time t1 and time t2. Note that FALL remains L between time t1 and time t2. At time t3, the input signal transitions from H to L.
- the delay circuit 242 makes a transition from H to L with a delay at time t4.
- the AND logic circuit 244 generates an output signal that is H only during a period in which the input signal is L and DO is H. That is, FALL is a pulse signal that is H only between time t3 and time t4. Note that RISE remains L between time t3 and time t4.
- FIG. 6 is a specific example of the high-side control circuit 120.
- the high side control circuit 120 includes a malfunction protection circuit 90, a control unit 28, and a high side driver 32.
- the malfunction protection circuit 90, the control unit 28, and the high-side driver 32 are connected to the positive and negative electrodes of the power supply 35 or the output of the high-side internal power supply circuit made from the power supply 35 (not shown).
- the malfunction protection circuit 90 of this example includes an AND logic circuit 91, an AND logic circuit 92, and an AND logic circuit 93.
- Each of the AND logic circuits 91, 92, and 93 receives setdrn, resetdrn, and LERdrrn obtained by level-shifting the set, reset, and LER input from the preceding circuit to the level shift circuit 70.
- the AND logic circuit 91 of this example outputs the logical product of the inverted voltage value of setdrn, the voltage value of resdrn, and the voltage value of LERdrn to the RS latch circuit 23 as ON_SET.
- the AND logic circuit 92 of this example outputs the logical product of the voltage value of setdrn and LERdrn and the inverted voltage value of resdrn to the RS latch circuit 23 as HSD_IN.
- the AND logic circuit 93 in this example outputs the logical product of the voltage value of setdrn, the inverted voltage value of resdrn, and the inverted voltage value of LERdrn to the RS latch circuit 26 as LER_SET.
- the control unit 28 outputs ON_OUT, HSD_OUT and LER_OUT to the high side driver 32 based on the three input signals.
- the high side driver 32 receives ON_OUT, LER_OUT, and HSD_OUT, and outputs a control signal HO to the transistor 34.
- the transistor 34 is switched on / off in accordance with HO as an input control signal.
- the transistor 34 in this example is turned on when HO is at a high level.
- the control unit 28 of this example includes an RS latch circuit 23, a timer circuit 25, an RS latch circuit 26, an AND logic circuit 27, and an inverter circuit 29.
- the high side driver 32 of this example includes a p-channel MOSFET 36, an n-channel MOSFET 37, and an n-channel MOSFET 38.
- the on-resistance of the n-channel MOSFET 37 is smaller than the on-resistance of the n-channel MOSFET 38.
- the RS latch circuit 23 outputs an output signal ON_FB to the inverter circuit 29 and the AND logic circuit 27 in response to the output signals of ON_SET and HSD_IN.
- the RS latch circuit 26 outputs LER_OUT, which is a control signal for the AND logic circuit 27 and the n-channel MOSFET 38, in accordance with LER_SET and the timer output signal TM.
- the inverter circuit 29 outputs ON_OUT, which is a control signal for the p-channel MOSFET 36.
- the AND logic circuit 27 outputs HSD_OUT that is a control signal of the n-channel MOSFET 37.
- the AND logic circuit 27 receives ON_FB and LER_OUT.
- the AND logic circuit 27 of this example outputs the logical product of the inverted voltage value of ON_FB and the inverted voltage value of LER_OUT to the gate of the n-channel MOSFET 37 as HSD_OUT. Note that ON_SET, HSD_IN, LER_SET, ON_OUT, and HSD_OUT, LER_OUT have high level or low level voltage values.
- the high level logical value is represented by 1 and the low level logical value is represented by 0.
- the timer circuit 25 outputs 1 as the output signal TM after a lapse of a predetermined period from the time point when LER_OUT changes from 0 to 1. In other cases, the output signal TM of the timer circuit 25 is zero. This state continues until the output TM of the timer circuit 25 becomes 1. When the output TM of the timer circuit 25 becomes 1, LER_OUT becomes 0, HSD_OUT becomes 1, and the n-channel MOSFET 37 is turned on and the n-channel MOSFET 38 is turned off. As a result, the soft shutdown Ls shifts to the hard shutdown Lh.
- drive soft shutdown reset in the “input signal instruction content” column in Lh means a hard shutdown after a soft shutdown.
- FIG. 7 is a diagram showing the state transition of the control unit 28.
- the IDLE state means that the output OUT of the control unit 28 is set to a low level in response to a drive reset or drive soft shutdown reset instruction.
- the DRV state means that OUT is set to a high level according to an instruction from the drive set.
- the SS state means that OUT is set to a low level according to an instruction from the drive soft shutdown set.
- One route is a route that enters the IDLE state by performing a hard shutdown from the DRV state. This corresponds to “drive reset” in the “input signal instruction content” column of Table 1.
- the high level logical value is represented by H
- the low level logical value is represented by L.
- the other path is a path that enters the IDLE state by hard shutdown from the SS state. This corresponds to “drive soft shutdown reset” in the “input signal instruction content” column of Table 1.
- the control unit 28 controls the high side driver 32 so as to maintain the current output state.
- FIG. 8 is a diagram illustrating a first operation example of the drive circuit 100.
- the vertical axis indicates the voltage value of the input signal HIN, abnormality detection signal, set, reset, LER, TM, ON_OUT, HSD_OUT, and LER_OUT, and the voltage value of the control signal HO for the high-side driver 32 in order from the top.
- the horizontal axis is time. On the horizontal axis, the right side is newer than the left side.
- the high level logical value is represented by H and the low level logical value is represented by L.
- the state of the high side control circuit 120 at time T0 is the IDLE state.
- (set, reset, LER) (H, L, L) is input.
- the state of the high side control circuit 120 becomes the DRV state.
- the control signal HO of the high side driver 32 becomes H.
- the set pulse signal at time T1 is generated by the input signal HIN that rises earlier than time T1.
- the set pulse signal at time T3 is generated by an input signal HIN that rises earlier than time T3.
- FIG. 8 shows the rising timings of the input signals HIN and set as substantially the same time.
- the reset pulse signal at time T2 is generated by the input signal HIN that falls earlier than time T2.
- the reset pulse signal at time T5 is generated by the input signal HIN that falls earlier than time T5.
- the falling timing of the input signal HIN and the rising timing of the reset are shown as substantially the same time.
- the reset pulse signal at time T4 is generated by an abnormality detection signal that rises earlier than time T4.
- the LER pulse signal at time T4 is generated by the abnormality detection signal that rises earlier than time T4 and the input signal that is H at time T4.
- the rise timing of the abnormality detection signal and the LER is shown as substantially the same time.
- the state of the high-side control circuit 120 becomes the IDLE state. That is, the control signal HO of the high side driver 32 is hard shut down. As a result, the control signal HO of the high side driver 32 becomes L.
- FIG. 9 is a diagram illustrating a second operation example of the drive circuit 100.
- this example is different from the example of FIG.
- the other points are the same as the example of FIG.
- a predetermined period from when the control unit 28 starts soft shutdown of the transistor 34 to when the control unit 28 shifts to hard shutdown of the transistor 34 is abbreviated as “SS state period” of the control unit 28.
- the period between T4 and T5 which is the SS state period, is several ⁇ sec to several tens ⁇ sec.
- the control unit 28 may determine the SS state period according to the type of abnormality detected in the preceding circuit.
- the abnormality detected in the preceding circuit may be one or more of a voltage abnormality (for example, a voltage drop) of the power supply 76 in the preceding circuit, an overcurrent or overheating of the transistor 74 as the second switching element.
- the control unit 28 may determine the SS state period by considering these abnormalities in the preceding circuit together.
- the control unit 28 may determine a time constant for soft shutdown according to the type of abnormality detected in the preceding circuit.
- the time constant may be appropriately determined according to applications such as industrial motors, air conditioners, and car motors.
- the operating voltage may be different depending on the operating voltage of each application. As an example, the time constant may be made smaller when shutting down earlier without generating a surge voltage.
- the high side control circuit 120 may be provided with a signal determination unit that determines the type of abnormality in the preceding circuit.
- the signal determination unit may count the number of LER pulses in a period after a reset pulse signal is input and until a reset pulse signal is input next.
- the signal determination unit may count the pulse width of LER.
- the signal determination unit may determine the type of abnormality according to the counted number of LER pulses.
- the signal determination unit may notify the control unit 28 of the type of abnormality corresponding to the number of pulses. Thereby, the control unit 28 can determine the time constant of the soft shutdown according to the type of abnormality detected in the previous circuit.
- FIG. 10 is a diagram showing a first modification of the high-side control circuit 120. As shown in FIG. If it is not necessary to consider the noise caused by the surge voltage described above, the malfunction protection circuit 90 of FIG. 3 may not be provided.
- FIG. 10 includes an inverter circuit 85, an inverter circuit 86, and an inverter circuit 87 instead of the malfunction protection circuit 90 of FIG. Other configurations are the same as those in FIG.
- the inverter circuit 85 inputs the signal setdrn which is the potential of the drain 57 and outputs ON_SET which is an inverted signal to the RS latch circuit 23.
- the inverter circuit 86 inputs a resdrn signal that is the potential of the drain 67 and outputs HSD_IN that is an inverted signal to the RS latch circuit 23.
- the inverter circuit 87 inputs a signal LERdrn which is the potential of the drain 47 and outputs an inverted signal LER_SET to the RS latch circuit 26.
- the operation of the high-side control circuit 120 in FIG. 10 is the same as that in FIGS. 8 and 9 which is the operation in the case of FIG.
- FIG. 11 is a diagram showing a second modification of the high-side control circuit 120. As shown in FIG. The difference from FIG. 3 is that an AND logic circuit 22 and an OR logic circuit 96 are provided. In this case, the AND logic circuit 230 and the OR logic circuit 248 are unnecessary in the pre-stage circuit 200 of FIG. In FIG. 2, the output of the noise filter 213 is directly input to the rising differential pulse generation circuit 241. The output of the falling differential pulse generation circuit 245 is set as reset.
- the AND logic circuit 22 of this example outputs the logical product of the inverted voltage value of LERdrn and the voltage value of the output signal ON_FB of the RS latch circuit 23 to the malfunction protection circuit 90 as LER_SET.
- LER_SET is also output to the OR logic circuit 96.
- the AND logic circuit 22 is a circuit that determines whether or not the transistor 34 is softly shut down. The operation of the high-side control circuit 120 in FIG. 11 is the same as that in FIGS.
- FIG. 12 shows a third modification of the high side control circuit 120.
- This example is an example in the case where it is not necessary to consider noise caused by a surge voltage as in the high-side control circuit 120 of FIG. 10, and does not include the malfunction protection circuit 90.
- an AND logic circuit 22 and an OR logic circuit 96 are provided as in the high side control circuit 120 of FIG.
- the AND logic circuit 230 and the OR logic circuit 248 are unnecessary in the pre-stage circuit 200 in FIG.
- the operation of the high-side control circuit 120 in FIG. 12 is the same as that in FIGS.
- FIG. 13 is a diagram showing a pre-stage circuit 202 as a first modification of the pre-stage circuit 200.
- the pre-stage circuit 202 of this example includes a first semiconductor chip 260 and a second semiconductor chip 270.
- the first semiconductor chip 260 includes a voltage detection circuit 250, an overheat detection circuit 251, an overcurrent detection circuit 252 and an OR logic circuit 248, and a rising differential pulse generation circuit 241 that is a part of the drive control circuit 131.
- the voltage detection circuit 250 receives an abnormality detection signal indicating a voltage abnormality in other parts of the pre-stage circuit 202.
- An abnormality detection signal indicating overheating of the transistor 74 in FIG. 1 is input to the overheat detection circuit 251.
- the overcurrent detection circuit 252 receives an abnormality detection signal indicating an overcurrent of the transistor 74 in FIG.
- the configurations of the voltage detection circuit 250, the overheat detection circuit 251 and the overcurrent detection circuit 252 are the same as those of the abnormality detection circuit 210 shown in FIG.
- the overheat detection circuit 251 and the overcurrent detection circuit 252 input the presence / absence of voltage abnormality, overheat, and overcurrent as an H signal to the OR logic circuit 248, respectively.
- the high level logical value is represented by H
- the low level logical value is represented by L.
- the OR logic circuit 248 outputs an H signal to the rising differential pulse generation circuit 241 when any one of the signals output from the voltage detection circuit 250, the overheat detection circuit 251 and the overcurrent detection circuit 252 is H. . Based on this, the rising differential pulse generation circuit 241 outputs an H signal indicating that there is an abnormality to the state signal input terminal 16 as LER.
- the second semiconductor chip 270 includes an input buffer circuit 220, a falling differential pulse generation circuit 245, and a rising differential pulse generation circuit 247. These functions are the same as those described in FIG.
- the input signal HIN is input to the input buffer circuit 220 from the other part of the pre-stage circuit 202.
- the falling differential pulse generation circuit 245 inputs reset to the reset signal input terminal 14, and the rising differential pulse generation circuit 247 inputs set to the set signal input terminal 12.
- the low side driver 72 of the drive circuit 100 may be provided in the first semiconductor chip 260 or the second semiconductor chip 270.
- the low-side driver 72 may be provided in a third semiconductor chip different from the first semiconductor chip 260 and the second semiconductor chip 270.
- FIG. 14 is a diagram showing a pre-stage circuit 204 as a second modification of the pre-stage circuit 200.
- the first semiconductor chip 260 is provided with a voltage detection circuit 250, an overheat detection circuit 251, an overcurrent detection circuit 252, and an OR logic circuit 248.
- the second semiconductor chip 270 is provided with an input buffer circuit 220, an AND logic circuit 230, and a pulse generation circuit 240.
- the configurations of the first semiconductor chip 260 and the second semiconductor chip 270 are different from those of the first modification. However, the function of each circuit is as described above.
- FIG. 15 is a diagram showing a pre-stage circuit 206 as a third modification of the pre-stage circuit 200.
- a voltage detection circuit 250 and an overheat detection circuit 251 are provided in the first semiconductor chip 260.
- the second semiconductor chip 270 is provided with an overcurrent detection circuit 252, an input buffer circuit 220, an OR logic circuit 248, an AND logic circuit 230, and a pulse generation circuit 240.
- the configurations of the first semiconductor chip 260 and the second semiconductor chip 270 are different from those of the first modification and the second modification. However, the function of each circuit is as described above.
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Abstract
Description
[先行技術文献]
[特許文献]
[特許文献1] 特開平9-200017号公報
[特許文献2] 米国特許第5917359号明細書
Claims (12)
- 前段回路からの入力信号を、前記入力信号よりも高い電圧の信号に変換するレベルシフト回路と、
前記レベルシフト回路の出力信号に基づいて、第1スイッチ素子をソフトシャットダウンするための信号を出力する制御部と
を備え、
前記第1スイッチ素子を駆動する、駆動回路。 - 前記前段回路は、異常検出回路を備え、
前記制御部は、前記異常検出回路の出力信号に基づいて前記第1スイッチをソフトシャットダウンするか否かを決定する
請求項1に記載の駆動回路。 - 前記第1スイッチ素子は、入力される制御信号に応じてオンおよびオフを切り替え、
前記駆動回路は、前記前段回路から前記レベルシフト回路に入力されるセット信号およびリセット信号に応じた前記制御信号を生成するラッチ回路を更に備え、
前記制御部は、前記ラッチ回路の出力と、前記異常検出回路の出力信号に基づいて生成される状態信号とに基づいて、前記第1スイッチ素子をソフトシャットダウンするか否かを決定する
請求項2に記載の駆動回路。 - 前記制御部は、前記ラッチ回路の出力信号が前記第1スイッチ素子をオンすべきことを示し、且つ、前記状態信号が前記前段回路において異常を検出したことを示す場合に、前記第1スイッチ素子をソフトシャットダウンさせる
請求項3に記載の駆動回路。 - 前記セット信号は、前記第1スイッチ素子をオンすべき場合に予め定められた論理値を示し、
前記リセット信号は、前記第1スイッチ素子をハードシャットダウンすべき場合に予め定められた論理値を示し、
前記状態信号は、前記前段回路において異常を検出した場合に予め定められた論理値を示し、
前記第1スイッチ素子をソフトシャットダウンさせる場合を除き、前記セット信号、前記リセット信号および前記状態信号のうちの2つ以上が前記予め定められた論理値である場合に、前記第1スイッチ素子のオンまたはオフを維持させる誤動作保護回路を更に備える
請求項3に記載の駆動回路。 - 前記レベルシフト回路は、前記状態信号のレベルをシフトする状態信号入力回路、前記セット信号のレベルをシフトするセット信号入力回路および前記リセット信号のレベルをシフトするリセット信号入力回路を備え、
前記状態信号入力回路、前記セット信号入力回路および前記リセット信号入力回路の各々は、高電位側に接続された抵抗素子、および、前記抵抗素子の低電位側にドレインが接続されたトランジスタを有し、
前記状態信号入力回路、前記セット信号入力回路および前記リセット信号入力回路において、
前記抵抗素子の前記高電位側は互いに接続されており、
前記抵抗素子の抵抗値および前記トランジスタの特性は同じである
請求項3に記載の駆動回路。 - 前記前段回路は、外部から入力された前記第1スイッチ素子を制御するための信号と、前記異常検出回路の出力信号とに基づいて前記第1スイッチ素子をソフトシャットダウンするか否かを決定する
請求項2に記載の駆動回路。 - 外部から入力された前記第1スイッチ素子を制御するための前記信号が前記第1スイッチ素子をオンすべきことを示し、且つ、前記異常検出回路の前記出力信号が異常を検出したことを示す場合に、前記前段回路は、前記第1スイッチ素子をソフトシャットダウンさせる状態信号を前記レベルシフト回路に出力する
請求項7に記載の駆動回路。 - 前記制御部は、前記第1スイッチ素子のソフトシャットダウンを開始してから、予め定められた期間が経過した後に前記第1スイッチ素子のハードシャットダウンに移行する
請求項1に記載の駆動回路。 - 前記制御部は、前記前段回路で検出された異常の種別に応じて、前記予め定められた期間を定める
請求項9に記載の駆動回路。 - 前記制御部は、前記前段回路で検出された異常の種別に応じて、ソフトシャットダウンの時定数を定める
請求項9に記載の駆動回路。 - 前記前段回路は、前記第1スイッチ素子の低電位側に直列接続される第2スイッチ素子のオンおよびオフを制御するローサイド制御回路を備え、
前記異常検出回路は、前記第2スイッチ素子の状態を検出する回路を備える
請求項2に記載の駆動回路。
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JP2017519055A JP6460230B2 (ja) | 2015-05-15 | 2016-03-28 | 駆動回路 |
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JP3429937B2 (ja) | 1996-01-12 | 2003-07-28 | 三菱電機株式会社 | 半導体装置 |
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JP2004260981A (ja) * | 2003-02-28 | 2004-09-16 | Hitachi Ltd | 電力変換装置及びこれを用いた電機システム |
JP4862527B2 (ja) | 2006-07-18 | 2012-01-25 | 三菱電機株式会社 | 半導体装置 |
JP5360304B2 (ja) * | 2010-09-28 | 2013-12-04 | 富士電機株式会社 | 半導体装置 |
JP5673449B2 (ja) | 2011-09-01 | 2015-02-18 | 三菱電機株式会社 | 半導体装置 |
JP5825144B2 (ja) * | 2012-02-28 | 2015-12-02 | 富士電機株式会社 | 半導体装置およびハイサイド回路の駆動方法 |
KR101529149B1 (ko) * | 2013-09-02 | 2015-06-17 | 엘에스산전 주식회사 | 게이트 구동 장치 |
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JP2000252809A (ja) * | 1999-03-02 | 2000-09-14 | Fuji Electric Co Ltd | レベルシフト回路 |
JP2011077629A (ja) * | 2009-09-29 | 2011-04-14 | Mitsubishi Electric Corp | 半導体回路 |
WO2011129263A1 (ja) * | 2010-04-14 | 2011-10-20 | 本田技研工業株式会社 | 短絡保護方法 |
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