WO2016155040A1 - 一种阵列基板的制作方法、阵列基板及显示面板 - Google Patents

一种阵列基板的制作方法、阵列基板及显示面板 Download PDF

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WO2016155040A1
WO2016155040A1 PCT/CN2015/076726 CN2015076726W WO2016155040A1 WO 2016155040 A1 WO2016155040 A1 WO 2016155040A1 CN 2015076726 W CN2015076726 W CN 2015076726W WO 2016155040 A1 WO2016155040 A1 WO 2016155040A1
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layer
metal
electrode
thin film
forming
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PCT/CN2015/076726
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English (en)
French (fr)
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吕晓文
曾志远
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深圳市华星光电技术有限公司
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Priority to US14/443,968 priority Critical patent/US20170040353A1/en
Publication of WO2016155040A1 publication Critical patent/WO2016155040A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device

Definitions

  • the present invention relates to the field of display, and in particular to a method for fabricating an array substrate, an array substrate, and a display panel.
  • OLED has become a hot spot in current research because of its self-illumination, wide viewing angle, fast response, light weight, and easy to be used in the field of flexible display. It is recognized as LCD, PDP. Then the mainstream of the next generation of display technology.
  • Oxide semiconductors have high mobility, and amorphous structures are highly compatible with current a-Si processes, and have been widely used in the production of OLED large-sized panels.
  • Oxide semiconductor backplane TFTs have many applications including etch stop (ESL) structures, back channel etch (BCE) structures, and coplanar (CP) structures, each of which has advantages and disadvantages, including ESL. Because the etch stop layer protects the oxide semiconductor, the device has good stability, but the etch stop structure Array process requires a mask, and the coupling capacitance is large, which is not conducive to the improvement of the yield and the cost.
  • ESL etch stop
  • BCE back channel etch
  • CP coplanar
  • the technical problem to be solved by the present invention is to provide a method for fabricating an array substrate, an array substrate and a display panel, which can reduce the damage of the metal layer and reduce the mask in the process, thereby improving the production yield.
  • a technical solution adopted by the present invention is to provide a method for fabricating an array substrate, wherein the method comprises: sequentially forming a first metal layer, an insulating layer, a first thin film layer, and an etch stop layer on the substrate. a second metal layer and an inorganic layer; forming a photoresist layer on the inorganic layer; forming an organic layer on the inorganic layer and the photoresist layer; and digging holes in the organic layer and the inorganic layer to form a first via hole, so that the second layer The metal layer portion is exposed; a second film layer is formed on the organic layer and the exposed second metal layer.
  • the step of sequentially forming a first metal layer, an insulating layer, a first thin film layer, an etch stop layer, a second metal layer, and an inorganic layer on the substrate specifically: forming a first metal layer on the substrate and patterning Forming a first metal electrode and a second metal electrode; forming an insulating layer on the substrate and the first metal layer and patterning to expose a portion of the second metal electrode; forming a first film layer on the insulating layer and patterning to form a first a thin film electrode and a second thin film electrode respectively corresponding to the first metal electrode and the second metal electrode; forming an etch stop layer on the thin film layer; and forming a second metal layer on the etch stop layer and the exposed second metal electrode, correspondingly forming a source/drain electrode; an inorganic layer is formed on the second metal layer.
  • forming an etch stop layer on the thin film layer and forming a second metal layer on the etch stop layer and the exposed second metal electrode corresponding to forming the source/drain electrodes, specifically: the first thin film electrode and the second thin film Forming a first etch stop layer and a second etch stop layer on the electrode; forming a second metal layer on the first etch stop layer, the second etch stop layer, and the exposed second metal electrode and patterning the first film Forming source/drain electrodes on the electrode and the second film electrode to form a first island-shaped semiconductor and a second island-shaped semiconductor; wherein the source or the drain of the first island-shaped semiconductor and the second island-shaped semiconductor are exposed
  • the second metal electrode is connected.
  • the step of forming a second thin film layer on the organic layer and the exposed second metal layer specifically: forming a second thin film layer on the organic layer and the exposed second metal layer and patterning to form a third thin film electrode Wherein the third thin film electrode is connected to the source or the drain of the second island-shaped semiconductor through the first via.
  • the step of digging a hole in the organic layer and the inorganic layer to form a first through hole and exposing the second metal layer is specifically: ashing the organic layer, and performing the inorganic layer as a photoresist on the inorganic layer The opening is patterned to form a first through hole.
  • the step of forming the photoresist layer on the inorganic layer is specifically: forming three kinds of red, green, and blue photoresists on the inorganic layer.
  • the first film layer is an IGZO material
  • the second film layer is an ITO material
  • an array substrate wherein the array substrate includes a substrate, a first metal layer sequentially formed on the substrate, an insulating layer, a first thin film layer, and an etch stop. a layer, a second metal layer, an inorganic layer, a photoresist layer, an organic layer and a second film layer; wherein the second metal layer comprises a source/drain electrode; the inorganic layer and the organic layer are provided with a first through hole for bare exposure The source or drain is connected to the second film layer.
  • the first metal layer includes a first metal electrode and a second metal electrode
  • the first thin film layer includes a first thin film electrode and a second thin film electrode respectively corresponding to the first metal electrode and the second metal electrode
  • the second metal layer includes Corresponding to a first source/drain of the first thin film electrode, and a second source/drain corresponding to the second thin film electrode
  • the first source or the first drain is connected to the second metal electrode
  • the second source The pole or the second drain is connected to the second film layer through the first through hole.
  • the photoresist layer comprises three colors of red, green and blue photoresist.
  • the first film layer is an IGZO material
  • the second film layer is an ITO material
  • the display panel includes an array substrate, the array substrate includes a substrate, and a first metal layer, an insulating layer, and a first layer formed on the substrate. a thin film layer, an etch stop layer, a second metal layer, an inorganic layer, a photoresist layer, an organic layer and a second thin film layer; wherein the second metal layer comprises a source/drain electrode; the inorganic layer and the organic layer are provided with a first layer
  • the via hole connects the exposed source or drain to the second film layer.
  • the first metal layer includes a first metal electrode and a second metal electrode
  • the first thin film layer includes a first thin film electrode and a second thin film electrode respectively corresponding to the first metal electrode and the second metal electrode
  • the second metal layer includes Corresponding to a first source/drain of the first thin film electrode, and a second source/drain corresponding to the second thin film electrode
  • the first source or the first drain is connected to the second metal electrode
  • the second source The pole or the second drain is connected to the second film layer through the first through hole.
  • the photoresist layer comprises three colors of red, green and blue photoresist.
  • the first film layer is an IGZO material
  • the second film layer is an ITO material
  • the invention has the beneficial effects that, in the process of fabricating the array substrate, the invention does not immediately punch holes after forming the inorganic layer, but first forms RGB photoresist on the inorganic layer, and then in the light.
  • the organic layer and the inorganic layer are perforated to expose the metal source/drain, thereby avoiding the corrosion damage to the metal source/drain when the RGB is first formed in the conventional process.
  • the organic layer and the inorganic layer are simultaneously punched, thereby avoiding the problem of accurate alignment when sequentially punching, improving the aperture ratio of the panel and reducing the process difficulty.
  • FIG. 1 is a flow chart showing a first embodiment of a method for fabricating an array substrate of the present invention
  • step 101 is a schematic structural view of step 101 in the first embodiment of the method for fabricating the array substrate of the present invention
  • step 102 is a schematic structural view of step 102 in the first embodiment of the method for fabricating the array substrate of the present invention
  • step 103 is a schematic structural view of step 103 in the first embodiment of the method for fabricating the array substrate of the present invention
  • step 104 is a schematic structural view of step 104 in the first embodiment of the method for fabricating the array substrate of the present invention
  • step 105 is a schematic structural view of step 105 in the first embodiment of the method for fabricating the array substrate of the present invention
  • FIG. 7 is a flow chart showing a second embodiment of a method for fabricating an array substrate of the present invention.
  • FIG. 8 is a schematic structural view of steps 701-705 in the second embodiment of the method for fabricating the array substrate of the present invention.
  • FIG. 9 is a schematic structural view of steps 706-709 in the second embodiment of the method for fabricating the array substrate of the present invention.
  • FIG. 10 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • a flowchart of a first embodiment of a method for fabricating an array substrate of the present invention includes:
  • Step 101 sequentially forming a first metal layer 201, an insulating layer 202, a first thin film layer 203, an etch stop layer 204, a second metal layer 205, and an inorganic layer 206 on the substrate 200;
  • step 101 specifically includes:
  • An insulating layer 202 is formed on the first metal layer 201, and the insulating layer 202 is also generally referred to as a gate insulating layer;
  • a first thin film layer 203 is formed on the insulating layer 202, and the thin film layer 203 is patterned such that the size of the thin film layer corresponds to the first metal layer 201; wherein the first thin film layer 203 is generally a transparent semiconductor material IGZO. It can also be other materials with similar functions such as ITO;
  • a second metal layer 205 is deposited on the exposed portion of the etch stop layer 204 and the first thin film layer 203, and patterned to form a source and a drain, respectively, and the source and the drain respectively correspond to the two ends of the first thin film layer 203. ;
  • An inorganic layer 206 is formed on the etch stop layer 204 and the second metal layer 205.
  • Step 102 forming a photoresist layer 207 on the inorganic layer 206;
  • the step 102 specifically includes: forming red, green, and blue light resists on the inorganic layer 206, respectively.
  • Step 103 forming an organic layer 208 on the inorganic layer 206 and the photoresist layer 207; (FIG. 4)
  • Step 104 Digging holes in the organic layer 208 and the inorganic layer 206 to form a first through hole 210, and partially exposing the second metal layer 205; (FIG. 5)
  • Step 105 Form a second thin film layer 209 on the organic layer 208 and the exposed second metal layer 205. ( Figure 6)
  • the inorganic layer is not immediately punched after forming the inorganic layer, but the RGB photoresist is formed on the inorganic layer, and then the organic layer is formed on the photoresist.
  • the organic layer and the inorganic layer are perforated to expose the metal source/drain, thereby avoiding corrosion damage to the metal source/drain when first puncturing and then forming RGB in the conventional process, and for the organic layer and the inorganic layer
  • the hole is punched, which avoids the problem of accurate alignment when the holes are punched successively, improves the opening ratio of the panel, and reduces the process difficulty.
  • a flowchart of a second embodiment of a method for fabricating an array substrate according to the present invention includes:
  • FIG. 8 is a schematic structural diagram of the following steps 701-705.
  • Step 701 forming a first metal layer on the substrate 800 and patterning to form a first metal electrode 8011 and a second metal electrode 8012;
  • Step 702 forming an insulating layer 802 on the substrate and the first metal layer and patterning to expose a portion of the second metal electrode 8012;
  • Step 703 forming a first thin film layer on the insulating layer 802 and patterning, forming a first thin film electrode 8031 and a second thin film electrode 8032, respectively, to correspond to the first metal electrode 8011 and the second metal electrode 8012;
  • Step 704 forming an etch stop layer 804 on the thin film layer and forming a second metal layer 805 on the etch stop layer 804 and the exposed second metal electrode 8012, correspondingly forming source/drain electrodes;
  • Step 705 forming an inorganic layer 806 on the second metal layer 805;
  • each semiconductor is small.
  • the islands each include a source and a drain, wherein a drain or a source of the first semiconductor island is connected to a gate of the second semiconductor island (ie, the second metal electrode 8012).
  • FIG. 9 is a schematic structural diagram of the following steps 706-709.
  • Step 706 forming a photoresist layer 807 on the inorganic layer 806;
  • Step 707 forming an organic layer 808 on the inorganic layer 806 and the photoresist layer 807;
  • Step 708 dig holes in the organic layer 808 and the inorganic layer 807 to form a first through hole, so that the second metal layer 805 is partially exposed;
  • the bare second metal layer 805 portion corresponds to the source or drain of the second semiconductor island as in FIG.
  • Step 709 Form a second film layer 809 on the organic layer 807 and the exposed second metal layer 805.
  • the second film layer is generally ITO, and may be a semiconductor material of other similar functions such as IGZO.
  • the array substrate includes:
  • the first metal layer 1010 includes a first metal electrode 1011 and a second metal electrode 1012.
  • the first thin film layer 1030 includes a first thin film electrode 1031 and a second thin film respectively corresponding to the first metal electrode 1011 and the second metal electrode 1012.
  • the electrode 1032; the second metal layer 1050 includes a first source/drain corresponding to the first film electrode 1031 (not shown), and a second source/drain corresponding to the second film electrode 1032 (not shown)
  • the first source or the first drain is connected to the second metal electrode 1012; the second source or the second drain is connected to the second thin film layer 1090 through the first via.
  • the inorganic layer is not immediately punched after forming the inorganic layer, but the RGB photoresist is formed on the inorganic layer, and then the organic layer is formed on the photoresist.
  • the organic layer and the inorganic layer are perforated to expose the metal source/drain, thereby avoiding corrosion damage to the metal source/drain when first puncturing and then forming RGB in the conventional process, and for the organic layer and the inorganic layer
  • the hole is punched, which avoids the problem of accurate alignment when the holes are punched successively, improves the opening ratio of the panel, and reduces the process difficulty.
  • the present invention also provides a display panel comprising the array substrate as described in the respective embodiments above.

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Abstract

一种阵列基板的制作方法、阵列基板及显示面板，该制作方法包括在基板上依次形成第一金属层（201）、绝缘层（202）、第一薄膜层（203）、蚀刻阻止层（204）、第二金属层（205）及无机层（206）；在无机层（206）上形成光阻层（207）；在无机层（206）及光阻层（207）上形成有机层（208）；在有机层（208）及无机层（206）上挖孔以形成第一通孔（210），使第二金属层（205）部分裸露出来；在有机层（208）以及裸露的第二金属层（205）上形成第二薄膜层（209）。通过上述方式，能够减小金属层的损坏以及减少制程中的光罩，提高生产率。

Description

一种阵列基板的制作方法、阵列基板及显示面板
【技术领域】
本发明涉及显示领域，特别是涉及一种阵列基板的制作方法、阵列基板及显示面板。
【背景技术】
OLED由于具有自发光，宽视角，响应快，轻薄，易于用于柔性显示领域等诸多优点而成为目前研究的热点，是公认的继LCD，PDP 之后下一代显示技术的主流。
氧化物半导体具有较高的迁移率，同时非晶结构与目前a-Si制程兼容性较高，在OLED大尺寸面板的生产中得到了广泛的应用。
氧化物半导体背板TFT应用较多的结构包括蚀刻阻止（ESL）结构，背沟道蚀刻（BCE）结构，共平面（CP）结构，这些结构各有优缺点，其中ESL 结构因为蚀刻阻止层保护氧化物半导体，器件稳定性较好，但是蚀刻阻止结构Array制程中需多一道光罩，且耦合电容较大，不利于良率的提升，及成本的下降。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板的制作方法、阵列基板及显示面板，能够减小金属层的损坏以及减少制程中的光罩，提高生产良率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板的制作方法，其中，方法包括：在基板上依次形成第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层及无机层；在有无机层上形成光阻层；在无机层及光阻层上形成有机层；在有机层及无机层上挖孔以形成第一通孔，使第二金属层部分裸露出来；在有机层以及裸露的第二金属层上形成第二薄膜层。
其中，在基板上依次形成第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层及无机层的步骤，具体为：在基板上形成第一金属层并图形化，以形成第一金属电极及第二金属电极；在基板及第一金属层上形成绝缘层并图形化，以裸露部分第二金属电极；在绝缘层上形成第一薄膜层并图形化，形成第一薄膜电极及第二薄膜电极，以分别对应第一金属电极及第二金属电极；在薄膜层上形成蚀刻阻止层以及在蚀刻阻止层和裸露的第二金属电极上形成第二金属层，对应形成源/漏电极；在第二金属层上形成无机层。
其中，在薄膜层上形成蚀刻阻止层以及在蚀刻阻止层和裸露的第二金属电极上形成第二金属层，对应形成源/漏电极的步骤，具体为：在第一薄膜电极及第二薄膜电极上分别形成第一蚀刻阻止层及第二蚀刻阻止层；在第一蚀刻阻止层、第二蚀刻阻止层和裸露的第二金属电极上形成第二金属层并图形化，以在第一薄膜电极及第二薄膜电极上分别形成源/漏电极，从而形成第一岛状半导体及第二岛状半导体；其中，第一岛状半导体的源极或漏极与第二岛状半导体中裸露的第二金属电极连接。
其中，在有机层以及裸露的第二金属层上形成第二薄膜层的步骤，具体为：在有机层以及裸露的第二金属层上形成第二薄膜层并图形化，以形成第三薄膜电极；其中，第三薄膜电极与第二岛状半导体的源极或漏极通过第一通孔连接。
其中，在有机层及无机层上挖孔以形成第一通孔，使第二金属层部分裸露出来的步骤，具体为：对有机层进行灰化，并以有机层作为光阻对无机层进行图形化开孔，以形成第一通孔。
其中，在有无机层上形成光阻层的步骤，具体为：在有无机层上分别形成红、绿、蓝三色光阻。
其中，第一薄膜层为IGZO材料，第二薄膜层为ITO材料。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，其中，阵列基板包括基板以及依次形成在基板上的第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层、无机层、光阻层、有机层以及第二薄膜层；其中，第二金属层包括源/漏电极；无机层及有机层上设有第一通孔，使裸露出来的源极或漏极与第二薄膜层连接。
其中，第一金属层包括第一金属电极及第二金属电极，第一薄膜层包括分别对应于第一金属电极及第二金属电极的第一薄膜电极及第二薄膜电极；第二金属层包括对应于第一薄膜电极的第一源极/漏极，以及对应于第二薄膜电极的第二源极/漏极；第一源极或第一漏极与第二金属电极连接；第二源极或第二漏极与第二薄膜层通过第一通孔连接。
其中，光阻层包括红、绿、蓝三色光阻。
其中，第一薄膜层为IGZO材料，第二薄膜层为ITO材料。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示面板，该显示面板包括阵列基板，该阵列基板包括基板以及依次形成在基板上的第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层、无机层、光阻层、有机层以及第二薄膜层；其中，第二金属层包括源/漏电极；无机层及有机层上设有第一通孔，使裸露出来的源极或漏极与第二薄膜层连接。
其中，第一金属层包括第一金属电极及第二金属电极，第一薄膜层包括分别对应于第一金属电极及第二金属电极的第一薄膜电极及第二薄膜电极；第二金属层包括对应于第一薄膜电极的第一源极/漏极，以及对应于第二薄膜电极的第二源极/漏极；第一源极或第一漏极与第二金属电极连接；第二源极或第二漏极与第二薄膜层通过第一通孔连接。
其中，光阻层包括红、绿、蓝三色光阻。
其中，第一薄膜层为IGZO材料，第二薄膜层为ITO材料。
本发明的有益效果是：区别于现有技术的情况，本发明在阵列基板的制作过程中，在形成无机层后不立即打孔，而是先在无机层上形成RGB光阻，再在光阻上形成有机层后，再对有机层和无机层打孔以使金属源极/漏极裸露出来，避免了传统的工艺中先打孔再形成RGB时对金属源极/漏极的腐蚀破坏，并且对有机层和无机层同时打孔，避免了先后打孔时对位要求精确的问题，提高了面板的开口率，降低了工艺难度。
【附图说明】
图1是本发明阵列基板的制作方法第一实施方式的流程图；
图2是本发明阵列基板的制作方法第一实施方式中步骤101的结构示意图；
图3是本发明阵列基板的制作方法第一实施方式中步骤102的结构示意图；
图4是本发明阵列基板的制作方法第一实施方式中步骤103的结构示意图；
图5是本发明阵列基板的制作方法第一实施方式中步骤104的结构示意图；
图6是本发明阵列基板的制作方法第一实施方式中步骤105的结构示意图；
图7是本发明阵列基板的制作方法第二实施方式的流程图；
图8是本发明阵列基板的制作方法第二实施方式中步骤701-705的结构示意图；
图9是本发明阵列基板的制作方法第二实施方式中步骤706-709的结构示意图；
图10是本发明阵列基板一实施方式的结构示意图。
【具体实施方式】
参阅图1，本发明阵列基板的制作方法第一实施方式的流程图，该方法包括：
步骤101：在基板200上依次形成第一金属层201、绝缘层202、第一薄膜层203、蚀刻阻止层204、第二金属层205及无机层206；
如图2所示，步骤101具体包括：
在基板200上沉积第一金属层201；其中，该基板200一般是玻璃基板，在基板200上沉积第一金属层201的方法一般是溅射沉积或者化学气相沉积；
在第一金属层201上形成绝缘层202，该绝缘层202一般也称为栅极绝缘层；
在绝缘层202上形成第一薄膜层203，对该薄膜层203图形化以使该薄膜层的大小对应于第一金属层201；其中，该第一薄膜层203一般是透明的半导体材料IGZO，也可以是ITO等其他具有类似功能的材料；
在第一薄膜层203上形成蚀刻阻止层204并图形化，以使图形化后的第一薄膜层203裸露两端部分；
在蚀刻阻止层204及第一薄膜层203裸露出来的部分沉积第二金属层205，并图形化以分别形成源极和漏极，源极和漏极分别对应于第一薄膜层203的两端；
在蚀刻阻止层204及第二金属层205上形成无机层206。
步骤102：在无机层206上形成光阻层207；
如图3所示，步骤102具体包括：在无机层206上分别形成红、绿、蓝三色光阻。
步骤103：在无机层206及光阻层207上形成有机层208；（如图4）
步骤104：在有机层208及无机层206上挖孔以形成第一通孔210，使第二金属层205部分裸露出来；（如图5）
步骤105：在有机层208以及裸露的第二金属层205上形成第二薄膜层209。（如图6）
区别于现有技术，本实施方式在阵列基板的制作过程中，在形成无机层后不立即打孔，而是先在无机层上形成RGB光阻，再在光阻上形成有机层后，再对有机层和无机层打孔以使金属源极/漏极裸露出来，避免了传统的工艺中先打孔再形成RGB时对金属源极/漏极的腐蚀破坏，并且对有机层和无机层同时打孔，避免了先后打孔时对位要求精确的问题，提高了面板的开口率，降低了工艺难度。
参阅图7，本发明阵列基板的制作方法第二实施方式的流程图，该方法包括：
如图8所示，图8为以下步骤701-705的结构示意图。
步骤701：在基板800上形成第一金属层并图形化，以形成第一金属电极8011及第二金属电极8012；
步骤702：在基板及第一金属层上形成绝缘层802并图形化，以裸露部分第二金属电极8012；
步骤703：在绝缘层802上形成第一薄膜层并图形化，形成第一薄膜电极8031及第二薄膜电极8032，以分别对应第一金属电极8011及第二金属电极8012；
步骤704：在薄膜层上形成蚀刻阻止层804以及在蚀刻阻止层804和裸露的第二金属电极8012上形成第二金属层805，对应形成源/漏电极；
步骤705：在第二金属层805上形成无机层806；
以上步骤与第一实施方式类似，不同之处在于在基板800上形成了两个栅电极以及与两个栅电极对应的半导体小岛，在对第二金属层805图形化后，每个半导体小岛均包括源极和漏极，其中，第一半导体小岛的漏极或源极与第二半导体小岛的栅极（即第二金属电极8012）连接。
如图9所示，图9为以下步骤706-709的结构示意图。
步骤706：在有无机层806上形成光阻层807；
步骤707：在无机层806及光阻层807上形成有机层808；
步骤708：在有机层808及无机层807上挖孔以形成第一通孔，使第二金属层805部分裸露出来；
其中，裸露的第二金属层805部分是对应于如图9中第二半导体小岛的源极或漏极。
步骤709：在有机层807以及裸露的第二金属层805上形成第二薄膜层809。
该第二薄膜层一般是ITO，也可以是IGZO等其他类似功能的半导体材料。
参阅图10，本发明阵列基板一实施方式的结构示意图，该阵列基板包括：
基板1000以及依次形成在基板1000上的第一金属层1010、绝缘层1020、第一薄膜层1030、蚀刻阻止层1040、第二金属层1050、无机层1060、光阻层1070、有机层1080以及第二薄膜层1090；其中，第二金属层1050包括源/漏电极；无机层1060及有机层1080上设有第一通孔，使裸露出来的源极或漏极与第二薄膜层1090连接。
其中，第一金属层1010包括第一金属电极1011及第二金属电极1012，第一薄膜层1030包括分别对应于第一金属电极1011及第二金属电极1012的第一薄膜电极1031及第二薄膜电极1032；第二金属层1050包括对应于第一薄膜电极1031的第一源极/漏极（图未示），以及对应于第二薄膜电极1032的第二源极/漏极（图未示）；第一源极或第一漏极与第二金属电极1012连接；第二源极或第二漏极与第二薄膜层1090通过第一通孔连接。
区别于现有技术，本实施方式在阵列基板的制作过程中，在形成无机层后不立即打孔，而是先在无机层上形成RGB光阻，再在光阻上形成有机层后，再对有机层和无机层打孔以使金属源极/漏极裸露出来，避免了传统的工艺中先打孔再形成RGB时对金属源极/漏极的腐蚀破坏，并且对有机层和无机层同时打孔，避免了先后打孔时对位要求精确的问题，提高了面板的开口率，降低了工艺难度。
另外，本发明还提供一种显示面板，该显示面板包括如上各个实施方式中所述的阵列基板。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种阵列基板的制作方法，其中，所述方法包括：
    在基板上依次形成第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层及无机层；
    在所述有无机层上形成光阻层；
    在所述无机层及所述光阻层上形成有机层；
    在所述有机层及所述无机层上挖孔以形成第一通孔，使所述第二金属层部分裸露出来；
    在所述有机层以及裸露的第二金属层上形成第二薄膜层。
  2. 根据权利要求1所述的方法，其中，所述在基板上依次形成第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层及无机层的步骤，具体为：
    在基板上形成第一金属层并图形化，以形成第一金属电极及第二金属电极；
    在所述基板及所述第一金属层上形成绝缘层并图形化，以裸露部分所述第二金属电极；
    在所述绝缘层上形成第一薄膜层并图形化，形成第一薄膜电极及第二薄膜电极，以分别对应所述第一金属电极及第二金属电极；
    在所述薄膜层上形成蚀刻阻止层以及在所述蚀刻阻止层和裸露的所述第二金属电极上形成第二金属层，对应形成源/漏电极；
    在所述第二金属层上形成无机层。
  3. 根据权利要求2所述的方法，其中，所述在所述薄膜层上形成蚀刻阻止层以及在所述蚀刻阻止层和裸露的所述第二金属电极上形成第二金属层，对应形成源/漏电极的步骤，具体为：
    在所述第一薄膜电极及第二薄膜电极上分别形成第一蚀刻阻止层及第二蚀刻阻止层；
    在所述第一蚀刻阻止层、第二蚀刻阻止层和裸露的所述第二金属电极上形成第二金属层并图形化，以在所述第一薄膜电极及第二薄膜电极上分别形成源/漏电极，从而形成第一岛状半导体及第二岛状半导体；
    其中，所述第一岛状半导体的源极或漏极与所述第二岛状半导体中裸露的所述第二金属电极连接。
  4. 根据权利要求3所述的方法，其中，所述在所述有机层以及裸露的第二金属层上形成第二薄膜层的步骤，具体为：
    在所述有机层以及裸露的第二金属层上形成第二薄膜层并图形化，以形成第三薄膜电极；
    其中，所述第三薄膜电极与所述第二岛状半导体的源极或漏极通过第一通孔连接。
  5. 根据权利要求1所述的方法，其中，所述在所述有机层及所述无机层上挖孔以形成第一通孔，使所述第二金属层部分裸露出来的步骤，具体为：
    对所述有机层进行灰化，并以所述有机层作为光阻对所述无机层进行图形化开孔，以形成所述第一通孔。
  6. 根据权利要求1所述的方法，其中，所述在所述有无机层上形成光阻层的步骤，具体为：
    在所述有无机层上分别形成红、绿、蓝三色光阻。
  7. 根据权利要求1所述的方法，其中，所述第一薄膜层为IGZO材料，所述第二薄膜层为ITO材料。
  8. 一种阵列基板，其中，所述阵列基板包括基板以及依次形成在所述基板上的第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层、无机层、光阻层、有机层以及第二薄膜层；
    其中，所述第二金属层包括源/漏电极；
    所述无机层及有机层上设有第一通孔，使裸露出来的源极或漏极与所述第二薄膜层连接。
  9. 根据权利要求8所述的阵列基板，其中，所述第一金属层包括第一金属电极及第二金属电极，所述第一薄膜层包括分别对应于所述第一金属电极和所述第二金属电极的第一薄膜电极和第二薄膜电极；
    所述第二金属层包括对应于所述第一薄膜电极的第一源极/漏极，以及对应于所述第二薄膜电极的第二源极/漏极；
    所述第一源极或第一漏极与所述第二金属电极连接；
    所述第二源极或第二漏极与所述第二薄膜层通过所述第一通孔连接。
  10. 根据权利要求8所述的阵列基板，其中，所述光阻层包括红、绿、蓝三色光阻。
  11. 根据权利要求8所述的阵列基板，其中，所述第一薄膜层为IGZO材料，所述第二薄膜层为ITO材料。
  12. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括基板以及依次形成在所述基板上的第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层、无机层、光阻层、有机层以及第二薄膜层；
    其中，所述第二金属层包括源/漏电极；
    所述无机层及有机层上设有第一通孔，使裸露出来的源极或漏极与所述第二薄膜层连接。
  13. 根据权利要求12所述的阵列基板，其中，所述第一金属层包括第一金属电极及第二金属电极，所述第一薄膜层包括分别对应于所述第一金属电极和所述第二金属电极的第一薄膜电极和第二薄膜电极；
    所述第二金属层包括对应于所述第一薄膜电极的第一源极/漏极，以及对应于所述第二薄膜电极的第二源极/漏极；
    所述第一源极或第一漏极与所述第二金属电极连接；
    所述第二源极或第二漏极与所述第二薄膜层通过所述第一通孔连接。
  14. 根据权利要求12所述的阵列基板，其中，所述光阻层包括红、绿、蓝三色光阻。
  15. 根据权利要求12所述的阵列基板，其中，所述第一薄膜层为IGZO材料，所述第二薄膜层为ITO材料。
PCT/CN2015/076726 2015-04-01 2015-04-16 一种阵列基板的制作方法、阵列基板及显示面板 WO2016155040A1 (zh)

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