WO2016131689A1 - Verfahren zur herstellung eines halbleiterkörpers - Google Patents
Verfahren zur herstellung eines halbleiterkörpers Download PDFInfo
- Publication number
- WO2016131689A1 WO2016131689A1 PCT/EP2016/052809 EP2016052809W WO2016131689A1 WO 2016131689 A1 WO2016131689 A1 WO 2016131689A1 EP 2016052809 W EP2016052809 W EP 2016052809W WO 2016131689 A1 WO2016131689 A1 WO 2016131689A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- mask
- recess
- semiconductor body
- mask layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 227
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 133
- 238000002161 passivation Methods 0.000 claims abstract description 91
- 238000005530 etching Methods 0.000 claims description 54
- 239000000463 material Substances 0.000 claims description 35
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 9
- 229910052731 fluorine Inorganic materials 0.000 claims description 9
- 239000011737 fluorine Substances 0.000 claims description 9
- 238000003631 wet chemical etching Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000003486 chemical etching Methods 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 312
- 239000000758 substrate Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 230000005855 radiation Effects 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 238000004886 process control Methods 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910001092 metal group alloy Inorganic materials 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000003595 spectral effect Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- -1 nitride compound Chemical class 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- 229910052703 rhodium Inorganic materials 0.000 description 2
- 239000010948 rhodium Substances 0.000 description 2
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002745 absorbent Effects 0.000 description 1
- 239000002250 absorbent Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- CXKCTMHTOKXKQT-UHFFFAOYSA-N cadmium oxide Inorganic materials [Cd]=O CXKCTMHTOKXKQT-UHFFFAOYSA-N 0.000 description 1
- CFEAAQFZALKQPA-UHFFFAOYSA-N cadmium(2+);oxygen(2-) Chemical compound [O-2].[Cd+2] CFEAAQFZALKQPA-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005191 phase separation Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/028—Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
- H01S5/0282—Passivation layers or treatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
Definitions
- a method for producing a semiconductor body having a recess is provided.
- one or more vias may be used which are interspersed by the
- the side flanks of the openings, in which through-contacts are arranged are usually provided with an electrically insulating layer, so that the plated-through hole within the
- Semiconductor layer sequence is only in electrical contact with the semiconductor layer to be contacted.
- an opening in the semiconductor layer sequence is thus produced on the one hand.
- the side edges of the opening to be provided with an electrically insulating layer, wherein the one Part of the opening in which the to be contacted
- Steps are commonly performed in the art using photoresist masks using two separate photo planes.
- a photomask for producing the openings in the semiconductor layer sequence is used and then another photomask for structuring the electrically insulating layer such that the openings in the region of the semiconductor layer to be contacted are at least partially free of the electrically insulating layer.
- a very accurate and therefore complex process control is needed because the second photomask requires a very high precision.
- At least one object of certain embodiments is to specify a method for producing a semiconductor body which has at least one recess provided with a passivation layer.
- a method for producing a semiconductor body is specified.
- the method may be a method for
- the semiconductor body may comprise one or more semiconductor layers which
- the semiconductor body may be a
- Semiconductor body having a semiconductor layer sequence with at least one optoelectronically active region, in particular a light-emitting or light-detecting region, which is arranged between further semiconductor layers, which may have different types of conduction. Alternatively, it may be at the
- Semiconductor body also act to a non-optoelectronically active semiconductor body.
- the semiconductor body also act to a non-optoelectronically active semiconductor body.
- Semiconductor chips such as transistors or other electronic components may be provided. Of the
- Semiconductor body can be mounted on a support element that
- the semiconductor body can, for example, on a
- Compound semiconductor material system in particular a
- III-V compound semiconductor system based and
- semiconductor layers comprising an arsenide, phosphide and / or nitride compound semiconductor material.
- Semiconductor body applied a first mask layer.
- the semiconductor body can have a growth direction with regard to its production in the form of one or more semiconductor layers, so that the semiconductor body terminates in the growth direction with a main surface.
- the first mask layer can be used in particular on the in
- the first mask layer may be a resist mask, ie in particular a photoresist.
- the first mask layer is applied in a structured manner with at least one first mask opening.
- the at least one first mask opening lies in the area in which
- the first mask layer may comprise one or a plurality of first mask openings in the region (s) in which one or more of them
- the first mask layer can, for example, be applied over a large area on the first mask layer
- a second mask layer is applied to the semiconductor body.
- the second mask layer is applied between the first mask layer and the semiconductor body. In other words, that means on the
- the second mask layer is applied unstructured and over a large area, that is to say in particular without an opening in the region of the at least one first mask opening of the first mask layer.
- Mask layer can thus be a non-structuring
- the second mask layer may in particular be a hard mask.
- the second mask layer may comprise or be an oxide or an oxynitride, preferably silicon dioxide (Si0 2 ) or silicon oxynitride (SiON).
- the first mask layer has a first mask opening, a second mask opening in the second mask layer and a second mask opening in the semiconductor body
- the first mask layer is thus used inter alia to structure the second mask layer, wherein this structuring is not in one Separate method but in the context of producing the at least one recess in the semiconductor body takes place.
- the at least one recess to be produced protrudes from the main surface on which the first mask layer is applied, preferably in a direction parallel to
- Semiconductor body form a blind hole-like recess, so a recess which projects into the semiconductor body, but does not extend through this.
- the recess may thus have a side surface and a bottom surface, which are formed by surfaces of the semiconductor body.
- Side surface surrounds the bottom surface and can be formed by different crystal surfaces of the semiconductor body.
- the at least one second mask opening and the at least one recess are produced by means of a common structuring method, in particular by means of a common etching method.
- the common etching process with which the first mask opening and the at least one recess are produced by means of a common structuring method, in particular by means of a common etching method.
- Forming the at least one second mask opening and the at least one recess may be in particular a wet chemical etching process.
- a first etching process may be used to form the at least one second mask opening and for
- Forming the at least one recess at least a second etching method is used.
- the formation of the at least one second mask opening and the formation of the at least one recess can thus take place with a two-stage etching method, that is, with first and second etching methods carried out successively.
- the first etching process may be a dry chemical etching process.
- the dry-chemical etching method for forming the at least one second mask opening may be an etching method in which a fluorine-containing gas, in particular a fluorine plasma, is used.
- the second etching process may be a wet chemical etching process.
- the first and the second etching method can in particular to the material of the second mask layer or the material of the
- the passivation layer can thus be applied, for example, directly on the second mask layer. After applying the passivation layer, this covers
- the passivation layer also covers the region of the recess in FIG.
- the passivation layer thus preferably forms a coherent layer which extends from the surface of the second mask layer facing away from the semiconductor body through the at least one second
- Mask opening extends through the undercut and over the surfaces of the at least one recess. This can be achieved by a non-directional deposition process
- a chemical vapor deposition method such as plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) may be used.
- PECVD plasma enhanced chemical vapor deposition
- ALD atomic layer deposition
- Passivation layer may in particular be an electrical
- the passivation layer may comprise, for example, an oxide or oxynitride, such as silicon dioxide (Si0 2 ) or silicon oxynitride (SiON).
- Passivation layer of the bottom surface of the at least one recess removed may in particular mean that at least part of the bottom surface of the at least one
- the passivation layer can also be removed from the side of the second mask layer facing away from the semiconductor body.
- the passivation layer can also be removed from the side of the second mask layer facing away from the semiconductor body.
- Passivation layer remains covered. Particularly preferably, the passivation layer remains only on the side surface of the at least one recess in the semiconductor body.
- the removal of the passivation layer can be effected, for example, by means of a directed etch back process, so that the passivation layer can be removed in a targeted manner from the bottom surface of the at least one recess and optionally from the side of the second mask layer facing away from the semiconductor body.
- the directional etch back process can for example, a dry chemical etching process, for example, using a fluorine-containing gas, such as a fluorine plasma. Because of that, the second
- Semiconductor body forms an undercut and thus the side surface of the at least one recess is shadowed by the second mask layer, it can be achieved that for the directed etch back through the at least one second mask opening through only the bottom surface, but not the side surface of the recess is accessible.
- a large-area directional etchback process can be used without the need for a separate mask. Rather, the second mask layer forms the mask required for removing the passivation layer.
- the method described here is therefore a self-sufficing process sequence by combining the definition of the at least one recess in FIG
- the second mask layer remains after selectively removing the
- Passivation layer on the semiconductor body Together with the passivation layer on the side surface of the at least one recess of the semiconductor body, a
- This insulating layer can be designed such that it essentially does not cover only the bottom surface of the at least one recess.
- an etching stop layer is applied between the first and second mask layers.
- the etch stop layer can thus be used as a cover layer on the second mask layer before the formation of the first
- Mask layer are applied with the at least one first mask opening.
- Mask opening in the second mask layer in the region of the at least one first mask opening of the first mask layer additionally formed an opening in the ⁇ tzstopp harsh.
- the formation of the opening in the etching stop layer can take place simultaneously, that is, with a same method, with the formation of the at least one second mask opening in the second mask layer.
- a separate method, in particular an etching method can be used to produce the at least one opening in the etch stop layer.
- the etch stop layer may comprise or be composed of alumina (Al 2 O 3 ).
- phosphoric acid (H 3 PO 4 ) may be suitable for selectively opening the etching stop layer.
- the etching stop layer can be applied over a large area even after the formation of the at least one second mask opening and the at least one recess.
- the etching stop layer can be applied after removal of the first mask layer.
- the etch stop layer may be applied before application of the
- Passivation layer in a manner as described above for the passivation layer. This may mean, in particular, that the etching stop layer covers the side surface and the bottom surface of the at least one recess in the semiconductor body after application in this case. Regardless of the time at which the etch stop layer
- Etching stop layer are applied so that the
- Etch stop layer after applying the passivation layer is completely covered by this. In other words, this means that in the event of a large-area application of the etch stop layer, the passivation layer
- the removal of the passivation layer, in particular at least from the bottom surface of the at least one recess, can also take place in the presence of an etching stop layer in the manner described above.
- the etch stop layer also covers the bottom surface of the at least one This recess may, after the selective removal of the passivation layer in the area of the bottom surface of the
- Recess in the semiconductor body in a similar manner as the passivation layer are selectively removed by a directional etching process.
- alumina may act as a material for the etching stop layer very selectively against fluorine-containing gases, so that in
- Etch stop layer can be used for further process control
- Etch stop layer deposited immediately before the passivation layer the etch stop layer remains at least partially together with the passivation on the
- the etch stop layer in this case forms a functional part of the passivation of the Side surface of the at least one recess in the
- a semiconductor body having at least one recess provided with a passivation layer in accordance with one or more of the previous embodiments
- Is recess free of the passivation layer is the electrically conductive material with which the recess is filled, only at the bottom surface with the corresponding, the
- Semiconductor body can be mounted on a support with the side formed by the second mask layer,
- connection layer for example, using a connection layer.
- Semiconductor layer can thus be contacted by the carrier side facing the semiconductor body ago.
- FIG. 1 shows a schematic illustration of an example of a semiconductor chip with plated-through holes
- FIGS. 1A to 2D are schematic representations of
- Figures 3A and 3B are schematic representations of
- FIGS. 4A to 4D are schematic representations of
- FIGS. 5A to 5E are schematic representations of
- identical, identical or identically acting elements can each be provided with the same reference numerals.
- the illustrated elements and their proportions with each other are not to be regarded as true to scale, but individual elements, such as layers, components, components and areas, for better representation and / or better understanding may be exaggerated. For a better understanding of the following
- a semiconductor chip 100 is shown in Figure 1, which has through holes in the form of so-called vias in a semiconductor body 101.
- the semiconductor chip 100 has a semiconductor layer sequence which forms the semiconductor body 101 and which has an active region 102 provided for generating light, which is arranged between a first semiconductor layer 103 and a second semiconductor layer 104.
- the semiconductor body 101 is in the example shown on a carrier 105th
- the first semiconductor layer 103 is on the side of the active region 102 facing away from the carrier 105
- a material for the carrier 105 is, for example, a semiconductor material such as germanium or silicon, which may be doped.
- Semiconductor layer 104 are different from each other
- the active region 102 is arranged in a diode structure.
- the first semiconductor layer 103 may be n-type and the second
- Semiconductor layer 104 may be p-type or
- the side facing away from the carrier 105 of the semiconductor body 101 forms a radiation exit surface 106 of the semiconductor chip 100.
- the semiconductor chip 100 In the operation of the semiconductor chip 100 is in the active
- Area 102 generates light, which preferably exits the semiconductor chip 100 predominantly through the radiation exit surface 106.
- the semiconductor body 101 in particular the active region 102, preferably contains a III-V semiconductor material.
- III-V semiconductor materials are for generating radiation in the ultraviolet - visible above the (In x Ga y Al x y N) (In x Ga y Al x - y N, in particular for blue to green radiation, or In x Ga y Al x _ y P, in particular for yellow to red radiation) to the infrared (In x Ga y Al x _ y As) spectral range
- the semiconductor body 101 is bonded by means of a connecting layer 107 to a semiconductor body 101
- connection layer 107 may be, for example, a
- Adhesive layer in particular an electrically conductive
- Adhesive layer or be a solder layer.
- the semiconductor body 101 has a plurality of recesses 109 extending through the second semiconductor layer 104 and through the active region 102 into the first
- Connection layer 108 extends through recesses 109 and forms an electrically conductive one from side of semiconductor body 101 facing carrier 105
- Connection layer 110 is formed, which is the electrical
- the plurality of recesses 109 and thus the plurality of plated-through holes serve for a laterally uniform injection of charge carriers via the first semiconductor layer 103 into the active region 102
- Recesses 109 may be arranged, for example, in the form of a matrix or in the form of a honeycomb pattern. In particular, given sufficient transverse conductivity of the first semiconductor layer 103, an embodiment of the semiconductor chip 100 is conceivable which has only a single recess 109 and thus a single via for the electrical contacting of the first semiconductor layer 103.
- Terminal layer 110 preferably includes one each
- first connection layer 108 and / or the second connection layer 110 may contain or consist of a transparent conductive oxide.
- Transparent conductive oxides are transparent, conductive materials, usually metal oxides, such as zinc oxide, tin oxide,
- Metal-oxygen compounds such as ZnO, Sn0 2 or ⁇ 2 ⁇ 3, ternary metal-oxygen compounds, such as Zn 2 Sn0 4, CdSn03, ZnSn03, Mgln 2 0 4, Galn03, ⁇ 2 ⁇ 2 ⁇ 5 or 4, Sn30i 2 or mixtures of different transparent conductive oxides to the group of TCOs.
- the TCOs do not necessarily correspond to one stoichiometric composition and may also be p- or n-doped.
- the second connection layer 110 furthermore preferably has a high reflectivity for the light generated in the active region 102. In the ultraviolet and blue
- Reflectivity example, silver, aluminum or rhodium, in the red and infrared spectral range, for example, gold.
- Terminal layer 110 may be light generated in active region 102 and radiated toward carrier 105
- Direction of the radiation exit surface 106 are deflected and exit through this from the semiconductor chip 100.
- the semiconductor chip 100 has contacts 111, 112, which are provided for external electrical contacting of the semiconductor chip 100. In operation of the semiconductor chip 100, by applying an electrical voltage between the
- Contacts 111, 112 charge carriers from different sides are injected into the active region 102 and recombine there under light emission.
- the contacts 111, 112 may in particular be associated with the first and second connection layers 108, 110
- metal or a metallic alloy with one of these materials or consist of such a material are mentioned.
- Solder connection can be produced.
- gold is particularly suitable as material for the contacts 111, 112.
- Insulation layer 113 is formed. Furthermore, the insulating layer 113 extends between the terminal layers 108 and
- an oxide such as silica or titanium oxide
- a nitride such as silicon nitride or a
- Oxynitride, about silicon oxynitride contain or consist of such a material.
- connection layers 108, 110 by means of the contacts 111, 112 takes place in the example shown only by way of example by means of an arrangement of the contacts
- the carrier 105 may also have at least one recess which extends in a vertical direction through the carrier 105 and the one with
- the carrier 105 may also be formed electrically insulating.
- the carrier 105 may comprise a ceramic such as aluminum nitride,
- Contain alumina or silicon nitride or consist of such a material Contain alumina or silicon nitride or consist of such a material.
- the side facing away from the semiconductor body 101 side of the carrier 105 may be formed deviating freely from an electrical contact from the example shown.
- the electrical contacts 111, 112 can therefore both on the
- Semiconductor body 101 facing side of the carrier 105 may be arranged.
- the contacts 111, 112 may be arranged on the side of the carrier 105 facing away from the semiconductor body 101, so that the semiconductor chip 100 can be electrically contacted exclusively from one side of the carrier 105.
- At least one recess in the, preferably electrically insulating, carrier 105 may be provided, each passing through the carrier 105 in the vertical direction extend.
- the semiconductor chip 100 shown in FIG. 1 is the semiconductor chip 100 shown in FIG. 1
- LED chip or may be formed as a laser diode chip is only to be understood as an example and not as a limitation for the following embodiments.
- the semiconductor chip 100 may also include a light in place of a light emitting active region 102
- the semiconductor chip 100 may additionally or alternatively have a non-optoelectronic functionality
- a non-light-emitting diode or a transistor for example in the form of a non-light-emitting diode or a transistor.
- FIGS. 2A to 5E exemplary embodiments of methods for producing at least one recess 10 provided with a passivation layer 8 in a semiconductor body 1 are shown.
- the at least one provided with a passivation layer 8 Recess 10 can also be used in the context of a method for producing a semiconductor chip with an electrically conductive material to form an above-described
- Connection layer are filled, so that in the
- Recess arranged electrically conductive material forms a via.
- the semiconductor bodies 1 shown below may be formed like the semiconductor body 101 of the semiconductor chip 100 of FIG. 1 and may also have features according to the example of FIG. 1 without further explicit references.
- the methods described below are also applicable to other semiconductor bodies which may, for example, have different layer sequences and / or materials than the semiconductor body 101 according to the preceding description.
- FIGS. 2A to 2D as well as in the following figures, a section of the semiconductor body 1 as well as of the layers, the openings and the layers applied thereto are respectively shown
- a semiconductor body 1 in the embodiment shown in the form of a
- MOVPE Metal-organic vapor deposition
- MBE molecular beam epitaxy
- At least one recess 10 is formed from the side of the semiconductor body facing away from the growth substrate or, if appropriate, the auxiliary carrier, which extends into the semiconductor body 1, as shown, for example, in FIG. 2B.
- This is expediently carried out after the completion of the deposition of the semiconductor layer sequence and thus after the completion of the production of the semiconductor body 1, so that the semiconductor body 1 terminates along a direction along the growth direction of the semiconductor layer sequence with a main surface which may be perpendicular to the growth direction.
- the at least one recess 10 extends from this
- Mask layer 6 is disposed between the first mask layer 5 and the semiconductor body 1. In other words, this means that first the second mask layer 6 is applied to the semiconductor body 1 and then the first mask layer 5 is applied to the second mask layer 6 is deposited.
- the mask layers 5, 6 are in particular on the along the growth direction
- the first mask layer 5 is applied in a structured manner with at least one first mask opening 50 on the second mask layer 6.
- a photoresist be applied as a material for the first mask layer 5, with the aid of suitable exposure and
- development steps for forming the first mask opening 50 is structured. As mentioned above, the first one is
- Mask opening 50 which defines the area in which the
- Recess 10 is to be produced in the semiconductor body 1, in Figure 2A and in the following figures only
- the first mask layer 5 may in particular have one or more first mask openings 50, depending on how many recesses 10 in the
- Semiconductor body to be formed.
- the second mask layer 6 is applied on the semiconductor body 1 over a large area and unstructured.
- the second mask layer 6 may be a hard mask comprising, for example, an oxide or oxynitride such as
- the formation of the second mask layer 6 can take place with a suitable, large-area process, for example a chemical or physical
- At least one second mask opening 60 in the second mask layer 6 and at least one recess 10 in the semiconductor body 1 in the region of the at least one first mask opening 50 of the first mask layer 5 is formed.
- an etching method can be used, for example a wet-chemical etching method.
- Formation of the at least one second mask opening 60 and the at least one recess 10 can be effected in particular by means of a common etching process.
- the etching parameters are set in such a way that the recess 10, which has a side surface 11 and a bottom surface 12, forms an undercut 13 with the second mask opening 60, viewed from the first mask opening 50.
- the second mask layer 6 projects beyond the recess 10 in the edge region of the recess 10, so that the lateral surface 11 of FIG. 11 is superimposed on the first or second mask layer 5, 6 and in the recess 10
- Recess 10 is shadowed by the second mask layer 6.
- the first and second mask openings 50, 60 and correspondingly the recess 10 may be round or angular
- Mask openings 50, 60 may each have dimensions in the range of tens of microns, for example about 30 ym to about 50 ym. The depth of the undercut of the
- Mask layer 6, ie the size of the undercut 13, is greater than or equal to the thickness of the later applied
- Passivation layer 8 may for example be up to 300 nm, while the depth of the recess 10 in the Semiconductor body 1, for example, about 600 nm to 700 nm, depending on how thick the range of
- Between the second mask layer 6 and the semiconductor body 1 may be at a distance, for example a distance of one or more micrometers, typically about 5 ym, a
- connection layer 110 such as the connection layer 110 described above in connection with Figure 1 may be arranged.
- the described dimensions are to be understood as purely exemplary and, depending on the design of the semiconductor body 1 and depending on the requirements of the semiconductor chip to be produced, may also deviate from the stated values.
- FIG. 2C a further method step, as shown in FIG. 2C, a large area and unstructured one
- Passivation layer 8 applied.
- the first mask layer 5 can be removed before the application of the passivation layer 8.
- the passivation layer 8 is applied by a method which is suitable for covering all exposed surfaces of the second mask layer 6 and all exposed surfaces of the recess 10 as uniformly as possible and at least with a closed layer.
- the passivation layer 8 comprises an electrically insulating material, for example an oxide or oxynitride such as silicon dioxide or Oxynitride.
- the passivation layer 8 may also have the same material as the second mask layer.
- FIG. 2D shows a further method step in which the passivation layer 8 is selectively removed from the one
- Mask layer 6 is removed from the bottom surface 12 of the at least one recess 10, so that the
- Re-etching 99 used as indicated by the arrows shown in Figure 2D.
- the etch-back method 90 can be used over a large area without the use of an additional mask
- the directional etching process 90 may include
- the passivation layer 8 after the etch-back method 99 remains exclusively at least partially on the side surface 11 of the at least one recess 10 in the semiconductor body 1.
- recess 10 in which the passivation layer 8 is removed again, and the production of the recess 10 itself merged into a common process step is the formation of the second mask opening 60 relative to the recess 10 in asj ustierenden
- Recess 10 can also be performed in a multi-stage etching process, as shown in connection with FIGS. 3A and 3B. For this purpose, for example, the formation of the at least one second mask opening 60 in the second
- Mask layer 6 by means of a first etching process. This may, for example, when using an oxide or oxynitride as the material for the second
- Mask layer 6 to a dry chemical etching process
- the semiconductor body 1 are removed.
- the possibly final formation of the at least one recess 10 in the semiconductor body 1 can take place.
- the second etching method which may be, for example, a wet-chemical etching method
- the undercut 13 can be formed by underetching the second mask layer 6 in the region of the edge of the second
- Such a multistage etching process may be advantageous, for example, in conjunction with a semiconductor body 1 based on an InAlGaN compound semiconductor material, since it may be possible with this material system that it is only possible with great difficulty to wet-chemically etch Ga-polar surfaces.
- FIGS. 4A to 4D a further exemplary embodiment of a method for producing a semiconductor body 1 having at least one with a semiconductor body 1 is provided
- Passivation layer 8 provided recess 10 described. Compared to those in conjunction with the previous ones
- the etch stop layer 9 can be applied over the second mask layer 6 over a large area and unstructured.
- the first mask layer 5 is formed with the at least one first mask opening 50.
- an opening 90 is also formed in the etching stop layer 9 in the region of the at least one first mask opening 50.
- the etch stop layer 9 remains after the
- etch stop layer 9 may include or be of alumina, which is very selective, particularly to fluorine-containing gases that are dry chemical
- Etching process for example, the second mask layer 6 or the passivation layer 8 can be used.
- the etching stop layer 9 in the region of the first mask opening 50 of the first mask layer 5 for example, when using aluminum oxide
- Phosphoric acid are suitable.
- Figures 4C and 4D are further shown.
- Passivation layer 8 is applied to the ⁇ tzstopp slaughter 9 so that it is covered by the passivation layer 8.
- Etch stopper be overetched longer without running into the problem that the second mask layer 6 is damaged or etched.
- FIGS. 5A to 5E A further method for producing a semiconductor body 1 having at least one recess 10 provided with a passivation layer 8 according to a further exemplary embodiment is described in connection with FIGS. 5A to 5E, in which, as in the previous one
- Embodiment also additionally an etch stop layer 9 is used.
- FIGS. 5A and 5B correspond to the method steps described in conjunction with FIGS. 2A and 2B and, if appropriate, the method steps described in conjunction with FIGS. 3A and 3B.
- an etching stop layer 9 is applied over a large area on all exposed surfaces of the second mask layer 6 and the at least one recess 10 in the semiconductor body 1. For this purpose can
- Passivation layer 8 described method can be used. Over the ⁇ tzstopp Mrs 9 as described in connection with the previous method over a large area
- Etch stop layer 9 is completely covered by the passivation layer 8.
- Embodiments may alternatively or additionally have further features described above in the general part.
- the invention is not limited by the description based on the embodiments of these. Rather, the invention includes every new feature and every combination of features, which in particular includes any combination of features i the claims, even if this feature or this combination itself is not explicitly in the
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Abstract
Description
Claims
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US15/552,181 US10468555B2 (en) | 2015-02-19 | 2016-02-10 | Method for producing a semiconductor body |
CN201680011290.7A CN107408531B (zh) | 2015-02-19 | 2016-02-10 | 用于制造半导体本体的方法 |
JP2017539299A JP6476305B2 (ja) | 2015-02-19 | 2016-02-10 | 半導体ボディの製造方法 |
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DE102015102378.4 | 2015-02-19 | ||
DE102015102378.4A DE102015102378B4 (de) | 2015-02-19 | 2015-02-19 | Verfahren zur Herstellung eines Halbleiterkörpers |
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JP (1) | JP6476305B2 (de) |
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DE102018003982A1 (de) * | 2018-05-17 | 2019-11-21 | 3-5 Power Electronics GmbH | Halbleiterbauelementherstellungsverfahren und Halbleiterbauelement |
EP4391093A1 (de) * | 2021-09-14 | 2024-06-26 | LG Electronics Inc. | Lichtemittierendes halbleiterelement und anzeigevorrichtung |
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JP6476305B2 (ja) | 2019-02-27 |
CN107408531A (zh) | 2017-11-28 |
JP2018508120A (ja) | 2018-03-22 |
DE102015102378A1 (de) | 2016-08-25 |
US10468555B2 (en) | 2019-11-05 |
DE102015102378B4 (de) | 2022-09-15 |
CN107408531B (zh) | 2021-02-05 |
US20180076359A1 (en) | 2018-03-15 |
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