WO2016119480A1 - 沟槽隔离结构的制备方法 - Google Patents

沟槽隔离结构的制备方法 Download PDF

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WO2016119480A1
WO2016119480A1 PCT/CN2015/090507 CN2015090507W WO2016119480A1 WO 2016119480 A1 WO2016119480 A1 WO 2016119480A1 CN 2015090507 W CN2015090507 W CN 2015090507W WO 2016119480 A1 WO2016119480 A1 WO 2016119480A1
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layer
barrier layer
substrate
trench
etching
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PCT/CN2015/090507
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English (en)
French (fr)
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宋华
王蛟
杨欢
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无锡华润上华半导体有限公司
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Priority to US15/547,200 priority Critical patent/US9972525B2/en
Publication of WO2016119480A1 publication Critical patent/WO2016119480A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Definitions

  • the present invention relates to the field of semiconductor fabrication technology, and in particular, to a method for preparing a trench isolation structure.
  • TEOS tetraethyl
  • SOI Silicon-On-Insulator
  • TEOS tetraethyl
  • the orthosilicate, tetraethyl orthosilicate layer acts as an etch barrier.
  • the trench isolation structure prepared by the method has better top flatness and a small critical dimension.
  • a method for preparing a trench isolation structure includes the following steps:
  • the oxidation barrier layer and the oxide layer on the surface of the substrate are removed.
  • the non-trench region can be masked during the oxidation of the trench by the oxidation barrier layer, thereby blocking the non-trench region from being oxidized, so that a large amount of wet etching is not required in the subsequent process.
  • the process removes the oxide layer in the non-trench region, reducing the amount of wet etching while avoiding lateral erosion caused by wet etching, making the critical dimension of the trench isolation structure small.
  • FIG. 1 is a flow chart showing a method of fabricating a trench isolation structure in an embodiment
  • FIG. 2 is a schematic structural view of the device after the step S130 shown in FIG. 1 is completed;
  • FIG. 3 is a schematic structural view of a device after performing photolithography on a photoresist layer in the embodiment shown in FIG. 1;
  • FIG. 4 is a schematic structural view of the device after the step S140 shown in FIG. 1 is completed;
  • FIG. 5 is a schematic structural view of a device after removing a photoresist layer in the embodiment shown in FIG. 1;
  • FIG. 6 is a schematic structural view of the device after the step S160 shown in FIG. 1 is completed;
  • FIG. 7 is a schematic structural view of the device after removing the tetraethyl orthosilicate layer in the embodiment shown in FIG. 1;
  • FIG. 8 is a schematic structural view of the device after the step S170 shown in FIG. 1 is completed;
  • FIG. 9 is a schematic structural view of a device after performing polysilicon filling on a trench region in the embodiment shown in FIG. 1;
  • FIG. 10 is a schematic structural view of the device after the polysilicon is etched in the embodiment shown in FIG. 1;
  • FIG. 11 is a schematic structural view of the device after the step S180 shown in FIG. 1 is completed.
  • a method for preparing a trench isolation structure includes the following steps.
  • the trench isolation structure is prepared on the basis of the SOI process, and therefore it is necessary to prepare the SOI structure after the substrate is provided. That is, after step S110, it is also necessary to perform the steps of sequentially forming a buried oxide layer and a top layer of silicon on the substrate to form an SOI structure.
  • the step of forming an oxide layer on the substrate is to form an oxide layer on the surface of the top silicon.
  • the oxide layer is mainly used to isolate the stress between the top silicon and the oxide barrier layer, so that a thinner oxide layer can be formed.
  • an oxidation barrier layer and a tetraethyl orthosilicate layer are sequentially formed on the surface of the oxide layer.
  • the oxidation barrier layer may be a substance capable of blocking thermal oxidation growth, such as silicon nitride.
  • the oxidation barrier layer is a silicon nitride layer.
  • Silicon nitride has a very high density, it is a good wet etching blocker, and can block external charges from entering the inside of the device, thus protecting the device and improving the operational reliability of the device.
  • the tetraethyl orthosilicate layer is formed by low pressure chemical vapor deposition (LPCVD).
  • the tetraethyl orthosilicate layer is a silica (SiO 2 ) film formed using tetraethyl orthosilicate (TEOS) as a gas source.
  • TEOS tetraethyl orthosilicate
  • FIG. 2 is a schematic structural view of the device after the step S130 is completed.
  • a buried oxide layer 204 and a top silicon 206 are formed on the substrate 202 to form an SOI structure.
  • An oxide layer 208, an oxidation barrier layer 210, and a tetraethyl orthosilicate layer 212 are sequentially formed on the surface of the top layer silicon 206.
  • the photoresist layer 214 is formed on the surface of the tetraethyl orthosilicate layer before the etching of the oxidation barrier layer 210 and the orthosilicate layer 212, and the photoresist layer 214 is photolithographically formed.
  • the lithography window is shown in Figure 3. Therefore, the oxide blocking layer 210 and the orthosilicate layer 212 are etched using the photoresist layer 214 as a masking layer to form a window region.
  • the corresponding position region of the oxide layer 208 is also etched, and the structure of the device after etching is as shown in FIG. 4 .
  • the photoresist layer 214 is also removed.
  • FIG. 5 is a schematic view showing the structure of the device after the photoresist layer is removed.
  • FIG. 6 is a schematic structural view of the device after the step S150 is completed.
  • the buried oxide layer 204 in the trench is etched to some extent while removing the orthosilicate layer 212, so that the trench region extends to the buried oxide layer 204 region.
  • Figure 7 is a schematic view showing the structure of the device after removing the tetraethyl orthosilicate layer.
  • the trench is oxidized with the oxide barrier layer 210 as a barrier layer.
  • the oxide barrier layer 210 is used as a barrier layer, so that the entire wafer (non-trench region and trench region) is oxidized during the trench oxidation process.
  • the oxide layer is several thousand angstroms or more. Therefore, when the active region is defined by the subsequent process, the oxide layer in the active region region needs to be removed, and the amount of wet etching required is large, resulting in large lateral erosion, resulting in a trench.
  • the critical size of the trench isolation structure is large, and a large recess is etched on the top of the trench isolation structure, which is disadvantageous for surface flattening of the trench isolation structure.
  • the oxidation barrier layer 210 can block the non-trench regions, thereby avoiding the formation of an oxide layer in the non-trench regions, thereby reducing the amount of wet etching in the subsequent process, thereby avoiding the wet etching process.
  • the lateral erosion and erosion of the top of the trench isolation structure facilitate the miniaturization of the critical dimensions of the trench isolation structure and the planarization of the surface.
  • Figure 8 is a schematic view showing the structure of the device after oxidizing the trench.
  • FIG. 1 A schematic diagram of the structure of the device after filling the trench region with polysilicon 216 is shown in FIG.
  • the polysilicon 216 is filled, in order to ensure that the polysilicon is not etched in the non-trench region, the polysilicon 216 is etched back to remove the polysilicon on the surface of the oxide barrier layer 210.
  • the process of etching polysilicon 216 is a method of finding the end point. When the polysilicon 216 is etched to the contact surface of the oxide layer 208 and the oxidation barrier layer 210, the etching is judged.
  • FIG. 10 is a schematic view showing the structure of the device after the polysilicon 216 is etched back.
  • an SOI structure is formed. Therefore, in this step, the oxidation barrier layer and the oxide layer on the top silicon surface are removed to complete the preparation process of the trench isolation structure.
  • the removal of the oxidation barrier layer is removed by a chemical mechanical polishing process, and the oxide layer is removed by a wet etching process. It can be understood that other processes commonly used in the art can also be used in step S180 to remove the oxide barrier layer and the oxide layer on the surface of the substrate.
  • FIG. 11 is a schematic structural view of the device after the step S180 is completed.
  • the non-trench region can be masked during the oxidation of the trench by the oxidation barrier layer, thereby blocking the non-trench region from being oxidized, so that a large amount of wet etching is not required in the subsequent process.
  • the process removes the oxide layer in the non-trench region, reducing the amount of wet etching while avoiding lateral erosion caused by wet etching, making the critical dimension of the trench isolation structure small.

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Abstract

一种沟槽隔离结构的制备方法，包括以下步骤：提供衬底；在衬底上形成氧化层；在氧化层表面依次生成氧化阻挡层以及正硅酸乙酯层；对氧化阻挡层和正硅酸乙酯层进行刻蚀；以氧化阻挡层和正硅酸乙酯层作为掩蔽层对衬底进行腐蚀形成沟槽；去除正硅酸乙酯层，并以氧化阻挡层作为阻挡层对沟槽的侧壁进行氧化；对沟槽进行多晶硅填充后对多晶硅进行回刻，将氧化阻挡层表面的多晶硅去除；去除氧化阻挡层和衬底表面的氧化层。

Description

沟槽隔离结构的制备方法
【技术领域】
本发明涉及半导体制备技术领域，特别是涉及一种沟槽隔离结构的制备方法。
【背景技术】
传统的制备工艺（例如SOI（Silicon-On-Insulator，绝缘衬底上的硅）工艺）中沟槽隔离结构制备过程通常选用TEOS（tetraethyl orthosilicate，正硅酸乙酯）层作为刻蚀阻挡层（hardmask）。采用这种方法制备沟槽隔离结构时，湿法腐蚀总量较大，在沟槽（Trench）顶部会形成较大的凹槽，其平坦度较差，容易导致多晶残留造成软连接影响产品性能。另外，通过这种方法获得的沟槽隔离结构的关键尺寸较大。
【发明内容】
基于此，有必要提供一种沟槽隔离结构的制备方法，通过该方法制备得到的沟槽隔离结构的顶部平坦度较好且关键尺寸较小。
一种沟槽隔离结构的制备方法，包括以下步骤：
提供衬底；
在所述衬底上形成氧化层；
在所述氧化层表面依次生成氧化阻挡层以及正硅酸乙酯层；
对所述氧化阻挡层和所述正硅酸乙酯层进行刻蚀；
以刻蚀后的所述氧化阻挡层和所述正硅酸乙酯层作为掩蔽层对所述衬底进行腐蚀形成沟槽；
去除所述正硅酸乙酯层，并以所述氧化阻挡层作为阻挡层对所述沟槽的侧壁进行氧化；
对所述沟槽行多晶硅填充后对所述多晶硅进行回刻，将所述氧化阻挡层表面的多晶硅去除；以及
去除所述氧化阻挡层和所述衬底表面的氧化层。
上述沟槽隔离结构的制备方法，通过氧化阻挡层可以在沟槽氧化过程中对非沟槽区域进行掩蔽，从而阻挡了非沟槽区域被氧化，因此在后续过程中无需通过大量的湿法腐蚀工艺对非沟槽区域的氧化层进行去除，减少了湿法腐蚀量的同时避免了湿法腐蚀所带来的横向侵蚀，使得沟槽隔离结构的关键尺寸较小。并且，还可以避免由于大量湿法腐蚀造成沟槽隔离结构的顶部形成较大的凹槽，使得沟槽隔离结构的顶部具有较好的平坦度。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中的沟槽隔离结构的制备方法的流程图；
图2为完成图1所示步骤S130后的器件结构示意图；
图3为完成图1所示实施例中对光刻胶层进行光刻后器件的结构示意图；
图4为完成图1所示步骤S140后器件的结构示意图；
图5为完成图1所示实施例中去除光刻胶层后器件的结构示意图；
图6为完成图1所示步骤S160后器件的结构示意图；
图7为完成图1所示实施例中去除正硅酸乙酯层后器件的结构示意图；
图8为完成图1所示步骤S170后器件的结构示意图；
图9为完成图1所示实施例中对沟槽区域进行多晶硅填充后器件的结构示意图；
图10为完成图1所示实施例中对多晶硅进行回刻后器件的结构示意图；
图11为完成图1所示步骤S180后器件的结构示意图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
图1为一实施例中的沟槽隔离结构的制备方法的流程图，该制备方法可以适用于如SOI工艺等半导体制备工艺过程中。一种沟槽隔离结构的制备方法，包括以下步骤。
S110，提供衬底。
在本实施例中，沟槽隔离结构是基于SOI工艺的基础上进行制备的，因此在提供衬底后还需要制备SOI结构。即在步骤S110后，还需要执行步骤：在衬底上顺次形成埋氧化层以及顶层硅以形成SOI结构。
S120，在衬底上形成氧化层。
在本实施例中，由于形成了SOI结构，因此在衬底上形成氧化层的步骤为在顶层硅的表面形成氧化层。氧化层主要用于隔离顶层硅和氧化阻挡层之间的应力，因此生成较薄的一层氧化层即可满足要求。
S130，在氧化层表面依次形成氧化阻挡层以及正硅酸乙酯层。
氧化阻挡层可以采用能够阻挡热氧化生长的物质，如硅的氮化物。在本实施例中，氧化阻挡层为氮化硅层。氮化硅具有极高的致密性，它是良好的湿法刻蚀阻挡剂，并且能阻挡外界电荷进入器件内部，因而起到保护器件、提高器件工作可靠性的作用。正硅酸乙酯层是通过低压化学气相淀积（LPCVD）形成的。正硅酸乙酯层是采用正硅酸乙酯（TEOS）为气体源生成的二氧化硅（SiO2）薄膜。图2为完成步骤S130后器件的结构示意图。衬底202上形成有埋氧化层204以及顶层硅206从而形成SOI结构。在顶层硅206的表面依次形成有氧化层208、氧化阻挡层210以及正硅酸乙酯层212。
S140，对氧化阻挡层和正硅酸乙酯层进行刻蚀。
在本实施例中，对氧化阻挡层210和正硅酸乙酯层212进行刻蚀前需要在正硅酸乙酯层的表面形成光刻胶层214，并对光刻胶层214进行光刻形成光刻窗口，如图3所示。因此，以光刻胶层214作为掩蔽层对氧化阻挡层210以及正硅酸乙酯层212进行刻蚀形成窗口区域。在本实施例中，在刻蚀过程中，也会对氧化层208的对应位置区域进行刻蚀，刻蚀后器件的结构示意图如图4所示。在刻蚀完成后，还会去除光刻胶层214。图5为去除光刻胶层后器件的结构示意图。
S150，以刻蚀后的氧化阻挡层和正硅酸乙酯层作为掩蔽层对衬底进行腐蚀形成沟槽。
以刻蚀后的氧化阻挡层210和正硅酸乙酯层212作为掩蔽层对顶层硅206进行腐蚀从而形成沟槽。图6为完成步骤S150后器件的结构示意图。
S160，去除正硅酸乙酯层，并以氧化阻挡层作为阻挡层对沟槽的侧壁进行氧化。
在本实施例中，在去除正硅酸乙酯层212的同时会对沟槽内的埋氧化层204进行一定程度的腐蚀，从而使得沟槽区域延伸至埋氧化层204区域。图7为去除正硅酸乙酯层后器件的结构示意图。
在去除正硅酸乙酯层后，以氧化阻挡层210为阻挡层对沟槽进行氧化。传统的沟槽制备过程中，仅仅只是用正硅酸乙酯层作为阻挡层，因此在沟槽氧化过程中，会对整个圆片（非沟槽区域和沟槽区域）进行氧化。一般的氧化层都在几千埃以上，因此在后续工艺定义有源区时，需要将有源区区域的氧化层进行去除，需要的湿法腐蚀量较大，导致横向侵蚀较大，使得沟槽隔离结构的关键尺寸较大，且会在沟槽隔离结构的顶部腐蚀出较大的凹槽，不利于实现沟槽隔离结构的表面平坦化。在本实施例中，氧化阻挡层210可以对非沟槽区域进行遮挡，从而使得避免在非沟槽区域形成氧化层，因此可以减少后续工艺过程中湿法腐蚀量，进而避免由于湿法腐蚀过程所带来的横向侵蚀以及对沟槽隔离结构顶部的侵蚀，有利于实现沟槽隔离结构的关键尺寸的小型化以及表面的平坦化。图8为对沟槽进行氧化后器件的结构示意图。
S170，对沟槽进行多晶硅填充后对多晶硅进行回刻，将氧化阻挡层表面的多晶硅去除。
对沟槽区域进行多晶硅216填充后器件的结构示意图如图9所示。在填充好多晶硅216后，为保证非沟槽区域的多晶硅刻蚀完，会对多晶硅216进行回刻，将氧化阻挡层210表面的多晶硅去除。对多晶硅216进行回刻的过程是采用找终点的方式。当多晶硅216刻蚀到氧化层208与氧化阻挡层210的接触面时即可判断刻蚀完。在这个基础上再增加一点刻蚀时间形成一定的过刻蚀即可确保多晶硅216刻蚀完，使得回刻后的多晶硅216表面低于氧化层208与氧化阻挡层210的接触面，获得具有理想形貌的多晶硅表面。在本实施例中，由于氧化层208较薄，达到氧化层208与氧化阻挡层210的接触面即可结束回刻工艺，从而避免在沟槽隔离结构的顶部形成较大的过刻蚀，影响沟槽隔离结构的表面平坦化。图10为对多晶硅216进行回刻后器件的结构示意图。
S180，去除氧化阻挡层和衬底表面的氧化层。
在本实施例中形成有SOI结构，因此本步骤为将氧化阻挡层以及顶层硅表面的氧化层去除后即完成了沟槽隔离结构的制备过程。在本实施例中，氧化阻挡层的去除采用化学机械抛光工艺来去除，而氧化层则采用湿法腐蚀工艺进行去除。可以理解，步骤S180中也可以采用其他本领域常用的工艺来进行氧化阻挡层以及衬底表面的氧化层的去除。图11为完成步骤S180后器件的结构示意图。
上述沟槽隔离结构的制备方法，通过氧化阻挡层可以在沟槽氧化过程中对非沟槽区域进行掩蔽，从而阻挡了非沟槽区域被氧化，因此在后续过程中无需通过大量的湿法腐蚀工艺对非沟槽区域的氧化层进行去除，减少了湿法腐蚀量的同时避免了湿法腐蚀所带来的横向侵蚀，使得沟槽隔离结构的关键尺寸较小。并且，还可以避免由于大量湿法腐蚀造成沟槽隔离结构的顶部形成较大的凹槽，使得沟槽隔离结构的顶部具有较好的平坦度。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种沟槽隔离结构的制备方法，包括以下步骤：
    提供衬底；
    在所述衬底上形成氧化层；
    在所述氧化层表面依次生成氧化阻挡层以及正硅酸乙酯层；
    对所述氧化阻挡层和所述正硅酸乙酯层进行刻蚀；
    以刻蚀后的所述氧化阻挡层和所述正硅酸乙酯层作为掩蔽层对所述衬底进行腐蚀形成沟槽；
    去除所述正硅酸乙酯层，并以所述氧化阻挡层作为阻挡层对所述沟槽的侧壁进行氧化；
    对所述沟槽进行多晶硅填充后对所述多晶硅进行回刻，将所述氧化阻挡层表面的多晶硅去除；以及
    去除所述氧化阻挡层和所述衬底表面的氧化层。
  2. 根据权利要求1所述的方法，其特征在于，所述氧化阻挡层为氮化硅层。
  3. 根据权利要求1所述的方法，其特征在于，在所述氧化层表面依次生成氧化阻挡层以及正硅酸乙酯层的步骤之后还包括在所述正硅酸乙酯层表面形成光刻胶层并进行光刻的步骤；
    所述对所述氧化阻挡层和所述正硅酸乙酯层进行刻蚀的步骤为以所述光刻胶层为掩蔽层对所述氧化阻挡层和所述正硅酸乙酯层进行刻蚀；
    所述对所述氧化阻挡层和所述正硅酸乙酯层进行刻蚀的步骤之后还包括去除所述光刻胶层的步骤。
  4. 根据权利要求1所述的方法，其特征在于，对所述氧化阻挡层和所述正硅酸乙酯层进行刻蚀的步骤中还包括对所述氧化层进行刻蚀。
  5. 根据权利要求1所述的方法，其特征在于，所述对所述沟槽进行多晶硅填充后对所述多晶硅进行回刻，将所述氧化阻挡层表面的多晶硅去除的步骤中，回刻后的多晶硅表面低于所述氧化层与所述氧化阻挡层的接触面。
  6. 根据权利要求1所述的方法，其特征在于，在所述氧化层表面依次生成氧化阻挡层以及正硅酸乙酯层的步骤中，所述正硅酸乙酯层是通过低压化学气相淀积形成。
  7. 根据权利要求1所述的方法，其特征在于，所述提供衬底的步骤之后、所述在所述衬底上形成氧化层的步骤之前还包括：在所述衬底上依次形成埋氧化层、顶层硅以形成SOI结构。
  8. 根据权利要求7所述的方法，其特征在于：在所述衬底上形成氧化层的步骤为在所述顶层硅的表面形成氧化层；
    以所述氧化阻挡层和所述正硅酸乙酯层作为掩蔽层对所述衬底进行腐蚀形成沟槽的步骤为以所述氧化阻挡层和所述正硅酸乙酯层为掩蔽层对所述顶层硅进行腐蚀形成所述沟槽。
  9. 根据权利要求1所述的方法，其特征在于，所述去除所述氧化阻挡层和所述衬底表面的氧化层完成沟槽隔离结构的制备的步骤中所述氧化阻挡层的去除是采用化学机械抛光工艺来完成的。
  10. 根据权利要求9所述的备方法，其特征在于，所述衬底表面的氧化层的去除是采用湿法腐蚀工艺来完成的。
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