WO2016119479A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2016119479A1
WO2016119479A1 PCT/CN2015/090476 CN2015090476W WO2016119479A1 WO 2016119479 A1 WO2016119479 A1 WO 2016119479A1 CN 2015090476 W CN2015090476 W CN 2015090476W WO 2016119479 A1 WO2016119479 A1 WO 2016119479A1
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Prior art keywords
oxide layer
gate
region
gate oxide
voltage device
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PCT/CN2015/090476
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English (en)
French (fr)
Inventor
李伟
郝龙
金炎
王德进
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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Priority to US15/547,239 priority Critical patent/US20180012890A1/en
Publication of WO2016119479A1 publication Critical patent/WO2016119479A1/zh
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    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
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    • H10D30/0215—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned selective metal deposition simultaneously on gate electrodes and the source regions or drain regions
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    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
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    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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Definitions

  • the present invention relates to the field of semiconductor fabrication technology, and in particular to a semiconductor device and a method of fabricating the same.
  • high voltage devices such as high voltage metal oxide semiconductor field effect transistors
  • source, drain and gate high voltage devices
  • the operating voltage is in the range of 10 to 40V.
  • Such products typically require the use of a thicker (>300 angstroms to achieve higher operating voltage) oxide layer as the gate oxide for high voltage devices during the manufacturing process. Since the high-voltage device source-drain injection (N+, P+) is usually small, the energy is small. If the thickness of the remaining oxide layer in the source-drain region of the high-voltage device is thick (>250 angstroms), the source-drain ion implantation will not reach the silicon surface, resulting in the formation of a highly doped surface, resulting in abnormal device characteristics.
  • the source and drain regions also need to form a metal silicide. If there is no special step to reduce the residual oxide layer in the source and drain regions of the high voltage device, then the metal silicide barrier layer (Silicide) Area Block, SAB) After etching, the source and drain regions of the high voltage device will have an oxide layer of >100 angstroms, resulting in the source and drain regions of the high voltage device not forming metal silicide normally, causing device anomalies.
  • High voltage devices are typically fabricated by integration with low voltage devices.
  • the surface of the high voltage device forms an oxide layer having a thickness greater than that of the surface of the low voltage device. Therefore, after the poly pattern is formed, it is necessary to add a special layer, cover the low-voltage device region with photoresist, expose all the high-voltage devices, and then dry the oxide layer in the high-voltage region by dry etching.
  • the thickness of the remaining oxide layer is generally controlled at 50 to 150 angstroms.
  • the thickness of the oxide layer in such high and low voltage device regions does not differ by more than 100 angstroms, and subsequent source-drain implantation and metal silicide formation are not affected. This preparation process is complicated and costly.
  • a method of fabricating a semiconductor device comprising the steps of:
  • first gate oxide layer in the non-gate region of the high voltage device region and the low voltage device region and forming a second gate oxide layer in a gate region of the high voltage device region; thickness of the second gate oxide layer Greater than the thickness of the first gate oxide layer;
  • a width of the second gate oxide layer is greater than a width of the second polysilicon gate
  • a metal silicide is formed on a surface of the first polysilicon gate surface, the second polysilicon gate surface, and the source/drain lead-out region.
  • a semiconductor device is also provided.
  • a semiconductor substrate comprising a low voltage device region and a high voltage device region
  • a first polysilicon gate formed on a surface of the first gate oxide layer of the low voltage device region
  • a second sidewall structure formed on a surface of the first gate oxide layer of the low voltage device region and located on a sidewall of the first polysilicon gate;
  • a second sidewall structure is formed on the surface of the second gate oxide layer and located on a sidewall of the second polysilicon gate; a second polysilicon gate and a second side formed on a surface of the second gate oxide layer Wall structure
  • a metal silicide blocking layer formed on the first gate oxide layer, the first polysilicon gate, the first spacer structure, the second gate oxide layer, the second polysilicon gate, and the second sidewall spacer Structural surface;
  • a metal silicide is formed on the source drain lead-out region, the first polysilicon gate, and the second polysilicon gate.
  • the gate oxide layer preparation process only the gate region of the high voltage device region is formed with the second gate oxide layer having a larger thickness, and in other regions (the non-gate region of the high voltage device and the low voltage device) The region) forms a first gate oxide layer having a small thickness. Therefore, the implantation of the source and drain ions can be directly performed after the polysilicon gate is formed without adding a separate process step to thin the remaining oxide layer of the high voltage device region, simplifying the process steps and reducing the process cost.
  • FIG. 1 is a flow chart showing a method of fabricating a semiconductor device in an embodiment
  • step S110 shown in FIG. 1;
  • FIG. 3 is a schematic structural view of the device after the step S114 shown in FIG. 1 is completed;
  • FIG. 4 is a schematic structural view of the device after the step S118 shown in FIG. 1 is completed;
  • FIG. 5 is a specific flowchart of step S120 shown in FIG. 1;
  • FIG. 6 is a schematic structural view of a high voltage device region after the step S120 shown in FIG. 1 is completed;
  • FIG. 7 is a schematic structural view of a high voltage device region after the step S130 shown in FIG. 1 is completed;
  • FIG. 8 is a schematic structural view of a high voltage device region after the step S140 shown in FIG. 1 is completed;
  • FIG. 9 is a schematic structural view of a high voltage device region after the step S160 shown in FIG. 1 is completed;
  • FIG. 10 is a schematic structural view of the high voltage device region after the step S170 shown in FIG. 1 is completed.
  • reference numerals N and P assigned to layers or regions mean that the layers or regions respectively include a large number of electrons or holes. Further, the reference marks + and - assigned to N or P indicate that the concentration of the dopant is higher or lower than the concentration in the layer which is not thus assigned to the mark. In the following description of the preferred embodiments and the drawings, like components are assigned like reference numerals and their redundant description is omitted.
  • a method of fabricating a semiconductor device capable of simultaneously preparing a low voltage device and a high voltage device capable of simultaneously preparing a low voltage device and a high voltage device.
  • the high voltage and the low voltage are relative to the operating voltage of the device prepared at the same time, that is, the device with a higher operating voltage in the device prepared at the same time is a high voltage device, and the device with a lower operating voltage is a low voltage device.
  • the prepared low voltage device and high voltage device are metal oxide semiconductor field effect transistors (MOS transistors). 1 is a method of fabricating a semiconductor device in an embodiment, the method of fabricating the semiconductor device comprising the following steps.
  • the step of providing a semiconductor substrate includes S112 to S118.
  • a lithography barrier layer is formed on the surface of the substrate, and the lithographic barrier layer is photolithographically formed to form a window region, and then the substrate silicon is etched to form a trench. Filling the formed trench with an insulating dielectric to form a trench isolation structure (Shallow Trench Isolation, STI).
  • a trench isolation structure is used to isolate the active area of the device.
  • the surface of the device after the trench isolation structure is formed is also subjected to chemical mechanical polishing (Chemical Mechanical Polishing, CMP) processing to achieve planarization of the device surface.
  • CMP chemical Mechanical Polishing
  • the trench isolation structure has a trench depth of about 3,000 to 8,000 angstroms.
  • FIG. 3 is a schematic structural view of the device after the step S114 is completed. Wherein 302 is a substrate and 304 is a trench isolation structure.
  • FIG. 4 is a schematic structural view of the device after performing step S118. As shown in FIG. 4, a first conductivity type well 306 is formed on the substrate 302, and a second conductivity type double diffusion region is formed on the first conductivity type well 306 (Double Diffused Drain, DDD) 308.
  • DDD Double Diffused Drain
  • the preparation of the semiconductor substrate is completed after completion of step S118.
  • a first gate oxide layer is formed in the non-gate region and the low voltage device region of the high voltage device region and a second gate oxide layer is formed in the gate region of the high voltage device region.
  • the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer. This is because the operating voltage of the high voltage device is higher than the operating voltage of the low voltage device, so a thicker gate oxide layer is required to meet the requirements.
  • the step of forming the first gate oxide layer and the second gate oxide layer includes S122 to S128, as shown in FIG.
  • a second gate oxide layer is grown over the entire surface of the provided semiconductor substrate.
  • the thickness of the second gate oxide layer can be set according to the operating voltage of the high voltage device.
  • the operating voltage of the high voltage device is between 10V and 40V, so the thickness of the second gate oxide layer is 300 to 700 angstroms.
  • a lithographic barrier layer formed on the surface of the second gate oxide layer is photolithographically etched to form a window in the non-gate region and the low voltage device region of the high voltage device region.
  • the second gate oxide layer of the window region is removed with the lithography barrier layer as a mask such that the non-gate region of the high voltage device region and the surface of the semiconductor substrate of the low voltage device region are exposed.
  • FIG. 6 is a schematic structural view of a high voltage device region after completion of step S128. Wherein 310 is a first gate oxide layer and 312 is a second gate oxide layer located in a gate region of the high voltage device region.
  • the gate oxide layer is prepared by step S120 such that a second gate oxide layer 312 having a relatively large thickness is formed only in the gate region of the high voltage device region, and in other regions (a non-gate region and a low voltage device of the high voltage device region).
  • the region) forms a first gate oxide layer 310 having a relatively small thickness.
  • the conventional preparation process forms a second gate oxide layer having a relatively large thickness on the entire surface of the high voltage device region.
  • a first polysilicon gate and a first sidewall structure are formed on a surface of the first gate oxide layer of the low voltage device region, and the first sidewall spacer structure is also located at a side of the first polysilicon gate.
  • a second polysilicon gate and a second spacer structure are formed on a surface of the second gate oxide layer of the high voltage device.
  • the width of the second gate oxide layer is greater than the width of the second polysilicon gate.
  • the width of the formed second gate oxide layer is 0.2 to 1 micrometer wider than the width of the second polysilicon gate, and the specific size can be adjusted according to device characteristics.
  • the second gate oxide layer of the high voltage device needs to withstand high voltage, if the second gate oxide layer does not extend to a certain size, the thickness of the edge region of the second gate oxide layer may not be reached due to the deviation of the alignment of the photolithography process. To the withstand voltage demand, it can not meet the high voltage requirements of high voltage devices, resulting in problems in the device.
  • the second sidewall structure of the high voltage device is located on the sidewall of the second polysilicon gate and is also located on the surface of the second gate oxide layer (ie, not in contact with the surface of the second conductivity type double diffusion region).
  • FIG. 7 is a schematic structural view of a region of the high voltage device after completion of step S130. Wherein 314 is a second polysilicon gate and 316 is a second sidewall structure. Since the preparation of the first polysilicon gate and the first spacer structure in the low voltage device region is the same as that in the high voltage device, it will not be described here.
  • Source-drain ion implantation is performed on the semiconductor substrate of the low voltage device region and the high voltage device region to form respective source and drain lead-out regions.
  • FIG. 8 is a schematic structural view of a high voltage device region after performing step S140.
  • a second conductivity type ion implantation is performed in the second conductivity type double diffusion region 308 to form a second conductivity type source drain extraction region 318.
  • the first conductivity type source drain lead-out region 320 is formed by implanting a first conductivity type ion on a region of the first conductivity type well 306 and located between the trench isolation structures 304.
  • the metal silicide blocking layer may be an oxide of silicon.
  • the formed metal silicide blocking layer is photolithographically etched to expose a portion of the surface of the first polysilicon gate, a portion of the surface of the second polysilicon gate, and a surface of the source and drain lead-out regions.
  • FIG. 9 is a schematic structural view of a high voltage device region after completion of step S160.
  • 322 is a metal silicide barrier layer and 324 is a metal silicide.
  • the metal silicide blocking layer 322 of the high voltage device is located on the surface of the second gate oxide layer 312 and a portion of the surface of the second sidewall spacer 316 and the second polysilicon gate 314.
  • Metal silicide 324 is formed on first conductivity type source drain lead-out region 320, second conductivity type source drain drain region 318, and second polysilicon gate 314.
  • the second gate oxide layer is formed on the entire surface of the high voltage device region, after the formation of the poly pattern, a special layer needs to be added, and the low voltage device is used by the photoresist.
  • the area is covered, and all the high-voltage devices are exposed, and the oxide layer in the high-voltage region is thinned by dry etching, and the thickness of the remaining oxide layer is generally controlled at 50 to 150 angstroms.
  • the thickness of the oxide layer in such high and low voltage device regions does not exceed 100 angstroms, and subsequent source/drain implantation and metal silicide formation are not affected, and the preparation process is complicated and costly.
  • the gate region of the high voltage device region is formed with the second gate oxide layer 312 having a larger thickness during the preparation of the gate oxide layer, and in other regions (the non-gate region of the high voltage device and The low voltage device region) forms a first gate oxide layer 310 having a smaller thickness. Therefore, after the second polysilicon gate 314 and the second spacer structure 316 are formed, the source and drain ions can be directly implanted without adding a separate The process steps reduce the gate oxide layer in the high voltage device region, simplifying the process steps while reducing process costs.
  • the first conductivity type is P type
  • the second conductivity type is N type, that is, the prepared semiconductor device is an NMOS device.
  • the first conductivity type may be an N type
  • the second conductivity type is a P type, that is, the prepared semiconductor device is a PMOS device.
  • step S170 is also performed.
  • FIG. 10 is a schematic structural view of a high voltage device region after completion of step S170.
  • 326 is an interlayer dielectric layer
  • 328 is a formed via structure filled with a conductive metal.
  • the present invention also provides a semiconductor device obtained by the method of fabricating the semiconductor device in the foregoing embodiment.
  • the semiconductor device includes: a semiconductor substrate including a low voltage device region and a high voltage device region; a first gate oxide layer formed in a non-gate region and a low voltage device region of the high voltage device region; and a surface of the gate region formed in the high voltage device region a second gate oxide layer; a first polysilicon gate formed on a surface of the first gate oxide layer of the low voltage device region; and a first sidewall spacer structure; a second polysilicon gate formed on a surface of the second gate oxide layer and a second side a wall structure, a width of the second gate oxide layer is greater than a width of the second polysilicon gate; a source/drain extraction region formed on the semiconductor substrate; formed on the first gate oxide layer, the first polysilicon gate, and the second side a wall structure, a second gate oxide layer, a metal silicide blocking layer on the surface of the second polysilicon gate and the second
  • FIG 10 is a schematic view showing the structure of a high voltage device region in the semiconductor device.
  • the high voltage device region includes a substrate 302, a trench isolation structure 304 formed on the substrate 302, and a first conductivity type well 306; a second conductivity type double diffusion region 308 formed on the first conductivity type well 306; a first gate oxide layer 310 on a surface of the trench isolation structure 304; a second gate oxide layer 312 formed on a surface of the gate region of the device; a second polysilicon gate 314 and a second surface formed on a surface of the second gate oxide layer 312 a sidewall structure 316; a second conductivity type source drain drain region 318 formed on the second conductivity type double diffusion region 308; a first conductivity type source drain drain region 320 formed on the first conductivity type well 304; a metal silicide blocking layer 322 on the surface of the second gate oxide layer 312, the second sidewall spacer structure 316 and the second polysilicon gate 314; formed on the second polysilicon gate 31
  • a via hole 328 is formed in the interlayer dielectric layer 326 for filling the metal to realize the connection of the device.
  • the width of the formed second gate oxide layer 312 is 0.2 to 1 micrometer wider than the width of the second polysilicon gate 314, and the specific size can be adjusted according to device characteristics. Because the second gate oxide layer of the high voltage device needs to withstand high voltage, if the second gate oxide layer does not extend to a certain size, the thickness of the edge region of the second gate oxide layer may not be reached due to the deviation of the alignment of the photolithography process. To the withstand voltage demand, it can not meet the high voltage requirements of high voltage devices, resulting in problems in the device.
  • the first conductivity type is P type
  • the second conductivity type is N type. In other embodiments, the first conductivity type may also be an N type, and the second conductivity type is a P type.

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Abstract

一种半导体器件的制备方法，包括步骤：提供包括低压器件区域和高压器件区域的半导体基底；在高压器件区域的非栅极区域和低压器件区域形成第一栅氧化层并在高压器件区域的栅极区域形成第二栅氧化层；第二栅氧化层的厚度大于第一栅氧化层的厚度；在低压器件区域的第一栅氧化层的表面形成第一多晶硅栅以及第一侧墙结构并在第二栅氧化层的表面形成第二多晶硅栅以及第二侧墙结构；第二栅氧化层的宽度大于第二多晶硅栅的宽度；进行源漏极离子注入形成源漏极引出区；淀积金属硅化物阻挡层后进行光刻腐蚀并形成金属硅化物。上述半导体器件的制备方法简化了工艺步骤的同时也降低了工艺成本。还涉及一种半导体器件。

Description

半导体器件及其制备方法
【技术领域】
本发明涉及半导体制备技术领域，特别是涉及一种半导体器件及其制备方法。
【背景技术】
集成电路产品中，很多需要用到高压器件（例如高压金属氧化物半导体场效晶体管），其包括源极、漏极以及栅极，且工作电压在10～40V区间。这类产品在生产工艺过程通常需要使用较厚（＞300埃，以实现较高的工作电压）的氧化层作为高压器件的栅氧。由于高压器件源漏极注入（N+，P+）通常能量小剂量大。如果高压器件的源漏极区域剩余氧化层厚度较厚（＞250埃），源漏极离子注入将会达不到硅表面，导致不能形成表面高掺杂区，造成器件特性异常。此外，源漏极区还需要形成金属硅化物（silicide），如果没有专门的步骤把高压器件的源漏极区域残留氧化层减薄，那么金属硅化物阻挡层（Silicide Area Block，SAB）蚀刻之后，高压器件的源漏极区域会残余＞100埃的氧化层，从而导致高压器件的源漏极区域不能正常形成金属硅化物，造成器件异常。
传统的高压器件的制备过程通常是与低压器件集成制备的。在栅氧化层形成的过程中，高压器件表面形成氧化层厚度大于低压器件表面的氧化层厚度。因此，在多晶硅（poly）图形形成之后，需要加一个特殊的层次，用光刻胶把低压器件区域盖起来，而把所有高压器件露出来，再用干法腐蚀把高压区域的氧化层吃薄，剩余氧化层厚度一般控制在50~150埃。这样高、低压器件区域的氧化层厚度差异不超过100埃，后续源漏注入和金属硅化物形成才不会受到影响。这种制备过程工艺复杂且成本较高。
【发明内容】
基于此，有必要提供一种工艺简单且成本较低的半导体器件的制备方法。
一种半导体器件的制备方法，包括步骤：
提供包括低压器件区域和高压器件区域的半导体基底；
在所述高压器件区域的非栅极区域和所述低压器件区域形成第一栅氧化层并在所述高压器件区域的栅极区域形成第二栅氧化层；所述第二栅氧化层的厚度大于所述第一栅氧化层的厚度；
在所述低压器件区域的第一栅氧化层的表面形成第一多晶硅栅以及第一侧墙结构并在所述第二栅氧化层的表面形成第二多晶硅栅以及第二侧墙结构；所述第二栅氧化层的宽度大于所述第二多晶硅栅的宽度；
对所述半导体基底上进行源漏极离子注入形成源漏极引出区；以及
在所述低压器件区域和所述高压器件区域的表面形成金属硅化物阻挡层并对所述金属硅化物阻挡层进行光刻腐蚀以暴露所述第一多晶硅栅的部分表面、所述第二多晶硅栅的部分表面和所述源漏极引出区的表面；
在所述第一多晶硅栅表面、所述第二多晶硅栅表面和所述源漏极引出区的表面形成金属硅化物。
还提供一种半导体器件。
一种半导体器件，其特征在于，包括：
半导体基底，包括低压器件区域和高压器件区域；
第一栅氧化层，形成于所述高压器件区域的非栅极区域和所述低压器件区域；
第二栅氧化层，形成于所述高压器件区域的栅极区域；
第一多晶硅栅，形成于所述低压器件区域的第一栅氧化层的表面；
第二侧墙结构，形成于所述低压器件区域的第一栅氧化层的表面且位于所述第一多晶硅栅的侧壁；
第二多晶硅栅，形成于所述第二栅氧化层表面；
第二侧墙结构形成于所述第二栅氧化层表面且位于所述第二多晶硅栅的侧壁；形成于所述第二栅氧化层表面的第二多晶硅栅和第二侧墙结构；
源漏极引出区，形成于所述半导体基底上；
金属硅化物阻挡层，形成于所述第一栅氧化层、第一多晶硅栅、第一侧墙结构、第二栅氧化层、所述第二多晶硅栅和所述第二侧墙结构表面；以及
金属硅化物，形成于所述源漏极引出区、所述第一多晶硅栅和所述第二多晶硅栅上。
上述半导体器件以及制备方法，在栅氧化层的制备过程中仅高压器件区域的栅极区域形成有厚度较大的第二栅氧化层，而在其他区域（高压器件的非栅极区域和低压器件区域）形成厚度较小的第一栅氧化层。因此，在多晶硅栅形成后可以直接进行源漏极离子的注入而无需增加单独的工艺步骤来对高压器件区域的剩余氧化层进行减薄，简化了工艺步骤的同时也降低了工艺成本。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中的半导体器件的制备方法的流程图；
图2为图1所示步骤S110的具体流程图；
图3为完成图1所示步骤S114后器件的结构示意图；
图4为完成图1所示步骤S118后器件的结构示意图；
图5为图1所示步骤S120的具体流程图；
图6为完成图1所示步骤S120后的高压器件区域的结构示意图；
图7为完成图1所示步骤S130后高压器件区域的结构示意图；
图8为完成图1所示步骤S140后高压器件区域的结构示意图；
图9为完成图1所示步骤S160后高压器件区域的结构示意图；
图10为完成图1所示步骤S170后高压器件区域的结构示意图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
在本说明书和附图中，分配给层或区域的参考标记N和P表示这些层或区域分别包括大量电子或空穴。进一步地，分配给N或P的参考标记＋和－表示掺杂剂的浓度高于或低于没有这样分配到标记的层中的浓度。在下文的优选实施例的描述和附图中，类似的组件分配有类似的参考标记且该处省略其冗余说明。
一种半导体器件的制备方法，可以同时制备低压器件和高压器件。其中，高压和低压是相对于同时制备的器件的工作电压而言的，即同时制备的器件中的工作电压较高的器件为高压器件，工作电压较低的器件则为低压器件。在本实施例中，制备的低压器件和高压器件为金属氧化物半导体场效应管（MOS管）。图1为一实施例中的半导体器件的制备方法，该半导体器件的制备方法包括以下步骤。
S110，提供半导体基底。
半导体器件需要同时制备低压器件和高压器件，因此在提供的半导体基底中包括高压器件区域以及低压器件区域。在本实施例中，提供半导体基底的步骤的流程如图2所示。提供半导体基底的步骤包括S112～S118。
S112，提供衬底。
S114，在衬底上制备沟槽隔离结构并进行表面平坦化。
在衬底表面形成光刻阻挡层，并对光刻阻挡层进行光刻形成窗口区域后对衬底硅进行腐蚀形成沟槽。对形成的沟槽进行绝缘介质填充形成沟槽隔离结构（Shallow Trench Isolation，STI）。沟槽隔离结构用于对器件的有源区进行隔离。在本实施例中，还会对形成的沟槽隔离结构后的器件表面进行化学机械抛光（Chemical Mechanical Polishing，CMP）处理，以实现器件表面的平坦化。根据不同的技术要求，沟槽隔离结构的沟槽（trench）深度约为3000～8000埃。图3为完成步骤S114后器件的结构示意图。其中，302为衬底，304则为沟槽隔离结构。
S116，在衬底上进行第一导电类型离子的注入形成第一导电类型阱。
S118，在第一导电类型阱中进行第二导电类型离子注入形成第二导电类型双扩散区。
图4为执行步骤S118后器件的结构示意图。如图4，在衬底302上形成有第一导电类型阱306，在第一导电类型阱306上形成有第二导电类型双扩散区（Double Diffused Drain，DDD）308。
完成步骤S118后即完成了对半导体基底的制备。
S120，形成第一栅氧化层和第二栅氧化层。
在高压器件区域的非栅极区域和低压器件区域形成第一栅氧化层并在高压器件区域的栅极区域形成第二栅氧化层。其中，第二栅氧化层的厚度大于第一栅氧化层的厚度。这是因为，高压器件的工作电压比低压器件的工作电压高，因此需要使用较厚的栅氧化层才能够满足要求。
在本实施例中，形成第一栅氧化层和第二栅氧化层的步骤包括S122～S128，如图5所示。
S122，形成第二栅氧化层。
在提供的半导体基底表面进行整面生长第二栅氧化层。第二栅氧化层的厚度可以根据高压器件的工作电压需要进行设定。在本实施例中，高压器件的工作电压在10V～40V之间，故第二栅氧化层的厚度为300～700埃。
S124，在第二栅氧化层表面形成光刻阻挡层并进行光刻腐蚀形成窗口。
对在第二栅氧化层表面形成的光刻阻挡层进行光刻腐蚀，从而在高压器件区域的非栅极区域和低压器件区域形成窗口。
S126，去除窗口区的第二栅氧化层。
以光刻阻挡层为掩膜将窗口区域的第二栅氧化层去除，使得高压器件区域的非栅极区域和低压器件区域的半导体基底的表面露出。
S128，形成第一栅氧化层。
在半导体基底的表面形成第一栅氧化层。在本实施例中，形成的第一栅氧化层的厚度为20～80埃。形成第一栅氧化层后还需要将光刻阻挡层去除。图6为完成步骤S128后高压器件区域的结构示意图。其中，310为第一栅氧化层，312为位于高压器件区域的栅极区域的第二栅氧化层。
通过步骤S120进行栅氧化层的制备，使得仅在高压器件区域的栅极区域形成有厚度相对较大的第二栅氧化层312，而在其他区域（高压器件区域的非栅极区域和低压器件区域）形成厚度相对较小的第一栅氧化层310。而传统的制备过程则会在高压器件区域的整个表面形成具有相对厚度较大的第二栅氧化层。
S130，形成多晶硅栅以及侧墙结构。
具体地，在低压器件区域的第一栅氧化层的表面形成第一多晶硅栅以及第一侧墙结构，第一侧墙结构同时也位于第一多晶硅栅的侧面。在高压器件的第二栅氧化层的表面形成第二多晶硅栅以及第二侧墙结构。其中，第二栅氧化层的宽度大于第二多晶硅栅的宽度。在本实施例中，形成的第二栅氧化层的宽度比第二多晶硅栅的宽度宽0.2～1微米，具体尺寸可根据器件特性要求来进行调整。因为高压器件的第二栅氧化层需要耐受高压，如果第二栅氧化层不延伸一定尺寸的话，由于光刻工艺对位的偏差，可能会导致第二栅氧化层的边缘区域的厚度达不到耐压需求，从而不能满足高压器件的耐高压的要求，导致器件出现问题。在本实施例中，高压器件的第二侧墙结构位于第二多晶硅栅的侧壁，且同样位于第二栅氧化层的表面（即不与第二导电类型双扩散区表面接触）。图7为完成步骤S130后高压器件区域的结构示意图。其中314为第二多晶硅栅，316为第二侧墙结构。由于低压器件区域第一多晶硅栅以及第一侧墙结构的制备与高压器件的制备工艺相同，此处不作介绍。
S140，在半导体基底上进行源漏极离子注入形成源漏极引出区。
对低压器件区域和高压器件区域的半导体基底进行源漏极离子注入形成各自的源漏极引出区。图8为执行步骤S140后的高压器件区域的结构示意图。在第二导电类型双扩散区308进行第二导电类型离子注入形成第二导电类型源漏极引出区318。在第一导电类型阱306上且位于沟槽隔离结构304之间的区域进行第一导电类型离子的注入形成第一导电类型源漏极引出区320。
S150，形成金属硅化物阻挡层并对金属硅化物阻挡层进行光刻腐蚀。
在低压器件区域和高压器件区域的表面形成金属硅化物阻挡层（Silicide Area Block，SAB），该金属硅化物阻挡层可以为硅的氧化物。对形成的金属硅化物阻挡层进行光刻腐蚀以暴露出第一多晶硅栅的部分表面、第二多晶硅栅的部分表面和源漏极引出区的表面。
S160，在第一多晶硅栅表面、第二多晶硅栅表面和源漏极引出区的表面形成金属硅化物。
在暴露出来的第一多晶硅栅表面、第二多晶硅栅表面和源漏极引出区的表面制备得到金属硅化物（Silicide）。金属硅化物的制备可以采用本领域常用的制备方法进行制备。图9为完成步骤S160后高压器件区域的结构示意图。其中，322为金属硅化物阻挡层，324为金属硅化物。在本实施例中，高压器件的金属硅化物阻挡层322位于第二栅氧化层312的表面以及第二侧墙结构316和第二多晶硅栅314的部分表面。金属硅化物324形成于第一导电类型源漏极引出区320、第二导电类型源漏极引出区318以及第二多晶硅栅314上。
传统的制备过程，由于在高压器件区域的表面整面形成了相对厚度较大的第二栅氧化层，在多晶硅（poly）图形形成之后，需要加一个特殊的层次，用光刻胶把低压器件区域盖起来，而把所有高压器件露出来，再用干法腐蚀把高压区域的氧化层吃薄，剩余氧化层厚度一般控制在50~150埃。这样高、低压器件区域的氧化层厚度差异不超过100埃，后续源漏注入和金属硅化物形成才不会受到影响，制备过程复杂且成本较高。而在本实施例中，由于在栅氧化层的制备过程中仅高压器件区域的栅极区域形成有厚度较大的第二栅氧化层312，而在其他区域（高压器件的非栅极区域和低压器件区域）则形成厚度较小的第一栅氧化层310，因此，在第二多晶硅栅314以及第二侧墙结构316形成后可以直接进行源漏极离子的注入而无需增加单独的工艺步骤来对高压器件区域的栅氧化层减薄，简化了工艺步骤的同时也降低了工艺成本。
在本实施例中，第一导电类型为P型，第二导电类型为N型，即制备得到的半导体器件为NMOS器件。在其他的实施例中，第一导电类型可以为N型，第二导电类型为P型，即制备得到的半导体器件为PMOS器件。
在本实施例中，还会执行步骤S170。
S170，形成层间介质层并对层间介质层进行光刻腐蚀形成通孔后对通孔进行金属填充。
在形成的器件表面进行层间介质层（Inter Layer Dielectric，ILD）淀积，并进行光刻腐蚀形成通孔。在形成通孔后对通孔进行金属填填充用于实现器件的连接。图10为完成步骤S170后高压器件区域的结构示意图。其中，326为层间介质层，328为形成的通孔结构，其内填充有导电金属。
本发明还提供了一种半导体器件，该器件是通过前述实施例中的半导体器件的制备方法获得的。该半导体器件包括：包括低压器件区域和高压器件区域的半导体基底；形成于高压器件区域的非栅极区域和低压器件区域的第一栅氧化层以及形成于高压器件区域的栅极区域表面的第二栅氧化层；形成于低压器件区域的第一栅氧化层表面的第一多晶硅栅以及第一侧墙结构；形成于第二栅氧化层表面的第二多晶硅栅以及第二侧墙结构，第二栅氧化层的宽度大于第二多晶硅栅的宽度；形成于半导体基底上的源漏极引出区；形成于第一栅氧化层、第一多晶硅栅、第二侧墙结构、第二栅氧化层、第二多晶硅栅和第二侧墙结构表面的金属硅化物阻挡层；以及形成于源漏极引出区、第一多晶硅栅以及第二多晶硅栅上的金属硅化物。在本实施例中，该半导体器件中的低压器件区域和高压器件区域中的器件均为双扩散型的MOS管。
图10为该半导体器件中的高压器件区域的结构示意图。高压器件区域包括：衬底302，形成于衬底302上的沟槽隔离结构304以及第一导电类型阱306；形成于第一导电类型阱306上的第二导电类型双扩散区308；形成于沟槽隔离结构304表面的第一栅氧化层310；形成于器件的栅极区域表面的第二栅氧化层312；形成于第二栅氧化层312表面的第二多晶硅栅314和第二侧墙结构316；形成于第二导电类型双扩散区308上的第二导电类型源漏极引出区318；形成于第一导电类型阱304上的第一导电类型源漏极引出区320；形成于第二栅氧化层312、第二侧墙结构316以及第二多晶硅栅314表面的金属硅化物阻挡层322；形成于第二多晶硅栅314、第一导电类型源漏极引出区320以及第二导电类型源漏极引出区318上的金属硅化物324；形成于器件表面的层间介质层326。层间介质层326中形成有通孔328用于填充金属实现器件的连接。在本实施例中，形成的第二栅氧化层312的宽度比第二多晶硅栅314的宽度宽0.2～1微米，具体尺寸可根据器件特性要求来进行调整。因为高压器件的第二栅氧化层需要耐受高压，如果第二栅氧化层不延伸一定尺寸的话，由于光刻工艺对位的偏差，可能会导致第二栅氧化层的边缘区域的厚度达不到耐压需求，从而不能满足高压器件的耐高压的要求，导致器件出现问题。第一导电类型为P型，第二导电类型为N型。在其他的实施例中，第一导电类型也可以为N型，第二导电类型为P型。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (11)

  1. 一种半导体器件的制备方法，包括步骤：
    提供包括低压器件区域和高压器件区域的半导体基底；
    在所述高压器件区域的非栅极区域和所述低压器件区域形成第一栅氧化层并在所述高压器件区域的栅极区域形成第二栅氧化层；所述第二栅氧化层的厚度大于所述第一栅氧化层的厚度；
    在所述低压器件区域的第一栅氧化层的表面形成第一多晶硅栅以及第一侧墙结构并在所述第二栅氧化层的表面形成第二多晶硅栅以及第二侧墙结构；所述第二栅氧化层的宽度大于所述第二多晶硅栅的宽度；
    对所述半导体基底上进行源漏极离子注入形成源漏极引出区；以及
    在所述低压器件区域和所述高压器件区域的表面形成金属硅化物阻挡层并对所述金属硅化物阻挡层进行光刻腐蚀以暴露所述第一多晶硅栅的部分表面、所述第二多晶硅栅的部分表面和所述源漏极引出区的表面；
    在所述第一多晶硅栅表面、所述第二多晶硅栅表面和所述源漏极引出区的表面形成金属硅化物。
  2. 根据权利要求1所述的方法，其特征在于，所述第二栅氧化层的宽度比所述第二多晶硅栅的宽度大0.2～1微米。
  3. 根据权利要求1所述的方法，其特征在于，所述在所述高压器件区域的非栅极区域和所述低压器件区域形成第一栅氧化层并在所述高压器件区域的栅极区域形成第二栅氧化层的步骤包括：
    在所述半导体基底上形成第二栅氧化层；
    在所述第二栅氧化层上形成光刻阻挡层并进行光刻腐蚀以在所述高压器件区域的非栅极区域和所述低压器件区域形成窗口；
    以所述光刻阻挡层为掩膜层将所述窗口中的第二栅氧化层去除；
    在所述半导体基底表面形成第一栅氧化层；以及
    去除所述光刻阻挡层。
  4. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述第一栅氧化层的厚度为20～80埃，所述第二栅氧化层的厚度为300～700埃。
  5. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述在所述第一多晶硅栅表面、所述第二多晶硅栅表面和所述源漏极引出区的表面形成金属硅化物的步骤之后还包括步骤：在所述高压器件区域和所述低压器件区域的表面形成层间介质层并对所述层间介质层进行光刻腐蚀形成通孔后对所述通孔进行金属填充。
  6. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述提供包括低压器件区域和高压器件区域的半导体基底的步骤包括：
    提供衬底；
    在所述衬底上制备沟槽隔离结构并进行表面平坦化；
    在所述衬底上进行第一导电类型离子注入形成第一导电类型阱；
    在所述第一导电类型阱中进行第二导电类型离子的注入形成第二导电类型双扩散区。
  7. 根据权利要求6所述的半导体器件的制备方法，其特征在于，所述第一导电类型为P型且所述第二导电类型为N型。
  8. 根据权利要求6所述的半导体器件的制备方法，其特征在于，所述第一导电类型为N型且所述第二导电类型为P型。
  9. 一种半导体器件，其特征在于，包括：
    半导体基底，包括低压器件区域和高压器件区域；
    第一栅氧化层，形成于所述高压器件区域的非栅极区域和所述低压器件区域；
    第二栅氧化层，形成于所述高压器件区域的栅极区域；
    第一多晶硅栅，形成于所述低压器件区域的第一栅氧化层的表面；
    第二侧墙结构，形成于所述低压器件区域的第一栅氧化层的表面且位于所述第一多晶硅栅的侧壁；
    第二多晶硅栅，形成于所述第二栅氧化层表面；
    第二侧墙结构形成于所述第二栅氧化层表面且位于所述第二多晶硅栅的侧壁；形成于所述第二栅氧化层表面的第二多晶硅栅和第二侧墙结构；
    源漏极引出区，形成于所述半导体基底上；
    金属硅化物阻挡层，形成于所述第一栅氧化层、第一多晶硅栅、第一侧墙结构、第二栅氧化层、所述第二多晶硅栅和所述第二侧墙结构表面；以及
    金属硅化物，形成于所述源漏极引出区、所述第一多晶硅栅和所述第二多晶硅栅上。
  10. 根据权利要求9所述的半导体器件，其特征在于，所述第二栅氧化层的宽度比所述第二多晶硅栅的宽度大0.2～1微米。
  11. 根据权利要求9所述的半导体器件，其特征在于，所述第一栅氧化层的厚度为20～80埃，所述第二栅氧化层的厚度为300～700埃。
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