WO2016115876A1 - 一种iii族半导体发光器件的制作方法 - Google Patents

一种iii族半导体发光器件的制作方法 Download PDF

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WO2016115876A1
WO2016115876A1 PCT/CN2015/086436 CN2015086436W WO2016115876A1 WO 2016115876 A1 WO2016115876 A1 WO 2016115876A1 CN 2015086436 W CN2015086436 W CN 2015086436W WO 2016115876 A1 WO2016115876 A1 WO 2016115876A1
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layer
type
electrode
deposited
pad
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PCT/CN2015/086436
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English (en)
French (fr)
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许顺成
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湘能华磊光电股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present application relates to the field of semiconductor illumination technology, and in particular to a method for fabricating a III-group semiconductor light-emitting device.
  • a gallium nitride-based light-emitting diode on a sapphire substrate may have the same P/N-type electrode deposited on the substrate, and the P-type electrode and the N-type electrode generally include a wire bond pad and a wire electrode.
  • the wire bond pads of the type electrodes are used to solder gold balls (the diameter of the gold balls is generally 75 um), so the size of the N-type electrode wire bond pads is large, which results in an excessive etching area of the active layer.
  • the current solution is as follows:
  • the vertical light-emitting device is fabricated by separating the substrate from the nitride semiconductor layer by laser stripping technology, although the vertical structure light-emitting diode technology solves the problems of the gallium nitride-based light-emitting diode on the conventional sapphire substrate, such as heat dissipation,
  • the source layer has an excessive etching area and uniform current distribution, but the substrate stripping process is complicated, the cost is high, and the yield is too low.
  • an object of the present invention is to provide a method for fabricating a III-group semiconductor light-emitting device to solve the problem of excessive etching of an active layer, increasing an active layer to improve photoelectric characteristics, and Provides a more uniform current distribution and increased antistatic performance through the new structure provided force.
  • the invention provides a method for fabricating a III-group semiconductor light-emitting device, comprising the following steps:
  • the substrate, the buffer layer, the n-type nitride semiconductor layer, the active layer, and the p-type nitride semiconductor layer are sequentially grown from bottom to top to form an epitaxial structure, and an upper surface of the epitaxial structure is the p-type nitride semiconductor layer Upper surface
  • the yellow light stripping process defines a P-type electrode and an N-type electrode pattern, and simultaneously deposits the P-type electrode and the N-type electrode, and removes the photoresist by using a stripping process to form a wafer
  • the N-type electrode comprises: An N-type line electrode and an N-type pad, the N-type line electrode being connected to the N-type pad, the N-type line electrode being deposited on the boss, active under the N-type line electrode The layer is etched away or the active layer under the N-type line electrode is partially etched away, the N-type pad being deposited over the active layer, the P-type electrode comprising: a P-type pad and a P a wire electrode, the P-type electrode being deposited on the boss;
  • the wafer is thinned, diced, split, tested, and sorted.
  • the yellow light stripping process defines a P-type electrode and an N-type electrode pattern, and simultaneously deposits the P-type electrode and the N-type electrode, and removes the photoresist by a lift-off process to form a wafer.
  • the N-type electrode includes: an N-type line electrode and an N-type pad, the N-type line electrode is connected to the N-type pad, the N-type line electrode is deposited on the boss, the N-type line An active layer under the electrode is etched away or an active layer under the N-type line electrode is partially etched away, the N-type pad being deposited over the active layer, the P-type electrode comprising: P a pad and a P-type wire electrode, the P-type electrode being deposited on the boss, further
  • the N-type pad is deposited on a surface of the insulating layer
  • the N-type line electrode is deposited on a surface of the n-type nitride semiconductor layer.
  • the yellow light stripping process defines a P-type electrode and an N-type electrode pattern, and simultaneously deposits the P-type electrode and the N-type electrode, and removes the photoresist by a lift-off process to form a wafer.
  • the N-type electrode includes: an N-type line electrode and an N-type pad, the N-type line electrode is connected to the N-type pad, the N-type line electrode is deposited on the boss, the N-type line An active layer under the electrode is etched away or an active layer under the N-type line electrode is partially etched away, the N-type pad being deposited over the active layer, the P-type electrode comprising: P a pad and a P-type wire electrode, the P-type electrode being deposited on the boss, further
  • the N-type pad is deposited on a surface of the insulating layer
  • the N-type line electrode is deposited between the n-type nitride semiconductor layer and the insulating layer.
  • the yellow light stripping process defines a P-type electrode and an N-type electrode pattern, and simultaneously deposits the P-type electrode and the N-type electrode, and removes the photoresist by a lift-off process to form a wafer.
  • the N-type electrode includes: an N-type line electrode and an N-type pad, the N-type line electrode is connected to the N-type pad, the N-type line electrode is deposited on the boss, the N-type line An active layer under the electrode is etched away or an active layer under the N-type line electrode is partially etched away, the N-type pad being deposited over the active layer, the P-type electrode comprising: P a pad and a P-type wire electrode, the P-type electrode being deposited on the boss, further
  • the N-type pad is deposited on a surface of the insulating layer
  • the N-type line electrode is deposited on a surface of the insulating layer.
  • the P-type pad is deposited on the insulating layer; the P-type line electrode is deposited on the transparent conductive layer, or deposited between the transparent conductive layer and the insulating layer, or partially deposited on On the insulating layer.
  • the P-type pad is deposited on a surface of the transparent conductive layer; the P-type line electrode is deposited on a surface of the transparent conductive layer, or deposited between the transparent conductive layer and the insulating layer, or Partially deposited on the surface of the insulating layer.
  • the P-type pad is deposited between the insulating layer and the transparent conductive layer; the P-type line electrode is deposited on the surface of the transparent conductive layer or deposited on the transparent conductive layer and the insulating layer Interposed or deposited on the surface of the insulating layer.
  • the P-type pad, the N-type pad, the P-type line electrode, and the N-type line electrode have the same structure, and further, the P-type pad, the N-type pad, the P-type line electrode, and the N-type line
  • the electrode is composed of a first Ni layer, an Al layer, an intermediate Cr layer, a second Ni layer, and an Au layer which are sequentially arranged from the inside to the outside, or a first Ni layer, an Al layer, an intermediate Cr layer, and a Pt layer which are sequentially arranged from the inside to the outside.
  • the Cr layer, the Pt layer, and the Au layer are composed of a first Cr layer, an Al layer, a second Ni layer, a Pt layer, and an Au layer which are sequentially arranged from the inside to the outside.
  • the P-type pad and the N-type pad structure further, wherein the thickness of the first Ni layer is 0.4 to 3 nm, the thickness of the Al layer is 50 to 300 nm, and the thickness of the intermediate Cr layer is 10 to 300 nm, the thickness of the second Ni layer is 10 to 300 nm, the thickness of the Au layer is 200 to 3000 nm, the thickness of the Pt layer is 10 to 300 nm, the thickness of the Ti layer is 10 to 300 nm, and the thickness of the first Cr layer is 0.4 to 5 nm. .
  • the insulating layer is an insulating layer made of one or more of aluminum oxide, silicon dioxide, titanium dioxide, antimony pentoxide, antimony pentoxide, silicon oxynitride or silicon nitride. .
  • the height difference between the N-type pad and the P-type pad is lower than or equal to 300 nm.
  • the method for fabricating the III-group semiconductor light-emitting device described in the present application has the following advantages:
  • the manufacturing method provided by the present invention has fewer production steps than the high-order manufacturing process, shortens the production cycle, greatly reduces the production cost, and also restores the active layer under the N-type pad to solve the active layer.
  • the problem of excessive etching increases the active layer to improve the photoelectric characteristics, restores the active layer under the N-type pad, and also restores the active layer under the partial N-type line electrode, thus increasing the light-emitting area. Since the light-emitting area becomes large, the operating voltage is lowered and the brightness is increased.
  • the present invention also provides that the structure of the P-type pad or the N-type pad can be deposited anywhere above the insulating layer, so that it is not involved in the current distribution at all, and only the wire electrode is involved in the current distribution, so it is easier to design the mask. pattern.
  • the present invention reduces the active layer under the N-type pad, and since the light-emitting area becomes large, the contact resistance of the transparent conductive layer and the p-type nitride semiconductor layer decreases, so the operating voltage decreases;
  • the transparent conductive layer is fabricated together with the mesa pattern, which not only simplifies a process, but also solves the problem of alignment of the transparent conductive layer with the mesa pattern.
  • a pattern to be involved in the current distribution can be defined, so that the P-type pad, the P-type line electrode, and the N-type line electrode 14 can define a pattern to be involved in the current distribution by etching the region of the insulating layer, so the mask Design is easier.
  • the present invention also provides a new structure for a wire bond pad (metal) / insulating layer / transparent conductive layer, the structure is a capacitor structure, which can increase the yield of antistatic capability;
  • the difference in height between the P-type pad or the N-type pad in the prior art is 1100-1600 nm, However, the height difference between the P-type pad and the N-type pad in the present invention is lower than or equal to 300 nm, which is more advantageous than the conventional one in the prior art.
  • the present invention reduces the active layer under the N-type pad, and the smaller the chip size is, the more the active layer under the N-type pad occupies the percentage of the light-emitting area, so the smaller the operating voltage is, the more the brightness decreases. The more you rise.
  • 1 is a top plan view of a prior art Group III semiconductor light emitting device
  • Figure 2 is a cross-sectional view taken along line A-B of Figure 1;
  • FIG. 3 is a top plan view of a group III semiconductor light emitting device provided by the present invention.
  • FIG. 4 is a cross-sectional view of the N-type pad of FIG. 3 along the I-J direction to the N-type line electrode;
  • 5a-5c are cross-sectional views of the P-type pad of FIG. 3 taken along the line M-N;
  • Figure 6 is a cross-sectional view of the N-type pad of Figure 3 taken along the line C-D;
  • 7a-7c are cross-sectional views of the P-type line electrode of FIG. 3 taken along the E-F direction;
  • FIG. 8a-8c are cross-sectional views of the N-type line electrode of Fig. 3 taken along the G-H direction;
  • Figure 9 is a plan view of an N-type line electrode and an active layer therebelow;
  • Figure 10 is a cross-sectional view of the N-type wire electrode of Figure 9 taken along the line K-L;
  • Figure 11 is a wire bonding pad-insulating layer-transparent conductive layer and its equivalent circuit in the present invention.
  • FIG. 13 is a flow chart showing the fabrication of a III-group semiconductor light-emitting device according to the present invention.
  • first device if a first device is coupled to a second device, the first device can be directly electrically coupled to the second device, or electrically coupled indirectly through other devices or coupling means. Connected to the second device.
  • the description of the specification is intended to be illustrative of the preferred embodiments of the invention. The scope of protection of the application is subject to the definition of the appended claims.
  • FIG. 3 is a top view of a group III semiconductor light emitting device provided in this embodiment, and FIG. 4 is a cross-sectional view of the N-type pad of FIG. 3 along the IJ direction to the N-type line electrode;
  • FIG. 5a to FIG. 3 is a cross-sectional view of the P-type pad in the MN direction;
  • FIG. 6 is a cross-sectional view of the N-type pad in FIG. 3 along the CD direction;
  • FIGS. 7a to 7c are the P-type line electrode of FIG.
  • FIG. 8a to FIG. 8c are cross-sectional views of the N-type line electrode of FIG. 3 in the GH direction;
  • FIG. 9 is a plan view of the N-type line electrode and the active layer therebelow;
  • FIG. 10 is the N-type of FIG.
  • FIG. 11 is a cross-sectional view of the wire electrode in the KL direction;
  • FIG. 11 is a wire bonding pad-insulating layer-transparent conductive layer and
  • a group III nitride semiconductor light-emitting device was fabricated with a specification of 300 um x 700 um. Referring to Figures 12a - 12c and Figure 13,
  • the epitaxial structure is sequentially grown from the bottom to the top of the substrate 1, the buffer layer 2, the n-type nitride semiconductor layer 3, the active layer 4, and the p-type nitride semiconductor layer 5, and the upper surface of the epitaxial structure is p
  • the upper surface of the type nitride semiconductor layer 5, the structure is an epitaxial structure, which is obtained by a manufacturing process in the prior art,
  • a method of fabricating a chip on the epitaxial structure includes the following steps:
  • the structure diagram is as shown in FIG. 12a, in which a transparent conductive layer 7 is deposited, and ITO (indium tin oxide) is deposited by electron beam evaporation or sputtering as a transparent conductive layer 7 deposited on the p-type nitride semiconductor layer 5.
  • the thickness of the transparent conductive layer 7 is 10-300 nm; and the pattern of the boss 16 is defined by a yellow etching process, and the transparent conductive layer 7, the p-type nitride semiconductor layer 5 and the active layer 4 are etched by ICP to expose the n-type nitrogen.
  • the semiconductor layer 3, and then the transparent conductive layer 7 is retracted by an etching solution, and finally the photoresist is removed to form a nitride semiconductor structure having a bump, wherein the ICP etching gas is BCl 3 /Cl 2 /Ar;
  • the high temperature annealing forms a good ohmic contact and transmittance between the transparent conductive layer 7 and the p-type nitride semiconductor layer 5.
  • the annealing method was rapidly annealed by a rapid annealing furnace (RTA) at a temperature of 560 ° C for 3 minutes.
  • RTA rapid annealing furnace
  • PECVD plasma enhanced chemical vapor deposition
  • SiO 2 as the insulating layer 15.
  • the thickness of SiO 2 is 50-300 nm, wherein the power is 50 W, the pressure is 850 mTorr, and the temperature is 200-400 ° C.
  • N 2 O is 1000 sccm
  • N 2 is 400 sccm
  • 5% SiH 4 /N 2 is 400 sccm
  • a pattern to be applied to the current distribution is defined by a yellow etching process, and the insulating layer 15 is etched by dry or wet etching, and finally the light is removed. Resistance,
  • the insulating layer in this embodiment is silicon dioxide.
  • silicon dioxide Of course, one or two of aluminum oxide, titanium dioxide, antimony pentoxide, antimony pentoxide, silicon oxynitride or silicon nitride may be deposited as insulation. Layer, there is no specific limit here.
  • the yellow light stripping process defines patterns of the P-type electrode 8 and the N-type electrode 9 (including the P-type pad 11, the N-type pad 12, the P-type line electrode 13, and the N-type line electrode 14), and is simultaneously deposited by electron beam evaporation.
  • the P-type electrode 8 and the N-type electrode 9 further remove the photoresist, wherein the N-type electrode 9 includes: an N-type line electrode 14 and an N-type pad 12, the N-type line electrode 14 and the N-type solder
  • the disk 12 is connected, the N-type wire electrode 14 is deposited on the land, the active layer under the N-type wire electrode 14 is etched away, and the active layer under the N-type wire electrode 13 is further Partially etched away, the N-type pad 12 is deposited over the active layer 4, the P-type electrode comprising: a P-type pad 11 and a P-type line electrode 13, the P-type electrode 8 being deposited on On the boss.
  • the structure is shown in FIG. 12c.
  • the P-type electrode 8 and the N-type electrode 9 have the same structure, and each of the first Ni layer, the Al layer, and the second Ni layer are sequentially arranged outward from the surface layer of the nitride semiconductor layer.
  • a Pt layer and an Au layer the first Ni layer has a thickness of 0.4 to 3 nm
  • the Al layer has a thickness of 50 to 300 nm
  • the second Ni layer has a thickness of 10 to 300 nm
  • the Pt layer has a thickness of 10 to 300 nm
  • the Au layer has a thickness of 10 to 300 nm.
  • the thickness is 50-3000 nm.
  • the difference in height between the deposited N-type pad and the P-type pad is lower than or equal to 300 nm.
  • the N-type pad 12 is deposited on the surface of the insulating layer 15, and may also be embedded in the insulating layer 15.
  • the deposition position of the N-type line electrode 14 has various possibilities, and may be deposited on the surface of the n-type nitride semiconductor layer 3 (or embedded in the n-type nitride semiconductor layer 3), or may be deposited on the n Between the type nitride semiconductor layer 3 and the insulating layer 15 (that is, it is in contact with the n-type nitride semiconductor layer 3 and the insulating layer 15 at the same time, a part is in contact with the n-type nitride semiconductor layer 3, and a part is in contact with the insulating layer 15) On the basis of the first two deposition conditions, the N-type line electrode 14 can also be deposited on the surface of the insulating layer 15 (but this case cannot occur alone, and can only be combined with the first two deposition conditions, that is, partially deposited on the insulating layer. 15
  • the P-type pad 11 may be deposited on the insulating layer 15 (may be deposited on the surface of the insulating layer 15 or may be embedded in the insulating layer).
  • the layer 15) may also be deposited on the transparent conductive layer (which may be deposited on the surface of the transparent conductive layer 7 or embedded in the transparent conductive layer 7), or may be deposited between the insulating layer 15 and the transparent conductive layer 7 ( That is, it is in contact with the insulating layer 15 and the transparent conductive layer 7, and a part is in contact with the insulating layer 15, and a part is in contact with the transparent conductive layer 7, the same applies hereinafter.
  • the P-type wire electrode 13 may be deposited on the surface of the transparent conductive layer 7, and may also be deposited between the transparent conductive layer 7 and the insulating layer 15 (ie, At the same time, it is in contact with the insulating layer 15 and the transparent conductive layer 7, a part is in contact with the insulating layer 15, and a part is in contact with the transparent conductive layer 7, the same below), and the insulating layer may be deposited on the insulating layer.
  • P-type line electrode 13 can only be partially deposited on insulating layer 15.
  • the P-type pad 11, the N-type pad 12, the P-type line electrode 13, and the N-type line electrode 14 herein may have the same structure, and are a first Ni layer, an Al layer, and an intermediate Cr arranged in order from the inside to the outside.
  • the layer, the second Ni layer, and the Au layer may be composed of a first Ni layer, an Al layer, an intermediate Cr layer, a Pt layer, and an Au layer, which may be sequentially arranged from the inside to the outside, or may be arranged first in order from the inside to the outside.
  • the Ni layer, the Al layer, the second Ni layer, the Pt layer, and the Au layer may be composed of a first Ni layer, an Al layer, a Ti layer, a Pt layer, and an Au layer which are sequentially arranged from the inside to the outside, or may be inwardly oriented.
  • the first Ni layer, the Al layer, the Ti layer, the Pt layer, the Ti layer, the Pt layer, the Ti layer, the Pt layer, and the Au layer are sequentially arranged, and may be a first Cr layer or an Al layer sequentially arranged from the inside to the outside.
  • the intermediate Cr layer, the Pt layer, and the Au layer are composed of a first Cr layer, an Al layer, a second Ni layer, a Pt layer, and an Au layer, wherein the thickness of the first Ni layer is 0.4 to 3 nm, the thickness of the Al layer is 50 to 300 nm, and the thickness of the intermediate Cr layer is 10 to 300 nm,
  • the thickness of the second Ni layer is 10 to 300 nm, the thickness of the Au layer is 200 to 3000 nm, the thickness of the Pt layer is 10 to 300 nm, the thickness of the Ti layer is 10 to 300 nm, and the thickness of the first Cr layer is 0.4 to 5 nm.
  • the structures of the P-type pad 11, the N-type pad 12, the P-type line electrode 13, and the N-type line electrode 14 are not specifically limited.
  • a semiconductor light-emitting device obtained by the above method as shown in FIG. 4, a substrate 1, a buffer layer 2, an n-type nitride semiconductor layer 3, an active layer 4, and a p-type nitride semiconductor layer which are sequentially disposed from bottom to top 5.
  • the five layers constitute a boss 16 structure, and the upper surface of the boss 16 is the upper surface of the p-type nitride semiconductor layer, and the land is provided with an N-type line electrode 14, an N-type line electrode 14 and an n-type.
  • the nitride semiconductor layer 3 is in contact with each other. As shown in FIG.
  • the light emitting device herein further includes a P-type electrode 8, including: a P-type pad 11 and a P-type line electrode 13, and the P-type electrode 8 is deposited on the boss 16.
  • a group III semiconductor light-emitting device is further provided, which is provided with a substrate 1, a buffer layer 2, an n-type nitride semiconductor layer 3, an active layer 4, and a bottom layer.
  • the p-type nitride semiconductor layer 5, the five layers constitute the structure of the bump 16, and the upper surface of the bump 16 is the upper surface of the p-type nitride semiconductor layer, and the bump is provided with an N-type line electrode 14, N type
  • the line electrode 14 is in contact with the n-type nitride semiconductor layer 3, as shown in FIG.
  • the light emitting device herein further includes a P-type electrode 8, including: a P-type pad 11 and a P-type line electrode 13, and the P-type electrode 8 is deposited on the boss 16.
  • a transparent conductive layer 7 is deposited on the upper surface of the p-type nitride semiconductor layer 5, and an insulating layer 15 is deposited on the upper surface of the transparent conductive layer 7 and the surface of the land 16.
  • the light emitting device shown in FIGS. 5a to 8c is provided with an insulating layer 15 deposited on the upper surface of the transparent conductive layer 7 and the surface of the boss 16, as can be seen from the figure, the insulating layer 15
  • the transparent conductive layer 7 and the boss 16 are all wrapped therein for the purpose of insulation.
  • the insulating layer 15 is made of an insulating material, preferably aluminum oxide, silicon dioxide, titanium dioxide or tantalum pentoxide.
  • An insulating layer made of one or more of antimony pentoxide, silicon oxynitride or silicon nitride.
  • the insulating material in this embodiment is silicon dioxide.
  • the material is not specifically limited herein, nor is it The production method of the insulating material is specifically limited, and may be determined according to actual conditions.
  • the P-type electrode 8 of the light emitting device includes: P Type pad 11 and P type line electrode 13, wherein:
  • the position of the P-type pad 11 can be variously arranged, and the P-type pad 11 is deposited on the insulating layer 15 in FIG. 5a, so the P-type pad 11 does not participate in the current distribution; in another embodiment provided by the present invention, As shown in FIG. 5b, a P-type pad 11 is deposited on the transparent conductive layer 7. In still another embodiment of the present invention, as shown in FIG. 5c, the P-type pad 11 is simultaneously deposited on the insulating layer 15 and transparently conductive. Between layers 7.
  • the shape of the P-type pad 11 is not specifically limited in the present invention.
  • the P-type pad 11 may be circular, twenty-five, square or elliptical. In this embodiment, the P-type pad is circular.
  • the P-type wire electrode 13 may be deposited on the transparent conductive layer 7, or may be deposited between the transparent conductive layer 7 and the insulating layer 15, or may be deposited on the insulating layer 15, but deposited on the insulating layer 15. It is not possible to appear alone, and the P-type wire electrode 13 can only be partially deposited on the insulating layer 15.
  • the structure of the P-type pad 11 in this embodiment is composed of a first Ni layer, an Al layer, a second Ni layer, a Pt layer and an Au layer which are sequentially arranged from the inside to the outside, wherein the first Ni
  • the thickness of the layer is 0.4-3 nm
  • the thickness of the Al layer is 50-300 nm
  • the thickness of the second Ni layer is 10-200 nm
  • the thickness of the Pt layer is 10-300 nm
  • the thickness of the Au layer is 50-3000 nm.
  • the structure of the P-type line electrode is the same as that of the P-type pad 11.
  • the N-type pad 12 and the N-type line electrode 14 in the N-type electrode 9 are further:
  • the N-type pad 12 is deposited on the insulating layer 15, such that the N-type pad is 100% not involved in the current distribution, and such a structure achieves the purpose of designing the mask pattern more easily.
  • the shape of the N-type pad 12 is not specifically limited in the present invention, and the N-type pad 12 may be circular, twenty-five, square or elliptical, and the N-type pad 12 in this embodiment. It is a square.
  • the N-type line electrode 14 may be deposited on the n-type nitride semiconductor layer 3, or between the n-type nitride semiconductor layer 3 and the insulating layer 15, or may be partially deposited on the insulating layer 15, if partially deposited. On the insulating layer 15, the N-type line electrode 14 is partially involved in the current distribution.
  • the structure of the N-type pad 12 is composed of a first Ni layer, an Al layer, a second Ni layer, a Pt layer, and an Au layer which are sequentially arranged from the inside to the outside, wherein the first Ni layer has a thickness of 0.4-3 nm,
  • the thickness of the Al layer is 50-300 nm
  • the thickness of the second Ni layer is 10-300 nm
  • the thickness of the Pt layer is 10-300 nm
  • the thickness of the Au layer is 50-3000 nm.
  • the structure of the N-type line electrode 14 is the same as that of the N-type pad 12.
  • the material or structure of the N-type electrode 9 and the P-type electrode 8 are the same in the present invention.
  • the N-type pad 12 and the P-type pad 11 are deposited in the present invention. On the same side, in the same straight line direction.
  • the N-type pad 12 and the P-type pad 11 are at diagonal positions.
  • the positions of the N-type pad 12 and the P-type pad 11 of the present invention may also be deposited at diagonal positions, but are preferably deposited on the same side, where the specific positions of the N-type pad 12 and the P-type pad 11 are present. No specific restrictions.
  • the difference in height between the N-type pad 12 and the P-type pad 11 is lower than or equal to 300 nm, which is more advantageous for wire bonding.
  • the wire bond pad herein refers to an N-type pad 12 or a P-type pad.
  • This structure is a P-type pad 11/N type pad, an insulating layer and a transparent conductive layer from top to bottom, which is substantially a capacitor structure, so that the antistatic capability can be effectively increased.
  • the III-group semiconductor light-emitting device provided in this embodiment is further provided with a transparent conductive layer 7 on the upper surface of the boss 16.
  • the light emitting device shown in FIGS. 5a to 8c is further provided with an insulating layer 15 deposited on the upper surface of the transparent conductive layer 7 and the surface of the boss 16, as can be seen from the figure, the insulation
  • the layer 15 encloses the transparent conductive layer 7 and the boss 16 therein for the purpose of insulation.
  • the material of the insulating layer 15 here is an insulating material, preferably aluminum oxide, silicon dioxide, titanium dioxide or tantalum pentoxide.
  • An insulating layer made of one or more of tantalum pentoxide, silicon oxynitride or silicon nitride.
  • the insulating material in this embodiment is silicon dioxide.
  • the material is not specifically limited herein.
  • the production method of the insulating material is specifically limited, and may be determined according to actual conditions.
  • the light emitting device further includes a P-type electrode 8, as shown in FIGS. 5a to 5c, and 7a to 7c, including: a P-type pad 11 and a P-type line electrode 13, wherein:
  • the position of the P-type pad 11 can be variously arranged, and the P-type pad 11 is deposited on the insulating layer 15 in FIG. 5a, so the P-type pad 11 does not participate in the current distribution; in another embodiment provided by the present invention, As shown in FIG. 5b, a P-type pad 11 is deposited on the transparent conductive layer 7. In still another embodiment of the present invention, as shown in FIG. 5c, a P-type pad 11 is deposited on the insulating layer 15 and the transparent conductive layer. Between 7. The P-type pad 11 in this embodiment is deposited on the insulating layer 15.
  • the shape of the P-type pad 11 is not specifically limited in the present invention.
  • the P-type pad 11 may be circular, twenty-five, square or elliptical. In this embodiment, the P-type pad is circular.
  • the P-type line electrode 13 may be deposited on the transparent conductive layer 7, or may be deposited between the transparent conductive layer 7 and the insulating layer 15, or partially deposited on the insulating layer 15 (refer to the P-type line electrode 13 only) Some are located on the insulation layer and cannot be completely on the insulation layer).
  • the P-type electrode 8 in this embodiment is composed of a first Ni layer, an Al layer, a second Ni layer, a Pt layer and an Au layer which are sequentially arranged from the inside to the outside, wherein the thickness of the first Ni layer
  • the thickness of the Al layer is 0.4 to 300 nm
  • the thickness of the second Ni layer is 10 to 200 nm
  • the thickness of the Pt layer is 10 to 300 nm
  • the thickness of the Au layer is 50 to 3000 nm.
  • the N-type pad 12 and the N-type line electrode 14 in the N-type electrode 9 are further:
  • the N-type pad 12 is deposited on the insulating layer 15, such that the N-type pad is 100% not involved in the current distribution, and such a structure achieves the purpose of designing the mask pattern more easily.
  • the shape of the N-type pad 12 is not specifically limited in the present invention, and the N-type pad 12 may be circular, twenty-five, square or elliptical, and the N-type pad 12 in this embodiment. It is a square.
  • the N-type line electrode 14 may be deposited on the n-type nitride semiconductor layer 3, deposited on the n-type nitride semiconductor layer 3 and the insulating layer 15, and may also be deposited on the insulating layer 15, if partially deposited on the insulating layer. On the 15th, then the N-type line electrode 14 is partially involved in the current distribution.
  • the N-type electrode 9 is composed of a first Ni layer, an Al layer, a second Ni layer, a Pt layer, and an Au layer which are sequentially arranged from the inside to the outside, wherein the first Ni layer has a thickness of 0.4 to 3 nm, and the Al
  • the thickness of the layer is 50-300 nm
  • the thickness of the second Ni layer is 10-300 nm
  • the thickness of the Pt layer is 10-300 nm
  • the thickness of the Au layer is 50-3000 nm.
  • the material or structure of the N-type electrode 9 and the P-type electrode 8 are the same in the present invention.
  • the N-type pad 12 and the P-type pad 11 of the present invention are deposited on the same side in the same linear direction.
  • the N-type pad 12 and the P-type pad 11 are at diagonal positions.
  • the difference in height between the N-type pad 12 and the P-type pad 11 is lower than or equal to 300 nm, which is more advantageous for wire bonding.
  • the structure of the present embodiment has a wire bonding pad (metal)-insulating layer-transparent conductive layer, which constitutes a capacitor structure, the antistatic capability can be effectively increased.
  • FIG. 3 is a plan view of the III-group semiconductor light-emitting device provided in the present embodiment
  • FIGS. 4 to 8c are cross-sectional views of FIG. 3, respectively.
  • FIG. 5a-5c and FIG. 6 are cross-sectional views of the P-type pad 11 and the N-type pad 12 of FIG. 3 taken along the line MN and CD, respectively, and it can be seen that both the P-type pad 11 and the N-type pad 12 are deposited.
  • the active layer 4 wherein the structure of FIGS. 5a, 6 can be deposited anywhere above the insulating layer, the reticle pattern is easier to design because it does not affect the current distribution.
  • the P-type pad 11 and the N-type pad 12 in FIGS. 5a and 6 are under the insulating layer, so they are not involved in the current distribution. Therefore, only the P-type line electrode 13 and the N-type line electrode 14 are involved in the current distribution.
  • the P-type pads 11 of Figure 5b are all involved in the current distribution.
  • the P-type pad 11 of FIG. 5c is partially deposited on the insulating layer 15 and partially deposited on the transparent conductive layer 7, so that the P-type pad 11 portion of FIG. 5c does not participate in current distribution and partially participate in current distribution.
  • the P-type pad 11 and the N-type pad 12 of FIGS. 5a and 6 are under the insulating layer, so they are not involved in current distribution, but can increase the yield of antistatic capability because the structure is a wire bond pad (metal) / insulation Layer/transparent conductive layer, this structure is a capacitor structure, so this structure is applied to a semiconductor light-emitting device, the equivalent circuit is shown in Fig.
  • SiO 2 is an insulating layer
  • SiO 2 has a thickness d of 200 nm, a relative dielectric constant ⁇ r of 4, and a vacuum dielectric constant ⁇ 0 of 8.85 ⁇ 10 -12 F/m, which is substituted into a capacitance formula.
  • C ⁇ 0 ⁇ r S / d, as shown in Figure 11, a circular pad is produced to produce a capacitance of 1.39pF, which can increase the antistatic ability.
  • FIG. 7a-8c are cross-sectional views of the P-type line electrode 13 and the N-type line electrode 14 of FIG. 3, respectively.
  • the structure of FIG. 7c is usually not separately present, and is not involved in the current distribution, so it will be compared with FIG. 7a and FIG. 7b.
  • the structure is used together.
  • FIG. 10 is a cross-sectional view of the N-type line electrode in FIG. 9 along the KL direction, wherein the structures of FIG. 8c and FIG. 10 are usually not separately present, and are not involved in the current distribution, so FIG. 8a and FIG.
  • the structure in 8b is used together.
  • the embodiment provides a manufacturing method with a new structure applied to a group III nitride semiconductor light-emitting device.
  • the size of the light-emitting device is 300 um ⁇ 700 um
  • the group III nitride semiconductor device includes a substrate 1 on the substrate 1
  • An epitaxial growth buffer layer 2 an n-type nitride semiconductor layer 3 epitaxially grown on the buffer layer 2
  • an active layer 4 epitaxially grown on the n-type nitride semiconductor layer 3, in the active layer 4
  • the epitaxially grown p-type nitride semiconductor layer 5 is formed by conventional techniques of the prior art, and is not specifically limited herein.
  • the chip fabrication method includes the following steps:
  • the first step depositing a transparent conductive layer 7, depositing ITO as a transparent conductive layer by electron beam evaporation, depositing on the p-type nitride semiconductor layer 5, the thickness of the transparent conductive layer is 10-300 nm; and defining by a yellow etching process
  • the pattern of the bumps 16 is used to etch the transparent conductive layer 7, the p-type nitride semiconductor layer 5 and the active layer 4 by ICP, expose the n-type nitride semiconductor layer 3, and then shrink the transparent conductive layer 7 with an etching solution.
  • Annealing method is rapidly annealed by rapid annealing furnace (RTA) at a temperature of 560 ° C for 3 minutes;
  • the second step depositing SiO 2 using PECVD.
  • the thickness of SiO 2 is 50-300 nm, wherein the power is 50 W, the pressure is 850 mTorr, the temperature is 200 ° C, the N 2 O is 1000 sccm, the N 2 is 400 sccm, 5% SiH. 4 / N 2 is 400 sccm; the yellow light etching process is used to define the pattern to be involved in the current distribution, and then the insulating layer 15 is etched by dry or wet etching, and finally the photoresist is removed;
  • the third step: the yellow light stripping process defines a pattern of the P-type electrode 8, the N-type electrode 9 (including the P-type pad 11, the N-type pad 12, the P-type line electrode 13, and the N-type line electrode 14), and uses electron beam evaporation.
  • the P-type electrode 8 and the N-type electrode 9 are simultaneously deposited by the plating method, and the photoresist is removed.
  • the structure is shown in FIG. 12c.
  • the P-type electrode 8 and the N-type electrode 9 have the same structure, and are all formed by the surface layer of the nitride semiconductor layer.
  • first Ni layer a first Ni layer, an Al layer, a second Ni layer, a Pt layer, and an Au layer arranged in order
  • first Ni layer has a thickness of 0.4 to 1 nm
  • Al layer has a thickness of 50 to 300 nm.
  • the thickness of the second Ni layer is 10-300 nm
  • the thickness of the Pt layer is 10-300 nm
  • the thickness of the Au layer is 50-3000 nm;
  • Step 4 Finally, the wafer is thinned, diced, back-plated, split, tested, and sorted.
  • a prior art Group III nitride semiconductor light-emitting device as shown in FIGS. 1 and 2, comprising a substrate 1 on which a buffer layer 2 is epitaxially grown on the buffer layer 2
  • An epitaxially grown n-type nitride semiconductor layer 3 an active layer 4 epitaxially grown on the n-type nitride semiconductor layer 3, and a p-type nitride semiconductor layer 5 epitaxially grown on the active layer 4
  • a current blocking layer 6, a transparent conductive layer 7 and a P-type electrode 8 (including a P-type pad 11, a P-type line electrode 13) are deposited on the p-type nitride semiconductor 5, respectively, by etching the p-type nitride semiconductor layer 5
  • the active layer 4 while the N-type electrode 9 (including the N-type pad 12, the N-type line electrode 14) is formed on the exposed n-type nitride semiconductor layer 3, and finally the passivation layer 10 is deposited.
  • the existing III-nitride semiconductor light-emitting device is obtained through five steps, as follows:
  • a P-type electrode and an N-type electrode depositing a P-type electrode and an N-type electrode together, the P-type electrode comprising a P-type pad and a P-type line electrode, the P-type line electrode being deposited on the transparent conductive layer, a P-type pad deposited on the p-type nitride semiconductor layer, the N-type electrode being deposited on the n-type nitride semiconductor layer;
  • test conditions are the same as in the first embodiment.
  • the product of the prior art is labeled as XY1, and the product number S1 produced according to the method provided in the first embodiment is tested under the same conditions.
  • the test results are shown in Table 1:
  • the reverse voltage of S1 (input current is -10uA) and leakage (input voltage is -5V) are similar to XY1; the yield of S1 antistatic capability is much better than XY1; the operating voltage (input current is In terms of 120 mA), S1 is 0.1V lower than XY1; in terms of brightness, the average brightness of S1 is 22lm (64.6mW), the average brightness of XY1 is 20.7lm (61mW), and the brightness of illumination is increased by 6%; the overall yield is improved. >85%, good stability.
  • the III-group semiconductor light-emitting device described in the present application has the following advantages:
  • the manufacturing method provided by the present invention has fewer production steps than the high-order manufacturing process, shortens the production cycle, greatly reduces the production cost, and also restores the active layer under the N-type pad;
  • the problem of excessive etching increases the active layer to improve the photoelectric characteristics, restores the active layer under the N-type pad, and also restores the active layer under the partial N-type line electrode, thus increasing the light-emitting area. Since the light-emitting area becomes large, the operating voltage is lowered and the brightness is increased.
  • the present invention also provides that the structure of the P-type pad or the N-type pad can be deposited anywhere above the insulating layer, so that it is not involved in the current distribution at all, and only the wire electrode is involved in the current distribution, so it is easier to design the mask. pattern.
  • the active layer under the N-type pad is reduced, and since the light-emitting area is increased, the contact resistance between the transparent conductive layer and the p-type nitride semiconductor layer is lowered, so that the operating voltage is lowered.
  • the transparent conductive layer is fabricated together with the mesa pattern, which not only simplifies a process, but also solves the problem of alignment of the transparent conductive layer with the mesa pattern.
  • a pattern to be involved in the current distribution can be defined, so the P-type pad, the P-type line electrode, and the N-type line electrode can define the pattern to be involved in the current distribution by etching the region of the insulating layer, so the mask design It's easier.
  • the present invention also provides a new structure of a wire bond pad (metal) / insulating layer / transparent conductive layer, which is a capacitor structure, which can increase the yield of antistatic capability.
  • the difference in height between the P-type pad or the N-type pad in the prior art is 1100 to 1600 nm, and the difference in height between the P-type pad and the N-type pad in the present invention is lower than or equal to 300 nm.
  • the present invention is more advantageous than wire laying.
  • the present invention reduces the active layer under the N-type pad, and the smaller the chip size is, the more the active layer under the N-type pad occupies the percentage of the light-emitting area, so the smaller the operating voltage is, the more the brightness decreases. The more you rise.
  • the invention discloses a method for manufacturing a group III semiconductor light-emitting device of A1, which comprises the following steps:
  • the substrate, the buffer layer, the n-type nitride semiconductor layer, the active layer, and the p-type nitride semiconductor layer are sequentially grown from bottom to top to form an epitaxial structure, and an upper surface of the epitaxial structure is the p-type nitride semiconductor layer Upper surface
  • the yellow light stripping process defines a P-type electrode and an N-type electrode pattern, and simultaneously deposits the P-type electrode and the N-type electrode, and removes the photoresist by using a stripping process to form a wafer
  • the N-type electrode comprises: An N-type line electrode and an N-type pad, the N-type line electrode being connected to the N-type pad, the N-type line electrode being deposited on the boss, active under the N-type line electrode The layer is etched away or the active layer under the N-type line electrode is partially etched away, the N-type pad being deposited over the active layer, the P-type electrode comprising: a P-type pad and a P a wire electrode, the P-type electrode being deposited on the boss;
  • the wafer is thinned, diced, split, tested, and sorted.
  • the method of fabricating a III-group semiconductor light-emitting device wherein the yellow light stripping process defines a P-type electrode and an N-type electrode pattern, and simultaneously deposits the P-type electrode, the N-type
  • the electrode is formed into a wafer by using a stripping process to remove the photoresist, wherein the N-type electrode includes: an N-type line electrode and an N-type pad, and the N-type line electrode is connected to the N-type pad, The N-type line electrode is deposited on the land, the active layer under the N-type line electrode is etched away or the active layer under the N-type line electrode is partially etched away, the N-type solder a disk is deposited over the active layer, the P-type electrode includes: a P-type pad and a P-type line electrode, the P-type electrode is deposited on the boss, further
  • the N-type pad is deposited on a surface of the insulating layer
  • the N-type line electrode is deposited on a surface of the n-type nitride semiconductor layer.
  • the method of fabricating a III-group semiconductor light-emitting device wherein the yellow light stripping process defines a P-type electrode and an N-type electrode pattern, and simultaneously deposits the P-type electrode, the N-type
  • the electrode is formed into a wafer by using a stripping process to remove the photoresist, wherein the N-type electrode includes: an N-type line electrode and an N-type pad, and the N-type line electrode is connected to the N-type pad, The N-type line electrode is deposited on the land, the active layer under the N-type line electrode is etched away or the active layer under the N-type line electrode is partially etched away, the N-type solder a disk is deposited over the active layer, the P-type electrode includes: a P-type pad and a P-type line electrode, the P-type electrode is deposited on the boss, further
  • the N-type pad is deposited on a surface of the insulating layer
  • the N-type line electrode is deposited between the n-type nitride semiconductor layer and the insulating layer.
  • the N-type electrode is formed into a wafer by using a lift-off process to remove the photoresist, wherein the N-type electrode includes: an N-type line electrode and an N-type pad, and the N-type line electrode and the N-type pad are Connecting, the N-type line electrode is deposited on the land, the active layer under the N-type line electrode is etched away or the active layer under the N-type line electrode is partially etched away, the N a pad is deposited over the active layer, the P-type electrode comprising: a P-type pad and a P-type line electrode, the P-type electrode being deposited on the boss, further
  • the N-type pad is deposited on a surface of the insulating layer
  • the N-type line electrode is deposited on a surface of the insulating layer.
  • the P-type line electrode is deposited on the transparent conductive layer, or deposited between the transparent conductive layer and the insulating layer, or partially deposited on the insulating layer.
  • the P-type pad is deposited on a surface of the transparent conductive layer
  • the P-type line electrode is deposited on the surface of the transparent conductive layer, or between the transparent conductive layer and the insulating layer, or partially deposited on the surface of the insulating layer.
  • the P-type pad is deposited between the insulating layer and the transparent conductive layer;
  • the P-type line electrode is deposited on the surface of the transparent conductive layer, or between the transparent conductive layer and the insulating layer, or deposited on the surface of the insulating layer.
  • A8 The method of fabricating a group III semiconductor light-emitting device according to claim A, wherein the P-type pad, the N-type pad, the P-type line electrode, and the N-type line electrode have the same structure, and further,
  • the P-type pad, the N-type pad, the P-type line electrode, and the N-type line electrode are arranged in order from the inside to the outside a first Ni layer, an Al layer, an intermediate Cr layer, a second Ni layer, and an Au layer, or a first Ni layer, an Al layer, an intermediate Cr layer, a Pt layer, an Au layer, which are sequentially arranged from the inside to the outside, or a first Ni layer, an Al layer, a second Ni layer, a Pt layer, an Au layer arranged in sequence from the inside to the outside, or a first Ni layer, an Al layer, a Ti layer, a Pt layer, and an Au layer arranged in order from the inside to the outside, Or a first Ni layer, an Al layer, a Ti layer, a Pt layer, a Ti layer, a Pt layer, a Ti layer, a Pt layer, and an Au layer arranged in order from the inside to the outside, or a first Cr layer, Al arranged in order from the inside to the outside.
  • the thickness of the Ti layer is 10 to 300 nm, and the thickness of the first Cr layer is 0.4 to 5 nm.
  • insulating layer is aluminum oxide, silicon dioxide, titanium dioxide, antimony pentoxide, antimony pentoxide, and nitrogen.
  • An insulating layer made of one or two or more of silicon oxide or silicon nitride.

Abstract

本申请公开了一种III族半导体发光器件的制作方法，包括以下步骤：衬底、缓冲层、n型氮化物半导体层、有源层和p型氮化物半导体层自下而上依次生长形成外延结构；沉积透明导电层在所述p型氮化物半导体层上，利用黄光蚀刻制程定义凸台图案，得到凸台；沉积绝缘层在所述透明导电层的上表面及所述凸台的表面上；黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，最后将所述圆片进行减薄、划片、裂片、测试、分选。本发明提供的制作方法，比正装高阶的生产工序更少，生产周期缩短，大大降低了生产成本，而且也还原了N型焊盘下方的有源层，发光面积变大，操作电压下降，亮度上升。

Description

一种III族半导体发光器件的制作方法 技术领域
本申请涉及半导体照明技术领域，具体地说，是涉及一种III族半导体发光器件的制作方法。
背景技术
氮化镓基发光二极管的发光效率近些年得到了很大程度上的提高，但外部量子效率、电流分布均匀性已经成为制约发光二极管性能进一步提高的主要技术瓶颈。现有技术中蓝宝石衬底上氮化镓基发光二极管会因其P/N型电极均沉积于衬底同一则，其P型电极、N型电极一般包括线接合焊盘以及线电极，由于N型电极的线接合焊盘要用来焊接金球(金球直径一般为75um)，因此N型电极线接合焊盘尺寸设计的较大，这样就导致有源层蚀刻面积过大。
为了解决蓝宝石衬底上氮化镓基发光二极管存在有源层蚀刻面积过大问题，目前解决方法如下：
1、由激光剥离技术将衬底与氮化物半导体层相剥离而制造垂直式发光器件，虽然垂直结构发光二极管技术解决了传统蓝宝石衬底上氮化镓基发光二极管存在的问题，如散热、有源层蚀刻面积过大、电流分布均匀性等问题，但是衬底剥离工艺复杂，成本高昂且良率过低。
2、通过在蓝宝石衬底里形成多个蓝宝石孔，蓝宝石衬底孔壁和底部沉积一种N型半导体金属，并且每个孔被填满另一种金属以形成一个N型电极触点进而形成垂直结构发光二极管。但是此方案存在蓝宝石钻多个孔工艺复杂，成本高昂并且工艺可靠性较低等问题。
发明内容
为了解决在上述现有技术中出现的问题，本发明的目的是提供一种III族半导体发光器件的制作方法，以解决有源层蚀刻过多的问题，增加有源层从而改善光电特性，并通过提供的新结构让电流分布更均匀及增加抗静电的能 力。
本发明提供了一种III族半导体发光器件的制作方法，包括以下步骤：
衬底、缓冲层、n型氮化物半导体层、有源层和p型氮化物半导体层自下而上依次生长形成外延结构，所述外延结构的上表面为所述p型氮化物半导体层的上表面；
沉积透明导电层在所述p型氮化物半导体层上，并利用黄光蚀刻制程定义凸台图案，再蚀刻所述透明导电层、p型氮化物半导体层和有源层，而暴露所述n型氮化物半导体层，再用蚀刻溶液将所述透明导电层内缩，最后去除光阻，得到凸台，且所述凸台的上表面有透明导电层；
沉积绝缘层在所述透明导电层的上表面及所述凸台的表面上，利用黄光蚀刻制程定义要参于电流分布的图案，再蚀刻绝缘层，最后去除光阻；
黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上；
最后将所述圆片进行减薄、划片、裂片、测试、分选。
优选地，所述黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上，进一步为，
所述N型焊盘沉积于所述绝缘层表面上；
所述N型线电极沉积于所述n型氮化物半导体层表面上。
优选地，所述黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述 N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上，进一步为，
所述N型焊盘沉积于所述绝缘层表面上；
所述N型线电极沉积于所述n型氮化物半导体层及绝缘层之间。
优选地，所述黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上，进一步为，
所述N型焊盘沉积于所述绝缘层表面上；
所述N型线电极沉积于所述绝缘层表面上。
优选地，所述P型焊盘沉积于所述绝缘层上；所述P型线电极沉积于所述透明导电层上、或沉积于所述透明导电层及绝缘层之间、或部分沉积于所述绝缘层上。
优选地，所述P型焊盘沉积于所述透明导电层表面上；所述P型线电极沉积于所述透明导电层表面上、或沉积于所述透明导电层及绝缘层之间、或部分沉积于所述绝缘层表面上。
优选地，所述P型焊盘沉积于所述绝缘层及透明导电层之间；所述P型线电极沉积于所述透明导电层表面上、或沉积于所述透明导电层及绝缘层之间、或沉积于所述绝缘层表面上。
优选地，所述P型焊盘、N型焊盘、P型线电极、N型线电极结构相同，进一步地，所述P型焊盘、N型焊盘、P型线电极、N型线电极为由内向外依次排列的第一Ni层、Al层、中间Cr层、第二Ni层以及Au层组成，或由内向外依次排列的第一Ni层、Al层、中间Cr层、Pt层、Au层组成，或由内向外依次 排列的第一Ni层、Al层、第二Ni层、Pt层、Au层组成，或由内向外依次排列的第一Ni层、Al层、Ti层、Pt层以及Au层组成，或由内向外依次排列的第一Ni层、Al层、Ti层、Pt层、Ti层、Pt层、Ti层、Pt层以及Au层组成，或由内向外依次排列的第一Cr层、Al层、中间Cr层、Pt层、Au层组成，或由内向外依次排列的第一Cr层、Al层、第二Ni层、Pt层、Au层组成。
优选地，所述P型焊盘和N型焊盘结构，进一步的，其中所述第一Ni层的厚度为0.4～3nm，Al层的厚度为50～300nm，中间Cr层的厚度为10～300nm，第二Ni层的厚度为10～300nm，Au层的厚度为200～3000nm，Pt层的厚度为10～300nm，Ti层的厚度为10～300nm，第一Cr层的厚度为0.4～5nm。
优选地，所述绝缘层，为三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅或氮化硅中的一种或两种以上制成的绝缘层。
优选地，所述N型焊盘与所述P型焊盘之间的高度差低于或等于300nm。
与现有技术相比，本申请所述的III族半导体发光器件的制作方法，具有以下优点：
(1)本发明提供的制作方法，比正装高阶的生产工序更少，生产周期得到缩短，大大降低了生产成本，而且也还原了N型焊盘下方的有源层，以解决有源层蚀刻过多的问题，增加了有源层从而改善光电特性，还原了N型焊盘下方的有源层，还可以还原部分N型线电极下方的有源层，这样增加了发光面积。由于发光面积变大，所以操作电压下降，亮度上升。
(2)本发明也提供P型焊盘或N型焊盘的结构可沉积于绝缘层上方的任何位置，所以完全不参于电流分布，只有线电极参于电流分布，因此更容易设计光罩图案。本发明还原了N型焊盘下方的有源层，由于发光面积变大，透明导电层与p型氮化物半导体层的接触电阻下降，所以操作电压下降；
(3)本发明的方法中将透明导电层与台面图案一起制作，不但简化了一道制程，也解决了透明导电层与台面图案对准的问题。此外本发明中可以定义要参于电流分布的图案，所以P型焊盘、P型线电极及N型线电极14可以靠蚀刻绝缘层的区域来定义要参于电流分布的图案，所以光罩设计更容易。
(4)本发明也提供一种新结构为线接合焊盘(金属)/绝缘层/透明导电层,此结构为电容结构，可以增加抗静电能力的良率；
(5)现有技术中的P型焊盘或N型焊盘之间的高度差达1100-1600nm， 而本发明中P型焊盘和N型焊盘之间的高度差低于或等于300nm，相比现有技术本发明的比传统更有利于打线。
(6)本发明还原了N型焊盘下方的有源层，芯片尺寸越小还原N型焊盘下方的有源层占发光面积的百分比越多，所以越小尺寸操作电压下降越多，亮度上升越多。
当然，实施本申请的方法不必一定需要同时达到以上所述的所有技术效果。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为现有技术中III族半导体发光器件的俯视图；
图2为图1沿A-B方向的剖面图；
图3为本发明提供的III族半导体发光器件的俯视图；
图4为图3中的N型焊盘沿I-J方向至N型线电极的剖面图；
图5a-图5c为图3中的P型焊盘沿M-N方向的剖面图；
图6为图3中的N型焊盘沿C-D方向的剖面图；
图7a-图7c为图3中的P型线电极沿E-F方向的剖面图；
图8a-图8c为图3中的N型线电极沿G-H方向的剖面图；
图9为N型线电极及其下方的有源层的俯视图；
图10为图9中的N型线电极沿K-L方向的剖面图；
图11为本发明中的线接合焊盘-绝缘层-透明导电层及其等效电路；
图12a-图12c为实施例1中各步骤的产品剖面图；
图13为本发明提供的III族半导体发光器件制作流程图。
具体实施方式
如在说明书及权利要求当中使用了某些词汇来指称特定组件。本领域技术人员应可理解，硬件制造商可能会用不同名词来称呼同一个组件。本说明书及权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。如在通篇说明书及权利要求当中所提及的“包含”为一开放式用语，故应解释成“包含但不限定于”。“大致”是指在可接收的误差范围内，本领域技术人员能够在一定误差范围内解决所述技术问题，基本达到所述技术效果。此外，“耦接”一词在此包含任何直接及间接的电性耦接手段。因此，若文中描述一第一装置耦接于一第二装置，则代表所述第一装置可直接电性耦接于所述第二装置，或通过其他装置或耦接手段间接地电性耦接至所述第二装置。说明书后续描述为实施本申请的较佳实施方式，然所述描述乃以说明本申请的一般原则为目的，并非用以限定本申请的范围。本申请的保护范围当视所附权利要求所界定者为准。
以下结合附图对本申请作进一步详细说明，但不作为对本申请的限定。
实施例1：
如图3所示，为本实施例提供的III族半导体发光器件的俯视图，图4为图3中的N型焊盘沿I-J方向至N型线电极的剖面图；图5a至图5c为图3中的P型焊盘沿M-N方向的剖面图；图6为图3中的N型焊盘沿C-D方向的剖面图；图7a至图7c为图3中的P型线电极沿E-F方向的剖面图；图8a至图8c为图3中的N型线电极沿G-H方向的剖面图；图9为N型线电极及其下方的有源层的俯视图；图10为图9中的N型线电极沿K-L方向的剖面图；图11为本发明中的线接合焊盘-绝缘层-透明导电层及其等效电路图。
制作Ⅲ族氮化物半导体发光器件，规格为300um×700um。结合图12a-图12c和图13所示，
S1301：
在衬底1、缓冲层2、n型氮化物半导体层3、有源层4和所述p型氮化物半导体层5自下而上依次生长形成外延结构，所述外延结构的上表面为p型氮化物半导体层5的上表面，此结构为外延结构，其为通过现有技术中的制作工艺得到的，
在所述外延结构上制作芯片的方法包括以下步骤：
S1302：
结构图如图12a所示，方法为沉积透明导电层7，使用电子束蒸镀法或溅镀法沉积ITO(氧化铟锡)当透明导电层7，沉积在p型氮化物半导体层5上，透明导电层7的厚度为10-300nm；并利用黄光蚀刻制程定义凸台16图案，再利用ICP蚀刻透明导电层7、p型氮化物半导体层5和有源层4，而暴露n型氮化物半导体层3，再用蚀刻溶液将透明导电层7内缩，最后去除光阻，形成具有凸台的氮化物半导体结构，其中ICP刻蚀气体为BCl3/Cl2/Ar；再将Wafer进行高温退火，使透明导电层7与p型氮化物半导体层5之间形成良好的欧姆接触和穿透率。退火方式用快速退火炉(RTA)快速退火，温度为560℃，时间为3分钟。
S1303：
结构图如图12b所示，使用PECVD(等离子体增强化学气相沉积法沉积)SiO2当绝缘层15，SiO2厚度为50-300nm，其中功率为50W，压力为850mTorr，温度为200～400℃，N2O为1000sccm，N2为400sccm，5％SiH4/N2为400sccm；利用黄光蚀刻制程定义要参于电流分布的图案，再利用干法或湿法蚀刻绝缘层15，最后去除光阻，
本实施例中的绝缘层为二氧化硅，当然，还可以沉积三氧化二铝、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅或氮化硅中的一种或两种作为绝缘层，这里不做具体限定。
S1304：
黄光剥离制程定义P型电极8和N型电极9(包含P型焊盘11、N型焊盘12及P型线电极13、N型线电极14)图案，使用电子束蒸镀法同时沉积P型电极8和N型电极9，再去除光阻，其中，所述N型电极9包括：N型线电极14与N型焊盘12，所述N型线电极14与所述N型焊盘12相连接，所述N型线电极14沉积在所述凸台上，所述N型线电极14下方的有源层被蚀刻掉，还可以所述N型线电极13下方的有源层被部分蚀刻掉，所述N型焊盘12沉积在所述有源层4的上方，所述P型电极包括：P型焊盘11与P型线电极13，所述P型电极8沉积在所述凸台上。其结构详见图12c；本实施例中P型电极8和N型电极9结构相同，且均为由氮化物半导体层的表层向外依次排列的第一Ni层、Al层、第二Ni层、Pt层以及Au层，第一Ni层的厚度为0.4～3nm，Al层的厚度为50-300nm，第二Ni层的厚度为10-300nm，Pt层的厚度为10-300nm，Au层的厚度为50-3000nm。 沉积后N型焊盘与所述P型焊盘之间的高度差低于或等于300nm。
本步骤中是N型焊盘12沉积于所述绝缘层15表面上，还可以嵌入到绝缘层15内。而N型线电极14的沉积位置有多种可能，可以沉积于所述n型氮化物半导体层3的表面上(或者嵌入到n型氮化物半导体层3内)，也可以沉积于所述n型氮化物半导体层3及绝缘层15之间(即同时与n型氮化物半导体层3及绝缘层15相接触，一部分与n型氮化物半导体层3相接触，一部分与绝缘层15相接触)，在前两种沉积情况的基础上N型线电极14还可以沉积于绝缘层15表面上(但是这种情况不能单独出现，只能与前两种沉积情况相配合，即部分沉积于绝缘层15表面上)。
对于P型焊盘11和P型线电极13的沉积位置，也有多种可能：P型焊盘11可以沉积于所述绝缘层15上(可以沉积在绝缘层15表面上，也可以嵌入到绝缘层15内)，还可以沉积在透明导电层上(可以沉积在透明导电层7表面上，也可以嵌入到透明导电层7内)，还可以沉积在绝缘层15及透明导电层7之间(即同时与绝缘层15及透明导电层7相接触，一部分与绝缘层15相接触，一部分与透明导电层7相接触，下同)。对于P型线电极13的沉积位置有以下几种可能：P型线电极13可以沉积于所述透明导电层7表面上，还可以沉积于所述透明导电层7及绝缘层15之间(即同时与绝缘层15及透明导电层7相接触，一部分与绝缘层15相接触，一部分与透明导电层7相接触，下同)，在前两种沉积位置的基础上还可以沉积于所述绝缘层15表面上，但是P型线电极13只能是部分沉积于绝缘层15上。
当然，这里的P型焊盘11、N型焊盘12、P型线电极13、N型线电极14可以是结构相同的，为由内向外依次排列的第一Ni层、Al层、中间Cr层、第二Ni层以及Au层组成，还是可以是由内向外依次排列的第一Ni层、Al层、中间Cr层、Pt层、Au层组成，也可以是由内向外依次排列的第一Ni层、Al层、第二Ni层、Pt层、Au层组成，也可以是由内向外依次排列的第一Ni层、Al层、Ti层、Pt层以及Au层组成，也可以是由内向外依次排列的第一Ni层、Al层、Ti层、Pt层、Ti层、Pt层、Ti层、Pt层以及Au层组成，也可以是由内向外依次排列的第一Cr层、Al层、中间Cr层、Pt层、Au层组成，还可以由内向外依次排列的第一Cr层、Al层、第二Ni层、Pt层、Au层组成，其中所述第一Ni层的厚度为0.4～3nm，Al层的厚度为50～300nm，中间Cr层的厚度为10～300nm，第 二Ni层的厚度为10～300nm，Au层的厚度为200～3000nm，Pt层的厚度为10～300nm，Ti层的厚度为10～300nm，第一Cr层的厚度为0.4～5nm，这里对P型焊盘11、N型焊盘12、P型线电极13和N型线电极14的结构不做具体限定。
S1305：最后将圆片进行减薄、划片、背镀、裂片、测试、分选。
利用上述方法制得的半导体发光器件，如图4所示，自下而上依次设置的衬底1、缓冲层2、n型氮化物半导体层3、有源层4和p型氮化物半导体层5，这五个层构成凸台16结构，凸台16的上表面即为p型氮化物半导体层的上表面，该凸台上设有N型线电极14，N型线电极14与n型氮化物半导体层3相接触，如图9所示，N型线电极14下方的有源层4被部分蚀刻掉，N型线电极14还连接有N型焊盘12，该N型焊盘12沉积于有源层4上方，N型线电极14与N型焊盘12组成N型电极9。这里的发光器件还包括P型电极8，包括：P型焊盘11与P型线电极13，该P型电极8沉积于所述凸台16上。
此外，在本发明的另一实施例中还提供一种III族半导体发光器件，其自下而上依次设置的衬底1、缓冲层2、n型氮化物半导体层3、有源层4和p型氮化物半导体层5，这五个层构成凸台16结构，凸台16的上表面即为p型氮化物半导体层的上表面，该凸台上设有N型线电极14，N型线电极14与n型氮化物半导体层3相接触，如图3所示，N型线电极14下方的有源层4全部被蚀刻掉，N型线电极14还连接有N型焊盘12，该N型焊盘12沉积于有源层4上方，N型线电极14与N型焊盘12组成N型电极9。这里的发光器件还包括P型电极8，包括：P型焊盘11与P型线电极13，该P型电极8沉积于所述凸台16上。
如图4至图8c所示，透明导电层7沉积于p型氮化物半导体层5上表面，绝缘层15沉积于透明导电层7的上表面及凸台16的表面。
如图5a至图8c中所示发光器件设有绝缘层15，该绝缘层15沉积于所述透明导电层7的上表面及所述凸台16的表面，从图中可以看出，绝缘层15将透明导电层7和凸台16全部包裹在其中以达到绝缘的目的，这里的绝缘层15的材质为绝缘材料，优选地是三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅或氮化硅中的一种或两种以上制成的绝缘层，本实施例中的绝缘材料为二氧化硅，当然这里不对其材质做具体限定，也不对其绝缘材料的生产方法做具体限定，具体可以实际情况而定。
如图5a至图5c、和图7a至图7c中所示，该发光器件的P型电极8，包括：P 型焊盘11和P型线电极13，其中：
P型焊盘11的位置可以有多种设置，图5a中P型焊盘11沉积于绝缘层15上，所以P型焊盘11不参与电流分布；在本发明提供的另外一个实施例中，如图5b所示，P型焊盘11沉积于透明导电层7上；在本发明提供的又一个实施例中，如图5c所示，P型焊盘11同时沉积于绝缘层15及透明导电层7之间。
本发明中不对P型焊盘11的形状做具体限定，P型焊盘11可以为圆形、二十五边形、正方形或椭圆形，本实施例中P型焊盘为圆形。
P型线电极13可以沉积于透明导电层7上，还可以沉积于所述透明导电层7及绝缘层15之间，也可以沉积于绝缘层15上，但是沉积于绝缘层15上这种情况不可以单独出现，P型线电极13只能是部分沉积于绝缘层15上。需要说明的是，本实施例中的P型焊盘11的结构为由内而外依次排列的第一Ni层、Al层、第二Ni层、Pt层和Au层组成，其中，第一Ni层的厚度为0.4-3nm，Al层的厚度为50-300nm，第二Ni层的厚度为10-200nm，Pt层的厚度为10-300nm，Au层的厚度为50-3000nm。而P型线电极的结构与P型焊盘11相同。
本发明提供的发光器件，其N型电极9中的N型焊盘12和N型线电极14进一步为：
N型焊盘12沉积于绝缘层15上，这样的N型焊盘是100％不参与电流分布的，这样的结构达到了更容易设计光罩图案的目的。
需要说明的是本发明中不对N型焊盘12的形状做具体限定，N型焊盘12可以为圆形、二十五边形、正方形或椭圆形，本实施例中的N型焊盘12为正方形。
再者，N型线电极14可以沉积于n型氮化物半导体层3上，或者沉积于n型氮化物半导体层3及绝缘层15之间，还可以部分沉积于绝缘层15上，如果部分沉积于绝缘层15上，那么N型线电极14就部分参与电流分布。N型焊盘12的结构为由内而外依次排列的第一Ni层、Al层、第二Ni层、Pt层和Au层组成，其中，所述第一Ni层的厚度为0.4-3nm，所述Al层的厚度为50-300nm，所述第二Ni层的厚度为10-300nm，所述Pt层的厚度为10-300nm，所述Au层的厚度为50-3000nm。这里N型线电极14的结构与N型焊盘12的结构相同。
由此可见，本发明中N型电极9与P型电极8的材质或结构是相同的。
从图3与图1的对比中可以看出，本发明中的N型焊盘12与P型焊盘11沉积 于同一侧，在同一直线方向。而现有技术中(如图1所示)，N型焊盘12和P型焊盘11是在对角的位置。本发明的N型焊盘12与P型焊盘11的位置也可以沉积于对角位置，只是较优的情况沉积于同一侧，这里对于N型焊盘12与P型焊盘11的具体位置不做具体限定。本发明的这种结构中N型焊盘12与P型焊盘11的高度差低于或等于300nm，这样更有利于打线。如图10所示，由于本实施例中结构中还具有线接合焊盘(金属)-绝缘层-透明导电层的结构，这里的线接合焊盘是指N型焊盘12或P型焊盘11，这种结构也就是自上而下依次为P型焊盘11/N型焊盘、绝缘层和透明导电层，其实质上是一个电容结构，所以能够有效地增加抗静电能力。
如图4至图8c所示，本实施例提供的III族半导体发光器件在凸台16上表面还设有透明导电层7。
如图5a至图8c中所示发光器件还设有绝缘层15，该绝缘层15沉积于所述透明导电层7的上表面及所述凸台16的表面，从图中可以看出，绝缘层15将透明导电层7和凸台16全部包裹在其中以达到绝缘的目的，这里的绝缘层15的材质为绝缘材料，优选地是三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅或氮化硅中的一种或两种以上制成的绝缘层，本实施例中的绝缘材料为二氧化硅，当然这里不对其材质做具体限定，也不对其绝缘材料的生产方法做具体限定，具体可以实际情况而定。
该发光器件还包括P型电极8，如图5a至图5c、和图7a至图7c中所示，包括：P型焊盘11和P型线电极13，其中：
P型焊盘11的位置可以有多种设置，图5a中P型焊盘11沉积于绝缘层15上，所以P型焊盘11不参与电流分布；在本发明提供的另外一个实施例中，如图5b所示，P型焊盘11沉积于透明导电层7上；在本发明提供的又一个实施例中，如图5c所示，P型焊盘11沉积于绝缘层15及透明导电层7之间。本实施例中的P型焊盘11沉积于绝缘层15上。
本发明中不对P型焊盘11的形状做具体限定，P型焊盘11可以为圆形、二十五边形、正方形或椭圆形，本实施例中P型焊盘为圆形。
P型线电极13可以沉积于透明导电层7上，也可以沉积于所述透明导7电层及绝缘层15之间，或者部分沉积于绝缘层15上(是指P型线电极13只能有一部分位于绝缘层上，不能完全位于绝缘层上)。
需要说明的是，本实施例中的P型电极8为由内而外依次排列的第一Ni层、Al层、第二Ni层、Pt层和Au层组成，其中，第一Ni层的厚度为0.4-3nm，Al层的厚度为50-300nm，第二Ni层的厚度为10-200nm，Pt层的厚度为10-300nm，Au层的厚度为50-3000nm。
本发明提供的发光器件，其N型电极9中的N型焊盘12和N型线电极14进一步为：
N型焊盘12沉积于绝缘层15上，这样的N型焊盘是100％不参与电流分布的，这样的结构达到了更容易设计光罩图案的目的。
需要说明的是本发明中不对N型焊盘12的形状做具体限定，N型焊盘12可以为圆形、二十五边形、正方形或椭圆形，本实施例中的N型焊盘12为正方形。
再者，N型线电极14可以沉积于n型氮化物半导体层3上，沉积于n型氮化物半导体层3及绝缘层15上，还可以沉积于绝缘层15上，如果部分沉积于绝缘层15上，那么N型线电极14就部分参与电流分布。
N型电极9为由内而外依次排列的第一Ni层、Al层、第二Ni层、Pt层和Au层组成，其中，所述第一Ni层的厚度为0.4-3nm，所述Al层的厚度为50-300nm，所述第二Ni层的厚度为10-300nm，所述Pt层的厚度为10-300nm，所述Au层的厚度为50-3000nm。
由此可见，本发明中N型电极9与P型电极8的材质或结构是相同的。
从图3与图1的对比中可以看出，本发明中的N型焊盘12与P型焊盘11沉积于同一侧，在同一直线方向。而现有技术中(如图1所示)，N型焊盘12和P型焊盘11是在对角的位置。本发明的这种结构中N型焊盘12与P型焊盘11的高度差低于或等于300nm，这样更有利于打线。
如图11所示，由于本实施例中结构中具有线接合焊盘(金属)-绝缘层-透明导电层的结构，其构成了一个电容结构，所以能够有效地增加抗静电能力。
实施例2：
在实施例1的基础上，图3是本实施例提供的III族半导体发光器件的俯视图，而图4至图8c分别是图3的截面图。
图5a-图5c、图6分别是图3的P型焊盘11和N型焊盘12沿M-N及C-D剖面线之截面图，可看出P型焊盘11和N型焊盘12皆沉积于有源层4的上方，其中图5a、图6的结构可沉积于绝缘层上方的任何位置，因为不影响电流分布，因此更容易设计光罩图案。
图5a、图6中的P型焊盘11和N型焊盘12下方是绝缘层，所以不参于电流分布，因此该结构只有P型线电极13、N型线电极14参于电流分布。图5b的P型焊盘11皆参于电流分布。而图5c的P型焊盘11部分沉积于绝缘层15上及部分沉积于透明导电层7上，所以图5c的P型焊盘11部分不参与电流分布及部分参与电流分布。
图5a、6的P型焊盘11和N型焊盘12下方是绝缘层，所以不参于电流分布，但是可以增加抗静电能力的良率，因为结构为线接合焊盘(金属)/绝缘层/透明导电层，此结构为电容结构，所以将此结构运用在半导体发光器件上，等效电路如图11，假设圆形焊盘的半径为50μm，圆形焊盘面积S为7.85×10-9m2，本实施例中SiO2为绝缘层，SiO2厚度d为200nm，相对介电常数εr为4，真空介电常数ε0为8.85×10-12F/m，代入电容公式C＝ε0εrS/d，如图11所示，得到一个圆形焊盘产生电容1.39pF，可以增加抗静电的能力。
图7a-图8c分别是图3的P型线电极13、N型线电极14的截面图，图7c的结构通常不单独存在，因为不参于电流分布，所以会和图7a、图7b的结构一起使用，另外图10为图9中的N型线电极沿K-L方向的剖面图，其中图8c和图10的结构通常不单独存在，因为不参于电流分布，所以会和图8a和图8b中的结构一起使用。
实施例3：
本实施例提供一种具有新结构运用于Ⅲ族氮化物半导体发光器件的制作方法，发光器件的规格为300um×700um，所述Ⅲ族氮化物半导体器件包括衬底1，在所述衬底1上外延生长缓冲层2，在所述缓冲层2上外延生长n型氮化物半导体层3，在所述n型氮化物半导体层3上外延生长的有源层4，在所述有源层4上外延生长的p型氮化物半导体层5，这些方法均为现有技术的常规技术手段实现，这里不做具体限定，其芯片制作方法包括以下步骤：
第一步：沉积透明导电层7，使用电子束蒸镀法沉积ITO当透明导电层， 沉积在p型氮化物半导体层5上，透明导电层厚度为10-300nm；并利用黄光蚀刻制程定义凸台16图案，再利用ICP蚀刻透明导电层7、p型氮化物半导体层5和有源层4，而暴露n型氮化物半导体层3,再用蚀刻溶液将透明导电层7内缩，最后去除光阻，形成具有凸台的氮化物半导体结构，其中ICP刻蚀气体为BCl3/Cl2/Ar；再将Wafer进行高温退火，使透明导电层7与p型氮化物半导体层5之间形成良好的欧姆接触和穿透率。退火方式用快速退火炉(RTA)快速退火，温度为560℃，时间为3分钟；
第二步：使用PECVD沉积SiO2当绝缘层15，SiO2厚度为50-300nm,其中功率为50W，压力为850mTorr，温度为200℃，N2O为1000sccm，N2为400sccm，5％SiH4/N2为400sccm；利用黄光蚀刻制程定义要参于电流分布的图案，再用干法或湿法蚀刻绝缘层15，最后去除光阻；
第三步：黄光剥离制程定义P型电极8、N型电极9(包含P型焊盘11、N型焊盘12及P型线电极13、N型线电极14)图案，使用电子束蒸镀法同时沉积P型电极8、N型电极9，再去除光阻，其结构详见图12c；所述P型电极8、N型电极9结构相同，且均为由氮化物半导体层的表层向外依次排列的第一Ni层、Al层、第二Ni层、Pt层、Au层，所述第一Ni层的厚度为0.4-1nm，所述Al层的厚度为50-300nm，所述第二Ni层的厚度为10-300nm，所述Pt层的厚度为10-300nm，所述Au层的厚度为50-3000nm；
第四步：最后将圆片进行减薄、划片、背镀、裂片、测试、分选。
对比试验：
对比试验:为现有技术的Ⅲ族氮化物半导体发光器件，如图1和图2所示：包括衬底1，在所述衬底1上外延生长缓冲层2，在所述缓冲层2上外延生长的n型氮化物半导体层3，在所述n型氮化物半导体层3上外延生长的有源层4，在所述有源层4上外延生长的p型氮化物半导体层5，在所述p型氮化物半导体5上分别沉积电流阻挡层6，透明导电层7及P型电极8(包含P型焊盘11，P型线电极13)，在通过蚀刻p型氮化物半导体层5和有源层4，而暴露n型氮化物半导体层3上形成N型电极9(包含N型焊盘12，N型线电极14)，最后沉积钝化层10。其制作流程如下：
现有的Ⅲ族氮化物半导体发光器件通过五个步骤获得，详情如下：
(1)制作凸形台面：通过蚀刻p型氮化物半导体层和有源层而暴露n型氮化物半导体层；
(2)制作电流阻挡层：沉积电流阻挡层在p型氮化物半导体层上；
(3)制作透明导电层：沉积在p型氮化物半导体层及电流阻挡层上；
(4)制作P型电极和N型电极：一起沉积P型电极以及N型电极，P型电极包括P型焊盘以及P型线电极，所述P型线电极沉积在透明导电层上，所述P型焊盘沉积在所述p型氮化物半导体层上，所述N型电极沉积在n型氮化物半导体层上；
(5)制作钝化层：最后沉积钝化层，并开孔让P型焊盘及N型电极中的N型焊盘露出。
试验条件与实施例1相同，将现有技术产品标号为XY1，按照实施例1提供的方法制作的产品标号S1，在同一条件下进行检测，测试结果如表1所示：
表1 S1、XY1比较数据表
Figure PCTCN2015086436-appb-000001
从表1中可知，S1的逆向电压(输入电流为-10uA)以及漏电(输入电压为-5V)特性与XY1差不多；S1抗静电能力的良率远好于XY1；在操作电压(输入电流为120mA)方面，S1与XY1比较，电压下降0.1V；在亮度方面，S1的平均亮度为22lm(64.6mW)，XY1的平均亮度为20.7lm(61mW)，发光亮度提升了6％；综合良率>85％，稳定性好。
与现有技术相比，本申请所述的III族半导体发光器件，具有以下优点：
(1)本发明提供的制作方法，比正装高阶的生产工序更少，生产周期得到缩短，大大降低了生产成本，而且也还原了N型焊盘下方的有源层；以解决有源层蚀刻过多的问题，增加了有源层从而改善光电特性，还原了N型焊盘下方的有源层，还可以还原部分N型线电极下方的有源层，这样增加了发光面积。由于发光面积变大，所以操作电压下降，亮度上升。
(2)本发明也提供P型焊盘或N型焊盘的结构可沉积于绝缘层上方的任何位置，所以完全不参于电流分布，只有线电极参于电流分布，因此更容易设计光罩图案。本发明还原了N型焊盘下方的有源层，由于发光面积变大，透明导电层与p型氮化物半导体层的接触电阻下降，所以操作电压下降。
(3)本发明的方法中将透明导电层与台面图案一起制作，不但简化了一道制程，也解决了透明导电层与台面图案对准的问题。此外本发明中可以定义要参于电流分布的图案，所以P型焊盘、P型线电极及N型线电极可以靠蚀刻绝缘层的区域来定义要参于电流分布的图案，所以光罩设计更容易。
(4)本发明也提供一种新结构为线接合焊盘(金属)/绝缘层/透明导电层,此结构为电容结构，可以增加抗静电能力的良率。
(5)现有技术中的P型焊盘或N型焊盘之间的高度差达1100～1600nm，而本发明中P型焊盘和N型焊盘之间的高度差低于或等于300nm，相比现有技术本发明的比传统更有利于打线。
(6)本发明还原了N型焊盘下方的有源层，芯片尺寸越小还原N型焊盘下方的有源层占发光面积的百分比越多，所以越小尺寸操作电压下降越多，亮度上升越多。
上述说明示出并描述了本申请的若干优选实施例，但如前所述，应当理解本申请并非局限于本文所披露的形式，不应看作是对其他实施例的排除，而可用于各种其他组合、修改和环境，并能够在本文所述申请构想范围内，通过上述教导或相关领域的技术或知识进行改动。而本领域人员所进行的改动和变化不脱离本申请的精神和范围，则都应在本申请所附权利要求的保护范围内。
本发明公开了A1一种III族半导体发光器件的制作方法，其特征在于，包括以下步骤：
衬底、缓冲层、n型氮化物半导体层、有源层和p型氮化物半导体层自下而上依次生长形成外延结构，所述外延结构的上表面为所述p型氮化物半导体层的上表面；
沉积透明导电层在所述p型氮化物半导体层上，并利用黄光蚀刻制程定义凸台图案，再蚀刻所述透明导电层、p型氮化物半导体层和有源层，而暴露所述n型氮化物半导体层，再用蚀刻溶液将所述透明导电层内缩，最后去 除光阻，得到凸台，且所述凸台的上表面有透明导电层；
沉积绝缘层在所述透明导电层的上表面及所述凸台的表面上，利用黄光蚀刻制程定义要参于电流分布的图案，再蚀刻绝缘层，最后去除光阻；
黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上；
最后将所述圆片进行减薄、划片、裂片、测试、分选。
A2、根据权利要求A1所述的III族半导体发光器件的制作方法，其特征在于，所述黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上，进一步为，
所述N型焊盘沉积于所述绝缘层表面上；
所述N型线电极沉积于所述n型氮化物半导体层表面上。
A3、根据权利要求A1所述的III族半导体发光器件的制作方法，其特征在于，所述黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上，进一步为，
所述N型焊盘沉积于所述绝缘层表面上；
所述N型线电极沉积于所述n型氮化物半导体层及绝缘层之间。
A4、根据权利要求A2或A3所述的III族半导体发光器件的制作方法，其特征在于，所述黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上，进一步为，
所述N型焊盘沉积于所述绝缘层表面上；
所述N型线电极沉积于所述绝缘层表面上。
A5、根据权利要求A4所述的III族半导体发光器件的制作方法，其特征在于，
所述P型焊盘沉积于所述绝缘层上；
所述P型线电极沉积于所述透明导电层上、或沉积于所述透明导电层及绝缘层之间、或部分沉积于所述绝缘层上。
A6、根据权利要求A4所述的III族半导体发光器件的制作方法，其特征在于，
所述P型焊盘沉积于所述透明导电层表面上；
所述P型线电极沉积于所述透明导电层表面上、或沉积于所述透明导电层及绝缘层之间、或部分沉积于所述绝缘层表面上。
A7、根据权利要求A4所述的III族半导体发光器件的制作方法，其特征在于，
所述P型焊盘沉积于所述绝缘层及透明导电层之间；
所述P型线电极沉积于所述透明导电层表面上、或沉积于所述透明导电层及绝缘层之间、或沉积于所述绝缘层表面上。
A8、根据权利要求A4所述的III族半导体发光器件的制作方法，其特征在于，所述P型焊盘、N型焊盘、P型线电极、N型线电极结构相同，进一步地，
所述P型焊盘、N型焊盘、P型线电极、N型线电极为由内向外依次排列 的第一Ni层、Al层、中间Cr层、第二Ni层以及Au层组成，或由内向外依次排列的第一Ni层、Al层、中间Cr层、Pt层、Au层组成，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Pt层、Au层组成，或由内向外依次排列的第一Ni层、Al层、Ti层、Pt层以及Au层组成，或由内向外依次排列的第一Ni层、Al层、Ti层、Pt层、Ti层、Pt层、Ti层、Pt层以及Au层组成，或由内向外依次排列的第一Cr层、Al层、中间Cr层、Pt层、Au层组成，或由内向外依次排列的第一Cr层、Al层、第二Ni层、Pt层、Au层组成。
A9、根据权利要求A8所述的III族半导体发光器件的制作方法，其特征在于，所述P型焊盘和N型焊盘结构，进一步的，其中所述第一Ni层的厚度为0.4～3nm，Al层的厚度为50～300nm，中间Cr层的厚度为10～300nm，第二Ni层的厚度为10～300nm，Au层的厚度为200～3000nm，Pt层的厚度为10～300nm，Ti层的厚度为10～300nm，第一Cr层的厚度为0.4～5nm。
A10、根据权利要求A1所述的III族半导体发光器件的制作方法，其特征在于，所述绝缘层，为三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅或氮化硅中的一种或两种以上制成的绝缘层。
A11、根据权利要求A1所述的III族半导体发光器件的制作方法，其特征在于，所述N型焊盘与所述P型焊盘之间的高度差低于或等于300nm。

Claims (11)

  1. 一种III族半导体发光器件的制作方法，其特征在于，包括以下步骤：
    衬底、缓冲层、n型氮化物半导体层、有源层和p型氮化物半导体层自下而上依次生长形成外延结构，所述外延结构的上表面为所述p型氮化物半导体层的上表面；
    沉积透明导电层在所述p型氮化物半导体层上，并利用黄光蚀刻制程定义凸台图案，再蚀刻所述透明导电层、p型氮化物半导体层和有源层，而暴露所述n型氮化物半导体层，再用蚀刻溶液将所述透明导电层内缩，最后去除光阻，得到凸台，且所述凸台的上表面有透明导电层；
    沉积绝缘层在所述透明导电层的上表面及所述凸台的表面上，利用黄光蚀刻制程定义要参于电流分布的图案，再蚀刻绝缘层，最后去除光阻；
    黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上；
    最后将所述圆片进行减薄、划片、裂片、测试、分选。
  2. 根据权利要求1所述的III族半导体发光器件的制作方法，其特征在于，所述黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上，进一步为，
    所述N型焊盘沉积于所述绝缘层表面上；
    所述N型线电极沉积于所述n型氮化物半导体层表面上。
  3. 根据权利要求1所述的III族半导体发光器件的制作方法，其特征在于，所述黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上，进一步为，
    所述N型焊盘沉积于所述绝缘层表面上；
    所述N型线电极沉积于所述n型氮化物半导体层及绝缘层之间。
  4. 根据权利要求2或3所述的III族半导体发光器件的制作方法，其特征在于，所述黄光剥离制程定义P型电极和N型电极图案，同时沉积所述P型电极、所述N型电极，利用剥离制程，去除光阻，制成圆片，其中，所述N型电极包括：N型线电极与N型焊盘，所述N型线电极与所述N型焊盘相连接，所述N型线电极沉积在所述凸台上，所述N型线电极下方的有源层被蚀刻掉或所述N型线电极下方的有源层被部分蚀刻掉，所述N型焊盘沉积在所述有源层的上方，所述P型电极包括：P型焊盘与P型线电极，所述P型电极沉积在所述凸台上，进一步为，
    所述N型焊盘沉积于所述绝缘层表面上；
    所述N型线电极沉积于所述绝缘层表面上。
  5. 根据权利要求4所述的III族半导体发光器件的制作方法，其特征在于，
    所述P型焊盘沉积于所述绝缘层上；
    所述P型线电极沉积于所述透明导电层上、或沉积于所述透明导电层及绝缘层之间、或部分沉积于所述绝缘层上。
  6. 根据权利要求4所述的III族半导体发光器件的制作方法，其特征在于，
    所述P型焊盘沉积于所述透明导电层表面上；
    所述P型线电极沉积于所述透明导电层表面上、或沉积于所述透明导电层及绝缘层之间、或部分沉积于所述绝缘层表面上。
  7. 根据权利要求4所述的III族半导体发光器件的制作方法，其特征在于，
    所述P型焊盘沉积于所述绝缘层及透明导电层之间；
    所述P型线电极沉积于所述透明导电层表面上、或沉积于所述透明导电层及绝缘层之间、或沉积于所述绝缘层表面上。
  8. 根据权利要求4所述的III族半导体发光器件的制作方法，其特征在于，所述P型焊盘、N型焊盘、P型线电极、N型线电极结构相同，进一步地，
    所述P型焊盘、N型焊盘、P型线电极、N型线电极为由内向外依次排列的第一Ni层、Al层、中间Cr层、第二Ni层以及Au层组成，或由内向外依次排列的第一Ni层、Al层、中间Cr层、Pt层、Au层组成，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Pt层、Au层组成，或由内向外依次排列的第一Ni层、Al层、Ti层、Pt层以及Au层组成，或由内向外依次排列的第一Ni层、Al层、Ti层、Pt层、Ti层、Pt层、Ti层、Pt层以及Au层组成，或由内向外依次排列的第一Cr层、Al层、中间Cr层、Pt层、Au层组成，或由内向外依次排列的第一Cr层、Al层、第二Ni层、Pt层、Au层组成。
  9. 根据权利要求8所述的III族半导体发光器件的制作方法，其特征在于，所述P型焊盘和N型焊盘结构，进一步的，其中所述第一Ni层的厚度为0.4～3nm，Al层的厚度为50～300nm，中间Cr层的厚度为10～300nm，第二Ni层的厚度为10～300nm，Au层的厚度为200～3000nm，Pt层的厚度为10～300nm，Ti层的厚度为10～300nm，第一Cr层的厚度为0.4～5nm。
  10. 根据权利要求1所述的III族半导体发光器件的制作方法，其特征在于，所述绝缘层，为三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二 铌、氮氧化硅或氮化硅中的一种或两种以上制成的绝缘层。
  11. 根据权利要求1所述的III族半导体发光器件的制作方法，其特征在于，所述N型焊盘与所述P型焊盘之间的高度差低于或等于300nm。
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CN104157765A (zh) * 2014-08-07 2014-11-19 湘能华磊光电股份有限公司 一种半导体发光器件及其制作方法
CN104538513A (zh) * 2015-01-20 2015-04-22 湘能华磊光电股份有限公司 一种 iii 族半导体发光器件的制作方法

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