WO2016177334A1 - Iii族半导体发光器件倒装结构的制作方法 - Google Patents

Iii族半导体发光器件倒装结构的制作方法 Download PDF

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Publication number
WO2016177334A1
WO2016177334A1 PCT/CN2016/081116 CN2016081116W WO2016177334A1 WO 2016177334 A1 WO2016177334 A1 WO 2016177334A1 CN 2016081116 W CN2016081116 W CN 2016081116W WO 2016177334 A1 WO2016177334 A1 WO 2016177334A1
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Prior art keywords
layer
type
contact metal
flip
insulating layer
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PCT/CN2016/081116
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English (en)
French (fr)
Inventor
许顺成
梁智勇
蔡炳傑
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湘能华磊光电股份有限公司
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Priority claimed from CN201510224859.5A external-priority patent/CN104952995B/zh
Priority claimed from CN201510222434.0A external-priority patent/CN104821350A/zh
Application filed by 湘能华磊光电股份有限公司 filed Critical 湘能华磊光电股份有限公司
Publication of WO2016177334A1 publication Critical patent/WO2016177334A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor

Definitions

  • the present application relates to the field of semiconductor illumination technology, and in particular to a method for fabricating a flip-chip structure of a III-group semiconductor light-emitting device.
  • the conventional light-emitting diode adopts a formal structure.
  • the transparent conductive layer adopts a material with high transmittance, such as ITO, AZO, etc.
  • the electrode generally adopts Cr/Pt/Au, etc., but in the flip-chip structure, the light excited by the active layer Directly emitted from the other side of the substrate, so the requirement for the P-type electrode becomes a highly reflective material covering the entire p-type nitride semiconductor layer as a mirror structure, the first being a p-type nitride semiconductor layer
  • a high-transparency transparent electrode is coated with a highly reflective metal such as ITO/Ag, and the other is a high-reflectivity metal directly plated on the p-type nitride semiconductor layer as an ohmic contact layer and a mirror.
  • a high-reflective metal layer 7 must be used behind the metal layer 6 to cover the highly reflective material to avoid instability.
  • the metal protective layer 7 material For example, “successively set titanium layer and tungsten layer” or “titanium tungsten alloy layer”, and then etch a plurality of vias, the structure is shown in Figure 1, the entire surface covers the first insulating layer, and the opening accesses the n-type nitrogen.
  • an object of the present invention is to provide a method for fabricating a flip-chip structure of a III-group semiconductor light-emitting device, comprising the steps of:
  • the epitaxial structure is formed by sequentially growing the substrate, the buffer layer, the n-type nitride semiconductor layer, the active layer, and the p-type nitride semiconductor layer from the bottom to the top, and the upper surface of the epitaxial structure is the upper surface of the p-type nitride semiconductor layer ;
  • the line convex mesa comprises: a first upper surface, a side surface and a second upper surface, the first upper surface and the second upper surface respectively forming an L-shaped structure with the side surface, and the first upper surface of the line convex mesa is p-type nitrogen
  • the upper surface of the semiconductor layer, the second upper surface of the line convex mesa is the n-type nitride half
  • the yellow etching process defines an isolation trench, and then etches the n-type nitride semiconductor layer and the buffer layer to expose the substrate, and finally removes the photoresist; and the isolation trench is not disposed in the flip-chip structure of the III semiconductor light emitting device. Or set the isolation trench at any step after the step;
  • first insulating layer structure is an oxide insulating layer
  • a connection pattern of the P-type contact metal and the transparent conductive layer and an N-type contact metal and the line convex mesa are defined by a yellow etching process a connection pattern of the second upper surface, etching a connection pattern of the first insulation layer structure, and finally removing the photoresist to obtain a first insulation layer structure
  • the yellow light stripping process defines a pattern of a P-type contact metal and an N-type contact metal, and simultaneously deposits a P-type contact metal and an N-type contact metal, and then uses a lift-off process to remove the photoresist to obtain a P-type contact metal and an N-type contact metal;
  • the lower end of the P-type contact metal is disposed on the surface of the transparent conductive layer and the first insulating layer structure, and the lower end of the N-type contact metal is disposed on the second upper surface of the line convex mesa and the first On the surface of the insulating layer structure;
  • the yellow light stripping process defines a pattern of flip-chip P-type electrodes and flip-chip N-type electrodes, deposits a flip-chip P-type electrode and a flip-chip N-type electrode, and then uses a stripping process to remove the photoresist to obtain a wafer;
  • the wafer is thinned, diced, split, tested, and sorted.
  • the first insulating layer structure is located on the first upper surface, the side surface, the second upper surface, the transparent conductive layer and the isolation trench.
  • the first insulating layer structure is a single-layer oxide insulating layer
  • the material of the single-layer oxide insulating layer is aluminum oxide, silicon dioxide, titanium dioxide, tantalum pentoxide, tantalum pentoxide, One of silicon oxynitride and silicon nitride.
  • the single-layer oxide insulating layer has a thickness of 30 to 200 nm.
  • the P-type contact metal is a full-surface metal, and a lower end of the P-type contact metal is disposed on the surface of the first insulating layer structure and on the transparent conductive layer;
  • the N-type contact metal is a full-surface metal, and a lower end of the N-type contact metal is disposed on the surface of the first insulating layer structure and on the second upper surface.
  • the P-type contact metal comprises: a P-type line electrode and a positive-loading P-type pad, a lower end of the pre-packed P-type pad is disposed on a surface of the first insulating layer structure, the P-type line electrode a lower end of the first insulating layer On the surface of the structure and on the transparent conductive layer;
  • the N-type contact metal includes: an N-type line electrode and a positive-mounted N-type pad, a lower end of the mounted N-type pad is disposed on a surface of the first insulating layer structure, and a lower end of the N-type line electrode is disposed On the first insulating layer structure and the second upper surface.
  • the P-type contact metal and the N-type contact metal structure are the same, and each of the first Ni layer, the Al layer, the second Ni layer, the Au layer, and the third Ni layer are sequentially arranged from the inside to the outside, or a Ti layer, an Al layer, a second Ni layer, an Au layer, and a third Ni layer arranged in series from the inside to the outside, or a Ti layer, an Al layer, and a third Ni layer sequentially arranged from the inside to the outside, or arranged in order from the inside to the outside a first Ni layer, an Al layer, a second Ni layer, a Pt layer, an Au layer, and a third Ni layer, or a Cr layer, a Pt layer, an Au layer, and a third Ni layer sequentially arranged from the inside to the outside, or
  • the first Ni layer, the Al layer, and the third Ni layer are sequentially arranged inside or outside, or are composed of a Rh layer, wherein the thickness of the Rh layer is 50-3000 nm, and the thickness of the Rh
  • the second insulating layer structure is located on an upper surface of the first insulating layer structure, an upper surface of the P-type contact metal, and an upper surface of the N-type contact metal.
  • the structure of the second insulating layer structure is a single-layer oxide insulating layer
  • the material of the single-layer oxide insulating layer is aluminum oxide, silicon dioxide, titanium dioxide, tantalum pentoxide, and pentoxide
  • the single-layer oxide insulating layer having a thickness of 30 to 200 nm.
  • a lower end of the flip-chip P-type electrode is disposed on a surface of the P-type contact metal and the second insulating layer structure;
  • the lower end of the flip-chip N-type electrode is disposed on the surface of the N-type contact metal and the second insulating layer structure.
  • the flip-chip P-type electrode has the same structure as the flip-chip N-type electrode, further consisting of a Ti layer, a second Ni layer, an Au layer arranged in sequence from the inside to the outside, or an intermediate Cr layer arranged in order from the inside to the outside.
  • the method for fabricating the flip-chip structure of the III-group semiconductor light-emitting device described in the present application has the following advantage:
  • the present invention uniformly replaces a plurality of vias techniques in the prior art by using a line-shaped mesa technology.
  • the first step of the present invention can be made by combining the transparent conductive layer with the line convex mesa pattern, which not only simplifies one process, but also solves the problem of alignment of the transparent conductive layer with the line convex mesa pattern.
  • the novel structure of the present invention is such that the first insulating layer structure 8-1 is a single-layer oxide insulating layer, and then the P-type contact metal 9, the N-type contact metal 10 is plated, and the P-type contact metal 9 and the N-type contact are used.
  • the metal 10 includes a P-type line electrode 15, an N-type line electrode 17, and a prefabricated P-type pad 16 and a positive-mounted N-type pad 18.
  • This structure 2e is a formal structure, and the photoelectric characteristics of the dressing can be measured at this step. Use this step to infer the optoelectronic characteristics of the flip-chip. If it is speculated that the optoelectronic characteristics of the flip-chip are not achieved, it can be shipped in formal form at this step.
  • the transparent conductive layer and the first insulating layer structure are sequentially disposed on the first upper surface of the linear convex mesa, that is, the present invention does not have a conductive "high reflection" above the p-type nitride semiconductor layer.
  • the metal layer 6" is in direct contact with the ITO or P-type nitride semiconductor layer, but is a non-conductive first insulating layer structure 8 (specifically an oxide insulating layer) and a transparent conductive layer over the p-type nitride semiconductor layer.
  • the direct contact makes the structure of the flip-chip LED chip provided by the present invention have another significant structural difference from the structure of the flip-chip LED chip of FIG.
  • FIG. 1 is a schematic view showing a flip-chip structure of a conventional group III nitride semiconductor light-emitting device
  • FIG. 2 is a schematic structural view corresponding to each step of the manufacturing process of the flip-chip LED chip in Embodiment 1;
  • 3a-3b are top and cross-sectional views of a plurality of vias in the prior art
  • Figure 4a - Figure 4b is a plan view and a cross-sectional view of the convex mesa
  • Figure 5 is a cross-sectional view of a P-type wire electrode
  • Figure 6 is a cross-sectional view of an N-type wire electrode
  • FIG. 7 is a schematic structural view of a flip-chip LED chip of Embodiment 5.
  • first device if a first device is coupled to a second device, the first device can be directly electrically coupled to the second device, or electrically coupled indirectly through other devices or coupling means. Connected to the second device.
  • the description of the specification is intended to be illustrative of the preferred embodiments of the invention. The scope of protection of the application is subject to the definition of the appended claims.
  • This embodiment provides a method for fabricating a flip-chip structure of a III-group semiconductor light-emitting device. See FIGS. 2a-2g for details, including the following steps:
  • First Step Structure Diagram As shown in FIG. 2a, the substrate 1, the buffer layer 2, the n-type nitride semiconductor layer 3, the active layer 4, and the p-type nitride semiconductor layer 5 are sequentially grown from bottom to top.
  • An epitaxial structure, an upper surface of the epitaxial structure is an upper surface of the p-type nitride semiconductor layer 5, and the structure is an epitaxial structure obtained by a fabrication process in the prior art, and the flip-chip is fabricated on the epitaxial structure
  • the chip method includes the following steps:
  • Second Step Structure Diagram As shown in FIG. 2b, a transparent conductive layer 14 is deposited on the upper surface of the p-type nitride semiconductor 5, and a pattern of the convex land 19 is defined by a yellow etching process, and the transparent conductive layer 14 and p-type are etched.
  • the nitride semiconductor layer 5 and the active layer 4 are exposed to expose the n-type nitride semiconductor layer 3, and then the transparent conductive layer 14 is indented by an etching solution, and finally the photoresist is removed to obtain a line convex mesa 19, and the line is convex
  • the upper surface of the shaped mesa 19 has a transparent conductive layer 14. It should be noted that this step can also separate the transparent conductive layer 14 from the convex land 19;
  • the simultaneous use of the transparent conductive layer 14 and the line-shaped mesa 19 means that the transparent conductive layer 14 is deposited on the entire surface of the p-type nitride semiconductor 5, and the transparent conductive layer 14 and the convex land 19 are in the same Obtained in the etching step.
  • the transparent conductive layer 14 is separated from the line convex mesa 19, one is to first make the transparent conductive layer 14, and then The line convex top surface 19 is formed.
  • the shape of the transparent conductive layer 14 is first defined, and the transparent conductive layer 14 is deposited on the p-type nitride semiconductor 5 by yellow etching, and the shape of the land is defined and etched to obtain a line convex surface. 19.
  • the second type is to first make the convex land 19, and then to make the transparent conductive layer 14, that is, to define the shape of the boss and etch the line convex surface 19, and then deposit the transparent conductive layer 14 on the boss by yellow etching.
  • the third step the structure diagram is as shown in FIG. 2c.
  • the method defines the isolation trench 20 pattern for the yellow etching process, and then etches the n-type nitride semiconductor layer 3 and the buffer layer 2 to expose the substrate 1, and finally removes the photoresist. Steps can be placed at any step;
  • the isolation trench 20 in the LED chip corresponds to any of the following cases:
  • the upper isolation trench contains only the second insulating layer 11-1;
  • the upper insulating layer only contains the first insulating layer 8-1 (when the package is shipped, or when the flip-chip is shipped, the isolation trench is provided before the first insulating layer 8-1 is disposed, and the second insulating layer is not disposed at the isolation trench) Layer 11-1).
  • the isolation trench 20 may or may not be included in the LED chip, and the isolation trench is generally disposed before the second insulating layer structure is disposed.
  • the isolation trench may be disposed before the first insulating layer structure 8-1 is disposed, such that the obtained isolation trench may include the first insulating layer 8-1 and the second insulating layer 11-1, or may only include the first insulating layer 8- 1; It is also possible to provide an isolation trench after any step of providing the first insulating layer structure 8-1 and before the second insulating layer 11-1 is provided, such that the resulting isolation trench contains only the second insulating layer 11-1.
  • the fourth step: the structure of the first insulating layer structure 8-1 is a single-layer oxide insulating layer, and the structure diagram is as shown in FIG. 2d.
  • the method is to deposit the structure of the first insulating layer structure 8-1 into a single-layer oxide insulating layer.
  • the connection pattern of the P-type contact metal 9 and the transparent conductive layer 14 and the N-type contact metal 10 and the second upper surface 19-3 of the line convex mesa is defined by a yellow etching process, and the first insulating layer structure 8-1 is etched again. Connection pattern, and finally remove the photoresist to obtain a first insulating layer structure 8-1;
  • the first insulating layer structure 8-1 is a single-layer oxide insulating layer or a plurality of oxide insulating layers, but is preferably a single-layer oxide insulating layer.
  • the shape of the connection pattern in the fourth step may be a dot shape, a line shape or a planar shape, which is not limited in the present invention.
  • Step 5 The structure diagram is as shown in Fig. 2e.
  • the method defines a P-type contact metal 9 and an N-type contact metal 10 pattern for the yellow light stripping process, and simultaneously deposits a P-type contact metal 9 and an N-type contact metal 10, and then uses a stripping process. And removing the photoresist to obtain a P-type contact metal 9 and an N-type contact metal 10;
  • the structure of the P-type contact metal 9 and the N-type contact metal 10 may be selected from the following three types:
  • the P-type contact metal 9 is a full-surface metal, and the lower end of the entire-surface metal is disposed on the surface of the first insulating layer structure 8-1 and on the transparent conductive layer 14, and the lower end of the entire surface metal will be The exposed transparent conductive layer 14 is completely covered;
  • the N-type contact metal 10 is a full-face metal, and the lower end of the full-surface metal is disposed on the surface of the first insulating layer structure 8-1 and the second upper surface 19-3 of the convex mesa, and the entire surface The lower end of the metal completely covers the exposed second upper surface 19-3;
  • the P-type contact metal 9 includes a P-type line electrode 15 and a front-mounted P-type pad 16, and a lower end of the mounted P-type pad 16 is disposed on a surface of the first insulating layer structure 8-1.
  • the lower end of the P-type line electrode 15 is disposed on the transparent conductive layer 6 or on the surface of the first insulating layer structure 8-1 and on the transparent conductive layer 6;
  • the N-type contact metal 10 includes an N-type line electrode 17 and a positive-load N-type pad 18, and a lower end of the mounted N-type pad 18 is disposed on a surface of the first insulating layer structure 8-1, the N-type The lower end of the wire electrode 17 is disposed on the second upper surface 19-3 of the line convex mesa or on the first insulating layer structure 8-1 and the second upper surface 19-3 of the line convex mesa;
  • the P-type contact metal 9 is a P-type line electrode 15 and a P-type connection metal, and a lower end of the P-type line electrode 15 is provided on the transparent conductive layer 6 or in the first insulating layer structure. 8-1 on the surface and on the transparent conductive layer 6, the lower end of the P-type connecting metal is disposed on the surface of the first insulating layer structure 8-1;
  • the N-type contact metal 10 is a profile electrode 17 and an N-type connection metal, and a lower end of the N-type wire electrode 17 is disposed on the second upper surface 19-3 of the line convex mesa or is disposed in the An insulating layer structure 8-1 and a second upper surface 19-3 of the line convex mesa, a lower end of the N-type connecting metal is disposed on a surface of the first insulating layer structure 8-1;
  • the contact metal may define a pattern of the P-type contact metal and the N-type contact metal by a yellow light stripping process, using electron beam evaporation simultaneously A P-type contact metal and an N-type contact metal are deposited, and then the photoresist is removed by a lift-off process to obtain a P-type contact metal and an N-type contact metal.
  • the sixth step the structure diagram is shown in FIG. 2f, the method is to deposit the second insulating layer structure 11-1, and define the opening of the P-type contact metal 9 and the N-type contact metal 10 by using a yellow etching process, and then etch the first The opening pattern of the second insulating layer structure 11-1, and finally the photoresist is removed;
  • the shape of the opening pattern accessed by the opening in this step may be a dot shape, a line shape or a surface shape, which is not limited in the present invention
  • the second insulating layer structure is a single-layer oxide insulating layer or a plurality of oxide insulating layers. It will be apparent to those skilled in the art that the P-type contact metal 9 and the N-type contact metal 10 belong to any of the above three structures, the second Each of the insulating layer structures 11-1 may be a single-layer oxide insulating layer or a plurality of oxide insulating layers.
  • Step 7 The structure diagram is as shown in Fig. 2g.
  • the method defines a flip-chip P/N type electrode 12, 13 pattern for the yellow stripping process, deposits the flip-chip P-type pad 12 and the N-type pad 13, and then uses the stripping process. And remove the photoresist;
  • Step 8 Finally, the wafer is thinned, diced, split, tested, and sorted, and the steps are obtained by the prior art manufacturing process.
  • a flip-chip structure of a III-group semiconductor light-emitting device includes: a substrate 1, a buffer layer 2, an n-type nitride semiconductor layer 3, an active layer 4, and a p-type nitride semiconductor layer 5, a first insulating layer structure 8-1, a P-type contact metal 9, an N-type contact metal 10, a second insulating layer structure 11-1, a flip-chip P-type electrode 12, a flip-chip N-type electrode 13 and a transparent conductive layer 14;
  • the substrate 1, the buffer layer 2, the n-type nitride semiconductor layer 3, the active layer 4, and the p-type nitride semiconductor layer 5 form a nitride semiconductor structure having a line convex mesas 19;
  • the line convex land 19 includes a first upper surface 19-1 of a line convex table, a side surface 19-2 of the line convex table, and a second upper surface 19-3 of the line convex table;
  • the first upper surface 19-1 of the line boss mesa is the upper surface of the p-type nitride semiconductor layer 5, which constitutes the upper plane of the line convex mesa
  • the second upper surface 19 of the line boss mesa -3 is the upper surface of the n-type nitride semiconductor layer 3, which constitutes a lower plane of the line convex mesa
  • the side surface 19-2 is connected to the first upper surface 19-1 and the second upper surface 19-3
  • the linear convex mesas 19 need to be etched away, and the etched areas are single or multiple lines, that is, the linear convex mesas 19 in the present invention are formed by etching the planar scribe lines.
  • a convex mesa it will be understood by those skilled in the art that although the etched area of the present invention necessarily contains a single or a plurality of lines, the etched portion may also include one or more punctiform etchings;
  • the line width of the line etching is not limited, and may be of a micron order or a nanometer order.
  • the material of the transparent conductive layer 14 may be a group consisting of indium tin oxide, cadmium tin oxide, zinc oxide, indium oxide, tin oxide, copper aluminum oxide, copper gallium oxide and copper beryllium oxide.
  • the first upper surface 19-1, the side surface 19-2, the second upper surface 19-3, and the upper surface of the transparent conductive layer 14 and the surface of the isolation trench 20 of the line convex mesa are provided with a first insulating layer structure 8 -1;
  • the structure of the first insulating layer structure 8-1 is a single-layer oxide insulating layer
  • the material of the single-layer oxide insulating layer is one of aluminum oxide, silicon dioxide, titanium dioxide, antimony pentoxide, antimony pentoxide, silicon oxynitride, and silicon nitride;
  • Each of the single-layer oxide insulating layers has a thickness of 30 to 2000 nm.
  • the P-type contact metal 9 and the N-type contact metal 10 have the same structure, and are composed of a first Ni layer, an Al layer, a second Ni layer, an Au layer, and a third Ni layer, which are sequentially arranged from the inside to the outside, or from the inward direction.
  • the first Ni layer, the Al layer, and the third Ni layer are sequentially arranged or composed of a Rh layer, wherein the thickness of the Rh layer is 50-3000 nm, the thickness of the first Ni layer is 0.3-300 nm, and the thickness of the Al layer It is 50-3000 nm, the thickness of the second Ni layer is 10-300 nm, the thickness of the Pt layer is 10-300 nm, the thickness of the Au layer is 10-3000 n
  • the first insulating layer structure 8-1, the P-type contact metal 9 and the upper surface of the N-type contact metal 10 are provided with a second insulating layer structure 11-1;
  • the structure of the second insulating layer structure 11-1 is a single-layer oxide insulating layer.
  • the material of the above single-layer oxide insulating layer is one of aluminum oxide, silicon dioxide, titanium oxide, antimony pentoxide, antimony pentoxide, silicon oxynitride, and silicon nitride.
  • the single-layer oxide insulating layer has a thickness of 30 to 2000 nm.
  • the lower end of the flip-chip P-type electrode 12 is disposed on the surface of the P-type contact metal 9 and the second insulating layer structure 11-1;
  • the lower end of the flip-chip N-type electrode 13 is disposed on the surface of the N-type contact metal 10 and the second insulating layer structure 11-1;
  • the structure of the flip-chip P-type electrode 12 and the flip-chip N-type electrode 13 is composed of a Ti layer, a second Ni layer, and an Au layer which are sequentially arranged from the inside to the outside, or an intermediate Cr layer, a Pt layer, and an Au which are sequentially arranged from the inside to the outside.
  • the thickness of the Al layer is 50 to 300 nm
  • the thickness of the Au layer is 20 to 3000 nm
  • the thickness of the intermediate Cr layer is 10 to 300 nm
  • the thickness of the Pt layer is 10 to 300 nm
  • the thickness of the AuSn layer is 1000 to 5000 nm.
  • the new structure of the present invention uniformly replaces a plurality of vias techniques using a line-shaped mesa 19 technique.
  • Figure 3a is a top view of a plurality of vias in the prior art
  • Figure 3b is a cross-sectional view of Figure 3a along the A-B direction.
  • FIG. 4a is a plan view of a line convex land
  • FIG. 4b is a cross-sectional view of FIG. 4a along the A-B direction.
  • the area where the line convex land 19 is etched away is a single or a plurality of lines;
  • the substrate 1, the buffer layer 2, the n-type nitride semiconductor layer 3, the active layer 4, and the p-type nitride semiconductor layer 5 form a nitride semiconductor structure having a line convex mesas 19;
  • the line convex land includes a first upper surface 19-1, a side surface 19-2, and a second upper surface 19-3, and both ends of the first upper surface are respectively provided by the side surface and the first An L-shaped surface formed by the upper surface;
  • the first upper surface 19-1 of the line convex mesa is an upper surface of the p-type nitride semiconductor layer
  • the second upper surface 19-3 of the line convex mesa is an upper surface of the n-type nitride semiconductor layer.
  • the lower end of the P-type line electrode 15 in the flip-chip structure obtained in this embodiment is disposed on the surface of the first insulating layer structure 8-1 and on the transparent conductive layer 14 (see FIG. 5). Shown).
  • the embodiment obtains a recess in which the N-type line electrode 17 fills the line convex land 19 in the flip-chip structure, and is located on the first insulating layer structure 8-1 and the line convex table. On the second upper surface 19-3 (as shown in Figure 6).
  • the first insulating layer structure 8-1 is provided as a single-layer oxide insulating layer.
  • the material of the single-layer oxide insulating layer is one of aluminum oxide, silicon dioxide, titanium dioxide, antimony pentoxide, antimony pentoxide, silicon oxynitride, and silicon nitride, wherein the single-layer oxide
  • Each layer of the insulating layer has a thickness of 30 to 2000 nm.
  • the first insulating layer structure 8-1 is a single-layer oxide insulating layer, and the method for manufacturing a single-layer oxide insulating layer by using a method such as chemical vapor deposition or optical coater deposition, and then utilizing yellow
  • the photo-etching process defines a pattern of the first insulating layer structure 8-1, and then the pattern of the first insulating layer structure 8-1 is dry-etched or wet-etched, and finally the photoresist is removed to obtain a first insulating layer structure 8-1, wherein
  • the dry etching etching gas is SF 6 /O 2 or CF 4 /CHF 3 /O 2 ;
  • the structure diagram is as shown in FIG. 2e or FIG. 7.
  • the method defines a P-type contact metal 9, a N-type contact metal 10 pattern for the yellow stripping process, and simultaneously deposits a P-type contact metal 9, N-type contact.
  • Metal 10 after using the stripping process, and then removing the photoresist, to obtain P-type contact metal 9, N-type contact metal 10;
  • the N-type contact metal 10 includes: a P-type line electrode 15, an N-type line electrode 17, a positive-loading P-type pad 16, and a positive-loading N-type pad 18, the positive-loading P-type soldering
  • the lower end of the disk 16 is disposed on the surface of the first insulating layer structure 8-1, and the lower end of the P-type line electrode 15 is disposed on the surface of the first insulating layer structure 8-1 and on the transparent conductive layer 14;
  • the N-type contact metal 10 includes an N-type line electrode 17 and a positive-load N-type pad 18, and a lower end of the mounted N-type pad 18 is disposed on a surface of the first insulating layer structure 8-1, the N-type line
  • the lower end of the electrode 17 is disposed on the first insulating layer structure 8-1 and the second upper surface 19-3 of the line convex mesa;
  • FIG. 7 is a view showing that the P-type contact metal 9 and the N-type contact metal 10 are a full-surface metal, and the lower end of the entire surface metal of the P-type contact metal 9 is disposed on the surface of the first insulating layer structure 8-1 and is transparent. a conductive metal layer 14; the entire lower metal end of the N-type contact metal 10 is disposed on the surface of the first insulating layer structure 8-1 and the second upper surface 19-3 of the convex mesa;
  • a group III nitride semiconductor flip-chip device is fabricated, and the specification is 760 um x 250 um, and the group III nitride
  • the semiconductor flip chip device manufacturing method comprises the following steps:
  • the structure diagram is as shown in FIG. 2a, in which the substrate 1, the buffer layer 2, the n-type nitride semiconductor layer 3, the active layer 4, and the p-type nitride semiconductor layer 5 are sequentially arranged from bottom to top.
  • the upper surface of the epitaxial structure is an upper surface of the p-type nitride semiconductor layer 5
  • the structure is an epitaxial structure obtained by a fabrication process in the prior art, and is fabricated on the epitaxial structure
  • the chip method includes the following steps:
  • the second step structure diagram shown in Figure 2b, using electron beam evaporation, or sputtering, or reactive plasma deposition (RPD) deposition of ITO (indium tin oxide) when the transparent conductive layer 14 is in the p-type
  • the upper surface of the nitride semiconductor 5 has an ITO thickness of 10 to 400 nm, and a pattern of the convex land 19 is defined by a yellow etching process, and the transparent conductive layer 14, the p-type nitride semiconductor layer 5, and the active layer 4 are etched by ICP, The n-type nitride semiconductor layer 3 is exposed, the transparent conductive layer 14 is further recessed by an etching solution, and finally the photoresist is removed to obtain a line convex mesa 19, and the upper surface of the line convex mesa 19 has a transparent conductive layer 14 (This step can also separate the transparent conductive layer 14 from the convex land 19;) Wafer is then annealed at a high temperature to
  • the third step the structure diagram is as shown in FIG. 2c.
  • the method defines the isolation trench 20 pattern for the yellow etching process, and then etches the n-type nitride semiconductor layer 3 and the buffer layer 2 to expose the substrate 1, and finally removes the photoresist. Steps can be placed at any step;
  • the fourth step a first insulating layer of a single-layer structure 8-1 structure of the oxide insulating layer, the structure shown in Figure 2d, when the first insulating layer 2 SiO structure using PECVD (Plasma Enhanced Chemical Vapor Deposition) deposition 8-1, SiO 2 has a thickness of 30-2000 nm, wherein the power is 50 W, the pressure is 850 mTorr, the temperature is 200-400 ° C, the N 2 O is 1000 sccm, the N 2 is 400 sccm, and the 5% SiH 4 /N 2 is 400 sccm;
  • the yellow etching process defines a connection pattern of the P-type contact metal 9 and the transparent conductive layer 14 and the N-type contact metal 10 and the second upper surface 19-3 of the line convex mesa, and then the first insulating layer is etched by dry or wet etching.
  • the connection pattern of the structure 8-1, and finally the photoresist is removed to obtain the first
  • Step 5 The structure diagram is as shown in Fig. 2e.
  • the method defines a P-type contact metal 9 and an N-type contact metal 10 pattern for the yellow light stripping process (including a P-type line electrode 15, an N-type line electrode 17 and a positive-loading P-type pad). 16.
  • the N-type pad 18) is mounted, and the P-type contact metal 9 and the N-type contact metal 10 are simultaneously deposited by electron beam evaporation, and then the stripping process is performed, and the photoresist is removed to obtain a P-type contact metal 9, N-type contact.
  • Metal 10
  • the P-type contact metal 9 and the N-type contact metal 10 have the same structure, and the first Ni layer, the Al layer, the second Ni layer, the Au layer, and the third Ni layer are sequentially arranged from the inside to the outside, wherein the first The thickness of the Ni layer is 0.4 to 3 nm, the thickness of the Al layer is 50 to 300 nm, the thickness of the second Ni layer is 10 to 300 nm, the thickness of the Au layer is 10 to 3000 nm, and the thickness of the third Ni layer is 0.4 to 3 nm.
  • Figure 2e is a formal structure.
  • the photoelectric characteristics of the final assembly can be measured.
  • This step can be used to estimate the photoelectric characteristics of the flip-chip. If it is speculated that the photoelectric characteristics of the flip-chip are not reached, it can be shipped in this step. .
  • the sixth step the structure of the second insulating layer structure 11-1 is a single-layer oxide insulating layer, and the structure diagram is as shown in FIG. 2f, and SiO 2 is deposited by PECVD (plasma enhanced chemical vapor deposition) as the second insulating layer structure.
  • PECVD plasma enhanced chemical vapor deposition
  • SiO 2 thickness is 30-2000 nm, wherein the power is 50 W, the pressure is 850 mTorr, the temperature is 200-400 ° C, the N 2 O is 1000 sccm, the N 2 is 400 sccm, and the 5% SiH 4 /N 2 is 400 sccm;
  • the yellow etching process defines an opening access pattern of the P-type contact metal 9, the N-type contact metal 10, and then dry- or wet-etches the opening pattern of the second insulating layer structure 11-1, and finally removes the photoresist;
  • Step 7 The structure diagram is as shown in Fig. 2g.
  • the method defines a flip-chip P-type electrode 12 and a flip-chip N-type electrode 13 pattern for the yellow light stripping process, and simultaneously deposits the flip-chip P-type electrode 12 by electron beam evaporation. After the N-type electrode 13 is mounted, the stripping process is used, and then the photoresist is removed;
  • the flip-chip P-type electrode 12 and the flip-chip N-type electrode 13 have the same structure, and all of the Ti layer, the second Ni layer, and the Au layer are sequentially arranged from the inside to the outside, or the first Ni is sequentially arranged from the inside to the outside.
  • a layer, an Al layer, a second Ni layer, and an Au layer wherein the thickness of the Ti layer is 10-300 nm, the thickness of the first Ni layer is 0.4-3 nm, the thickness of the second Ni layer is 10-300 nm, and the thickness of the Al layer
  • the thickness of the Au layer is from 50 to 300 nm, and is from 20 to 3000 nm.
  • Step 8 Finally, the wafer is thinned, diced, split, tested, and sorted, and the steps are obtained by the prior art manufacturing process.
  • Step 9 Package the flip chip and measure the photoelectric characteristics.
  • the photoelectric characteristics of the product can be seen from Fig. 8 and Fig. 9.
  • the product voltage is 2.82V
  • the product brightness is 23.4lm (color temperature 6807K)
  • the peak wavelength is 449.5nm
  • the product The voltage is 3.02V
  • the product brightness is 50.3lm (color temperature 7095K)
  • the peak wavelength is 447.3nm
  • the product voltage is 3.56V
  • the product brightness is 116.3lm (color temperature 7832K)
  • the peak wavelength is 447.3nm
  • the product can have a higher operating current and a lower voltage, a higher brightness, and a smaller wavelength shift than the main assembly.
  • the manufacturing method of the embodiment is the same as that of the seventh embodiment.
  • the difference is that in the fifth step, the P-type contact metal 9 and the N-type contact metal 10 in the embodiment are full-surface metals, and the other steps are the same.
  • the assembly structure is shown in Figure 7.
  • the test conditions are the same as in the case of the seventh embodiment.
  • the technical product of the seventh embodiment is designated as S1, and the product number S2 produced according to the method provided in the embodiment 7 is tested under the same conditions.
  • the test results are as shown in Table 1: The photoelectric characteristics of S1 and S2 are similar.
  • the method for fabricating the flip-chip structure of the III-group semiconductor light-emitting device described in the present application has the following advantages:
  • the new structure of the present invention uniformly replaces a plurality of vias techniques in the prior art by a line convex mesa technique.
  • the first step of the present invention can be made by combining the transparent conductive layer with the line convex mesa pattern, which not only simplifies one process, but also solves the problem of alignment of the transparent conductive layer with the line convex mesa pattern.
  • the novel structure of the present invention is such that the first insulating layer structure 8-1 is a single-layer oxide insulating layer, and then the P-type contact metal 9, the N-type contact metal 10 is plated, and the P-type contact metal 9 and the N-type contact are used.
  • the metal 10 includes a P-type line electrode 15, an N-type line electrode 17, and a prefabricated P-type pad 16 and a positive-mounted N-type pad 18.
  • This structure 2e is a formal structure, and the photoelectric characteristics of the dressing can be measured at this step. Use this step to infer the optoelectronic characteristics of the flip chip, if it is speculated that the optoelectronic characteristics of the flip chip are not achieved, You can ship in formal order at this step.

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Abstract

一种III族半导体发光器件倒装结构的制作方法，包括步骤：自下而上依次生长衬底（1）、缓冲层（2）、n型氮化物半导体层（3）、有源层（4）和p型氮化物半导体层（5）形成外延结构，所述外延结构的上表面为p型氮化物半导体层（5）的上表面；沉积透明导电层（14）；黄光蚀刻制程定义隔离槽；沉积第一绝缘层结构（8-1）；沉积P型接触金属（9）与N型接触金属（10）；沉积第二绝缘层结构（11-1）；沉积倒装P型电极（12）与倒装N型电极（13），得到圆片；将圆片进行减薄、划片、裂片、测试、分选。一律采用线凸形台面技术取代现有技术中的多个孔洞vias技术。第一步骤可将透明导电层（14）与线凸形台面（19）图案一起制作，不但简化了一道制程，也解决了透明导电层（14）与线凸形台面（19）图案对准的问题。

Description

III族半导体发光器件倒装结构的制作方法 技术领域
本申请涉及半导体照明技术领域，具体地说，是涉及一种III族半导体发光器件倒装结构的制作方法。
背景技术
传统发光二极管采用正装结构，一般透明导电层采用高穿透率的材料，如ITO、AZO…等，而电极一般采用Cr/Pt/Au等，然而在倒装结构中，有源层激发的光直接从电极的另一面衬底发出，所以对P型电极的要求变成覆盖在整面p型氮化物半导体层的高反射材料来当反射镜结构，第一种是在p型氮化物半导体层上镀高穿透率的透明电极再加上高反射金属，例如ITO/Ag等，另一种是在p型氮化物半导体层上直接镀上高反射率的金属同时作为欧姆接触层和反射镜，例如Ag、Al等，不管选用哪一种方法，在高反射率的金属层6后面必须使用金属保护层7(guard metal)覆盖高反射材料，以避免不稳定，所述金属保护层7材料例如为“先后设置的钛层和钨层”或“钛钨合金层”，再蚀刻多个孔洞(vias)，结构示意图如图1，整面覆盖第一绝缘层，开孔存取n型氮化物半导体层及金属保护层，再镀P型接触金属与N型接触金属，整面再覆盖第二绝缘层，开孔存取P型接触金属与N型接触金属，最后镀倒装P型电极和N型电极，由于蚀刻孔洞的精度要求比较高，所以工艺复杂，生产成本也较高。
发明内容
为了解决在上述现有技术中出现的问题，本发明的目的是提供一种III族半导体发光器件倒装结构的制作方法，包括步骤：
自下而上依次生长衬底、缓冲层、n型氮化物半导体层、有源层和p型氮化物半导体层形成外延结构，所述外延结构的上表面为p型氮化物半导体层的上表面；
沉积透明导电层在所述p型氮化物半导体上表面，并利用黄光蚀刻制程定义线凸形台面图案，再蚀刻透明导电层、p型氮化物半导体层和有源层，暴露n型氮化物半导体层，再用蚀刻溶液将透明导电层内缩，最后去除光阻，得到线凸形台面，且所述线凸形台面的上表面有透明导电层，其中，所述线凸形台面包括：第一上表面、侧表面和第二上表面，所述第一上表面和第二上表面分别与所述侧表面形成L形结构，所述线凸形台面的第一上表面为p型氮化物半导体层的上表面，所述线凸形台面的第二上表面为所述n型氮化物半 导体层的上表面；此步骤中也可以将透明导电层与线凸形台面分开做，即不在同一个蚀刻步骤中同时得到透明导电层与线凸形台面，而是先形成透明导电层和后形成所述线凸形台面，或先形成所述线凸形台面和后形成透明导电层；
黄光蚀刻制程定义隔离槽，再蚀刻n型氮化物半导体层和缓冲层、而暴露衬底，最后去除光阻；也可以在所述III族半导体发光器件倒装结构中并不设置隔离槽，或者在该步骤之后的任意步骤设置隔离槽；
沉积第一绝缘层结构，所述第一绝缘层结构为氧化物绝缘层，利用黄光蚀刻制程定义P型接触金属与透明导电层的连接图案及N型接触金属与所述线凸形台面的第二上表面的连接图案，再蚀刻第一绝缘层结构的连接图案，最后去除光阻，得到第一绝缘层结构；
黄光剥离制程定义P型接触金属与N型接触金属的图案，同时沉积P型接触金属与N型接触金属，然后利用剥离制程，再去除光阻，得到P型接触金属与N型接触金属；其中，所述P型接触金属的下端设置在所述透明导电层及第一绝缘层结构表面上，所述N型接触金属的下端设置在所述线凸形台面的第二上表面及第一绝缘层结构表面上；
沉积第二绝缘层结构，利用黄光蚀刻制程定义开孔存取P型接触金属与N型接触金属的图案，再蚀刻第二绝缘层结构的开孔图案，最后去除光阻；
黄光剥离制程定义倒装P型电极与倒装N型电极的图案，沉积倒装P型电极与倒装N型电极，后利用剥离制程，再去除光阻，得到圆片；
将圆片进行减薄、划片、裂片、测试、分选。
优选地，所述第一绝缘层结构，位于所述第一上表面、侧表面、第二上表面、透明导电层以及隔离槽上。
优选地，所述第一绝缘层结构为单层氧化物绝缘层，所述单层氧化物绝缘层的材料为三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅以及氮化硅中的一种。
优选地，所述单层氧化物绝缘层的厚度为30-200nm。
优选地，所述P型接触金属为整面金属，该P型接触金属的下端设置在所述第一绝缘层结构表面上及透明导电层上；
所述N型接触金属为整面金属，该N型接触金属的下端设置在所述第一绝缘层结构表面上及所述第二上表面上。
优选地，所述P型接触金属，包括：P型线电极和正装P型焊盘，所述正装P型焊盘的下端设置在所述第一绝缘层结构表面上，所述P型线电极的下端设置在所述第一绝缘层 结构表面及透明导电层上；
所述N型接触金属，包括：N型线电极和正装N型焊盘，所述正装N型焊盘的下端设置在所述第一绝缘层结构表面上，所述N型线电极的下端设置在所述第一绝缘层结构以及第二上表面上。
优选地，所述P型接触金属和N型接触金属结构相同，且均为由内向外依次排列的第一Ni层、Al层、第二Ni层、Au层以及第三Ni层组成，或由内向外依次排列的Ti层、Al层、第二Ni层、Au层以及第三Ni层组成，或由内向外依次排列的Ti层、Al层以及第三Ni层组成，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Pt层、Au层以及第三Ni层组成，或由内向外依次排列的Cr层、Pt层、Au层以及第三Ni层组成，或由内向外依次排列的第一Ni层、Al层、以及第三Ni层组成，或由Rh层组成，其中，Rh层的厚度为50-3000nm，第一Ni层的厚度为0.3-300nm，Al层的厚度为50-3000nm，第二Ni层的厚度为10-300nm，Pt层的厚度为10-300nm，Au层的厚度为10-3000nm，第三Ni层的厚度为0.3-300nm。
优选地，所述第二绝缘层结构位于所述第一绝缘层结构的上表面、P型接触金属的上表面以及N型接触金属的上表面。
优选地，所述第二绝缘层结构的结构为单层氧化物绝缘层，所述单层氧化物绝缘层的材料为三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅以及氮化硅中的一种，所述单层氧化物绝缘层的厚度为30-200nm。
优选地，所述倒装P型电极的下端设置在所述P型接触金属以及第二绝缘层结构的表面上；
所述倒装N型电极的下端设置在所述N型接触金属以及第二绝缘层结构表面上。
优选地，所述倒装P型电极与倒装N型电极结构相同，进一步为，由内向外依次排列的Ti层、第二Ni层、Au层组成，或由内向外依次排列的中间Cr层、Pt层、Au层、第二Ni层、Pt层、第二Ni层、AuSn层组成，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Au层组成，或由内向外依次排列的中间Cr层、Pt层、Au层组成，或由内向外依次排列的第一Ni层、Al层、中间Cr层、第二Ni层以及Au层组成，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Pt层、Au层组成，其中，所述第一Ni层的厚度为0.4-3nm，第二Ni层的厚度为10-300nm，Ti层的厚度为10-300nm，Al层的厚度为50-300nm，Au层的厚度为20-3000nm，中间Cr层的厚度为10-300nm，Pt层的厚度为10-300nm，AuSn层的厚度为1000-5000nm。
与现有技术相比，本申请所述的III族半导体发光器件倒装结构的制作方法，具有以下 优点：
(1)本发明一律采用线凸形台面技术取代现有技术中的多个孔洞(vias)技术。
(2)本发明的第一步骤可将透明导电层与线凸形台面图案一起制作，不但简化了一道制程，也解决了透明导电层与线凸形台面图案对准的问题。
(3)本发明新结构假如使用第一绝缘层结构8-1为单层氧化物绝缘层，然后镀P型接触金属9、N型接触金属10，所述P型接触金属9、N型接触金属10包括P型线电极15、N型线电极17以及正装P型焊盘16与正装N型焊盘18，此结构图2e就是正装结构，可在此步骤可测出正装的光电特性，可利用此步骤推测倒装的光电特性，假如推测没有达到倒装的光电特性，可以在此步骤可以以正装出货。
(4)本发明新结构中透明导电层和第一绝缘层结构依次设置在线凸形台面的第一上表面上，也即本发明在p型氮化物半导体层上方并未设置导电的“高反射率的金属层6”与ITO或P型氮化物半导体层直接接触，而是不导电的第一绝缘层结构8(具体是氧化物绝缘层)与位于p型氮化物半导体层上方的透明导电层直接接触，使得本发明提供的倒装LED芯片的结构与图1中倒装LED芯片的结构存在又一个显著的结构区别。
当然，实施本申请的任一产品必不一定需要同时达到以上所述的所有技术效果。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1是现有的Ⅲ族氮化物半导体发光器件的倒装结构示意图；
图2a-图2g实施例1中倒装LED芯片的制作流程各步骤对应的结构示意图；
图3a-图3b现有技术中多个孔洞(vias)的俯视图以及剖面图；
图4a-图4b线凸形台面的俯视图以及剖面图；
图5为P型线电极的剖面图；
图6为N型线电极的剖面图；
图7为实施例5的倒装LED芯片的结构示意图；
图8为实施例7的倒装LED芯片的亮度-电流-电压特性；
图9为实施例7的倒装LED芯片的峰值波长-电流特性图；
图中：1、衬底，2、缓冲层，3、n型氮化物半导体层，4、有源层，5、p型氮化物半导体层，6、高反射率的金属层，7、金属保护层，8-1、第一绝缘层，9、P型接触金属，10、N型接触金属，11-1、第二绝缘层结构，12、倒装P型电极，13、倒装N型电极，14、 透明导电层，15、P型线电极，16、正装P型焊盘，17、N型线电极，18、正装N型焊盘，19、线凸形台面，19-1、第一上表面，19-2、侧表面，19-3、第二上表面，20、隔离槽。
具体实施方式
如在说明书及权利要求当中使用了某些词汇来指称特定组件。本领域技术人员应可理解，硬件制造商可能会用不同名词来称呼同一个组件。本说明书及权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。如在通篇说明书及权利要求当中所提及的“包含”为一开放式用语，故应解释成“包含但不限定于”。“大致”是指在可接收的误差范围内，本领域技术人员能够在一定误差范围内解决所述技术问题，基本达到所述技术效果。此外，“耦接”一词在此包含任何直接及间接的电性耦接手段。因此，若文中描述一第一装置耦接于一第二装置，则代表所述第一装置可直接电性耦接于所述第二装置，或通过其他装置或耦接手段间接地电性耦接至所述第二装置。说明书后续描述为实施本申请的较佳实施方式，然所述描述乃以说明本申请的一般原则为目的，并非用以限定本申请的范围。本申请的保护范围当视所附权利要求所界定者为准。
以下结合附图对本申请作进一步详细说明，但不作为对本申请的限定。
实施例1：
本实施例提供一种III族半导体发光器件倒装结构的制作方法，详见图2a-图2g，包括以下步骤：
第一步：结构图如图2a所示，在衬底1、缓冲层2、n型氮化物半导体层3、有源层4和所述p型氮化物半导体层5自下而上依次生长形成外延结构，所述外延结构的上表面为p型氮化物半导体层5的上表面，此结构为外延结构，其为通过现有技术中的制作工艺得到的，在所述外延结构上制作倒装芯片的方法包括以下步骤：
第二步：结构图如图2b所示，沉积透明导电层14在p型氮化物半导体5上表面，并利用黄光蚀刻制程定义线凸形台面19图案，再蚀刻透明导电层14、p型氮化物半导体层5和有源层4，而暴露n型氮化物半导体层3，再用蚀刻溶液将透明导电层14内缩，最后去除光阻，得到线凸形台面19，且所述线凸形台面19的上表面有透明导电层14，需要说明的是此步骤也可以将透明导电层14与线凸形台面19分开做；
在本发明中，透明导电层14与线凸形台面19同时做是指先在p型氮化物半导体5上整面沉积透明导电层14，再使透明导电层14和线凸形台面19在同一个蚀刻步骤中得到。而将透明导电层14与线凸形台面19分开做则有两种情况，一种是先做透明导电层14，后 做线凸形台面19，具体是先定义透明导电层14的形状，并利用黄光蚀刻把透明导电层14沉积在p型氮化物半导体5上，再定义凸台形状并蚀刻得到线凸形台面19。第二种是先做线凸形台面19，后做透明导电层14，即先定义凸台形状并蚀刻得到线凸形台面19，再用黄光蚀刻把透明导电层14沉积在凸台的第一上表面19-1上；
第三步：结构图如图2c所示，方法为黄光蚀刻制程定义隔离槽20图案，再蚀刻n型氮化物半导体层3和缓冲层2、而暴露衬底1，最后去除光阻，此步骤可以放在任何步骤；
本发明中，LED芯片中所述隔离槽20相应为如下几种情况中的任意一种：
1)不设置隔离槽(如共晶焊的情况)；
2)隔离槽上方只含有第二绝缘层11-1；
3)隔离槽上方含有第一绝缘层8-1和第二绝缘层11-1；
4)隔离槽上方只含有第一绝缘层8-1(正装出货时，或倒装出货时在设置第一绝缘层8-1之前设置隔离槽、且在隔离槽处不设置第二绝缘层11-1)。
如上所述，在LED芯片中可以有隔离槽20，也可以不含有隔离槽，且隔离槽一般在设置第二绝缘层结构之前设置。具体可以在设置第一绝缘层结构8-1之前设置隔离槽，这样所得隔离槽上方可含有第一绝缘层8-1和第二绝缘层11-1，也可以仅含有第一绝缘层8-1；也可以在设置第一绝缘层结构8-1之后和设置第二绝缘层11-1之前的任何步骤设置隔离槽，这样所得隔离槽上方只含有第二绝缘层11-1。
第四步：第一绝缘层结构8-1的结构为单层氧化物绝缘层，结构图如图2d所示，方法为沉积第一绝缘层结构8-1的结构为单层氧化物绝缘层，利用黄光蚀刻制程定义P型接触金属9与透明导电层14及N型接触金属10与线凸形台面的第二上表面19-3的连接图案，再蚀刻第一绝缘层结构8-1的连接图案，最后去除光阻，得到第一绝缘层结构8-1；
本发明中，所述第一绝缘层结构8-1为单层氧化物绝缘层或多层氧化物绝缘层，但优选为单层氧化物绝缘层。第四步中所述连接图案的形状可以是点状、线状或面状，这在本发明中不受限制。
第五步：结构图如图2e所示，方法为黄光剥离制程定义P型接触金属9与N型接触金属10图案，同时沉积P型接触金属9与N型接触金属10，后利用剥离制程，再去除光阻，得到P型接触金属9与N型接触金属10；
事实上，所述P型接触金属9与N型接触金属10的结构可从下列三种中任选一种：
(1)所述P型接触金属9为整面金属，所述整面金属的下端设置在所述第一绝缘层结构8-1表面上及透明导电层14上，且整面金属的下端将露出的透明导电层14完全覆盖；
所述N型接触金属10为整面金属，所述整面金属的下端设置在所述第一绝缘层结构8-1表面上以及凸形台面的第二上表面19-3上，且整面金属的下端将露出的第二上表面19-3完全覆盖；
(2)所述P型接触金属9包括P型线电极15以及正装P型焊盘16，所述正装P型焊盘16的下端设置在所述第一绝缘层结构8-1表面上，所述P型线电极15的下端设置在所述透明导电层6上或者设置在所述第一绝缘层结构8-1表面上及透明导电层6上；
所述N型接触金属10包括N型线电极17以及正装N型焊盘18，所述正装N型焊盘18的下端设置在所述第一绝缘层结构8-1表面上，所述N型线电极17的下端设置在所述线凸形台面的第二上表面19-3上或者设置在所述第一绝缘层结构8-1以及线凸形台面的第二上表面19-3上；
(3)所述P型接触金属9为P型线电极15以及P型连接金属，所述P型线电极15的下端设置在所述透明导电层6上或者设置在所述第一绝缘层结构8-1表面上及透明导电层6上，所述P型连接金属的下端设置在所述第一绝缘层结构8-1表面上；
所述N型接触金属10为型线电极17以及N型连接金属，所述N型线电极17的下端设置在所述线凸形台面的第二上表面19-3上或者设置在所述第一绝缘层结构8-1以及线凸形台面的第二上表面19-3上，所述N型连接金属的下端设置在所述第一绝缘层结构8-1表面上；
本领域技术人员可知的，上述第(2)种方案中的焊盘和第(3)种方案中的连接金属的主要区别在于，焊盘的形状和尺寸均固定，而连接金属的形状和尺寸均不受限制。
另外，不论上述(1)至(3)中哪种情况的接触金属，所述接触金属都可以通过黄光剥离制程定义P型接触金属与N型接触金属的图案，使用电子束蒸镀法同时沉积P型接触金属与N型接触金属，然后利用剥离制程，再去除光阻，得到P型接触金属与N型接触金属。
第六步：结构图如图2f所示，方法为沉积第二绝缘层结构11-1，利用黄光蚀刻制程定义开孔存取P型接触金属9与N型接触金属10图案，再蚀刻第二绝缘层结构11-1的开孔图案，最后去除光阻；
同样的，该步骤中开孔存取的开孔图案的形状可以是点状、线状或面状，这在本发明中不受限制；
所述第二绝缘层结构为单层氧化物绝缘层或多层氧化物绝缘层。本领域技术人员可知的，无论P型接触金属9与N型接触金属10属于上述三种结构中的任意一种，所述第二 绝缘层结构11-1都可以是单层氧化物绝缘层或多层氧化物绝缘层。
第七步：结构图如图2g所示，方法为黄光剥离制程定义倒装P/N型电极12、13图案，沉积倒装P型焊盘12与N型焊盘13，后利用剥离制程，再去除光阻；
第八步：最后将圆片进行减薄、划片、裂片、测试、分选，其步骤为通过现有技术中的制作工艺得到的。
通过上述方法，得到了一种III族半导体发光器件的倒装结构，结构包括：衬底1、缓冲层2、n型氮化物半导体层3、有源层4、p型氮化物半导体层5、第一绝缘层结构8-1、P型接触金属9、N型接触金属10、第二绝缘层结构11-1、倒装P型电极12、倒装N型电极13以及透明导电层14；
所述衬底1、缓冲层2、n型氮化物半导体层3、有源层4以及p型氮化物半导体层5形成具有线凸形台面19的氮化物半导体结构；
所述线凸形台面19包括线凸形台面的第一上表面19-1、线凸形台面的侧表面19-2以及线凸形台面的第二上表面19-3；
所述线凸台台面的第一上表面19-1为p型氮化物半导体层5的上表面，它构成线凸形台面的在上的平面，所述线凸台台面的第二上表面19-3为n型氮化物半导体层3的上表面，它构成线凸形台面的在下的平面，所述侧表面19-2连接在第一上表面19-1和第二上表面19-3之间，三者共同形成线凸台台面；
本发明中需要将所述线凸形台面19蚀刻掉，被蚀刻掉的区域为单一或多个线条，也就是说本发明中所述线凸形台面19是指对平面划线蚀刻后形成的凸形台面；本领域技术人员能理解的，虽然本发明中被蚀刻掉的区域必然包含单一或多个线条，但被蚀刻掉的部分也还可以包含一个或多个点状蚀刻；本发明中，线蚀刻的线宽不限，为微米级或纳米级皆可。
所述透明导电层14的材料可为氧化铟锡、氧化镉锡、氧化锌、氧化铟、氧化锡、氧化铜铝、氧化铜镓以及氧化锶铜所组成之一族群。
所述线凸形台面的第一上表面19-1、侧表面19-2、第二上表面19-3以及透明导电层14的上表面以及隔离槽20表面均设有第一绝缘层结构8-1；
所述第一绝缘层结构8-1的结构为单层氧化物绝缘层；
所述单层氧化物绝缘层的材料为三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅以及氮化硅中的一种；
所述单层氧化物绝缘层的每层厚度为30-2000nm。
所述P型接触金属9和N型接触金属10结构相同，且均为由内向外依次排列的第一Ni层、Al层、第二Ni层、Au层以及第三Ni层组成，或由内向外依次排列的Ti层、Al层、第二Ni层、Au层以及第三Ni层组成，或由内向外依次排列的Ti层、Al层以及第三Ni层组成，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Pt层、Au层以及第三Ni层组成，或由内向外依次排列的Cr层、Pt层、Au层以及第三Ni层组成，或由内向外依次排列的第一Ni层、Al层、以及第三Ni层组成，或由Rh层组成，其中Rh层的厚度为50-3000nm，第一Ni层的厚度为0.3-300nm，Al层的厚度为50-3000nm，第二Ni层的厚度为10-300nm，Pt层的厚度为10-300nm，Au层的厚度为10-3000nm，第三Ni层的厚度为0.3-300nm。
所述第一绝缘层结构8-1、P型接触金属9以及N型接触金属10的上表面设有第二绝缘层结构11-1；
所述第二绝缘层结构11-1的结构为单层氧化物绝缘层。
上述单层氧化物绝缘层的材料为三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅以及氮化硅中的一种。
所述单层氧化物绝缘层的厚度为30-2000nm。
所述倒装P型电极12的下端设置在所述P型接触金属9以及第二绝缘层结构11-1表面上；
所述倒装N型电极13的下端设置在所述N型接触金属10以及第二绝缘层结构11-1表面上；
上述倒装P型电极12、倒装N型电极13的结构为由内向外依次排列的Ti层、第二Ni层、Au层组成，或由内向外依次排列的中间Cr层、Pt层、Au层、第二Ni层、Pt层、第二Ni层、AuSn层组成，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Au层组成，或由内向外依次排列的中间Cr层、Pt层、Au层组成，或由内向外依次排列的第一Ni层、Al层、中间Cr层、第二Ni层以及Au层组成，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Pt层、Au层组成，其中所述第一Ni层的厚度为0.4～3nm，第二Ni层的厚度为10～300nm，Ti层的厚度为10～300nm，Al层的厚度为50～300nm，Au层的厚度为20～3000nm，中间Cr层的厚度为10～300nm，Pt层的厚度为10～300nm，AuSn层的厚度为1000～5000nm。
实施例2：
本发明新结构一律采用线凸形台面19技术取代多个孔洞(vias)技术。
如图3a所示为现有技术中多个孔洞(vias)的俯视图，图3b为图3a沿A-B方向的剖面图。
如图4a所示为线凸形台面的俯视图，图4b为图4a沿A-B方向的剖面图。
所述线凸形台面19被蚀刻掉的区域为单一或多个线条；
所述衬底1、缓冲层2、n型氮化物半导体层3、有源层4以及p型氮化物半导体层5形成具有线凸形台面19的氮化物半导体结构；
所述线凸形台面包括第一上表面19-1、侧表面19-2以及第二上表面19-3，所述第一上表面的两端分别设有由所述侧表面以及所述第二上表面形成的L形表面；
所述线凸形台面的第一上表面19-1为p型氮化物半导体层的上表面，所述线凸形台面的第二上表面19-3为n型氮化物半导体层的上表面。
实施例3：
在实施例1的基础上，本实施例得到的倒装结构中所述P型线电极15的下端设置在所述第一绝缘层结构8-1表面上及透明导电层14上(如图5所示)。
实施例4：
在实施例1的基础上，本实施例得到倒装结构中所述N型线电极17填满线凸形台面19的凹槽，位于所述第一绝缘层结构8-1以及线凸形台面的第二上表面19-3上(如图6所示)。
实施例5：
在制作芯片的第四步，如图2d所示，本实施例提供第一绝缘层结构8-1为单层氧化物绝缘层。
上述单层氧化物绝缘层的材料为三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅以及氮化硅中的一种，其中所述单层氧化物绝缘层的每层厚度为30-2000nm。
以上技术方案中，所述第一绝缘层结构8-1为单层氧化物绝缘层的制作方法如下，使用化学气相沉积或光学镀膜机沉积等方法来制造单层氧化物绝缘层，再利用黄光蚀刻制程定义第一绝缘层结构8-1的图案，再用干法或湿法蚀刻第一绝缘层结构8-1的图案，最后去除光阻，得到第一绝缘层结构8-1，其中干法蚀刻的刻蚀气体为SF6/O2或CF4/CHF3/O2；
实施例6：
在制作芯片的第五步骤，结构图如图2e或图7所示，方法为黄光剥离制程定义P型接触金属9、N型接触金属10图案，同时沉积P型接触金属9、N型接触金属10，后利用剥离制程，再去除光阻，得到P型接触金属9、N型接触金属10；
图2e为所述P型接触金属9、N型接触金属10包括：P型线电极15、N型线电极17以及正装P型焊盘16、正装N型焊盘18，所述正装P型焊盘16的下端设置在所述第一绝缘层结构8-1表面上，所述P型线电极15的下端设置在所述第一绝缘层结构8-1表面上及透明导电层14上；所述N型接触金属10包括N型线电极17以及正装N型焊盘18，所述正装N型焊盘18的下端设置在所述第一绝缘层结构8-1表面上，所述N型线电极17的下端设置在所述第一绝缘层结构8-1以及线凸形台面的第二上表面19-3上；
图7为所述P型接触金属9、N型接触金属10为整面金属，所述P型接触金属9的整面金属的下端设置在所述第一绝缘层结构8-1表面上及透明导电层14上；所述N型接触金属10的整面金属下端设置在所述第一绝缘层结构8-1表面上以及凸形台面的第二上表面19-3上；
实施例7：
在实施例1、实施例2、实施例3、实施例4、实施例5和实施例6的基础上，制作Ⅲ族氮化物半导体倒装发光器件，规格为760um×250um，该Ⅲ族氮化物半导体倒装器件其制作方法包括以下步骤：
第一步：结构图如图2a所示，方法为在衬底1、缓冲层2、n型氮化物半导体层3、有源层4和所述p型氮化物半导体层5自下而上依次生长形成外延结构，所述外延结构的上表面为p型氮化物半导体层5的上表面，此结构为外延结构，其为通过现有技术中的制作工艺得到的，在所述外延结构上制作芯片的方法包括以下步骤：
第二步：结构图如图2b所示，使用电子束蒸镀法、或溅镀法、或反应等离子体(reactive plasma deposition，RPD)沉积ITO(氧化铟锡)当透明导电层14在p型氮化物半导体5上表面，ITO厚度为10-400nm，并利用黄光蚀刻制程定义线凸形台面19图案，再利用ICP蚀刻透明导电层14、p型氮化物半导体层5和有源层4，而暴露n型氮化物半导体层3，再用蚀刻溶液将透明导电层14内缩，最后去除光阻，得到线凸形台面19，且所述线凸形台面19的上表面有透明导电层14(此步骤也可以将透明导电层14与线凸形台面19分开做)；再将Wafer进行高温退火，使透明导电层14与p型氮化物半导体层5之间形成良好的欧姆接触和穿透率。退火方式用快速退火炉(RTA)快速退火，温度为560℃，时间为3分钟。
第三步：结构图如图2c所示，方法为黄光蚀刻制程定义隔离槽20图案，再蚀刻n型氮化物半导体层3和缓冲层2、而暴露衬底1，最后去除光阻，此步骤可以放在任何步骤；
第四步：第一绝缘层结构8-1的结构为单层氧化物绝缘层，结构图如图2d所示，使用PECVD(等离子体增强化学气相沉积法)沉积SiO2当第一绝缘层结构8-1，SiO2厚度为 30-2000nm，其中功率为50W，压力为850mTorr，温度为200～400℃，N2O为1000sccm，N2为400sccm，5％SiH4/N2为400sccm；利用黄光蚀刻制程定义P型接触金属9与透明导电层14及N型接触金属10与线凸形台面的第二上表面19-3的连接图案，再利用干法或湿法蚀刻第一绝缘层结构8-1的连接图案，最后去除光阻，得到第一绝缘层结构8-1；
第五步：结构图如图2e所示，方法为黄光剥离制程定义P型接触金属9、N型接触金属10图案(包括P型线电极15、N型线电极17以及正装P型焊盘16、正装N型焊盘18)，使用电子束蒸镀法同时沉积P型接触金属9、N型接触金属10，后利用剥离制程，再去除光阻，得到P型接触金属9、N型接触金属10；
本实施例中P型接触金属9和N型接触金属10结构相同，且均为由内向外依次排列第一Ni层、Al层、第二Ni层、Au层以及第三Ni层，其中第一Ni层的厚度为0.4-3nm，Al层的厚度为50-300nm，第二Ni层的厚度为10-300nm，Au层的厚度为10-3000nm，第三Ni层的厚度为0.4-3nm。
此结构图2e就是正装结构，可在此步骤可测出正装的光电特性，可利用此步骤推测倒装的光电特性，假如推测没有达到倒装的光电特性，可以在此步骤可以以正装出货。
第六步：第二绝缘层结构11-1的结构为单层氧化物绝缘层，结构图如图2f所示，使用PECVD(等离子体增强化学气相沉积法)沉积SiO2当第二绝缘层结构11-1，SiO2厚度为30-2000nm，其中功率为50W，压力为850mTorr，温度为200～400℃，N2O为1000sccm，N2为400sccm，5％SiH4/N2为400sccm；利用黄光蚀刻制程定义开孔存取P型接触金属9、N型接触金属10图案，再利用干法或湿法蚀刻第二绝缘层结构11-1的开孔图案，最后去除光阻；
第七步：结构图如图2g所示，方法为黄光剥离制程定义倒装P型电极12、倒装N型电极13图案，使用电子束蒸镀法同时沉积倒装P型电极12、倒装N型电极13，后利用剥离制程，再去除光阻；
本实施例中倒装P型电极12和倒装N型电极13结构相同，且均为由内向外依次排列Ti层、第二Ni层、以及Au层，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Au层组成，其中Ti层的厚度为10-300nm，第一Ni层的厚度为0.4～3nm，第二Ni层的厚度为10-300nm，Al层的厚度为50～300nm，Au层的厚度为20-3000nm。
第八步：最后将圆片进行减薄、划片、裂片、测试、分选，其步骤为通过现有技术中的制作工艺得到的。
第九步：将倒装芯片封装，测量光电特性。
按照实施例7提供的方法制作的产品，特性测试结果如图8和图9所示：
从图8和图9中可知产品的光电特性，在输入电流为60mA时，产品电压为2.82V，产品亮度为23.4lm(色温6807K)，峰值波长为449.5nm；在输入电流为150mA时，产品电压为3.02V，产品亮度为50.3lm(色温7095K)，峰值波长为447.3nm；在输入电流为620mA时，产品电压为3.56V，产品亮度为116.3lm(色温7832K)，峰值波长为447.3nm；由图8和图9可知此产品可以比正装的操作电流更高且电压更低，亮度更高，波长位移更少。
实施例8：
本实施例和实施例7的制作方法是一样的，区别在于第五步，本实施例中的P型接触金属9、N型接触金属10为整面金属，其他步骤一样，实施例7的倒装结构图如图7所示。
试验条件与实施例7相同，将实施例7的技术产品标号为S1，按照实施例7提供的方法制作的产品标号S2，在同一条件下进行检测，测试结果如表1：从表1中可知，S1与S2的光电特性差不多。
表1产品检测结果比对
Figure PCTCN2016081116-appb-000001
与现有技术相比，本申请所述的III族半导体发光器件倒装结构的制作方法，具有以下优点：
(1)本发明的新结构一律采用线凸形台面技术取代现有技术中的多个孔洞(vias)技术。
(2)本发明的第一步骤可将透明导电层与线凸形台面图案一起制作，不但简化了一道制程，也解决了透明导电层与线凸形台面图案对准的问题。
(3)本发明新结构假如使用第一绝缘层结构8-1为单层氧化物绝缘层，然后镀P型接触金属9、N型接触金属10，所述P型接触金属9、N型接触金属10包括P型线电极15、N型线电极17以及正装P型焊盘16与正装N型焊盘18，此结构图2e就是正装结构，可在此步骤可测出正装的光电特性，可利用此步骤推测倒装的光电特性，假如推测没有达到倒装的光电特性， 可以在此步骤可以以正装出货。
上述说明示出并描述了本申请的若干优选实施例，但如前所述，应当理解本申请并非局限于本文所披露的形式，不应看作是对其他实施例的排除，而可用于各种其他组合、修改和环境，并能够在本文所述申请构想范围内，通过上述教导或相关领域的技术或知识进行改动。而本领域人员所进行的改动和变化不脱离本申请的精神和范围，则都应在本申请所附权利要求的保护范围内。

Claims (11)

  1. 一种III族半导体发光器件倒装结构的制作方法，其特征在于，包括步骤：
    自下而上依次生长衬底、缓冲层、n型氮化物半导体层、有源层和p型氮化物半导体层形成外延结构，所述外延结构的上表面为p型氮化物半导体层的上表面；
    沉积透明导电层在所述p型氮化物半导体上表面，并利用黄光蚀刻制程定义线凸形台面图案，再蚀刻透明导电层、p型氮化物半导体层和有源层，暴露n型氮化物半导体层，再用蚀刻溶液将透明导电层内缩，最后去除光阻，得到线凸形台面，且所述线凸形台面的上表面有透明导电层，其中，所述线凸形台面包括：第一上表面、侧表面和第二上表面，所述第一上表面和第二上表面分别与所述侧表面形成L形结构，所述线凸形台面的第一上表面为p型氮化物半导体层的上表面，所述线凸形台面的第二上表面为所述n型氮化物半导体层的上表面；此步骤中也可以将透明导电层与线凸形台面分开做，即不在同一个蚀刻步骤中同时得到透明导电层与线凸形台面，而是先形成透明导电层和后形成所述线凸形台面，或先形成所述线凸形台面和后形成透明导电层；
    黄光蚀刻制程定义隔离槽，再蚀刻n型氮化物半导体层和缓冲层、而暴露衬底，最后去除光阻；也可以在所述III族半导体发光器件倒装结构中并不设置隔离槽，或者在该步骤之后的任意步骤设置隔离槽；
    沉积第一绝缘层结构，所述第一绝缘层结构为氧化物绝缘层，利用黄光蚀刻制程定义P型接触金属与透明导电层的连接图案及N型接触金属与所述线凸形台面的第二上表面的连接图案，再蚀刻第一绝缘层结构的连接图案，最后去除光阻，得到第一绝缘层结构；
    黄光剥离制程定义P型接触金属与N型接触金属的图案，同时沉积P型接触金属与N型接触金属，然后利用剥离制程，再去除光阻，得到P型接触金属与N型接触金属；其中，所述P型接触金属的下端设置在所述透明导电层及第一绝缘层结构表面上，所述N型接触金属的下端设置在所述线凸形台面的第二上表面及第一绝缘层结构表面上；
    沉积第二绝缘层结构，利用黄光蚀刻制程定义开孔存取P型接触金属与N型接触金属的图案，再蚀刻第二绝缘层结构的开孔图案，最后去除光阻；
    黄光剥离制程定义倒装P型电极与倒装N型电极的图案，沉积倒装P型电极与倒装N型电极，后利用剥离制程，再去除光阻，得到圆片；
    将圆片进行减薄、划片、裂片、测试、分选。
  2. 根据权利要求1所述的III族半导体发光器件倒装结构的制作方法，其特征在于，所述第一绝缘层结构，位于所述第一上表面、侧表面、第二上表面、透明导电层以及可选的隔离槽上。
  3. 根据权利要求2所述的III族半导体发光器件倒装结构的制作方法，其特征在于，所述第一绝缘层结构为单层氧化物绝缘层，所述单层氧化物绝缘层的材料为三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅以及氮化硅中的一种。
  4. 根据权利要求3所述的III族半导体发光器件倒装结构的制作方法，其特征在于，所述单层氧化物绝缘层的厚度为30-200nm。
  5. 根据权利要求1所述的III族半导体发光器件倒装结构的制作方法，其特征在于，所述P型接触金属为整面金属，该P型接触金属的下端设置在所述第一绝缘层结构表面上及透明导电层上；
    所述N型接触金属为整面金属，该N型接触金属的下端设置在所述第一绝缘层结构表面上及所述第二上表面上。
  6. 根据权利要求1所述的III族半导体发光器件倒装结构的制作方法，其特征在于，所述P型接触金属包括P型线电极和正装P型焊盘，所述正装P型焊盘的下端设置在所述第一绝缘层结构表面上，所述P型线电极的下端设置在所述第一绝缘层结构表面及透明导电层上；所述N型接触金属包括N型线电极和正装N型焊盘，所述正装N型焊盘的下端设置在所述第一绝缘层结构表面上，所述N型线电极的下端设置在所述第一绝缘层结构以及第二上表面上。
  7. 根据权利要求5或6所述的III族半导体发光器件倒装结构的制作方法，其特征在于，所述P型接触金属和N型接触金属结构相同，且均为由内向外依次排列的第一Ni层、Al层、第二Ni层、Au层以及第三Ni层组成，或由内向外依次排列的Ti层、Al层、第二Ni层、Au层以及第三Ni层组成，或由内向外依次排列的Ti层、Al层以及第三Ni层组成，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Pt层、Au层以及第三Ni层组成，或由内向外依次排列的Cr层、Pt层、Au层以及第三Ni层组成，或由内向外依次排列的 第一Ni层、Al层、以及第三Ni层组成，或由Rh层组成，其中，Rh层的厚度为50-3000nm，第一Ni层的厚度为0.3-300nm，Al层的厚度为50-3000nm，第二Ni层的厚度为10-300nm，Pt层的厚度为10-300nm，Au层的厚度为10-3000nm，第三Ni层的厚度为0.3-300nm。
  8. 根据权利要求1所述的III族半导体发光器件倒装结构的制作方法，其特征在于，所述第二绝缘层结构位于所述第一绝缘层结构的上表面、P型接触金属的上表面以及N型接触金属的上表面。
  9. 根据权利要求8所述的III族半导体发光器件倒装结构的制作方法，其特征在于，所述第二绝缘层结构的结构为单层氧化物绝缘层，所述单层氧化物绝缘层的材料为三氧化二铝、二氧化硅、二氧化钛、五氧化二钽、五氧化二铌、氮氧化硅以及氮化硅中的一种，所述单层氧化物绝缘层的厚度为30-200nm。
  10. 根据权利要求1所述的III族半导体发光器件倒装结构的制作方法，其特征在于，所述倒装P型电极的下端设置在所述P型接触金属以及第二绝缘层结构的表面上；
    所述倒装N型电极的下端设置在所述N型接触金属以及第二绝缘层结构表面上。
  11. 根据权利要求10所述的III族半导体发光器件倒装结构的制作方法，其特征在于，所述倒装P型电极与倒装N型电极结构相同，进一步为，由内向外依次排列的Ti层、第二Ni层、Au层组成，或由内向外依次排列的中间Cr层、Pt层、Au层、第二Ni层、Pt层、第二Ni层、AuSn层组成，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Au层组成，或由内向外依次排列的中间Cr层、Pt层、Au层组成，或由内向外依次排列的第一Ni层、Al层、中间Cr层、第二Ni层以及Au层组成，或由内向外依次排列的第一Ni层、Al层、第二Ni层、Pt层、Au层组成，其中，所述第一Ni层的厚度为0.4-3nm，第二Ni层的厚度为10-300nm，Ti层的厚度为10-300nm，Al层的厚度为50-300nm，Au层的厚度为20-3000nm，中间Cr层的厚度为10-300nm，Pt层的厚度为10-300nm，AuSn层的厚度为1000-5000nm。
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