WO2019054943A1

WO2019054943A1 - Light-emitting device and method of forming the same

Info

Publication number: WO2019054943A1
Application number: PCT/SG2018/050464
Authority: WO
Inventors: Xueliang ZHANG; Swee Tiam TAN; Hilmi Volkan Demir
Original assignee: Nanyang Technological University
Priority date: 2017-09-15
Filing date: 2018-09-11
Publication date: 2019-03-21

Abstract

Various embodiments may provide a light-emitting device. The light-emitting device may include an epitaxial stack arrangement. The epitaxial stack arrangement may also include a first semiconductor layer of a first conductivity type. The epitaxial stack arrangement may further include a second semiconductor layer of a second conductivity type different from the first conductivity type. The epitaxial stack arrangement may additionally include an active layer between the first semiconductor layer and the second semiconductor layer. The light-emitting device may also include a reflector stack arrangement over the epitaxial stack arrangement. The reflector stack arrangement may include a first dielectric structure. The reflector stack arrangement may also include a second dielectric structure on the first dielectric structure. The reflector stack arrangement may further include a reflector structure on the second dielectric structure. The reflector stack arrangement may additionally include a third dielectric structure on the reflector layer.

Description

LIGHT-EMITTING DEVICE AND METHOD OF FORMING THE SAME

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of Singapore application No. 10201707588V filed on September 15, 2017, the contents of it being hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

[0002] Various aspects of this disclosure may relate to a light-emitting device. Various aspects of this disclosure may relate to a method of forming a light-emitting device.

BACKGROUND

[0003] Light-emitting diodes are important solid state devices that convert electrical power to light output. For example, in diodes based on gallium nitride (GaN), the light is generated from an active region which is "sandwiched" between a p-type semiconductor layer and an n-type semiconductor layer. The device architecture of diodes may be classified into conventional horizontal structured diodes, flip chip structured diodes, and vertical structured diodes. In the conventional horizontal structured diodes, part of the area in the device would be covered by both the p-electrode and the n-electrode, which reduce the lighting emitting area and light extraction efficiency, and may also lead to current crowding problems, especially at a high operating current regime.

[0004] The vertical structured diode has several advantages in comparison with horizontal structured diode. However, the mass production of vertical structured diodes is limited because of low yield of complex processes, which include carrier transfer. The flip chip structured device may combine the advantages of the above two structures, i.e. having high process yield and an electrode structure design that may solve the problem of current crowding. Typically, for the flip chip structured diode, the p-electrode and the n-electrode are fabricated at the bottom of the device. Such an electrode arrangement increases the light-emitting area and also reduces the current crowding effect. Moreover, the flip chip structured diode could be mounted or attached to pre-set electrodes on a carrier, which is beneficial to thermal management and current spreading issues.

[0005] FIG. 1 shows a schematic of a flip-chip structured light-emitting diode. The diode may include an epitaxial layer stack 10 including a p-doped gallium nitride (GaN) layer 10c, and a n- doped gallium nitride (GaN) layer 10a separated by the multiple-quantum well (MQW) layer 10b. The device may typically be grown on a selected carrier (not shown in FIG. 1) such as sapphire (AI2O3), silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).

[0006] A reflective layer 20 is deposited to be in contact with the surface of the p-type semiconductor layer 10c. The reflective layer 20 serves as both the ohmic contact layer and the light reflection layer. Generally, the reflector 20 is formed by a high reflectivity metal layer, as aluminium (Al), silver (Ag) or combination thereof. A conductive layer 21, including P-type barrier layer 21a and N-type electrode layer 21b, is also formed as part of the device. The P-type barrier layer 21a is formed in contact with the reflector 20 to reduce or prevent metal diffusion and may be beneficial for current spreading. The N-type electrode layer 21b is formed in the mesa region of the epitaxial layer stack 10. The N-type electrode layer 21b contacts the n-doped GaN layer 10a for current spreading. A passivation layer 31 with good transmittance property, such as silicon oxide, is formed to provide an insulation between the P-type barrier layer 21a and the N- type electrode layer 21b.

[0007] The blind region is generated in the intermediate region 31a (circled by dashed line) between P-type barrier layer 21a and N-type electrode layer 21b. Light may not be reflected well and light extraction may be reduced in the blind region. Cracks may easily be formed during the forming process of passivation layer 31 and during the bonding process between device and carrier, leading to current leakage issues. An N-type pad 41 is connected to N-type electrode layer 21b for bonding with carrier. Flip-chip structured GaN-based light-emitting diodes typically suffer from device performance and may be restricted by material reflectivity of the reflector 20, thus fettering light extraction efficiency improvements.

SUMMARY

[0008] Various embodiments may provide a light-emitting device. The light-emitting device may include an epitaxial stack arrangement. The epitaxial stack arrangement may include a first semiconductor layer of a first conductivity type. The epitaxial stack arrangement may further include a second semiconductor layer of a second conductivity type different from the first conductivity type. The epitaxial stack arrangement may additionally include an active layer between the first semiconductor layer and the second semiconductor layer. The light-emitting device may also include a reflector stack arrangement over the epitaxial stack arrangement. The reflector stack arrangement may include a first dielectric structure. The reflector stack arrangement may also include a second dielectric structure on the first dielectric structure. The reflector stack arrangement may further include a reflector structure on the second dielectric structure. The reflector stack arrangement may additionally include a third dielectric structure on the reflector layer.

[0009] Various embodiments may provide a method of forming a light-emitting device. The method may include forming an epitaxial stack arrangement. The epitaxial stack arrangement may include a first semiconductor layer of a first conductivity type. The epitaxial stack arrangement may also include a second semiconductor layer of a second conductivity type different from the first conductivity type. The epitaxial stack arrangement may additionally include an active layer between the first semiconductor layer and the second semiconductor layer. The method may further include forming a reflector stack arrangement over the epitaxial stack arrangement. The reflector stack arrangement may include a first dielectric structure. The reflector stack arrangement may also include a second dielectric structure on the first dielectric structure. The reflector stack arrangement may further include a reflector structure on the second dielectric structure. The reflector stack arrangement may also include a third dielectric structure on the reflector structure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The invention will be better understood with reference to the detailed description when considered in conjunction with the non-limiting examples and the accompanying drawings, in which:

FIG. 1 shows a schematic of a flip-chip structured light-emitting diode.

FIG. 2 is a general illustration of a light-emitting device according to various embodiments.

FIG. 3 is a general illustration of a method of forming a light-emitting device according to various embodiments. FIG. 4A shows a top view of a light-emitting diode according to various embodiments. The diode may have a flip chip structure and may demonstrate high reflectivity.

FIG. 4B shows a cross-sectional side view of the light-emitting diode shown in FIG. 4A along the line A-A' according to various embodiments.

FIG. 4C shows an enlarged view of the broken-line frame of FIG. 4B.

FIG. 4D shows a schematic of the reflecting layer stack structure according to various embodiments.

FIG. 4E shows a schematic of the reflecting layer stack structure according to various other embodiments.

FIG. 4F shows a schematic of the reflecting layer stack structure according to yet various other embodiments.

FIG. 5 A is a plot of reflectance (in percent or %) as a function of wavelength (in nanometer or nm) comparing the reflectivity of the reflecting layer stack structure shown in FIG. 4D according to various embodiments and the reflectivity of a silver (Ag) - based mirror.

FIG. 5B is a plot of reflectance (in percent or %) as a function of wavelength (in nanometer or nm) comparing the reflectivity of the reflecting layer stack structure shown in FIG. 4E according to various embodiments and the reflectivity of a silver (Ag) - based mirror.

FIG. 5C is a plot of reflectance (in percent or %) as a function of wavelength (in nanometer or nm) comparing the reflectivity of the reflecting layer stack structure shown in FIG. 4F according to various embodiments and the reflectivity of a silver (Ag) - based mirror.

FIG. 5D shows a plot of power Po (in milli Watts or mW) / voltage Vf (in volts or V) as a function of current I (in milli Amperes or mA) comparing the reflectivity performance of different embodiments.

FIG. 6 shows a top view of a light-emitting diode according to various other embodiments.

DETAILED DESCRIPTION

[0011] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, and logical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[0012] Embodiments described in the context of one of the methods or devices are analogously valid for the other methods or devices. Similarly, embodiments described in the context of a method are analogously valid for a device, and vice versa.

[0013] Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

[0014] The word "over" used with regards to a deposited material formed "over" a side or surface, may be used herein to mean that the deposited material may be formed "directly on", e.g. in direct contact with, the implied side or surface. The word "over" used with regards to a deposited material formed "over" a side or surface, may also be used herein to mean that the deposited material may be formed "indirectly on" the implied side or surface with one or more additional layers being arranged between the implied side or surface and the deposited material. In other words, a first layer "over" a second layer may refer to the first layer directly on the second layer, or that the first layer and the second layer are separated by one or more intervening layers.

[0015] The device as described herein may be operable in various orientations, and thus it should be understood that the terms "top", "topmost", "bottom", "bottommost" etc., when used in the following description are used for convenience and to aid understanding of relative positions or directions, and not intended to limit the orientation of the device.

[0016] In the context of various embodiments, the articles "a", "an" and "the" as used with regard to a feature or element include a reference to one or more of the features or elements.

[0017] In the context of various embodiments, the term "about" or "approximately" as applied to a numeric value encompasses the exact value and a reasonable variance.

[0018] As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0019] Various embodiments may provide a light-emitting device. The light-emitting device may be a light-emitting diode. FIG. 2 is a general illustration of a light-emitting device according to various embodiments. The light-emitting device may include an epitaxial stack arrangement 200a. The epitaxial stack arrangement 200a may include a first semiconductor layer 202 of a first conductivity type. The epitaxial stack arrangement 200a may further include a second semiconductor layer 204 of a second conductivity type different from the first conductivity type. The epitaxial stack arrangement 200a may additionally include an active layer 206 between the first semiconductor layer 202 and the second semiconductor layer 204. The light-emitting device may also include a reflector stack arrangement 200b over the epitaxial stack arrangement 200a. The reflector stack arrangement 200b may include a first dielectric structure 208. The reflector stack arrangement 200b may also include a second dielectric structure 210 on or in contact with the first dielectric structure 208. The reflector stack arrangement 200b may further include a reflector structure 212 on or in contact with the second dielectric structure 210. The reflector stack arrangement 200b may additionally include a third dielectric structure 214 on or in contact with the reflector layer 212.

[0020] In other words, the light-emitting device may include an epitaxial stack arrangement 200a and a reflector stack arrangement 200b. The epitaxial stack arrangement 200a may include an active layer 206 between two doped semiconductor layers 202, 204 of opposite charge polarity. The reflector stack arrangement 200b may include dielectric structures 208, 210, 214 and a reflector structure 212.

[0021] Various embodiments may seek to address or mitigate the issues facing conventional devices. Various embodiments may seek to improve light extraction. In various embodiments, reflectivity may be improved. The reflector stack arrangement 200b may provide better reflectivity. Various embodiments may improve uniformity of current spreading.

[0022] The reflector stack arrangement 200b may also be referred to as a reflecting layer stack structure or a reflecting layer stack. The epitaxial stack arrangement 200a may also be referred to as an epitaxial layer stack.

[0023] In various embodiments, the first dielectric structure 208 may be a layer. The second dielectric structure 210 may be another layer. The first dielectric structure 208 and the second dielectric structure 210 may be single layers. The first dielectric structure 208 may include a first dielectric material, and the second dielectric structure 210 may include a second dielectric material different from the first dielectric material. The first dielectric structure 208 may include a dielectric material selected from a group consisting of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride. In various embodiments, the second dielectric structure 210 may another dielectric material selected from a group consisting of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride. The single layer films may not reflect light, but may allow light to pass through, thus improving light extraction efficiency.

[0024] In various other embodiments, the first dielectric structure 208 may be a layer. The second dielectric structure 210 may include or consist of a plurality of layers. The second dielectric structure 210 may be a dielectric stack (or multilayer film) including or consisting of alternating layers of different dielectric materials. A first layer of the plurality of layers may include a first dielectric material, while a second layer of the plurality of layers adjoining or in contact with the first layer may include a second dielectric material different from the first dielectric material. A refractive index of the first dielectric material and a refractive index of the second dielectric material may be different. A first layer of the plurality of layers may include a first dielectric material selected from a group consisting of silicon oxide, titanium oxide, tantalum oxide, niobium oxide, and aluminum oxide, and a second layer of the plurality of layers may include a second dielectric material selected from a group consisting of silicon oxide, titanium oxide, tantalum oxide, niobium oxide, and aluminum oxide.

[0025] In various embodiments, the reflector structure 212 may be a metal reflector layer. The metal reflector layer may include, but may not be limited to, a suitable metal such as silver (Ag), aluminum (Al), rhodium (Rh), or any combination thereof.

[0026] In various other embodiments, the reflector structure 212 may include or consist of a plurality of dielectric layers. The plurality of dielectric layers may form a distributed Bragg reflector (DBR) or an omni-directional reflector (ODR). Each of the plurality of dielectric layers may include an insulative inorganic material. Each of the plurality of dielectric layers may include any one material selected from a group consisting of silicon oxide (SiOx), silicon nitride (SiNx), titanium oxide (TiO_x), tantalum oxide (TaO_x), niobium oxide (NbO_x), aluminium oxide (AI2O3), magnesium fluoride (MgF₂), and zirconium oxide (Zr0₂). The plurality of dielectric layers may form a multilayer film structure. [0027] The dielectric stack (or multilayer film) may be configured to reflect at least a portion of light incident on the dielectric stack (or multilayer film). The dielectric stack (or multilayer film) may also be configured to provide electrical isolation.

[0028] In various embodiments, the reflector structure 212 may include or consist of a metal reflector layer, and a barrier layer in contact with the metal reflector layer. The barrier layer may be on or in contact with the metal reflector layer. The metal reflector layer may include, but may not be limited to, a suitable metal such as silver (Ag), aluminum (Al), rhodium (Rh), or any combination thereof. The barrier layer may include, but may not be limited to, a metal such as nickel (Ni), tungsten (W), chromium (Cr), copper (Cu), or the like. The reflector structure may also be referred to as a reflecting structure. Similarly, a reflector layer may also be referred to as a reflecting layer. The reflector structure or the reflector layer may also be referred to as a reflector.

[0029] In yet various other embodiments, the first dielectric structure 208 may include or consist of a plurality of layers. The second dielectric structure 210 may be a layer. The first dielectric structure 208 may be a dielectric stack (or multilayer film) including or consisting of alternating layers of different dielectric materials. A first layer of the plurality of layers may include a first dielectric material, while a second layer of the plurality of layers adjoining the first layer may include a second dielectric material different from the first dielectric material. A refractive index of the first dielectric material and a refractive index of the second dielectric material may be different. A first layer of the plurality of layers may include a first dielectric material selected from a group consisting of silicon oxide, titanium oxide, tantalum oxide, niobium oxide, and aluminum oxide, and a second layer of the plurality of layers may include a second dielectric material selected from a group consisting of silicon oxide, titanium oxide, tantalum oxide, niobium oxide, and aluminum oxide

[0030] In various other embodiments, the first dielectric structure 208 may include or consist of a first plurality of layers. The second dielectric structure 210 may include or consist of a second plurality of layers. The first dielectric structure 208 may be a dielectric stack (or multilayer film) including or consisting of alternating layers of different dielectric materials. The second dielectric structure 210 may also be a dielectric stack (or multilayer film) including or consisting of alternating layers of different dielectric materials. [0031] In the current context, a "dielectric structure" may refer to a single dielectric layer, or a multilayer stack including or consisting of a plurality of dielectric layers. A "reflector structure" or a "reflector" may refer to a single reflector layer, or a multilayer stack including a plurality of layers.

[0032] The active layer 206 may include a multi-quantum well. In various embodiments, a bandgap of the first semiconductor layer 202 and/or a bandgap of the second semiconductor layer 204 may be greater than a bandgap of the active layer 206.

[0033] The light-emitting device may also include a first electrode in electrical connection with the second semiconductor layer 204. The first electrode may be of the second conductivity type. The light-emitting device may further include a second electrode in electrical connection with the first semiconductor layer 202. The second electrode may be of the first conductivity type.

[0034] In the current context, "conductivity type" of a layer or structure refers to electrical or charge conductivity, i.e. the charge polarity of the layer or structure. The doping of the first semiconductor layer, and the doping of the second electrode in electrical connection with the first semiconductor layer 202 may be of the same polarity. The doping of the second semiconductor layer, and the doping of the first electrode in electrical connection with the second semiconductor layer may be of the same polarity. The first electrode may be of the second conductivity type, while the second electrode may be of the first conductivity type.

[0035] In various embodiments, the first semiconductor layer 202 may be doped with a n-type dopant, i.e. the first conductivity type may be n-type. The second electrode may also be doped with a n-type dopant. Conversely, the second semiconductor layer 204 may be doped with a p-type dopant, i.e. the second conductivity type may be p-type. The first electrode may also be doped with a p-type dopant.

[0036] In various other embodiments, the first semiconductor layer 202 may be doped with a p-type dopant, i.e. the first conductivity type may be p-type. The second electrode may also be doped with a p-type dopant. Conversely, the second semiconductor layer 204 may be doped with a n-type dopant, i.e. the second conductivity type may be n-type. The first electrode may also be doped with a n-type dopant. [0037] The first electrode may be on a bottom of a well or hole. The second electrode may be on a bottom of another well or hole. In various embodiments, the device may include a plurality of first electrodes, and/or a plurality of second electrodes.

[0038] The light-emitting device may also include an electrical conductor layer in contact with the second semiconductor layer 204. The first electrode is in contact with the electrical conductor layer. The second semiconductor layer 204 and the first electrode may be in contact with opposing surfaces of the electrical conductor layer. The second semiconductor layer 204 may be in contact with a first surface of the electrical conductor layer, while the first electrode may be in contact with a second surface of the electrical conductor layer opposite the first surface.

[0039] In various embodiments, the light-emitting device may also include a first current spreader layer in electrical connection with the first electrode. The light-emitting device may also include a second current spreader layer in electrical connection with the second electrode.

[0040] The first current spreader may be of the second conductivity type. The second current spreader may be of the first conductivity type. The first current spreader or the second current spreader may include a metal or an alloy such as rhodium (Rh), titanium (Ti), nickel (Ni), platinum (Pt), aluminum (Al), gold (Au), chromium (Cr), tungsten (W), palladium (Pd), titanium nitride (TiN), or any combination thereof. The first current spreader or the second current spreader may have a thickness of any value from about 0.01 μπι to about 2 μπι, preferably from about 0.1 μπι to about 1 μπι.

[0041] The light-emitting device may also include a first electrode pad in electrical connection with the first current spreader. The light-emitting device may further include a second electrode pad in electrical connection with the second current spreader. The first electrode pad or the second electrode pad may include a metal or an alloy such as titanium, nickel, platinum, aluminum, gold, chromium, tungsten, copper, tin, titanium nitride, or any combination thereof.

[0042] The light-emitting device may further include a fourth dielectric structure configured to electrically insulate the first electrode pad from the second current spreader and configured to electrically insulate the second electrode pad from the first current spreader.

[0043] The fourth dielectric structure may include an inorganic material or an organic material.

The organic material may be silicon oxide, silicon oxynitride (or silicon nitride oxide), silicon nitride, titanium oxide, aluminum oxide, magnesium oxide, hafnium oxide, or tantalum oxide. Organic material may be a polymer, a resist such as NR-7 or SU-8, or the like.

[0044] FIG. 3 is a general illustration of a method of forming a light-emitting device according to various embodiments. The method may include, in 302, forming an epitaxial stack arrangement. The epitaxial stack arrangement may include a first semiconductor layer of a first conductivity type. The epitaxial stack arrangement may also include a second semiconductor layer of a second conductivity type different from the first conductivity type. The epitaxial stack arrangement may additionally include an active layer between the first semiconductor layer and the second semiconductor layer. The method may further include, in 304, forming a reflector stack arrangement over the epitaxial stack arrangement. The reflector stack arrangement may include a first dielectric structure. The reflector stack arrangement may also include a second dielectric structure on or in contact with the first dielectric structure. The reflector stack arrangement may further include a reflector structure on or in contact with the second dielectric structure. The reflector stack arrangement may also include a third dielectric structure on or in contact with the reflector structure

[0045] In other words, the method may relate to forming a light-emitting device, such as a light- emitting diode, including an epitaxial stack arrangement and a reflector arrangement.

[0046] For avoidance of doubt, the steps shown in FIG. 3 is not intended to be in sequence. In various embodiments, step 302 may be before step 304. In various other embodiments, step 302 may be concurrent or after step 304.

[0047] In various embodiments, the first dielectric structure may be a layer. The second dielectric structure may be another layer.

[0048] In various other embodiments, the first dielectric structure may be a layer. The second dielectric structure may include or consist of a plurality of layers.

[0049] In yet various other embodiments, the first dielectric structure may include or consist of a plurality of layers. The second dielectric structure may be a layer.

[0050] In various other embodiments, the first dielectric structure may include or consist of a first plurality of layers. The second dielectric structure may include or consist of a second plurality of layers. [0051] In various embodiments, the method may further include forming a first electrode in electrical connection with the second semiconductor layer. The method may also include forming a second electrode in electrical connection with the first semiconductor layer.

[0052] In various embodiments, the method may also include forming an electrical conductor layer in contact with the second semiconductor layer. The first electrode may be in contact with the electrical conductor layer.

[0053] In various embodiments, the method may further include forming a first current spreader layer in electrical connection with the first electrode. The method may also include forming a second current spreader layer in electrical connection with the second electrode.

[0054] In various embodiments, the method may also include forming a first electrode pad in electrical connection with the first current spreader. The method may further include forming a second electrode pad in electrical connection with the second current spreader.

[0055] In various embodiments, the method may also include forming a fourth dielectric structure configured to electrically insulate the first electrode pad from the second current spreader and configured to electrically insulate the second electrode pad from the first current spreader.

[0056] Various embodiments may relate to a structure with reflecting layer stack for flip chip structured light emitting diodes which may improve the light reflectivity and uniformity of current spreading, and thus contribute to the light efficiency improvement and reduction of the forward voltage in the devices. Various embodiments may relate to a flip chip with the reflecting layer stack structure, the reflecting layer stack structure including a first dielectric layer, a second dielectric layer, a reflecting layer, and a third dielectric layer.

[0057] Each of the first dielectric structure or layer and the second dielectric structure or layer may be a single layer film, or a multilayer film structure with different dielectric layers. The reflecting structure or layer may be a multilayer film structure with different dielectric layers, or a metal reflecting layer.

[0058] A third dielectric structure or layer may be formed as a passivation layer for the reflecting layer stack.

[0059] In a first embodiment, each of the first dielectric structure and the second dielectric structure may be a single layer film, and the reflecting structure may be formed by a metal reflecting layer. In a second embodiment, each of the first dielectric structure and the second dielectric structure may be a multilayer film structure, and the reflecting layer may be formed by a metal reflecting layer. In a third embodiment, the first dielectric structure may be a single layer film, and the second dielectric structure may be a multilayer film structure. A reflectivity comparison between different reflecting layer stacks, and different metal reflecting structures or layers may be carried out by simulation, as described in more detail later.

[0060] Various embodiments may provide structure designs, and designs with reflecting layer stack structures for flip chip structured light emitting diodes, which may improve the light efficiency, uniformity of current spreading, and which may address the reduction of efficiency drop in the devices.

[0061] In the typical structure design of flip chip LEDs, the p- and n-electrodes patterned with finger structure on the device by photolithography may block the light generated from the active region. Furthermore, the layout of these electrodes may also affect the current spreading, which may cause efficiency drop, especially under the high current injection conditions. In contrast, various embodiments may provide structures with improved current guiding designs for flip chip light-emitting devices (LEDs). The current guiding design (or current guide structures) at both the p-contact and n-contact, may be implemented by a series of via holes rather than fingers. The proposed design may reduce the light blocking caused by absorption of n-electrode and p- electrode, and may contribute to an improvement in current spreading by optimizing the distribution of these via holes, thus reducing the efficiency drop in the devices.

[0062] The reflecting layer stack structure may improve the light reflection as compared to a conventional mirror layer, hence also enhancing the output power of the devices compared to the conventional mirror layer. These may be due to the high reflectivity of the reflecting layer stack designs. More importantly, various embodiments may have two or more engineered reflecting layer stack groups with different materials, which may be able to cover the whole visible light spectrum while maintaining high reflectivity.

[0063] In various embodiments, the device, e.g. a flip chip structured diode, may include current guide structures. The p- and n- contacts may be achieved by a series of via holes of which the arrangement/distribution may be calculated and optimized for better uniformity of current spreading. In various embodiments, the device may include a highly reflective structure implemented by a metal layer, and multiple dielectric layers made of different components. The advantages are as follows.

[0064] Firstly, improved electrical properties including a lower forward voltage may be obtained attributing to the optimized layout of the p- and n-electrodes, thus achieving a reduction in efficiency drop. The p- and n-contacts may be made by a series of via holes, which may effectively reduce the forward voltage. The distribution of these via holes may be optimized for more uniform current spreading that contributes to improved electrical properties and reduction of the efficiency drop.

[0065] Secondly, the optical output power from the devices may be improved. The electrode layout with via holes structure may reduce the area occupied by the electrodes as compared to conventional designs with fingers. Therefore, the light absorption by these electrodes may be significantly decreased and more light may be reflected and emitted out from the device. Moreover, most of the n-electrodes may be located at the edge of the devices, which may leave more room for light generation, as the margin effect may result in a low light efficiency in these areas.

[0066] Thirdly, the adoption of the reflecting layer stack structures may further improve the light output power. The reflective layer or stack structure may include a metal layer, and multiple dielectric layers, which has a relatively high reflectivity and thus more light may be reflected out. The designed reflecting layer stack structure may include a metal layer and multiple dielectric layers made by varied materials, which enable the reflecting layer stack structure to achieve a high reflectivity over the entire spectrum. Moreover, the reflective metal layer may further enhance the light reflection.

[0067] Fourthly, the current leakage may be reduced and the reliability for the diode may be improved. In addition to the passivation at the mesa edge of the device to protect the MQWs and p-doped layer, the surface of the electrode may be also protected by silicon oxide (S1O2), which may further reduce the current leakage and improve the device reliability.

[0068] FIG. 4A shows a top view of a light-emitting diode according to various embodiments. The diode may have a flip chip structure and may demonstrate high reflectivity. FIG. 4B shows a cross-sectional side view of the light-emitting diode shown in FIG. 4A along the line A-A' according to various embodiments. FIG. 4C shows an enlarged view of the broken-line frame of FIG. 4B. In order to avoid clutter and improve clarity, not all features that are identical have been labelled.

[0069] The diode may include an epitaxial layer stack 400a. The epitaxial layer stack 400a may include, for example, from the lower side to the upper side, an n-type semiconductor layer 402, a multi-quantum well (MQW) active layer 406 on the n-type semiconductor layer 402, and a p-type semiconductor layer 404 on the active layer 406. The device may be grown on a carrier 416 which may include, but may not be limited to sapphire (AI2O3), silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

[0070] The n-type semiconductor layer 402, the multi-quantum well (MQW) active layer 406, and the p-type semiconductor layer 404 may include, but may not be specifically limited to, for example, gallium nitride -based semiconductor materials such as InxAlyGai-χ-γΝ (0≤X, 0≤Y, X+Y≤l). Other suitable materials, may for instance, be silicon or germanium.

[0071] The epitaxial layer stack 400a may have multiple exposed portions (e.g. wells) which are defined at an upper surface side, thus exposing the n-type semiconductor layer 402. Those exposed portions may be arranged in a region different from a region where the p-electrode 418 is arranged. The exposed portions may be formed partly by etching corresponding portions of the p- type semiconductor layer 404 and the multi-quantum well (MQW) active layer 406 over the n- type semiconductor layer 402.

[0072] The edge of the exposed region may be referred to as mesa edge 420. The multiple exposed portions may be used for electrically connecting the n-type semiconductor layer 402 with the n-electrode 422. In other words, the n-electrode 422 may be arranged on the exposed portions of the n-type semiconductor layer 402, i.e. at the bottom of the well formed on the n-type semiconductor layer 402. The epitaxial layer stack 400a may be formed using a metal-organic chemical vapor deposition (MOCVD) technology or a molecular beam epitaxy (MBE) technology. The layers 402, 404, 406 may be formed using MOCVD or MBE. The n-type semiconductor layer 402 may be patterned to be partially exposed using a photolithography and etching process.

[0073] An electrical conducting structure or layer 424 may be connected to the p-type semiconductor layer 404. The electrical conducting structure or layer 424 may be a single-layer or may be a multi-layer stack formed on the surface of the p-type semiconductor layer 404. The electrical conducting structure or layer 424 may play the role as a current conductor, and may form an ohmic contact with the p-type semiconductor layer 404. The electrical conducting layer 424 may be a single light transparent electrically conductive layer or a multilayer stack including a plurality of light transparent electrically conductive layers. In other words, the electrical conducting structure or layer 424 may be configured to allow at least a portion of light to pass through, and may be electrically conductive.

[0074] The electrical conducting structure or layer 424 may include at least one element selected from the group consisting of zinc, indium, tin, gallium, and magnesium. The light transparent electrically conductive layer may include, for instance, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium-doped zinc oxide (GZO), indium oxide (ln₂0₃), and tin oxide (Sn0₂). In various embodiments, the electrical conducting layer 424 may be formed of ITO, and the thickness of the electrical conducting layer 424 may be any value selected from a range from about 15 nm to about 300 nm.

[0075] The p-electrode 418 may be formed on the surface of the electrical conducting layer 424, and the n-electrode 422 may be formed on the n-type semiconductor layer 402. The p- electrode 418 and the n-electrode 422 may be arranged on the epitaxial layer stack 400a surface side, i.e. the upper surface side opposite the side adjoining the substrate 416. There may be no particular limitation on the width, length, number and shape of the electrodes 418, 422. The electrodes 418, 422 may be suitably configured to the shape and property of the light emitting diode. In various embodiments, the electrodes 418, 422 may each have a circular shape as shown in FIG. 4A.

[0076] Each of the p-electrode 418 and the n-electrode 422 may include but may not be limited to titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), silver (Ag), chromium (Cr), tungsten (W), platinum (Pt), titanium nitride (TiN), or any combination thereof. In various embodiments, the p- electrode 418 and/or the n-electrode 422 may include aluminum or an alloy of aluminum, wherein the aluminum or the alloy of aluminum may improve reflectivity of the p-electrode 418 and/or n- electrode 422. In various other embodiments, the p-electrode 418 and/or the n-electrode 422 may be formed with a multi-layer film with the lower layers of Cr/Al (i.e. a first layer including Cr and a second layer including Al), Ni/Al (i.e. a first layer including Ni and a second layer including Al), Al alloy, or the like, stacked from the epitaxial layer stack 400a side. In other words, the first formed layers of the multi-layer film (e.g. layers first formed on the epitaxial layer stack 400a side) may include Cr/Al (i.e. a first layer including Cr and a second layer including Al), Ni/Al (i.e. a first layer including Ni and a second layer including Al), Al alloy. The thickness of the p-electrode 418 and/or the n-electrode 422 may be of any suitable value.

[0077] The p-electrode 418 may be electrically connected to the electrical conducting layer 424, and the n-electrode 422 may be electrically connected with the n-type semiconductor layer 402. The n-electrode 422 may be patterned to reduce or prevent current leakage, and the edge of the n-electrode pattern may be indicated as 422'. The p-electrode 418 and/or n-electrode 422 may serve as an electrical contact member as well as a reflection member that reflects light.

[0078] A reflecting layer stack structure 400b may be formed on or over the "epitaxial stack" 400a, i.e. on the "epitaxial stack" 400a surface side. The reflecting layer stack structure 400b a first dielectric structure or layer 408, a second dielectric structure or layer 410, a reflecting structure or layer 412, and a third dielectric structure or layer 414. The reflecting layer stack 400b may be designed to realize high reflectivity index and electrical isolation. In other words, the reflecting layer stack 400b may be configured to reflect light, and also to provide electrical insulation. The different structures or layers 408, 410, 412, 414 may be formed by methods such as sputtering, electron beam deposition, and/or plasma enhanced chemical vapor deposition (PECVD).

[0079] In various embodiments, the first dielectric structure 408 and the second dielectric structure 410 may each be a single layer film including aluminum oxide (AI2O3), silicon oxide (S1O2), silicon nitride (SiN_x), silicon oxynitride (SiON), or the like. The single layer films may not reflect (a huge portion of) light, but may allow light to pass through, which may improve the light extraction efficacy.

[0080] In various other embodiments, the first dielectric structure 408 and the second dielectric structure 410 may each be a multilayer film structure with different dielectric layers. The multilayer film structure may include two dielectric materials with different refractive index arranged in an alternating sequence. The dielectric materials may include but may not be limited to silicon oxide (S1O2), titanium oxide (TiOx), tantalum oxide (Ta₂Os), niobium oxide (Nb₂Os), aluminum oxide (A1₂0₃) or the like.

[0081] In addition, the thickness of the multilayer film may be an integral multiple of λ/4 (λ is the wavelength of the light emitted from the multi-quantum well (MQW) active layer 406 or the wavelength of the light excited from the phosphor of the device package). The thickness of the first dielectric structure 408 may be of any value selected from around 20 nm to around 1000 nm, e.g. from around 200 nm to around 800 nm, e.g. around 500 nm. The thickness of the second dielectric structure 410 may be of any value selected from around 200 nm to around 3000 nm.

[0082] In various embodiments, the reflecting structure or layer 412 may include a plurality of different dielectric layers or sub-layers. The reflecting structure or layer 412 may be a multilayer film structure. In various other embodiments, the reflecting structure or layer 412 may be formed by or may include a metal reflecting layer. The metal reflecting layer may include but may not be limited to silver (Ag), aluminum (Al), rhodium (Rh), or any combination thereof. A barrier layer may be formed over the metal reflecting layer. The barrier layer may include but may not be limited to nickel (Ni), titanium (Ti), tungsten (W), chromium (Cr), copper (Cu), or the like. The thickness of the reflecting stucture or layer 412 may be of any value in the range from around 80 nm to around 500 nm.

[0083] A third dielectric layer 414 is deposited as a passivation layer for the reflecting layer stack 140. The material used for the third dielectric layer 140d may be insulative inorganics such as silicon oxide (SiO_x) or silicon nitride oxide (SiON), silicon nitride (SiN_x), titanium oxide (TiO_x), aluminium oxide (AI2O3), MgO, HfO, and tantalum oxide (Ta₂05) or organic materials such as photoresist, polymer, NR-7, and SU-8. The thickness of the third dielectric layer 140d may be of any value selected in a range from around 100 nm to around 1000 nm.

[0084] The reflecting layer stack structure 400b may have multiple exposed portions which are defined at an upper surface side with the reflecting layer stack edge 400b', to expose the p- electrode 418 and the n-electrode 422. Those exposed portions may be arranged in regions where the p-electrode 418 and the n-electrode 422 are arranged. The exposed portions may be partly formed by removing or etching corresponding portions of the first dielectric layer 408, the second dielectric layer 410, and the third dielectric layer 414. The edge of the reflecting layer 412' may be formed. The edge of the reflecting layer 412' may or may not be flush with the edge of the reflecting layer stack edge 400b. The exposed edge of reflecting layer 412' may or may not be the same as the edge reflecting layer stack edge 400b'. [0085] The edge of reflecting layer 412' may be located between the mesa edge 420 and the edge of the n-electrode pattern 422'. In another case (not shown), the edge of reflecting layer 412' may be located at the side which is opposite to the mesa edge 420.

[0086] The profile shape including the mesa edge 420, the edge of the n-electrode pattern 422', the edge of reflecting layer 412', and the reflecting layer stack edge 400b'; may be vertical as shown in FIG.4B. In another embodiment (not shown), the profile shape may be inclined with a controllable inclination angle formed by various manufacturing methods.

[0087] A reflecting layer stack 400b may have higher reflectivity compared with a conventional metal reflecting layer like a common silver (Ag) mirror. The embodiments for the reflecting layer stack 400b are shown as FIGS.4D to 4F. FIGS. 5A - C show simulation graph for reflectivity comparison of the different embodiments.

[0088] FIG. 4D shows a schematic of the reflecting layer stack structure 400b according to various embodiments.

[0089] In FIG.4D, each of the first dielectric structure 408 and the second dielectric structure 410 may be a single layer film formed of aluminum oxide (AI2O3), silicon oxide (S1O2), silicon nitride (SiN_x), SiON or the like, which may be transparent and may allow the light to pass through to improve light extraction efficacy. For instance, AI2O3 may be included in the first dielectric layer 408, and S1O2 may be included in the second dielectric layer 410. The reflector structure 412 may be a metal reflecting layer including a metal such as silver (Ag), aluminum (Al), rhodium (Rh), or any combination thereof. In various embodiments, the reflecting layer stack structure 400b may include the first dielectric structure 408, the second dielectric structure 410 on the first dielectric structure 408, a reflector structure 412 on the second dielectric structure, and the third dielectric structure 414 on the reflector structure 412.

[0090] FIG. 5A is a plot of reflectance (in percent or %) as a function of wavelength (in nanometer or nm) comparing the reflectivity of the reflecting layer stack structure 400b shown in FIG. 4D according to various embodiments and the reflectivity of a silver (Ag) - based mirror. CO indicates data related to the silver (Ag) - based mirror, while CI denotes data related to the reflecting layer stack structure 400b shown in FIG. 4D.

[0091] FIG. 4E shows a schematic of the reflecting layer stack structure 400b according to various other embodiments. [0092] In FIG. 4E, the first dielectric structure 408 may include a low refractive index layer 408a and a high refractive index layer 408b. The first dielectric structure 408 may include a plurality of low refractive index layers 408a, and a plurality of high index layers 408b. The first dielectric structure 408 may include alternating low refractive index layers 408a and high refractive index layers 408b. The first dielectric structure 408 may include a low refractive index layer 408a, a high refractive index layer 408b on the low refractive index layer 408a, a further low refractive index layer 408a on the high refractive index layer 408b, a further high refractive index layer 408b on the further low refractive index layer 408a etc.

[0093] The second dielectric structure 410 may include a low refractive index layer 410a and a high refractive index layer 410b. The second dielectric structure 410 may include a plurality of low refractive index layers 410a, and a plurality of high index 410b. The second dielectric structure 410 may include alternating low refractive index layers 410a and high refractive index layers 410b. The second dielectric structure 410 may include a low refractive index layer 410a, a high refractive index layer 410b on the low refractive index layer 410a, a further low refractive index layer 410a on the high refractive index layer 410b, a further high refractive index layer 410b on the further low refractive index layer 410a etc.

[0094] The multilayer film structure may show relatively high reflectivity, but may transmit visible light of a long wavelength range. The second dielectric structure 410 may be disposed above the first dielectric structure 408 to reflect light transmitted through the first dielectric structure 408, thereby improving light emission efficiency.

[0095] Each of the first dielectric structure 408 and the second dielectric structure 410 may include a multilayer structure, i.e. a multilayer structure with alternating low refractive index layers 408a, 410a (e.g. including S1O2) and high refractive index layers 408b, 410b (e.g. including TiO_x) The number of pairs of multilayers may range from 1 to 6, e.g. from 2 to 4. In other words, each of the first dielectric structure 408 and the second dielectric structure 410 may have a number of pairs of low refractive index layers 408a, 410a and high refractive index layers 408b, 410b selected from a range from 1 to 6, e.g. from 2 to 4. The second dielectric structure 410 may be on the first dielectric structure 408, a reflector structure 412 may be on the second dielectric structure 410, and a third dielectric structure 414 may be on the reflector structure 412. [0096] The reflectivity property of the structure or arrangement 400b at the wavelengths of 450-460 nm (blue light emitted from multi-quantum well (MQW) active layer 406) and at the wavelengths of 520~580nm (yellow light excited from phosphor) may be considered separately.

[0097] FIG. 5B is a plot of reflectance (in percent or %) as a function of wavelength (in nanometer or nm) comparing the reflectivity of the reflecting layer stack structure 400b shown in FIG. 4E according to various embodiments and the reflectivity of a silver (Ag) - based mirror. CO indicates data related to the silver (Ag) - based mirror, while C2 denotes data related to the reflecting layer stack structure 400b shown in FIG. 4E. The data for two examples of the reflecting layer stack structure 400b shown in FIG. 4E is shown in FIG. 5B. The solid continuous line shows a reflecting layer stack structure 400b in which the metal reflector layer 412 is a silver (Ag) layer, while the line with long dashes shows a reflecting layer stack structure 400b in which the metal reflector structure 412 is an aluminum (Al) layer.

[0098] FIG. 4F shows a schematic of the reflecting layer stack structure 400b according to yet various other embodiments.

[0099] In FIG.4F, the first dielectric structure 408 may be a single layer film, and the second dielectric structure 410 may be a multilayer film structure. The second dielectric structure 410 may include a low refractive index layer 410c and a high refractive index layer 410d. The second dielectric structure 410 may include a plurality of low refractive index layers 410c and a plurality of high index layers 410d.

[00100] The first dielectric structure 408 may include silicon oxide (S1O2). The second dielectric structure 410 may include alternating low refractive index layers 410c (e.g. including S1O2) and high refractive index layers 410d (e.g. including TiOx). The second dielectric structure 410 may include a low refractive index layer 410c, a high refractive index layer 410d on the low refractive index layer 410c, a further low refractive index layer 410c on the high refractive index layer 410d, a further high refractive index layer 410d on the further low refractive index layer 410c etc.

[00101] The second dielectric structure 410 may have a number of pairs of low refractive index layers 410c and high refractive index layers 410d selected from a range from 1 to 6, e.g. from 2 to 4. [00102] The second dielectric structure 410 may be on the first dielectric structure 408, a reflector structure 412 may be on the second dielectric structure 410, and a third dielectric structure 414 may be on the reflector structure 412.

[00103] FIG. 5C is a plot of reflectance (in percent or %) as a function of wavelength (in nanometer or nm) comparing the reflectivity of the reflecting layer stack structure 400b shown in FIG. 4F according to various embodiments and the reflectivity of a silver (Ag) - based mirror.

[00104] CO indicates data related to the silver (Ag) - based mirror, while C3 denotes data related to the reflecting layer stack structure 400b shown in FIG. 4F. The data for two examples of the reflecting layer stack structure 400b shown in FIG. 4F is shown in FIG. 5C. The solid continuous line shows a reflecting layer stack structure 400b in which the metal reflector layer 412 is a silver (Ag) layer, while the line with long dashes shows a reflecting layer stack structure 400b in which the metal reflector structure 412 is an aluminum (Al) layer.

[00105] As shown in FIGS. 5A-C, within the useable range of 445nm to 460nm, light total reflectance of different reflecting layer stack structure 400b according to various embodiments may be improved by 2% -6% as compared to the conventional Ag - based mirror.

[00106] FIG. 5D shows a plot of power Po (in milli Watts or mW) / voltage Vf (in volts or V) as a function of current I (in milli Amperes or mA) comparing the reflectivity performance of different embodiments.

[00107] Each sample illustrated in FIG. 5D is a 380 μπι*760 μηι chip device in a bare chip package. The results show the light power of C3 (i.e. with reflecting layer stack structure 400b shown in FIG. 4F) having a reflector structure 412 of aluminum (Al) may be improved by about 9% as compared with the light power of CO reference having the Ag-base mirror. Further, the light efficiency of C3 may be improved over the light efficiency of CO by about 6%.

[00108] Referring back to FIGS. 4B-4C, reflectivity of the electrodes 418, 422 may generally be much lower than that of the reflecting layer stack 400b. The smaller diameter or width of the electrodes 418, 422 may help to avoid blocking of light. The diameter or width of the electrode 418 and/or the electrode 422 may be any value selected from a range from about 1 μπι to about 50 μπι, preferably from about 5 μπι to about 20 μπι.

[00109] The device may further include a P-type current spreading layer 426 and a N-type current spreading layer 428. The P-type current spreading layer 426 may be electrically connected with the p-electrode 418, and the N-type current spreading layer 428 may be electrically connected with the n-electrode 422. The current spreading layers 426, 428 may be patterned according to the pattern of the p-electrode 418 and the n-electrode 422 respectively. In addition, the device may include a separate region 430 which may be reserved to avoid mechanical damage during contact of the device with a sorting needle. The separate region 430 may be between the P-type current spreading layer 426 and the N-type current spreading layer 428.

[00110] The material of the current spreading layer 426 and/or the current spreading layer 428 may include, but may not be limited to rhodium (Rh), titanium (Ti), nickel (Ni), platinum (Pt), aluminum (Al), gold (Au), chromium (Cr), tungsten (W), palladium (Pd), titanium nitride (TiN) or any combination thereof. The current spreading layer 426 and/or the current spreading layer 428 may have a thickness of a value selected from a range from about 0.01 μπι to about 2 μπι, e.g. from about 0.1 μπι to about 1 μπι.

[00111] A fourth dielectric layer 432 may be formed on the surface of the device. The fourth dielectric layer 432 may be formed on or over the "epitaxial stack" 400a and/or the reflecting layer stack structure 400b. The fourth dielectric layer 432 may include an inorganic material such as silicon oxide (SiO_x), silicon nitride oxide or silicon oxynitride (SiON), silicon nitride (SiN_x), titanium oxide (TiO_x), aluminum oxide (AI2O3), magnesium oxide (MgO), hafnium oxide (HfO), or tantalum oxide (Ta₂05), or an organic material such as a polymer, a photoresist such as NR-7 or SU-8, or the like. The fourth dielectric layer 432 may be formed from any suitable material. The fourth dielectric layer 432 may be of a suitable thickness so that it is able to provide electrical insulation.

[00112] The device may further include a P-type electrode pad 434 connected to P-type current spreading layer 426, as well as a N-type electrode pad 436 connected to N-type current spreading layer 428.

[00113] The material of the P-type electrode pad 434 and/or the N-type electrode pad 436 may include, but may not be limited to titanium (Ti), nickel (Ni), platinum (Pt), aluminum (Al), gold (Au), chromium (Cr), tungsten (W), copper (Cu), tin (Sn), titanium nitride (TiN), or any combination thereof. For example, the P-type electrode pad 434 and the N-type electrode pad 436 may include a material selected from a group consisting of nickel (Ni), gold (Au), copper (Cu), and an alloy formed from any combination thereof (from Ni, Au, and/or Cu). [00114] The fourth dielectric layer 432 may serve as electrical insulation between the P-type current spreading layer 426 and the N-type electrode pad 436, and may also serve as electrical insulation between the N-type current spreading layer 428 and the P-type electrode pad 434. In other words, the P-type current spreading layer 426 may be electrically connected to the P-type electrode pad 434 and electrically insulated from the N-type electrode pad 436, while the N-type current spreading layer 428 may be electrically connected to the N-type electrode pad 436 and electrically insulated from the P-type electrode pad 434.

[00115] Meanwhile, the layout of the electrodes 418, 422 may affect both the effect of current spreading and the non-sheltered pattern area of the reflecting layer stack 400b, which may be critical for total light efficiency of light emitting diodes.

[00116] The electrodes 418, 422 may occupy any percentage selected in a range from 1 % to 5% of the total area of the light-emitting diode. The non-sheltered pattern area of the reflecting layer stack 400b may occupy any percentage selected in a range from 70% to 98% of the total area of the light-emitting diode. The layout of the electrodes in various other embodiments is shown in FIG.6. FIG. 6 shows a top view of a light-emitting diode according to various other embodiments. The electrodes 618 may correspond to the electrodes 418 in FIG. 4A, the electrodes 622 may correspond to the electrodes 422 in FIG. 4A. The edge of the reflecting layer 612', the edge reflecting layer stack edge 600b, and the electrical conducting layer 624 are also indicated in FIG. 6.

[00117] For instance, the electrodes 418, 422 may occupy 1.8% of the total area of the device shown in FIG. 4A, and the electrodes 618, 622 may occupy 1.2% of the total area of the device shown in FIG. 6. Also, the non-sheltered pattern area of the reflecting layer stack 400b may occupy 92.9% of the total area of the device shown in FIG. 4A , and the non-sheltered pattern area of the reflecting layer stack may occupy the 93.9% of the total area of the device shown in FIG. 6.

[00118] Various embodiments may relate to a light emitting diode. The light-emitting diode may include an epitaxial layer stack including a n-type semiconductor layer, a p-type semiconductor layer, and an active layer disposed between the n-type semiconductor layer and the p-type semiconductor layer. The light-emitting diode may further include a reflecting layer stack disposed above the epitaxial layer stack. The reflecting layer stack may include a first dielectric structure or layer, a second dielectric structure or layer disposed on the first dielectric structure or layer, a reflecting structure or layer disposed on the second dielectric structure or layer, and a third dielectric structure or layer disposed on the reflecting structure or layer.

[00119] In various embodiments, both the first dielectric layer and the second dielectric layer may be a single layer film. In various other embodiments, both the first dielectric structure and the second dielectric structure may be a multilayer film structure. In yet various other embodiments, the first dielectric layer may be a single layer film and the second dielectric structure may be a multilayer film structure, or the first dielectric structure may be a multilayer film structure and the second dielectric layer may be a single layer film.

[00120] In various embodiments, the reflecting layer may be a metal layer. In various other embodiments, the reflecting structure may be a multilayer film structure with different dielectric layers.

[00121] Various embodiments may be used to manufacture a semiconductor light emitting diodes with flip chip structure and high reflectivity. These semiconductor light emitting diodes may be used as light sources, displays, or other specific applications.

[00122] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

1. A light-emitting device comprising: an epitaxial stack arrangement comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type different from the first conductivity type; and

an active layer between the first semiconductor layer and the second semiconductor layer; and

a reflector stack arrangement over the epitaxial stack arrangement, the reflector stack arrangement comprising:

a first dielectric structure;

a second dielectric structure on the first dielectric structure;

a reflector structure on the second dielectric structure; and

a third dielectric structure on the reflector structure.

2. The light-emitting device according to claim 1 , wherein the first dielectric structure is a layer; and

wherein the second dielectric structure is another layer.

3. The light-emitting device according to claim 2, wherein the first dielectric structure comprises a dielectric material selected from a group consisting of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride; and

wherein the second dielectric structure comprises another dielectric material selected from a group consisting of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride.

The light-emitting device according to claim 1 , wherein the first dielectric structure is a layer; and

wherein the second dielectric structure comprises a plurality of layers.

The light-emitting device according to claim 4, wherein a first layer of the plurality of layers comprises a first dielectric material selected from a group consisting of silicon oxide, titanium oxide, tantalum oxide, niobium oxide, and aluminum oxide; and

wherein a second layer of the plurality of layers comprises a second dielectric material selected from a group consisting of silicon oxide, titanium oxide, tantalum oxide, niobium oxide, and aluminum oxide

The light-emitting device according to claim 1 , wherein the first dielectric structure comprises a plurality of layers; and wherein the second dielectric structure is a layer.

The light-emitting device according to claim 1 , wherein the first dielectric structure comprises a first plurality of layers; and wherein the second dielectric structure comprises a second plurality of layers.

The light-emitting device according to any one of claim 1 to claim 7, further comprising: a first electrode in electrical connection with the second semiconductor layer; and a second electrode in electrical connection with the first semiconductor layer.

The light-emitting device according to claim 8, further comprising: an electrical conductor layer in contact with the second semiconductor layer; wherein the first electrode is in contact with the electrical conductor layer.

10. The light-emitting device according to claim 8 or claim 9, wherein the first electrode is of the second conductivity type; and

wherein the second electrode is of the first conductivity type.

11. The light-emitting device according to any one of claim 8 to claim 10, further

comprising:

a first current spreader layer in electrical connection with the first electrode; and a second current spreader layer in electrical connection with the second electrode.

12. The light-emitting device according to claim 11,

wherein the first current spreader is of the second conductivity type; and wherein the second current spreader is of the first conductivity type.

13. The light-emitting device according to claim 11 or claim 12, further comprising: a first electrode pad in electrical connection with the first current spreader; and a second electrode pad in electrical connection with the second current spreader.

14. The light-emitting device according to any one of claim 11 to claim 13, further

comprising:

a fourth dielectric structure configured to electrically insulate the first electrode pad from the second current spreader and configured to electrically insulate the second electrode pad from the first current spreader.

15. The light-emitting device according to claim 14, wherein the fourth dielectric structure comprises an inorganic material or an organic material.

16. A method of forming a light-emitting device, the method comprising: forming an epitaxial stack arrangement comprising:

a first semiconductor layer of a first conductivity type;

forming a reflector stack arrangement over the epitaxial stack arrangement, the reflector stack arrangement comprising:

a first dielectric structure;

a second dielectric structure on the first dielectric structure;

a reflector structure on the second dielectric structure; and

a third dielectric structure on the reflector structure.

17. The method according to claim 16

wherein the first dielectric structure is a layer; and

wherein the second dielectric structure is another layer.

18. The method according to claim 16,

wherein the first dielectric structure is a layer; and

wherein the second dielectric structure comprises a plurality of layers.

19. The method according to claim 16,

wherein the first dielectric structure comprises a plurality of layers; and wherein the second dielectric structure is a layer.

20. The method according to claim 16,

wherein the first dielectric structure comprises a first plurality of layers; and wherein the second dielectric structure comprises a second plurality of layers.

21. The method according to any one of claim 16 to claim 20, further comprising:

forming a first electrode in electrical connection with the second semiconductor layer; and

forming a second electrode in electrical connection with the first semiconductor layer.

22. The method according to claim 21, further comprising:

forming an electrical conductor layer in contact with the second semiconductor layer;

wherein the first electrode is in contact with the electrical conductor layer.

23. The method according to claim 21 or claim 22, further comprising:

forming a first current spreader layer in electrical connection with the first electrode; and

forming a second current spreader layer in electrical connection with the second electrode.

24. The method according to claim 23, further comprising:

forming a first electrode pad in electrical connection with the first current spreader; and

forming a second electrode pad in electrical connection with the second current spreader.

25. The method according to claim 24, further comprising:

forming a fourth dielectric structure configured to electrically insulate the first electrode pad from the second current spreader and configured to electrically insulate the second electrode pad from the first current spreader.