WO2016106926A1 - 一种应用于平板显示器的goa驱动电路及平板显示器 - Google Patents

一种应用于平板显示器的goa驱动电路及平板显示器 Download PDF

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Publication number
WO2016106926A1
WO2016106926A1 PCT/CN2015/071711 CN2015071711W WO2016106926A1 WO 2016106926 A1 WO2016106926 A1 WO 2016106926A1 CN 2015071711 W CN2015071711 W CN 2015071711W WO 2016106926 A1 WO2016106926 A1 WO 2016106926A1
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Prior art keywords
inverter
electrically connected
gate
output
input end
Prior art date
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PCT/CN2015/071711
Other languages
English (en)
French (fr)
Inventor
郝思坤
Original Assignee
深圳市华星光电技术有限公司
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Filing date
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to KR1020177021420A priority Critical patent/KR102043534B1/ko
Priority to JP2017534652A priority patent/JP6502503B2/ja
Priority to GB1706898.2A priority patent/GB2546684B/en
Priority to US14/433,648 priority patent/US9727162B2/en
Priority to RU2017125767A priority patent/RU2667459C1/ru
Priority to DE112015005105.8T priority patent/DE112015005105B4/de
Publication of WO2016106926A1 publication Critical patent/WO2016106926A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04104—Multi-touch detection in digitiser, i.e. details about the simultaneous detection of a plurality of touching locations, e.g. multiple fingers or pen and finger
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA driving circuit and a flat panel display applied to a flat panel display.
  • Array substrate row driver (gate driver on array GOA) has the advantages of lowering production cost and narrow bezel design, and has been gradually applied in the field of liquid crystal display (LCD).
  • Touch sensing technology that can provide a natural interface between electronic systems and users has also been used in various fields. Wide range of applications, especially embedded touch (in-cell) Touch), which has the advantages of thin thickness and sensitive touch.
  • the advanced GOA circuit drives the scanning, and after all the gate lines are scanned, the touch signal output scanning is performed.
  • the GOA circuit drives the scanning process without interruption. Therefore, the frequency of the GOA circuit driving scanning is consistent with the frequency of the touch signal output scanning, that is, one GOA circuit driving scanning can only correspond to one touch signal output scanning, which limits the touch. scanning frequency.
  • the technical problem to be solved by the present invention is to provide a GOA driving circuit and a flat panel display applied to a flat panel display, which can realize scanning interruption of the GOA driving circuit and increase the touch scanning frequency.
  • a technical solution adopted by the present invention is to provide a GOA driving circuit applied to a flat panel display, including:
  • the front stage circuit includes a plurality of cascaded GOA driving subunits
  • a middle-segment circuit comprising two cascaded GOA driver sub-units, wherein an input end of a previous one of the GOA driving sub-units in the middle-segment circuit is electrically connected to a last one of the GOA drivers in the front-end circuit The output of the unit;
  • a back-end circuit comprising a plurality of cascaded GOA driving sub-units, wherein an input end of the first one of the GOA driving sub-units in the back-end circuit is electrically connected to the latter one of the middle-segment circuits The output of the GOA driver subunit;
  • the GOA driving sub-units in the front-end circuit, the middle-segment circuit, and the back-end circuit respectively receive the first clock signal and the second clock signal to sequentially generate corresponding gate driving signals, and the first clock signal and An interrupt period is set in the second clock signal to generate an interrupt between the corresponding gate drive signals sequentially generated, and the flat panel display performs a touch detection operation in the interrupted interval;
  • the interrupt period is greater than one pulse signal time and less than one frame time.
  • the GOA driving sub-units in each of the front-end circuit, the middle-segment circuit, and the back-end circuit are electrically connected to a corresponding gate line, respectively, to sequentially output corresponding gate driving signals to the corresponding The gate line.
  • the first clock signal and the second clock signal respectively include a first period, the interrupt period, a recovery period, and a second period;
  • the first clock signal and the second clock signal respectively output a pulse signal in the first period, and the polarity of the pulse signal output by the first clock signal and the second clock signal output The polarity of the pulse signal is reversed, and the GOA driving sub-units in the front-end circuit in the GOA driving circuit sequentially output part of the gate driving signals to drive the gates of the portions on the flat panel display. line;
  • the first clock signal is maintained at a first logic and the second clock signal is maintained at a second logic, wherein a polarity of the first logic and a pole of the second logic The opposite is true, and during the interruption period, the middle segment circuit and the rear segment circuit in the GOA driving circuit stop outputting the gate driving signal;
  • the first clock signal is maintained in the second logic during the recovery period, and the second clock signal outputs a second logic signal and a first logic signal, the mid-segment circuit in the GOA driving circuit Start to restore the output of the next two levels of gate drive signals;
  • the first clock signal and the second clock signal respectively output a pulse signal, and a polarity of a pulse signal output by the first clock signal and a pulse output by the second clock signal
  • the polarity of the signal is just the opposite, and the latter circuit in the GOA driver circuit outputs the remaining gate drive signals.
  • the first logic is a logic low level and the second logic is a logic high level.
  • the interrupt period is adjusted according to actual needs.
  • the front segment circuit, the middle segment circuit and the back segment circuit respectively comprise an odd-numbered GOA driving sub-unit and an even-numbered GOA driving sub-unit.
  • the odd-numbered GOA driving sub-unit and the even-numbered GOA driving sub-unit in the front-end circuit respectively include:
  • the first inverter includes an input end, a first clock control end, a second clock control end, and an output end, wherein the input end is electrically connected to an output end of the upper GOA driving subunit;
  • first NOR gate and a second NOR gate
  • first input end of the first NOR gate is electrically connected to the output end of the second inverter, and the second input end thereof is electrically connected to the An output of the second NOR gate
  • the output end of the first NOR gate is electrically connected to the first input end of the second NOR gate
  • the second input end of the second NOR gate is electrically connected An input end of the second inverter
  • NAND gate wherein the first input end of the NAND gate is electrically connected to the first clock signal or the second clock signal, and the second input end thereof is electrically connected to the output of the second NOR gate end;
  • a fourth inverter wherein an input end of the fourth inverter is electrically connected to an output end of the third inverter, and an output end of the fourth inverter is used as the GOA of the current stage Driving the output of the subunit to output a corresponding gate driving signal;
  • the first clock control end of the first inverter in the odd-numbered GOA driving sub-unit is electrically connected to the first clock signal, and the second clock control end is electrically connected to the second clock signal. And the first input end of the NAND gate is electrically connected to the first clock signal;
  • a first clock control end of the first inverter in the even-numbered-level GOA driving sub-unit is electrically connected to the second clock signal, and a second clock control end thereof is electrically connected to the first clock signal, and The first input end of the NAND gate is electrically connected to the second clock control signal.
  • the odd-numbered GOA driver sub-unit in the middle-segment circuit includes:
  • a first inverter comprising an input terminal, a first clock control terminal, a second clock control terminal and an output terminal, wherein the input terminal is electrically connected to an output of a last one of the GOA driving subunits in the front segment circuit end;
  • first NOR gate and a second NOR gate
  • first input end of the first NOR gate is electrically connected to the output end of the second inverter, and the second input end thereof is electrically connected to the An output of the second NOR gate
  • the output end of the first NOR gate is electrically connected to the first input end of the second NOR gate
  • the second input end of the second NOR gate is electrically connected An input end of the second inverter
  • a three-state NAND gate comprising a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal is electrically connected to the output end of the second NOR gate;
  • a fourth inverter wherein an input end of the fourth inverter is electrically connected to an output end of the third inverter, and an output end of the fourth inverter is used as the GOA of the current stage Driving the output of the subunit to output a corresponding gate driving signal;
  • the first clock control end of the first inverter and the second input end of the three-state NAND gate in the odd-numbered GOA driving sub-unit are electrically connected to the first clock signal, respectively.
  • the second clock control end of the first inverter and the third input end of the tri-state NAND gate are electrically connected to the second clock signal respectively;
  • the even-numbered GOA driving sub-units in the middle-segment circuit include:
  • the first inverter includes an input end, a first clock control end, a second clock control end, and an output end, wherein the input end is electrically connected to an output end of the upper GOA driving subunit;
  • first NOR gate and a second NOR gate
  • first input end of the first NOR gate is electrically connected to the output end of the second inverter, and the second input end thereof is electrically connected to the An output of the second NOR gate
  • the output end of the first NOR gate is electrically connected to the first input end of the second NOR gate
  • the second input end of the second NOR gate is electrically connected An input end of the second inverter
  • a fourth inverter comprising: a first input end, a second input end, and an output end, the first input end of the fourth inverter is electrically connected to the output end of the third inverter;
  • a fifth inverter wherein an input end of the fifth inverter is electrically connected to an output end of the fourth inverter, and an output end of the fifth inverter is used as the GOA of the current stage Driving the output of the subunit to output a corresponding gate driving signal;
  • the first clock control end of the first inverter and the second input end of the fourth inverter in the even-numbered GOA driving sub-unit are electrically connected to the second clock signal, respectively.
  • the second clock control terminal of the first inverter is electrically connected to the first clock signal.
  • the odd-numbered GOA driving sub-unit and the even-numbered GOA driving sub-unit in the back-end circuit respectively include:
  • a first inverter comprising an input terminal, a first clock control terminal, a second clock control terminal and an output terminal, wherein the input terminal is electrically connected to an output of a last one of the GOA driving subunits in the front segment circuit end;
  • first NOR gate and a second NOR gate
  • first input end of the first NOR gate is electrically connected to the output end of the second inverter, and the second input end thereof is electrically connected to the An output of the second NOR gate
  • the output end of the first NOR gate is electrically connected to the first input end of the second NOR gate
  • the second input end of the second NOR gate is electrically connected An input end of the second inverter
  • NAND gate wherein the first input end of the NAND gate is electrically connected to the first clock signal or the second clock signal, and the second input end thereof is electrically connected to the output of the second NOR gate end;
  • a fourth inverter wherein an input end of the fourth inverter is electrically connected to an output end of the third inverter, and an output end of the fourth inverter is used as the GOA of the current stage Driving the output of the subunit to output a corresponding gate driving signal;
  • the first clock control end of the first inverter in the odd-numbered GOA driving sub-unit is electrically connected to the first clock signal, and the second clock control end is electrically connected to the second clock signal. And the first input end of the NAND gate is electrically connected to the first clock signal;
  • a first clock control end of the first inverter in the even-numbered-level GOA driving sub-unit is electrically connected to the second clock signal, and a second clock control end thereof is electrically connected to the first clock signal, and The first input end of the NAND gate is electrically connected to the second clock control signal.
  • a GOA driving circuit applied to a flat panel display including:
  • the front stage circuit includes a plurality of cascaded GOA driving subunits
  • a middle-segment circuit comprising two cascaded GOA driver sub-units, wherein an input end of a previous one of the GOA driving sub-units in the middle-segment circuit is electrically connected to a last one of the GOA drivers in the front-end circuit The output of the unit;
  • a back-end circuit comprising a plurality of cascaded GOA driving sub-units, wherein an input end of the first one of the GOA driving sub-units in the back-end circuit is electrically connected to the latter one of the middle-segment circuits The output of the GOA driver subunit;
  • the GOA driving sub-units in the front-end circuit, the middle-segment circuit, and the back-end circuit respectively receive the first clock signal and the second clock signal to sequentially generate corresponding gate driving signals, and the first clock signal and An interrupt period is set in the second clock signal to generate an interrupt between the corresponding gate drive signals sequentially generated, and the flat panel display performs a touch detection operation in the interrupted interval.
  • the GOA driving sub-units in each of the front-end circuit, the middle-segment circuit, and the back-end circuit are electrically connected to a corresponding gate line, respectively, to sequentially output corresponding gate driving signals to the corresponding The gate line.
  • the first clock signal and the second clock signal respectively include a first period, the interrupt period, a recovery period, and a second period;
  • the first clock signal and the second clock signal respectively output a pulse signal in the first period, and the polarity of the pulse signal output by the first clock signal and the second clock signal output The polarity of the pulse signal is reversed, and the GOA driving sub-units in the front-end circuit in the GOA driving circuit sequentially output part of the gate driving signals to drive the gates of the portions on the flat panel display. line;
  • the first clock signal is maintained at a first logic and the second clock signal is maintained at a second logic, wherein a polarity of the first logic and a pole of the second logic The opposite is true, and during the interruption period, the middle segment circuit and the rear segment circuit in the GOA driving circuit stop outputting the gate driving signal;
  • the first clock signal is maintained in the second logic during the recovery period, and the second clock signal outputs a second logic signal and a first logic signal, the mid-segment circuit in the GOA driving circuit Start to restore the output of the next two levels of gate drive signals;
  • the first clock signal and the second clock signal respectively output a pulse signal, and a polarity of a pulse signal output by the first clock signal and a pulse output by the second clock signal
  • the polarity of the signal is just the opposite, and the latter circuit in the GOA driver circuit outputs the remaining gate drive signals.
  • the first logic is a logic low level and the second logic is a logic high level.
  • the interrupt period is adjusted according to actual needs.
  • the front segment circuit, the middle segment circuit and the back segment circuit respectively comprise an odd-numbered GOA driving sub-unit and an even-numbered GOA driving sub-unit.
  • the odd-numbered GOA driving sub-unit and the even-numbered GOA driving sub-unit in the front-end circuit respectively include:
  • the first inverter includes an input end, a first clock control end, a second clock control end, and an output end, wherein the input end is electrically connected to an output end of the upper GOA driving subunit;
  • first NOR gate and a second NOR gate
  • first input end of the first NOR gate is electrically connected to the output end of the second inverter, and the second input end thereof is electrically connected to the An output of the second NOR gate
  • the output end of the first NOR gate is electrically connected to the first input end of the second NOR gate
  • the second input end of the second NOR gate is electrically connected An input end of the second inverter
  • NAND gate wherein the first input end of the NAND gate is electrically connected to the first clock signal or the second clock signal, and the second input end thereof is electrically connected to the output of the second NOR gate end;
  • a fourth inverter wherein an input end of the fourth inverter is electrically connected to an output end of the third inverter, and an output end of the fourth inverter is used as the GOA of the current stage Driving the output of the subunit to output a corresponding gate driving signal;
  • the first clock control end of the first inverter in the odd-numbered GOA driving sub-unit is electrically connected to the first clock signal, and the second clock control end is electrically connected to the second clock signal. And the first input end of the NAND gate is electrically connected to the first clock signal;
  • a first clock control end of the first inverter in the even-numbered-level GOA driving sub-unit is electrically connected to the second clock signal, and a second clock control end thereof is electrically connected to the first clock signal, and The first input end of the NAND gate is electrically connected to the second clock control signal.
  • the odd-numbered GOA driver sub-unit in the middle-segment circuit includes:
  • a first inverter comprising an input terminal, a first clock control terminal, a second clock control terminal and an output terminal, wherein the input terminal is electrically connected to an output of a last one of the GOA driving subunits in the front segment circuit end;
  • first NOR gate and a second NOR gate
  • first input end of the first NOR gate is electrically connected to the output end of the second inverter, and the second input end thereof is electrically connected to the An output of the second NOR gate
  • the output end of the first NOR gate is electrically connected to the first input end of the second NOR gate
  • the second input end of the second NOR gate is electrically connected An input end of the second inverter
  • a three-state NAND gate comprising a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal is electrically connected to the output end of the second NOR gate;
  • a fourth inverter wherein an input end of the fourth inverter is electrically connected to an output end of the third inverter, and an output end of the fourth inverter is used as the GOA of the current stage Driving the output of the subunit to output a corresponding gate driving signal;
  • the first clock control end of the first inverter and the second input end of the three-state NAND gate in the odd-numbered GOA driving sub-unit are electrically connected to the first clock signal, respectively.
  • the second clock control end of the first inverter and the third input end of the tri-state NAND gate are electrically connected to the second clock signal respectively;
  • the even-numbered GOA driving sub-units in the middle-segment circuit include:
  • the first inverter includes an input end, a first clock control end, a second clock control end, and an output end, wherein the input end is electrically connected to an output end of the upper GOA driving subunit;
  • first NOR gate and a second NOR gate
  • first input end of the first NOR gate is electrically connected to the output end of the second inverter, and the second input end thereof is electrically connected to the An output of the second NOR gate
  • the output end of the first NOR gate is electrically connected to the first input end of the second NOR gate
  • the second input end of the second NOR gate is electrically connected An input end of the second inverter
  • a fourth inverter comprising: a first input end, a second input end, and an output end, the first input end of the fourth inverter is electrically connected to the output end of the third inverter;
  • a fifth inverter wherein an input end of the fifth inverter is electrically connected to an output end of the fourth inverter, and an output end of the fifth inverter is used as the GOA of the current stage Driving the output of the subunit to output a corresponding gate driving signal;
  • the first clock control end of the first inverter and the second input end of the fourth inverter in the even-numbered GOA driving sub-unit are electrically connected to the second clock signal, respectively.
  • the second clock control terminal of the first inverter is electrically connected to the first clock signal.
  • the odd-numbered GOA driving sub-unit and the even-numbered GOA driving sub-unit in the back-end circuit respectively include:
  • a first inverter comprising an input terminal, a first clock control terminal, a second clock control terminal and an output terminal, wherein the input terminal is electrically connected to an output of a last one of the GOA driving subunits in the front segment circuit end;
  • first NOR gate and a second NOR gate
  • first input end of the first NOR gate is electrically connected to the output end of the second inverter, and the second input end thereof is electrically connected to the An output of the second NOR gate
  • the output end of the first NOR gate is electrically connected to the first input end of the second NOR gate
  • the second input end of the second NOR gate is electrically connected An input end of the second inverter
  • NAND gate wherein the first input end of the NAND gate is electrically connected to the first clock signal or the second clock signal, and the second input end thereof is electrically connected to the output of the second NOR gate end;
  • a fourth inverter wherein an input end of the fourth inverter is electrically connected to an output end of the third inverter, and an output end of the fourth inverter is used as the GOA of the current stage Driving the output of the subunit to output a corresponding gate driving signal;
  • the first clock control end of the first inverter in the odd-numbered GOA driving sub-unit is electrically connected to the first clock signal, and the second clock control end is electrically connected to the second clock signal. And the first input end of the NAND gate is electrically connected to the first clock signal;
  • a first clock control end of the first inverter in the even-numbered-level GOA driving sub-unit is electrically connected to the second clock signal, and a second clock control end thereof is electrically connected to the first clock signal, and The first input end of the NAND gate is electrically connected to the second clock control signal.
  • another technical solution adopted by the present invention is to provide a flat display including the above GOA driving circuit.
  • the GOA driving circuit applied to the flat panel display of the present invention comprises a front-end circuit, a middle-segment circuit and a rear-segment circuit which are sequentially connected, and respectively pass the first clock signal and the second, respectively, different from the prior art.
  • the clock signal provides signals to the forward segment circuit, the middle segment circuit, and the rear segment circuit to sequentially generate corresponding gate drive signals.
  • the present invention sets an interrupt period in the first clock signal and the second clock signal, and the first clock signal And when the second clock signal scan reaches the interrupt period, causing the GOA driving circuit to generate an interrupt in the corresponding gate driving signal sequentially generated, and after the interruption period, the GOA driving circuit resumes generating the corresponding gate driving signal.
  • the flat panel display performs the touch detection operation, so that the touch detection operation is performed during the gate line driving scanning process, and the touch detection operation is not performed until the gate line driving scanning ends. Increases the frequency of touch detection operations and enables multi-touch.
  • FIG. 1 is a schematic structural view of an embodiment of a GOA driving circuit applied to a flat panel display according to the present invention
  • FIG. 2 is a circuit diagram of an odd-numbered GOA driving sub-unit in a front-end circuit according to an embodiment of the present invention
  • FIG. 3 is a circuit diagram of an even-numbered GOA driving sub-unit in a front-end circuit according to an embodiment of the present invention
  • FIG. 4 is a circuit diagram of an odd-numbered GOA driving sub-unit in a mid-segment circuit according to an embodiment of the present invention
  • FIG. 5 is a circuit diagram of an even-numbered GOA driving sub-unit in a middle-segment circuit according to an embodiment of the present invention
  • FIG. 6 is a circuit diagram of an odd-numbered GOA driving sub-unit in a back-end circuit according to an embodiment of the present invention
  • FIG. 7 is a circuit diagram of an even-numbered GOA driving sub-unit in a back-end circuit according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram showing an output timing state of a GOA driving circuit according to an embodiment of the present invention.
  • An embodiment of the present invention provides a GOA driving circuit applied to a flat panel display.
  • the GOA driving circuit is integrated on an array substrate for providing a driving signal to a gate line.
  • the GOA driving circuit includes a front-end circuit electrically connected in sequence. 1.
  • the front circuit 1 includes a plurality of cascaded GOA driving subunits; the middle circuit 2 includes two cascaded GOA driving subunits, wherein the previous GOA in the middle circuit 2
  • the input end of the driving subunit is electrically connected to the output end of the last GOA driving subunit in the front stage circuit 1;
  • the rear end circuit 3 includes a plurality of cascaded GOA driving subunits, wherein the first one of the rear stage circuits 3
  • the input ends of the GOA driving subunits are electrically connected to the output end of the latter GOA driving subunit in the middle circuit 2; wherein the concatenation refers to the series connection, that is, the previous GOA driving subunit of the plurality of GOA driving subunits
  • the output end is connected to the input end of a GOA driving subunit, and the front end circuit 1 and the rear end circuit 3 respectively comprise two or more GOA driving subunits, and the GOA driving subunit of the embodiment of the present invention passes the shifting Bit register implementation.
  • the GOA driving subunits in the front segment circuit 1, the middle segment circuit 2, and the rear segment circuit 3 respectively receive the first clock signal and the second clock signal to sequentially generate corresponding gate driving signals, and connect the gate lines to the GOA driver.
  • a gate driving signal is provided to the gate line through the GOA driving sub-unit, and an interrupt period is set in the first clock signal and the second clock signal to generate between the corresponding gate driving signals sequentially generated.
  • the flat panel display performs a touch detection operation in the interrupted interval; when the first clock signal and the second clock signal are scanned to the interrupt period, the signal of a certain GOA driving subunit in the GOA driving circuit is interrupted, that is, no signal is generated.
  • the interrupt can occur in any GOA driver subunit other than the first and last in the GOA driver circuit.
  • the GOA driver circuit stops supplying the driving signal to the gate line, and the flat panel display can perform touch detection. Operation, after the interruption period, the GOA driving subunit resumes the signal and continues to provide the driving signal to the gate line.
  • two or more interrupt periods may be set in the first clock signal and the second clock signal.
  • the GOA driving circuit applied to the flat panel display includes a front segment circuit 1, a middle segment circuit 2 and a rear segment circuit 3 connected in series, and respectively passes the first clock signal and the second clock signal to the front segment
  • the circuit 1, the middle circuit 2 and the rear circuit 3 provide signals to sequentially generate corresponding gate driving signals
  • the embodiment of the present invention sets an interrupt period in the first clock signal and the second clock signal, the first clock signal and
  • the GOA driving circuit generates an interrupt in the corresponding gate driving signal generated sequentially, and after the interruption period, the GOA driving circuit resumes generating the corresponding gate driving signal, in the interrupt period.
  • the flat panel display performs the touch detection operation, so that the touch detection operation during the gate line driving scanning process is realized, and the touch detection operation is not performed until all the gate line driving scanning ends, and the touch is increased. Control the frequency of detection operations to achieve multi-touch.
  • each stage GOA driving sub-unit in the front-end circuit 1, the middle-segment circuit 2 and the back-end circuit 3 is electrically connected to a corresponding gate line, respectively, to sequentially output corresponding gate driving signals to corresponding ones. Gate line.
  • the output ends of the GOA driving sub-units connected in sequence in the front-end circuit, the middle-segment circuit, and the back-end circuit are sequentially connected to successively adjacent plurality of gate lines, for example, if the output end of one of the GOA driving sub-units is connected to the gate line Gn, the output of the previous GOA driving subunit is connected to the gate line Gn-1, and the output end of the next GOA driving subunit is connected to the gate line Gn+1; when the first clock signal and the second clock signal are scanned When the interrupt period is reached, the signal of the GOA driving circuit is interrupted.
  • the interrupt occurs in the GOA driving sub-unit connected to the gate line Gn at the output end, that is, during the interrupt period, the GOA driving sub-unit does not go to the gate line.
  • Gn outputs a gate driving signal, and at this time, a touch detection operation can be performed.
  • the GOA driving subunit resumes outputting a gate driving signal to the gate line Gn, and simultaneously transmits the signal to the output terminal thereof.
  • the latter GOA driving sub-unit causes the latter GOA driving sub-unit to output a gate driving signal to the gate line Gn+1, so that the GOA driving circuit resumes driving signal scanning.
  • the first clock signal and the second clock signal respectively include a first period, an interrupt period, a recovery period, and a second period;
  • the first clock signal and the second clock signal respectively output a pulse signal
  • the polarity of the pulse signal output by the first clock signal is opposite to the polarity of the pulse signal output by the second clock signal
  • the GOA driving sub-units in the front-end circuit in the GOA driving circuit sequentially output part of the gate driving signals to drive the gate lines of the portions on the flat panel display; that is, in the first period, the GOA driving sub-units in the front-end circuits are oriented a gate line connected thereto outputs a gate driving signal;
  • the first clock signal is maintained at the first logic and the second clock signal is maintained at the second logic, wherein the polarity of the first logic is opposite to the polarity of the second logic, and during the interrupt period, the GOA The middle circuit and the rear circuit in the driving circuit stop outputting the gate driving signal; that is, in the interruption period, the output of the GOA driving subunit in the middle circuit does not output a signal, and does not output a gate driving signal to the gate line connected thereto. Therefore, during the interrupt period, the gate line is interrupted, and the touch signal can be scanned.
  • the length of the interrupt period in the embodiment of the present invention can be adjusted according to actual needs, and generally controlled to be greater than one pulse signal time and less than one frame. Picture time
  • the first clock signal is maintained in the second logic, and the second clock signal outputs a second logic signal and a first logic signal, and the middle circuit in the GOA driving circuit begins to recover the output of the next two stages of gate driving.
  • the GOA driving subunit in the middle circuit resumes outputting the gate driving signal to the gate line connected thereto, that is, after the touch signal scanning ends, the GOA driving circuit continues the uncompleted gate line driving.
  • the first clock signal and the second clock signal respectively output a pulse signal, and the polarity of the pulse signal output by the first clock signal is opposite to the polarity of the pulse signal output by the second clock signal, and the GOA driving circuit
  • the latter stage circuit outputs the remaining gate drive signal to complete the gate line drive signal scan.
  • the embodiment of the present invention divides the first clock signal and the second clock signal into a first period, an interrupt period, a recovery period, and a second period, and is disposed in the first period, and outputs a driving signal to the gate line by the front-end circuit.
  • the driving signal is transmitted to the middle circuit, and during the interruption period, the middle circuit does not output the signal, thereby stopping the transmission of the driving signal to the gate line, so During the interruption period, the touch signal can be scanned, and when the recovery period is reached, the middle circuit resumes outputting the driving signal to the gate line, and in the second period, the driving signal is transmitted to the rear stage circuit, and in the second period, the rear stage circuit A drive signal is output to the gate line connected thereto.
  • the first logic is a logic low level and the second logic is a logic high level.
  • the front-end circuit, the middle-segment circuit and the back-end circuit respectively comprise an odd-numbered GOA driving sub-unit and an even-numbered GOA driving sub-unit connected; that is, the GOA driving circuit of the embodiment of the present invention includes a total of Six GOA driving sub-units can provide driving signals to six gate lines Gn, Gn+1, Gn+2, Gn+3, Gn+4, Gn+5.
  • the odd-numbered GOA driving sub-units and the even-numbered-level GOA driving sub-units in the preceding circuit have the same structure, respectively:
  • the first inverters 11, 21 include an input terminal, a first clock control terminal, a second clock control terminal and an output terminal, wherein the input terminal is electrically connected to the output end of the upper-level GOA driving sub-unit as the GOA driver of the current level a signal input terminal of the unit; in the embodiment of the present invention, the input end of the first inverter 11 of the odd-numbered GOA driving sub-unit of the front-end circuit is connected to the start signal of the GOA driving circuit, and the even-numbered GOA driving sub-unit of the front-end circuit The input end of the first inverter 21 is connected to the output end of the fourth inverter 17 of the odd-numbered GOA driving sub-unit of the front-end circuit;
  • NOR gate 13 , 23 and a second NOR gate 14 , 24 wherein the first input end of the first NOR gates 13 , 23 is electrically connected to the output end of the second inverter 12 , 22 ,
  • the two input terminals are electrically connected to the output ends of the second NOR gates 14, 24, and the output ends of the first NOR gates 13, 23 are electrically connected to the first input end of the second NOR gates 14, 24, the second or the second
  • the second input ends of the gates 14, 24 are electrically connected to the input ends of the second inverters 12, 22;
  • a NAND gate 15, 25 wherein the first input terminal of the NAND gates 15, 25 is electrically connected to the first clock signal CK or the second clock signal XCK, and the second input terminal is electrically connected to the second NOR gate 14, The output of 24;
  • a third inverter 16, 26 wherein the input ends of the third inverters 16, 26 are electrically connected to the output ends of the NAND gates 15, 25;
  • the first clock control end of the first inverter 11 of the odd-numbered GOA driving sub-unit in the front-end circuit is electrically connected to the first clock signal CK, and the second clock control end is electrically connected to the second clock signal XCK.
  • the first input end of the NAND gate 15 is electrically connected to the first clock signal CK;
  • the first clock control end of the first inverter 21 in the even-numbered stage of the GOA driving sub-unit is electrically connected to the second clock signal XCK, and the second clock control end is electrically connected to the first clock signal CK, and The first input end of the NOT gate 25 is electrically connected to the second clock control signal XCK.
  • the output terminal of the fourth inverter 17 of the odd-numbered GOA driving sub-unit in the preceding-stage circuit of the embodiment of the present invention is connected to the input terminal of the first inverter 21 of the even-stage GOA driving sub-unit in the preceding-stage circuit.
  • the first clock signal and the second clock signal having opposite polarity of the output pulse signal enable the front stage circuit to output the driving signal to the corresponding gate line.
  • the odd-numbered GOA driver sub-unit in the middle-segment circuit includes:
  • the first inverter 31 includes an input terminal, a first clock control terminal, a second clock control terminal and an output terminal, wherein the input terminal is electrically connected to the output end of the last GOA driving subunit in the front segment circuit as the current level
  • the signal input end of the GOA driving subunit in the embodiment of the present invention, the input end of the first inverter 31 of the odd-numbered GOA driving sub-unit in the middle-stage circuit and the fourth end of the even-numbered GOA driving sub-unit in the front-end circuit
  • the output of the phase comparator 27 is connected;
  • a second inverter 32 wherein the input end of the second inverter 32 is electrically connected to the output end of the first inverter 31;
  • first NOR gate 33 and a second NOR gate 34, wherein the first input end of the first NOR gate 33 is electrically connected to the output end of the second inverter 32, and the second input end is electrically connected to the second end
  • the output of the first NOR gate 33 is electrically connected to the first input end of the second NOR gate 34, and the second input end of the second NOR gate 34 is electrically connected to the second inverter. Input of 32;
  • a three-state NAND gate 35 comprising a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal is electrically connected to the output end of the second NOR gate 34;
  • a third inverter 36 wherein the input end of the third inverter 36 is electrically connected to the output end of the tri-state NAND gate 35;
  • a fourth inverter 37 wherein an input end of the fourth inverter 37 is electrically connected to an output end of the third inverter 36, and an output end of the fourth inverter 37 is used as a GOA driving subunit of the current stage.
  • the output terminal is connected to the gate line Gn+2 to output a corresponding gate driving signal;
  • the first clock control end of the first inverter 31 and the second input end of the tri-state NAND gate 35 in the odd-numbered GOA driving sub-unit are electrically connected to the first clock signal CK, respectively, and the first inverter 31
  • the second clock control terminal and the third input terminal of the tri-state NAND gate 35 are electrically connected to the second clock signal XCK;
  • the even-numbered GOA driver subunits in the middle circuit include:
  • the first inverter 41 includes an input terminal, a first clock control terminal, a second clock control terminal and an output terminal, wherein the input terminal is electrically connected to the output end of the upper-level GOA driving sub-unit, that is, the odd-level GOA driver is connected to the middle-segment circuit.
  • a second inverter 42 wherein an input end of the second inverter 42 is electrically connected to an output end of the first inverter 41;
  • first NOR gate 43 and a second NOR gate 44, wherein the first input end of the first NOR gate 43 is electrically connected to the output end of the second inverter 42 and the second input end thereof is electrically connected to the second end
  • the output of the first NOR gate 43 is electrically connected to the first input end of the second NOR gate 44, and the second input end of the second NOR gate 44 is electrically connected to the second inverting end.
  • a third inverter 45 wherein the input end of the third inverter 45 is electrically connected to the output end of the second NOR gate 44;
  • the fourth inverter 46 includes a first input terminal, a second input terminal, and an output terminal, and the first input terminal of the fourth inverter 46 is electrically connected to the output end of the third inverting device 45;
  • a fifth inverter 47 wherein an input end of the fifth inverter 47 is electrically connected to an output end of the fourth inverter 46, and an output end of the fifth inverter 47 is used as a GOA driving subunit of the current stage.
  • the output terminal is connected to the gate line Gn+3 to output a corresponding gate driving signal;
  • the first clock control terminal of the first inverter 41 and the second input terminal of the fourth inverter 46 of the even-numbered GOA driving sub-unit are electrically connected to the second clock signal XCK, respectively.
  • the second clock control terminal is electrically connected to the first clock signal CK.
  • the first clock signal and the second clock signal of the first logic and the second logic having opposite polarities are respectively maintained, so that the odd-numbered GOA driving sub-units in the middle-end circuit do not output signals, so that the gate
  • the epipolar driving signal scan is interrupted, and when the recovery period is reached, when the first clock signal outputs a second logic and the second clock signal outputs a second logic, the odd-numbered GOA driving sub-unit in the middle-segment circuit recovers the output signal, and When the first clock signal continues to output a second logic and the second clock signal outputs a first logic, the even-numbered stages of the middle-stage circuit drive the sub-unit output signal, thereby causing the GOA drive circuit to resume delivering the drive signal to the gate line.
  • the odd-numbered GOA driver sub-units and the even-numbered-level GOA driver sub-units in the latter stage circuit have the same structure, and respectively include:
  • the first inverter 61, 71 includes an input terminal, a first clock control terminal, a second clock control terminal and an output terminal, wherein the input terminal is electrically connected to the output end of the upper-level GOA driving sub-unit as the GOA driver of the current level a signal input terminal of the unit; in the embodiment of the present invention, the first inverter 61 of the odd-numbered GOA driving sub-unit of the back-end circuit is connected to the fifth inverter of the even-numbered GOA driving sub-unit of the mid-segment circuit The output end of 47 is used as the signal input end of the odd-numbered GOA driving sub-unit in the back-end circuit, and the input terminal of the first inverter 71 of the even-numbered GOA driving sub-unit in the rear-end circuit is connected to the odd-numbered GOA in the back-end circuit.
  • a second inverter 62, 72 wherein the input ends of the second inverters 62, 72 are electrically connected to the output ends of the first inverters 61, 71;
  • NOR gate 63, 73 a first NOR gate 63, 73 and a second NOR gate 64, 74, wherein the first input end of the first NOR gate 63, 73 is electrically connected to the output end of the second inverter 62, 72,
  • the two input terminals are electrically connected to the output ends of the second NOR gates 64, 74, and the output ends of the first NOR gates 63, 73 are electrically connected to the first input end of the second NOR gates 64, 74, the second or the second
  • the second input ends of the gates 64, 74 are electrically connected to the input ends of the second inverters 62, 72;
  • a NAND gate 65, 75 wherein the first input terminal of the NAND gates 65, 75 is electrically connected to the first clock signal CK or the second clock signal XCK, and the second input terminal is electrically connected to the second NOR gate 64, The output of 74;
  • a third inverter 66, 76 wherein the input ends of the third inverters 66, 76 are electrically connected to the output ends of the NAND gates 65, 75;
  • a fourth inverter 67, 77 wherein the input terminals of the fourth inverters 67, 77 are electrically connected to the output terminals of the third inverters 66, 76, and the outputs of the fourth inverters 67, 77 are used as The output end of the GOA driving sub-unit of the current stage outputs a corresponding gate driving signal; the output end of the fourth inverter 67 is connected to the gate line Gn+4, and the output end of the fourth inverter 77 is connected to the gate line Gn+5;
  • the first clock control end of the first inverter 61 in the odd-numbered GOA driving sub-unit is electrically connected to the first clock signal CK, and the second clock control end is electrically connected to the second clock signal XCK, and the NAND gate
  • the first input end of 65 is electrically connected to the first clock signal CK;
  • the first clock control end of the first inverter 71 in the even-numbered GOA driving sub-unit is electrically connected to the second clock signal XCK, and the second clock control end is electrically connected to the first clock signal CK, and the NAND gate 75
  • the first input terminal is electrically connected to the second clock control signal XCK.
  • the first clock signal and the second clock signal having opposite polarity of the output pulse signal enable the latter circuit to output the driving signal to the corresponding gate line.
  • the front-end circuit may further include more than two GOA driving sub-units, and when the current segment circuit includes more than two GOA driving sub-units, the structure of the odd-numbered GOA driving sub-units And the connection manner is the same as the odd-numbered GOA driving sub-unit in the preceding-stage circuit in the above embodiment, and the structure and connection manner of the even-numbered GOA driving sub-units and the even-numbered GOA driver in the preceding-stage circuit in the above embodiment
  • the units are the same; for example, the front-end circuit includes five sequentially connected GOA driving sub-units, and the structure and connection manner of the first, third, and fifth GOA driving sub-units and the odd-numbered GOA driver in the front-end circuit in the above embodiment
  • the units are the same, and the structure and connection manner of the 2nd and 4th GOA driving subunits are the same as those of the even-numbered GOA driving subunits in the preceding circuit in the above embodiment.
  • the back-end circuit may further include more than two GOA driving sub-units, and when the back-end circuit includes more than two GOA driving sub-units, the odd-numbered GOA driving sub-units thereof
  • the structure and connection manner are the same as the odd-numbered GOA driving sub-units in the back-end circuit in the above embodiment, and the structure and connection mode of the even-numbered GOA driving sub-units are the same as those in the latter-stage circuit in the above embodiment.
  • the stage GOA driving subunits are the same; for example, the rear stage circuit includes five sequentially connected GOA driving subunits, and the structures and connection manners of the first, third, and fifth GOA driving subunits are in the latter stage circuit in the above embodiment.
  • the odd-numbered GOA driver sub-units are identical, and the second and fourth GOA driver sub-units are identical in structure and connection to the even-numbered GOA driver sub-units in the latter stage circuit in the above embodiment.
  • Another embodiment of the present invention provides a flat panel display including the GOA driving circuit in the above embodiment.
  • the GOA driving circuit of the flat panel display includes a front segment circuit, a middle segment circuit and a rear segment circuit which are sequentially connected, and respectively passes the first clock signal and the second clock signal to the forward segment circuit and the middle segment circuit, respectively.
  • the latter circuit provides a signal to sequentially generate a corresponding gate driving signal.
  • the embodiment of the present invention sets an interrupt period in the first clock signal and the second clock signal, and the first clock signal and the second clock signal are scanned to reach an interrupt period.
  • the GOA driving circuit When the GOA driving circuit generates an interrupt corresponding to the corresponding gate driving signal, the GOA driving circuit resumes generating the corresponding gate driving signal after the interruption period, and the flat panel display performs the touch detection during the interruption period. Operation, so that the touch detection operation during the gate line driving scanning process is realized, and the touch detection operation is not performed until all the gate line driving scanning ends, thereby increasing the frequency of the touch detection operation and realizing multi touch.

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Abstract

一种应用于平板显示器的GOA驱动电路及平板显示器，所述GOA驱动电路包括前段电路（1）、中段电路（2）和后段电路（3），其中，所述前段电路（1）、中段电路（2）和后段电路（3）中的GOA驱动子单元分别接收第一时钟信号（CK）和第二时钟信号（XCK）以依次产生对应的栅极驱动信号，且所述第一时钟信号（CK）和所述第二时钟信号（XCK）中设定有中断周期，以在依次产生的对应的所述栅极驱动信号之间产生中断，所述平板显示器在所述中断的区间内执行触控侦测操作。通过上述方式，能够实现GOA驱动电路扫描中断，增加触控扫描频率。

Description

一种应用于平板显示器的GOA驱动电路及平板显示器
【技术领域】
本发明涉及显示器技术领域，特别是涉及一种应用于平板显示器的GOA驱动电路及平板显示器。
【背景技术】
阵列基板行驱动（gate driver on array GOA）具有降低生产成本和窄边框设计的优点，已逐渐在液晶显示器(LCD)领域得到应用；同时能在电子系统与使用者之间提供自然界面的触控感应技术也已在各种领域中的广泛应用，特别是嵌入式触控（in-cell touch），其具有厚度薄、触控灵敏等优点。
现有技术在将GOA驱动电路和触控技术结合应用时，通常情况下，当面板正常工作时，先进性GOA电路驱动扫描，等所有的栅极线扫描结束后，再进行触控信号输出扫描，GOA电路驱动扫描的过程不存在中断，因此GOA电路驱动扫描的频率和触控信号输出扫描的频率相一致，即一次GOA电路驱动扫描只能对应一次触控信号输出扫描，这限制了触控扫描频率。
【发明内容】
本发明主要解决的技术问题是提供一种应用于平板显示器的GOA驱动电路及平板显示器，能够实现GOA驱动电路扫描中断，增加触控扫描频率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种应用于平板显示器的GOA驱动电路，包括：
前段电路，包括多个级联的GOA驱动子单元；
中段电路，包括两个级联的GOA驱动子单元，其中，所述中段电路中的前一个所述GOA驱动子单元的输入端电性连接至所述前段电路中的最后一个所述GOA驱动子单元的输出端；
后段电路，包括多个级联的GOA驱动子单元，其中，所述后段电路中的第一个所述GOA驱动子单元的输入端电性连接至所述中段电路中的后一个所述GOA驱动子单元的输出端；
其中，所述前段电路、中段电路和后段电路中的所述GOA驱动子单元分别接收第一时钟信号和第二时钟信号以依次产生对应的栅极驱动信号，且所述第一时钟信号和所述第二时钟信号中设定有中断周期，以在依次产生的对应的所述栅极驱动信号之间产生中断，所述平板显示器在所述中断的区间内执行触控侦测操作；所述中断周期大于一个脉冲信号时间且小于一帧画面时间。
其中，所述前段电路、中段电路和后段电路中的每级所述GOA驱动子单元分别电性连接一条对应的栅极线，以依次地输出相应的所述栅极驱动信号至所述对应的栅极线。
其中，所述第一时钟信号和所述第二时钟信号分别包括第一周期、所述中断周期、恢复周期和第二周期；
其中，在所述第一周期内，所述第一时钟信号和所述第二时钟信号分别输出脉冲信号，且所述第一时钟信号输出的脉冲信号的极性与所述第二时钟信号输出的脉冲信号的极性正好相反，且所述GOA驱动电路中的所述前段电路中的所述GOA驱动子单元分别依次输出部分的栅极驱动信号以驱动所述平板显示器上的部分的栅极线；
在所述中断周期内，所述第一时钟信号维持在第一逻辑，而所述第二时钟信号维持在第二逻辑，其中，所述第一逻辑的极性与所述第二逻辑的极性相反，且在所述中断周期内，所述GOA驱动电路中的所述中段电路和所述后段电路停止输出栅极驱动信号；
在所述恢复周期内，所述第一时钟信号维持在第二逻辑，而所述第二时钟信号输出一个第二逻辑信号和一个第一逻辑信号，所述GOA驱动电路中的所述中段电路开始恢复输出下两级的栅极驱动信号；
在所述第二周期内，所述第一时钟信号和所述第二时钟信号分别输出脉冲信号，且所述第一时钟信号输出的脉冲信号的极性与所述第二时钟信号输出的脉冲信号的极性正好相反，所述GOA驱动电路中的所述后段电路输出剩下的栅极驱动信号。
其中，所述第一逻辑为逻辑低电平，而所述第二逻辑为逻辑高电平。
其中，所述中断周期根据实际需要而进行调整。
其中，所述前段电路、中段电路和后段电路分别包括奇数级GOA驱动子单元和偶数级GOA驱动子单元。
其中，所述前段电路中的所述奇数级GOA驱动子单元和所述偶数级GOA驱动子单元分别包括：
第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接上级所述GOA驱动子单元的输出端；
第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
与非门，其中，所述与非门的第一输入端电性连接所述第一时钟信号或者所述第二时钟信号，其第二输入端电性连接所述第二或非门的输出端；
第三反相器，其中，所述第三反相器的输入端电性连接所述与非门的输出端；
第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第一时钟信号，其第二时钟控制端电性连接所述第二时钟信号，且所述与非门的第一输入端电性连接所述第一时钟信号；
所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第二时钟信号，其第二时钟控制端电性连接所述第一时钟信号，且所述与非门的第一输入端电性连接所述第二时钟控制信号。
其中，所述中段电路中的所述奇数级GOA驱动子单元包括：
第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接所述前段电路中的最后一个所述GOA驱动子单元的输出端；
第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
三态与非门，其包括第一输入端，第二输入端，第三输入端和输出端，所述第一输入端电性连接所述所述第二或非门的输出端；
第三反相器，其中，所述第三反相器的输入端电性连接所述三态与非门的输出端；
第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端和所述三态与非门的第二输入端分别电性连接所述第一时钟信号，所述第一反相器的第二时钟控制端和所述三态与非门的第三输入端分别电性连接所述第二时钟信号；
所述中段电路中的所述偶数级GOA驱动子单元包括：
第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接上级所述GOA驱动子单元的输出端；
第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
第三反相器，其中，所述第三反相器的输入端电性连接所述第二或非门的输出端；
第四反相器，包括第一输入端、第二输入端和输出端，所述第四反相器的第一输入端电性连接所述第三反相器的输出端；
第五反相器，其中，所述第五反相器的输入端电性连接所述第四反相器的输出端，且所述第五反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
其中，所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端和所述第四反相器的第二输入端分别电性连接所述第二时钟信号，所述第一反相器的第二时钟控制端电性连接所述第一时钟信号。
其中，所述后段电路中的所述奇数级GOA驱动子单元和所述偶数级GOA驱动子单元分别包括：
第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接所述前段电路中的最后一个所述GOA驱动子单元的输出端；
第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
与非门，其中，所述与非门的第一输入端电性连接所述第一时钟信号或者所述第二时钟信号，其第二输入端电性连接所述第二或非门的输出端；
第三反相器，其中，所述第三反相器的输入端电性连接所述与非门的输出端；
第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第一时钟信号，其第二时钟控制端电性连接所述第二时钟信号，且所述与非门的第一输入端电性连接所述第一时钟信号；
所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第二时钟信号，其第二时钟控制端电性连接所述第一时钟信号，且所述与非门的第一输入端电性连接所述第二时钟控制信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种应用于平板显示器的GOA驱动电路，包括：
前段电路，包括多个级联的GOA驱动子单元；
中段电路，包括两个级联的GOA驱动子单元，其中，所述中段电路中的前一个所述GOA驱动子单元的输入端电性连接至所述前段电路中的最后一个所述GOA驱动子单元的输出端；
后段电路，包括多个级联的GOA驱动子单元，其中，所述后段电路中的第一个所述GOA驱动子单元的输入端电性连接至所述中段电路中的后一个所述GOA驱动子单元的输出端；
其中，所述前段电路、中段电路和后段电路中的所述GOA驱动子单元分别接收第一时钟信号和第二时钟信号以依次产生对应的栅极驱动信号，且所述第一时钟信号和所述第二时钟信号中设定有中断周期，以在依次产生的对应的所述栅极驱动信号之间产生中断，所述平板显示器在所述中断的区间内执行触控侦测操作。
其中，所述前段电路、中段电路和后段电路中的每级所述GOA驱动子单元分别电性连接一条对应的栅极线，以依次地输出相应的所述栅极驱动信号至所述对应的栅极线。
其中，所述第一时钟信号和所述第二时钟信号分别包括第一周期、所述中断周期、恢复周期和第二周期；
其中，在所述第一周期内，所述第一时钟信号和所述第二时钟信号分别输出脉冲信号，且所述第一时钟信号输出的脉冲信号的极性与所述第二时钟信号输出的脉冲信号的极性正好相反，且所述GOA驱动电路中的所述前段电路中的所述GOA驱动子单元分别依次输出部分的栅极驱动信号以驱动所述平板显示器上的部分的栅极线；
在所述中断周期内，所述第一时钟信号维持在第一逻辑，而所述第二时钟信号维持在第二逻辑，其中，所述第一逻辑的极性与所述第二逻辑的极性相反，且在所述中断周期内，所述GOA驱动电路中的所述中段电路和所述后段电路停止输出栅极驱动信号；
在所述恢复周期内，所述第一时钟信号维持在第二逻辑，而所述第二时钟信号输出一个第二逻辑信号和一个第一逻辑信号，所述GOA驱动电路中的所述中段电路开始恢复输出下两级的栅极驱动信号；
在所述第二周期内，所述第一时钟信号和所述第二时钟信号分别输出脉冲信号，且所述第一时钟信号输出的脉冲信号的极性与所述第二时钟信号输出的脉冲信号的极性正好相反，所述GOA驱动电路中的所述后段电路输出剩下的栅极驱动信号。
其中，所述第一逻辑为逻辑低电平，而所述第二逻辑为逻辑高电平。
其中，所述中断周期根据实际需要而进行调整。
其中，所述前段电路、中段电路和后段电路分别包括奇数级GOA驱动子单元和偶数级GOA驱动子单元。
其中，所述前段电路中的所述奇数级GOA驱动子单元和所述偶数级GOA驱动子单元分别包括：
第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接上级所述GOA驱动子单元的输出端；
第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
与非门，其中，所述与非门的第一输入端电性连接所述第一时钟信号或者所述第二时钟信号，其第二输入端电性连接所述第二或非门的输出端；
第三反相器，其中，所述第三反相器的输入端电性连接所述与非门的输出端；
第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第一时钟信号，其第二时钟控制端电性连接所述第二时钟信号，且所述与非门的第一输入端电性连接所述第一时钟信号；
所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第二时钟信号，其第二时钟控制端电性连接所述第一时钟信号，且所述与非门的第一输入端电性连接所述第二时钟控制信号。
其中，所述中段电路中的所述奇数级GOA驱动子单元包括：
第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接所述前段电路中的最后一个所述GOA驱动子单元的输出端；
第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
三态与非门，其包括第一输入端，第二输入端，第三输入端和输出端，所述第一输入端电性连接所述所述第二或非门的输出端；
第三反相器，其中，所述第三反相器的输入端电性连接所述三态与非门的输出端；
第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端和所述三态与非门的第二输入端分别电性连接所述第一时钟信号，所述第一反相器的第二时钟控制端和所述三态与非门的第三输入端分别电性连接所述第二时钟信号；
所述中段电路中的所述偶数级GOA驱动子单元包括：
第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接上级所述GOA驱动子单元的输出端；
第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
第三反相器，其中，所述第三反相器的输入端电性连接所述第二或非门的输出端；
第四反相器，包括第一输入端、第二输入端和输出端，所述第四反相器的第一输入端电性连接所述第三反相器的输出端；
第五反相器，其中，所述第五反相器的输入端电性连接所述第四反相器的输出端，且所述第五反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
其中，所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端和所述第四反相器的第二输入端分别电性连接所述第二时钟信号，所述第一反相器的第二时钟控制端电性连接所述第一时钟信号。
其中，所述后段电路中的所述奇数级GOA驱动子单元和所述偶数级GOA驱动子单元分别包括：
第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接所述前段电路中的最后一个所述GOA驱动子单元的输出端；
第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
与非门，其中，所述与非门的第一输入端电性连接所述第一时钟信号或者所述第二时钟信号，其第二输入端电性连接所述第二或非门的输出端；
第三反相器，其中，所述第三反相器的输入端电性连接所述与非门的输出端；
第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第一时钟信号，其第二时钟控制端电性连接所述第二时钟信号，且所述与非门的第一输入端电性连接所述第一时钟信号；
所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第二时钟信号，其第二时钟控制端电性连接所述第一时钟信号，且所述与非门的第一输入端电性连接所述第二时钟控制信号。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种平面显示器，包括上述的GOA驱动电路。
本发明的有益效果是：区别于现有技术的情况，本发明的应用于平板显示器的GOA驱动电路包括依次连接的前段电路、中段电路及后段电路，且分别通过第一时钟信号和第二时钟信号向前段电路、中段电路及后段电路提供信号以使其依次产生对应的栅极驱动信号，本发明在第一时钟信号和所述第二时钟信号中设定中断周期，第一时钟信号和第二时钟信号扫描到达中断周期时，使GOA驱动电路在依次产生的对应的所述栅极驱动信号产生中断，而过了中断周期后，GOA驱动电路恢复产生对应的所述栅极驱动信号，在中断周期内，平板显示器执行触控侦测操作，这样便实现了在栅极线驱动扫描过程中进行触控侦测操作，而不必等到栅极线驱动扫描结束才进行触控侦测操作，增加了触控侦测操作的频率，实现多点触控。
【附图说明】
图1是本发明一种应用于平板显示器的GOA驱动电路实施方式的结构示意图；
图2是本发明实施方式的前段电路中奇数级GOA驱动子单元的电路示意图；
图3是本发明实施方式的前段电路中偶数级GOA驱动子单元的电路示意图；
图4是本发明实施方式的中段电路中奇数级GOA驱动子单元的电路示意图；
图5是本发明实施方式的中段电路中偶数级GOA驱动子单元的电路示意图；
图6是本发明实施方式的后段电路中奇数级GOA驱动子单元的电路示意图；
图7是本发明实施方式的后段电路中偶数级GOA驱动子单元的电路示意图；
图8是本发明实施方式的GOA驱动电路输出时序状态示意图。
【具体实施方式】
本发明实施方式提供一种应用于平板显示器的GOA驱动电路，该GOA驱动电路集成在阵列基板上，用于对栅极线提供驱动信号，如图1，GOA驱动电路包括依次电连接的前段电路1、中段电路2和后段电路3，前段电路1包括多个级联的GOA驱动子单元；中段电路2，包括两个级联的GOA驱动子单元，其中，中段电路2中的前一个GOA驱动子单元的输入端电性连接至前段电路1中的最后一个GOA驱动子单元的输出端；后段电路3包括多个级联的GOA驱动子单元，其中，后段电路3中的第一个GOA驱动子单元的输入端电性连接至中段电路2中的后一个GOA驱动子单元的输出端；其中级联是指串联，即多个GOA驱动子单元中的前一个GOA驱动子单元的输出端连接后一个GOA驱动子单元的输入端，前段电路1和后段电路3分别包括两个或两个以上的GOA驱动子单元，本发明实施方式的GOA驱动子单元通过移位寄存器实现。
其中，前段电路1、中段电路2和后段电路3中的GOA驱动子单元分别接收第一时钟信号和第二时钟信号以依次产生对应的栅极驱动信号，将栅极线连接到GOA驱动子单元上便可通过GOA驱动子单元向栅极线提供栅极驱动信号，且第一时钟信号和第二时钟信号中设定有中断周期，以在依次产生的对应的栅极驱动信号之间产生中断，平板显示器在中断的区间内执行触控侦测操作；当第一时钟信号和第二时钟信号扫描到中断周期时，GOA驱动电路中某个GOA驱动子单元的信号中断，即不产生信号，该中断可以发生在GOA驱动电路中的除第一个和最后一个外的任何一个GOA驱动子单元中，这时GOA驱动电路中止向栅极线提供驱动信号，平板显示器可进行触控侦测操作，过了中断周期后，该GOA驱动子单元恢复信号，继续向栅极线提供驱动信号。本发明其它实施方式中可在第一时钟信号和第二时钟信号中设定两个或两个以上中断周期。
区别于现有技术，本发明实施方式的应用于平板显示器的GOA驱动电路包括依次连接的前段电路1、中段电路2及后段电路3，且分别通过第一时钟信号和第二时钟信号向前段电路1、中段电路2及后段电路3提供信号以使其依次产生对应的栅极驱动信号，本发明实施方式在第一时钟信号和第二时钟信号中设定中断周期，第一时钟信号和第二时钟信号扫描到达中断周期时，使GOA驱动电路在依次产生的对应的栅极驱动信号产生中断，而过了中断周期后，GOA驱动电路恢复产生对应的栅极驱动信号，在中断周期内，平板显示器执行触控侦测操作，这样便实现了在栅极线驱动扫描过程中进行触控侦测操作，而不必等到所有栅极线驱动扫描结束才进行触控侦测操作，增加了触控侦测操作的频率，实现多点触控。
其中，如图1，前段电路1、中段电路2和后段电路3中的每级GOA驱动子单元分别电性连接一条对应的栅极线，以依次地输出相应的栅极驱动信号至对应的栅极线。
前段电路、中段电路和后段电路中依次连接的GOA驱动子单元的输出端分别依次连接到依次相邻的多条栅极线上，例如若其中一个GOA驱动子单元的输出端连接栅极线Gn，则其前一个GOA驱动子单元的输出端连接栅极线Gn-1，其后一个GOA驱动子单元的输出端连接栅极线Gn+1；当第一时钟信号和第二时钟信号扫描到中断周期时，GOA驱动电路的信号会中断，例如，该中断发生在输出端与栅极线Gn连接的GOA驱动子单元，即在该中断周期内，该GOA驱动子单元不向栅极线Gn输出栅极驱动信号，此时可进行触控侦测操作，而过了中断周期，该GOA驱动子单元恢复向栅极线Gn输出栅极驱动信号，同时将信号传送至与其输出端连接的后一个GOA驱动子单元，使后一个GOA驱动子单元向栅极线Gn+1输出栅极驱动信号，使得GOA驱动电路恢复驱动信号扫描。
其中，第一时钟信号和第二时钟信号分别包括第一周期、中断周期、恢复周期和第二周期；
其中，在第一周期内，第一时钟信号和第二时钟信号分别输出脉冲信号，且第一时钟信号输出的脉冲信号的极性与第二时钟信号输出的脉冲信号的极性正好相反，且GOA驱动电路中的前段电路中的GOA驱动子单元分别依次输出部分的栅极驱动信号以驱动平板显示器上的部分的栅极线；即在第一周期内，前段电路中的GOA驱动子单元向与其连接的栅极线输出栅极驱动信号；
在中断周期内，第一时钟信号维持在第一逻辑，而第二时钟信号维持在第二逻辑，其中，第一逻辑的极性与第二逻辑的极性相反，且在中断周期内，GOA驱动电路中的中段电路和后段电路停止输出栅极驱动信号；即在中断周期内，中段电路中的GOA驱动子单元输出端不输出信号，不向与其连接的栅极线输出栅极驱动信号，所以在该中断周期内，栅极线驱动中断，可进行触控信号扫描；本发明实施方式的中断周期的长度可根据实际需要而进行调整，一般控制为大于一个脉冲信号时间且小于一帧画面时间；
在恢复周期内，第一时钟信号维持在第二逻辑，而第二时钟信号输出一个第二逻辑信号和一个第一逻辑信号，GOA驱动电路中的中段电路开始恢复输出下两级的栅极驱动信号；在恢复周期内，中段电路中的GOA驱动子单元恢复向与其连接的栅极线输出栅极驱动信号，即在触控信号扫描结束后，GOA驱动电路继续进行未完成的栅极线驱动信号扫描；
在第二周期内，第一时钟信号和第二时钟信号分别输出脉冲信号，且第一时钟信号输出的脉冲信号的极性与第二时钟信号输出的脉冲信号的极性正好相反，GOA驱动电路中的后段电路输出剩下的栅极驱动信号，以完成栅极线驱动信号扫描。
本发明实施方式将第一时钟信号和第二时钟信号分成第一周期、中断周期、恢复周期和第二周期几个部分，并且设置在第一周期中，由前段电路向栅极线输出驱动信号，而第一时钟信号和第二时钟信号到达中断周期时，驱动信号传送至中段电路，并且在中断周期使，中段电路不输出信号，由此便中止了向栅极线传送驱动信号，所以在中断周期中可进行触控信号扫描，而到了恢复周期，中段电路又恢复向栅极线输出驱动信号，到第二周期，驱动信号传送至后段电路，并且在第二周期中，后段电路向与其连接的栅极线输出驱动信号。
其中，第一逻辑为逻辑低电平，而第二逻辑为逻辑高电平。
其中，如图2至图8，前段电路、中段电路和后段电路分别包括相连接的一个奇数级GOA驱动子单元和一个偶数级GOA驱动子单元；即本发明实施方式的GOA驱动电路一共包括六个GOA驱动子单元，可向六条栅极线Gn、Gn+1、Gn+2、Gn+3、Gn+4、Gn+5提供驱动信号。
其中，如图2和图3，前段电路中的奇数级GOA驱动子单元和偶数级GOA驱动子单元具有相同结构，分别包括：
第一反相器11、21，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，输入端电性连接上级GOA驱动子单元的输出端，作为本级GOA驱动子单元的信号输入端；在本发明实施方式中，前段电路的奇数级GOA驱动子单元的第一反相器11的输入端接GOA驱动电路的起始信号，前段电路的偶数级GOA驱动子单元的第一反相器21的输入端连接前段电路的奇数级GOA驱动子单元的第四反相器17的输出端；
第二反相器12、22，其中，第二反相器12、22的输入端电性连接第一反相器11、21的输出端；
第一或非门13、23和第二或非门14、24，其中，第一或非门13、23的第一输入端电性连接第二反相器12、22的输出端，其第二输入端电性连接第二或非门14、24的输出端，第一或非门13、23的输出端电性连接第二或非门14、24的第一输入端，第二或非门14、24的第二输入端电性连接第二反相器12、22的输入端；
与非门15、25，其中，与非门15、25的第一输入端电性连接第一时钟信号CK或者第二时钟信号XCK，其第二输入端电性连接第二或非门14、24的输出端；
第三反相器16、26，其中，第三反相器16、26的输入端电性连接与非门15、25的输出端；
第四反相器17、27，其中，第四反相器17、27的输入端电性连接第三反相器16、26的输出端，且第四反相器17、27的输出端作为本级的GOA驱动子单元的输出端，以输出对应的栅极驱动信号；第四反相器17的输出端与栅极线Gn连接，第四反相器27的输出端与栅极线Gn+1连接；
其中，前段电路中的奇数级GOA驱动子单元中的第一反相器11的第一时钟控制端电性连接第一时钟信号CK，其第二时钟控制端电性连接第二时钟信号XCK，且与非门15的第一输入端电性连接第一时钟信号CK；
前段电路中的偶数级GOA驱动子单元中的第一反相器21的第一时钟控制端电性连接第二时钟信号XCK，其第二时钟控制端电性连接第一时钟信号CK，且与非门25的第一输入端电性连接第二时钟控制信号XCK。
本发明实施方式的前段电路中的奇数级GOA驱动子单元的第四反相器17的输出端连接前段电路中的偶书级GOA驱动子单元的第一反相器21的输入端。
通过上述电路设计，第一周期内，输出脉冲信号极性相反的第一时钟信号和第二时钟信号使得前段电路能够向对应的栅极线输出驱动信号。
中段电路中的奇数级GOA驱动子单元和偶数级GOA驱动子单元的结构略有不同，其中如图4，中段电路中的奇数级GOA驱动子单元包括：
第一反相器31，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，输入端电性连接前段电路中的最后一个GOA驱动子单元的输出端，作为本级GOA驱动子单元的信号输入端；本发明实施方式中，中段电路中的奇数级GOA驱动子单元的第一反相器31的输入端与前段电路中的偶数级GOA驱动子单元的第四反相器27的输出端连接；
第二反相器32，其中，第二反相器32的输入端电性连接第一反相器31的输出端；
第一或非门33和第二或非门34，其中，第一或非门33的第一输入端电性连接第二反相器32的输出端，其第二输入端电性连接第二或非门的输出端，第一或非门33的输出端电性连接第二或非门34的第一输入端，第二或非门34的第二输入端电性连接第二反相器32的输入端；
三态与非门35，其包括第一输入端，第二输入端，第三输入端和输出端，第一输入端电性连接第二或非门34的输出端；
第三反相器36，其中，第三反相器36的输入端电性连接三态与非门35的输出端；
第四反相器37，其中，第四反相器37的输入端电性连接第三反相器36的输出端，且第四反相器37的输出端作为本级的GOA驱动子单元的输出端，与栅极线Gn+2连接，以输出对应的栅极驱动信号；
其中，奇数级GOA驱动子单元中的第一反相器31的第一时钟控制端和三态与非门35的第二输入端分别电性连接第一时钟信号CK，第一反相器31的第二时钟控制端和三态与非门35的第三输入端分别电性连接第二时钟信号XCK；
如图5，中段电路中的偶数级GOA驱动子单元包括：
第一反相器41，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，输入端电性连接上级GOA驱动子单元的输出端，即连接中段电路奇数级GOA驱动子单元中的第四反相器37的输出端；
第二反相器42，其中，第二反相器42的输入端电性连接第一反相器41的输出端；
第一或非门43和第二或非门44，其中，第一或非门43的第一输入端电性连接第二反相器42的输出端，其第二输入端电性连接第二或非门44的输出端，第一或非门43的输出端电性连接第二或非门44的第一输入端，第二或非门44的第二输入端电性连接第二反相器42的输入端；
第三反相器45，其中，第三反相器45的输入端电性连接第二或非门44的输出端；
第四反相器46，包括第一输入端、第二输入端和输出端，第四反相器46的第一输入端电性连接第三反相45器的输出端；
第五反相器47，其中，第五反相器47的输入端电性连接第四反相器46的输出端，且第五反相器47的输出端作为本级的GOA驱动子单元的输出端，与栅极线Gn+3连接，以输出对应的栅极驱动信号；
其中，偶数级GOA驱动子单元中的第一反相器41的第一时钟控制端和第四反相器46的第二输入端分别电性连接第二时钟信号XCK，第一反相器41的第二时钟控制端电性连接第一时钟信号CK。
通过上述电路设计，中断周期内，分别维持在极性相反的第一逻辑和第二逻辑的第一时钟信号和第二时钟信号使得中段电路中的奇数级GOA驱动子单元不输出信号，使栅极线驱动信号扫描中断，而到了恢复周期时，当第一时钟信号输出一个第二逻辑，第二时钟信号输出一个第二逻辑时，中段电路中的奇数级GOA驱动子单元恢复输出信号，而当第一时钟信号继续输出一个第二逻辑，第二时钟信号输出一个第一逻辑时，中段电路中的偶数级GOA驱动子单元输出信号，从而使得GOA驱动电路恢复向栅极线输送驱动信号。
如图6和图7，后段电路中的奇数级GOA驱动子单元和偶数级GOA驱动子单元具有相同结构，分别包括：
第一反相器61、71，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，输入端电性连接上级GOA驱动子单元的输出端，作为本级GOA驱动子单元的信号输入端；在本发明实施方式中，后段电路的奇数级GOA驱动子单元的第一反相器61输入端接性连接中段电路的偶数级GOA驱动子单元的第五反相器47的输出端，作为后段电路中奇数级GOA驱动子单元的信号输入端，后段电路中的偶数级GOA驱动子单元的第一反相器71的输入端接后段电路中奇数级GOA驱动子单元的第四反相器67的输出端；
第二反相器62、72，其中，第二反相器62、72的输入端电性连接第一反相器61、71的输出端；
第一或非门63、73和第二或非门64、74，其中，第一或非门63、73的第一输入端电性连接第二反相器62、72的输出端，其第二输入端电性连接第二或非门64、74的输出端，第一或非门63、73的输出端电性连接第二或非门64、74的第一输入端，第二或非门64、74的第二输入端电性连接第二反相器62、72的输入端；
与非门65、75，其中，与非门65、75的第一输入端电性连接第一时钟信号CK或者第二时钟信号XCK，其第二输入端电性连接第二或非门64、74的输出端；
第三反相器66、76，其中，第三反相器66、76的输入端电性连接与非门65、75的输出端；
第四反相器67、77，其中，第四反相器67、77的输入端电性连接第三反相器66、76的输出端，且第四反相器67、77的输出端作为本级的GOA驱动子单元的输出端，以输出对应的栅极驱动信号；第四反相器67的输出端连接栅极线Gn+4，第四反相器77的输出端连接栅极线Gn+5；
其中，奇数级GOA驱动子单元中的第一反相器61的第一时钟控制端电性连接第一时钟信号CK，其第二时钟控制端电性连接第二时钟信号XCK，且与非门65的第一输入端电性连接第一时钟信号CK；
偶数级GOA驱动子单元中的第一反相器71的第一时钟控制端电性连接第二时钟信号XCK，其第二时钟控制端电性连接第一时钟信号CK，且与非门75的第一输入端电性连接第二时钟控制信号XCK。
通过上述电路设计，第二周期内，输出脉冲信号极性相反的第一时钟信号和第二时钟信号使得后段电路能够向对应的栅极线输出驱动信号。
在本发明其它实施方式中，前段电路还可包括多于多于两个的GOA驱动子单元，当前段电路包括多于两个的GOA驱动子单元时，其第奇数个GOA驱动子单元的结构和连接方式与上述实施方式中的前段电路中的奇数级GOA驱动子单元相同，而其第偶数个GOA驱动子单元的结构和连接方式与上述实施方式中的前段电路中的偶数级GOA驱动子单元相同；例如，前段电路包括5个依次连接的GOA驱动子单元，则第1、3、5个GOA驱动子单元的结构和连接方式与上述实施方式中的前段电路中的奇数级GOA驱动子单元相同，而第2、4个GOA驱动子单元的结构和连接方式与上述实施方式中的前段电路中的偶数级GOA驱动子单元相同。
在本发明其它实施方式中，后段电路还可包括多于多于两个的GOA驱动子单元，当后段电路包括多于两个的GOA驱动子单元时，其第奇数个GOA驱动子单元的结构和连接方式与上述实施方式中的后段电路中的奇数级GOA驱动子单元相同，而其第偶数个GOA驱动子单元的结构和连接方式与上述实施方式中的后段电路中的偶数级GOA驱动子单元相同；例如，后段电路包括5个依次连接的GOA驱动子单元，则第1、3、5个GOA驱动子单元的结构和连接方式与上述实施方式中的后段电路中的奇数级GOA驱动子单元相同，而第2、4个GOA驱动子单元的结构和连接方式与上述实施方式中的后段电路中的偶数级GOA驱动子单元相同。
本发明另一实施方式提供一种平板显示器，该平板显示器包括上述实施方式中的GOA驱动电路。
区别于现有技术，本发明实施方式的平板显示器的GOA驱动电路包括依次连接的前段电路、中段电路及后段电路，且分别通过第一时钟信号和第二时钟信号向前段电路、中段电路及后段电路提供信号以使其依次产生对应的栅极驱动信号，本发明实施方式在第一时钟信号和第二时钟信号中设定中断周期，第一时钟信号和第二时钟信号扫描到达中断周期时，使GOA驱动电路在依次产生的对应的栅极驱动信号产生中断，而过了中断周期后，GOA驱动电路恢复产生对应的栅极驱动信号，在中断周期内，平板显示器执行触控侦测操作，这样便实现了在栅极线驱动扫描过程中进行触控侦测操作，而不必等到所有栅极线驱动扫描结束才进行触控侦测操作，增加了触控侦测操作的频率，实现多点触控。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其它相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种应用于平板显示器的GOA驱动电路，其中，包括：
    前段电路，包括多个级联的GOA驱动子单元；
    中段电路，包括两个级联的GOA驱动子单元，其中，所述中段电路中的前一个所述GOA驱动子单元的输入端电性连接至所述前段电路中的最后一个所述GOA驱动子单元的输出端；
    后段电路，包括多个级联的GOA驱动子单元，其中，所述后段电路中的第一个所述GOA驱动子单元的输入端电性连接至所述中段电路中的后一个所述GOA驱动子单元的输出端；
    其中，所述前段电路、中段电路和后段电路中的所述GOA驱动子单元分别接收第一时钟信号和第二时钟信号以依次产生对应的栅极驱动信号，且所述第一时钟信号和所述第二时钟信号中设定有中断周期，以在依次产生的对应的所述栅极驱动信号之间产生中断，所述平板显示器在所述中断的区间内执行触控侦测操作；所述中断周期大于一个脉冲信号时间且小于一帧画面时间。
  2. 根据权利要求1所述的GOA驱动电路，其中，所述前段电路、中段电路和后段电路中的每级所述GOA驱动子单元分别电性连接一条对应的栅极线，以依次地输出相应的所述栅极驱动信号至所述对应的栅极线。
  3. 根据权利要求1或者2所述的GOA驱动电路，其中，所述第一时钟信号和所述第二时钟信号分别包括第一周期、所述中断周期、恢复周期和第二周期；
    其中，在所述第一周期内，所述第一时钟信号和所述第二时钟信号分别输出脉冲信号，且所述第一时钟信号输出的脉冲信号的极性与所述第二时钟信号输出的脉冲信号的极性正好相反，且所述GOA驱动电路中的所述前段电路中的所述GOA驱动子单元分别依次输出部分的栅极驱动信号以驱动所述平板显示器上的部分的栅极线；
    在所述中断周期内，所述第一时钟信号维持在第一逻辑，而所述第二时钟信号维持在第二逻辑，其中，所述第一逻辑的极性与所述第二逻辑的极性相反，且在所述中断周期内，所述GOA驱动电路中的所述中段电路和所述后段电路停止输出栅极驱动信号；
    在所述恢复周期内，所述第一时钟信号维持在第二逻辑，而所述第二时钟信号输出一个第二逻辑信号和一个第一逻辑信号，所述GOA驱动电路中的所述中段电路开始恢复输出下两级的栅极驱动信号；
    在所述第二周期内，所述第一时钟信号和所述第二时钟信号分别输出脉冲信号，且所述第一时钟信号输出的脉冲信号的极性与所述第二时钟信号输出的脉冲信号的极性正好相反，所述GOA驱动电路中的所述后段电路输出剩下的栅极驱动信号。
  4. 根据权利要求3所述的GOA驱动电路，其中，所述第一逻辑为逻辑低电平，而所述第二逻辑为逻辑高电平。
  5. 根据权利要求3所述的GOA驱动电路，其中，所述中断周期根据实际需要而进行调整。
  6. 根据权利要求3所述的GOA驱动电路，其中，所述前段电路、中段电路和后段电路分别包括奇数级GOA驱动子单元和偶数级GOA驱动子单元。
  7. 根据权利要求6所述的GOA驱动电路，其中，所述前段电路中的所述奇数级GOA驱动子单元和所述偶数级GOA驱动子单元分别包括：
    第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接上级所述GOA驱动子单元的输出端；
    第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
    第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
    与非门，其中，所述与非门的第一输入端电性连接所述第一时钟信号或者所述第二时钟信号，其第二输入端电性连接所述第二或非门的输出端；
    第三反相器，其中，所述第三反相器的输入端电性连接所述与非门的输出端；
    第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
    其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第一时钟信号，其第二时钟控制端电性连接所述第二时钟信号，且所述与非门的第一输入端电性连接所述第一时钟信号；
    所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第二时钟信号，其第二时钟控制端电性连接所述第一时钟信号，且所述与非门的第一输入端电性连接所述第二时钟控制信号。
  8. 根据权利要求6所述的GOA驱动电路，其中，所述中段电路中的所述奇数级GOA驱动子单元包括：
    第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接所述前段电路中的最后一个所述GOA驱动子单元的输出端；
    第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
    第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
    三态与非门，其包括第一输入端，第二输入端，第三输入端和输出端，所述第一输入端电性连接所述所述第二或非门的输出端；
    第三反相器，其中，所述第三反相器的输入端电性连接所述三态与非门的输出端；
    第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
    其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端和所述三态与非门的第二输入端分别电性连接所述第一时钟信号，所述第一反相器的第二时钟控制端和所述三态与非门的第三输入端分别电性连接所述第二时钟信号；
    所述中段电路中的所述偶数级GOA驱动子单元包括：
    第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接上级所述GOA驱动子单元的输出端；
    第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
    第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
    第三反相器，其中，所述第三反相器的输入端电性连接所述第二或非门的输出端；
    第四反相器，包括第一输入端、第二输入端和输出端，所述第四反相器的第一输入端电性连接所述第三反相器的输出端；
    第五反相器，其中，所述第五反相器的输入端电性连接所述第四反相器的输出端，且所述第五反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
    其中，所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端和所述第四反相器的第二输入端分别电性连接所述第二时钟信号，所述第一反相器的第二时钟控制端电性连接所述第一时钟信号。
  9. 根据权利要求6所述的GOA驱动电路，其中，所述后段电路中的所述奇数级GOA驱动子单元和所述偶数级GOA驱动子单元分别包括：
    第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接所述前段电路中的最后一个所述GOA驱动子单元的输出端；
    第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
    第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
    与非门，其中，所述与非门的第一输入端电性连接所述第一时钟信号或者所述第二时钟信号，其第二输入端电性连接所述第二或非门的输出端；
    第三反相器，其中，所述第三反相器的输入端电性连接所述与非门的输出端；
    第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
    其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第一时钟信号，其第二时钟控制端电性连接所述第二时钟信号，且所述与非门的第一输入端电性连接所述第一时钟信号；
    所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第二时钟信号，其第二时钟控制端电性连接所述第一时钟信号，且所述与非门的第一输入端电性连接所述第二时钟控制信号。
  10. 一种应用于平板显示器的GOA驱动电路，其中，包括：
    前段电路，包括多个级联的GOA驱动子单元；
    中段电路，包括两个级联的GOA驱动子单元，其中，所述中段电路中的前一个所述GOA驱动子单元的输入端电性连接至所述前段电路中的最后一个所述GOA驱动子单元的输出端；
    后段电路，包括多个级联的GOA驱动子单元，其中，所述后段电路中的第一个所述GOA驱动子单元的输入端电性连接至所述中段电路中的后一个所述GOA驱动子单元的输出端；
    其中，所述前段电路、中段电路和后段电路中的所述GOA驱动子单元分别接收第一时钟信号和第二时钟信号以依次产生对应的栅极驱动信号，且所述第一时钟信号和所述第二时钟信号中设定有中断周期，以在依次产生的对应的所述栅极驱动信号之间产生中断，所述平板显示器在所述中断的区间内执行触控侦测操作。
  11. 根据权利要求10所述的GOA驱动电路，其中，所述前段电路、中段电路和后段电路中的每级所述GOA驱动子单元分别电性连接一条对应的栅极线，以依次地输出相应的所述栅极驱动信号至所述对应的栅极线。
  12. 根据权利要求10或者11所述的GOA驱动电路，其中，所述第一时钟信号和所述第二时钟信号分别包括第一周期、所述中断周期、恢复周期和第二周期；
    其中，在所述第一周期内，所述第一时钟信号和所述第二时钟信号分别输出脉冲信号，且所述第一时钟信号输出的脉冲信号的极性与所述第二时钟信号输出的脉冲信号的极性正好相反，且所述GOA驱动电路中的所述前段电路中的所述GOA驱动子单元分别依次输出部分的栅极驱动信号以驱动所述平板显示器上的部分的栅极线；
    在所述中断周期内，所述第一时钟信号维持在第一逻辑，而所述第二时钟信号维持在第二逻辑，其中，所述第一逻辑的极性与所述第二逻辑的极性相反，且在所述中断周期内，所述GOA驱动电路中的所述中段电路和所述后段电路停止输出栅极驱动信号；
    在所述恢复周期内，所述第一时钟信号维持在第二逻辑，而所述第二时钟信号输出一个第二逻辑信号和一个第一逻辑信号，所述GOA驱动电路中的所述中段电路开始恢复输出下两级的栅极驱动信号；
    在所述第二周期内，所述第一时钟信号和所述第二时钟信号分别输出脉冲信号，且所述第一时钟信号输出的脉冲信号的极性与所述第二时钟信号输出的脉冲信号的极性正好相反，所述GOA驱动电路中的所述后段电路输出剩下的栅极驱动信号。
  13. 根据权利要求12所述的GOA驱动电路，其中，所述第一逻辑为逻辑低电平，而所述第二逻辑为逻辑高电平。
  14. 根据权利要求12所述的GOA驱动电路，其中，所述中断周期根据实际需要而进行调整。
  15. 根据权利要求12所述的GOA驱动电路，其中，所述前段电路、中段电路和后段电路分别包括奇数级GOA驱动子单元和偶数级GOA驱动子单元。
  16. 根据权利要求15所述的GOA驱动电路，其中，所述前段电路中的所述奇数级GOA驱动子单元和所述偶数级GOA驱动子单元分别包括：
    第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接上级所述GOA驱动子单元的输出端；
    第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
    第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
    与非门，其中，所述与非门的第一输入端电性连接所述第一时钟信号或者所述第二时钟信号，其第二输入端电性连接所述第二或非门的输出端；
    第三反相器，其中，所述第三反相器的输入端电性连接所述与非门的输出端；
    第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
    其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第一时钟信号，其第二时钟控制端电性连接所述第二时钟信号，且所述与非门的第一输入端电性连接所述第一时钟信号；
    所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第二时钟信号，其第二时钟控制端电性连接所述第一时钟信号，且所述与非门的第一输入端电性连接所述第二时钟控制信号。
  17. 根据权利要求15所述的GOA驱动电路，其中，所述中段电路中的所述奇数级GOA驱动子单元包括：
    第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接所述前段电路中的最后一个所述GOA驱动子单元的输出端；
    第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
    第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
    三态与非门，其包括第一输入端，第二输入端，第三输入端和输出端，所述第一输入端电性连接所述所述第二或非门的输出端；
    第三反相器，其中，所述第三反相器的输入端电性连接所述三态与非门的输出端；
    第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
    其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端和所述三态与非门的第二输入端分别电性连接所述第一时钟信号，所述第一反相器的第二时钟控制端和所述三态与非门的第三输入端分别电性连接所述第二时钟信号；
    所述中段电路中的所述偶数级GOA驱动子单元包括：
    第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接上级所述GOA驱动子单元的输出端；
    第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
    第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
    第三反相器，其中，所述第三反相器的输入端电性连接所述第二或非门的输出端；
    第四反相器，包括第一输入端、第二输入端和输出端，所述第四反相器的第一输入端电性连接所述第三反相器的输出端；
    第五反相器，其中，所述第五反相器的输入端电性连接所述第四反相器的输出端，且所述第五反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
    其中，所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端和所述第四反相器的第二输入端分别电性连接所述第二时钟信号，所述第一反相器的第二时钟控制端电性连接所述第一时钟信号。
  18. 根据权利要求15所述的GOA驱动电路，其中，所述后段电路中的所述奇数级GOA驱动子单元和所述偶数级GOA驱动子单元分别包括：
    第一反相器，包括输入端、第一时钟控制端、第二时钟控制端和输出端，其中，所述输入端电性连接所述前段电路中的最后一个所述GOA驱动子单元的输出端；
    第二反相器，其中，所述第二反相器的输入端电性连接所述第一反相器的输出端；
    第一或非门和第二或非门，其中，所述第一或非门的第一输入端电性连接所述第二反相器的输出端，其第二输入端电性连接所述第二或非门的输出端，所述第一或非门的输出端电性连接所述第二或非门的第一输入端，所述第二或非门的第二输入端电性连接所述第二反相器的输入端；
    与非门，其中，所述与非门的第一输入端电性连接所述第一时钟信号或者所述第二时钟信号，其第二输入端电性连接所述第二或非门的输出端；
    第三反相器，其中，所述第三反相器的输入端电性连接所述与非门的输出端；
    第四反相器，其中，所述第四反相器的输入端电性连接所述第三反相器的输出端，且所述第四反相器的输出端作为本级的所述GOA驱动子单元的输出端，以输出对应的栅极驱动信号；
    其中，所述奇数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第一时钟信号，其第二时钟控制端电性连接所述第二时钟信号，且所述与非门的第一输入端电性连接所述第一时钟信号；
    所述偶数级GOA驱动子单元中的所述第一反相器的第一时钟控制端电性连接所述第二时钟信号，其第二时钟控制端电性连接所述第一时钟信号，且所述与非门的第一输入端电性连接所述第二时钟控制信号。
  19. 一种平面显示器，其中，包括如权利要求10-18任意一项所述的GOA驱动电路。
PCT/CN2015/071711 2014-12-30 2015-01-28 一种应用于平板显示器的goa驱动电路及平板显示器 WO2016106926A1 (zh)

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CN203858844U (zh) * 2014-04-24 2014-10-01 敦泰科技有限公司 驱动电路、显示装置和电子设备

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DE112015005105B4 (de) 2021-11-11
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