WO2015180214A1 - 阵列基板行驱动电路及液晶显示装置 - Google Patents

阵列基板行驱动电路及液晶显示装置 Download PDF

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Publication number
WO2015180214A1
WO2015180214A1 PCT/CN2014/079928 CN2014079928W WO2015180214A1 WO 2015180214 A1 WO2015180214 A1 WO 2015180214A1 CN 2014079928 W CN2014079928 W CN 2014079928W WO 2015180214 A1 WO2015180214 A1 WO 2015180214A1
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WIPO (PCT)
Prior art keywords
gate
input end
pull
thin film
film transistor
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PCT/CN2014/079928
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English (en)
French (fr)
Inventor
虞晓江
李长晔
赖梓杰
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深圳市华星光电技术有限公司
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Priority to US14/386,820 priority Critical patent/US9214124B1/en
Publication of WO2015180214A1 publication Critical patent/WO2015180214A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G09G2300/0478—Details of the physics of pixel operation related to liquid crystal pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display panel technologies, and in particular, to an array substrate row driving circuit and a liquid crystal display device.
  • the traditional narrow frame design technology generally uses multi-layer metal wiring or GOA (Gate driver On Array) Two technologies to achieve.
  • GOA Gate driver On Array
  • the GOA technology can use the existing process of the display panel to make the driving circuit for controlling the horizontal scanning line on the substrate around the panel display area, so as to replace the IC to complete the driving of the horizontal scanning line.
  • GOA technology can simplify the manufacturing process of display panels, reduce costs, and make display panels more suitable for making narrow-frame or borderless display products. In recent years, it has received extensive attention in the field of flat panel display.
  • TFT elements constituting a GOA circuit may exhibit threshold voltage drift due to stress-resistance stress effects, thereby affecting the stability of the output of the GOA circuit.
  • An object of the present invention is to provide an array substrate row driving circuit and a liquid crystal display device which can avoid threshold voltage drift of a TFT element in a GOA circuit, thereby improving stability of a GOA circuit output.
  • An array substrate row driving circuit comprising a plurality of stages of array substrate row driving units, wherein the nth row in the array substrate row driving circuit Level array substrate row drive unit, comprising:
  • n is a positive integer greater than 3;
  • n-3th stage signal input end is connected to the second output end of the n-3th stage array substrate row driving unit; the n-2th stage signal input end and the n-2th stage array substrate
  • the first output end of the row driving unit is connected; the n+2th stage signal input end is connected to the first output end of the n+2th array substrate row driving unit; the second output end and the n+3th
  • the n-3th stage signal input end of the array substrate driving unit is connected; the first output end is connected to the n-2th stage signal input end of the n+2th array substrate row driving unit, and
  • the n+th stage signal input end of the n-2 stage array substrate row driving unit is connected to provide a scan signal to the nth horizontal scanning line of the display area;
  • the nth stage array substrate row driving unit further includes:
  • a pull-up control unit includes a first thin film transistor, the first thin film transistor has a first gate, a first source, and a first drain, and the first gate is electrically connected to the nth- a 3-level signal input end, the first source is electrically connected to the n-2th stage signal input end, the first drain is electrically connected to the pull-down control unit, and the pull-down unit and the upper
  • the pull unit is commonly connected to the second output end; wherein a peak voltage of the signal of the n-3th stage signal input end is twice the peak voltage of the signal of the n-2th stage signal input end, and is used for Pulling the potential of the second output terminal;
  • the pull-up unit includes a capacitor and a second thin film transistor, the second thin film transistor has a second gate, a second source, and a second drain, and the capacitor includes a first plate and a second plate
  • the second gate is commonly connected to the second output end of the pull-up control unit and the first plate of the capacitor, and the second source and the high-frequency clock signal input end are electrically connected
  • Connecting, the second drain is electrically connected to the first output end, and is configured to charge the signal of the first output end to bring the second output end to a higher potential;
  • the pull-down control unit is respectively connected to the low-level input terminal, the pull-up control unit and the pull-up unit, and is configured to control the second output when the signal of the first output terminal is in a non-charging state The terminal and the first output are kept at a low potential;
  • the pull-down unit is respectively connected to the n+2th stage signal input end, the low level input end, the pull-down control unit, and is connected to the pull-up unit and the pull-up control unit
  • the second output terminal is configured to pull down a potential of the second output end.
  • the pull-down control unit comprises a first pull-down control sub-unit
  • the first pull-down control sub-unit includes a third thin film transistor, and the third thin film transistor has a third gate, a third source, and a third drain;
  • the third gate is connected to the first drain, and the third drain is connected to the low level input terminal;
  • the first pull-down control sub-unit further includes a fourth thin film transistor and a fifth thin film transistor, the fourth thin film transistor has a fourth gate, a fourth source, and a fourth drain, and the fifth thin film transistor has a fifth gate, a fifth source, and a fifth drain;
  • the fourth gate and the fifth gate are connected to the third source, the fourth source and the fifth source are connected to the second plate of the capacitor, and the first output Connected; the fourth drain is connected to the low level input, and the fifth drain is connected to the third gate.
  • the stage array substrate row driving unit further includes a first input end of the low frequency clock signal and a second input end of the low frequency clock signal;
  • the first pull-down control sub-unit further includes a sixth thin film transistor and a seventh thin film transistor, the sixth thin film transistor has a sixth gate, a sixth source, and a sixth drain, and the seventh thin film transistor has a seventh gate, a seventh source, and a seventh drain;
  • the sixth gate, the sixth source and the seventh source are connected to the first input end of the low frequency clock signal, and the seventh gate is connected to the second input end of the low frequency clock signal; A drain and the seventh drain are connected to the fourth gate.
  • the nth-level array substrate row driving unit further comprises a second pull-down control sub-unit
  • the second pull-down control sub-unit includes an eighth thin film transistor, and the eighth thin film transistor has an eighth gate, an eighth source, and an eighth drain;
  • the eighth gate is connected to the first drain, and the eighth drain is connected to the low level input terminal;
  • the second pull-down control sub-unit further includes a ninth thin film transistor having a ninth gate, a ninth source, and a ninth drain, and a tenth thin film transistor having a a ten gate, a tenth source, and a tenth drain;
  • the ninth gate and the tenth gate are connected to the eighth source, and the ninth source and the tenth source are both connected to the fourth source and the fifth source, and are connected a second plate to the capacitor and connected to the first output; the ninth drain is connected to the low level input, and the tenth drain is connected to the eighth gate .
  • the eleventh thin film transistor has an eleventh gate, an eleventh source a twelfth thin film transistor having a twelfth gate, a twelfth source, and a twelfth drain;
  • the eleventh gate, the eleventh source and the twelfth source are connected to the second input end of the low frequency clock signal, and the twelfth gate is connected to the first input end of the low frequency clock signal;
  • the eleventh drain and the twelfth drain are connected to a ninth gate.
  • the pull-down unit is a thirteenth thin film transistor, and the thirteenth thin film transistor has a thirteenth gate, a thirteenth source, and a thirteenth drain;
  • the thirteenth gate is connected to the n+2th stage signal input end, the thirteenth drain is connected to the low level input end, and the thirteenth source and the second gate are connected Extremely connected.
  • An array substrate row driving circuit comprising a plurality of stages of array substrate row driving units, wherein, for the array substrate driving circuit, the nth The stage array substrate row driving unit comprises an n-3th stage signal input end, an n-2th stage signal input end, an n+2th stage signal input end, a first output end, a second output end, and a low level input end And a high frequency clock signal input end, n is a positive integer greater than 3;
  • n-3th stage signal input end is connected to the second output end of the n-3th stage array substrate row driving unit; the n-2th stage signal input end and the n-2th stage array substrate
  • the first output end of the row driving unit is connected; the n+2th stage signal input end is connected to the first output end of the n+2th array substrate row driving unit; the second output end and the n+3th
  • the n-3th stage signal input end of the array substrate driving unit is connected; the first output end is connected to the n-2th stage signal input end of the n+2th array substrate row driving unit, and
  • the n+th stage signal input end of the n-2 stage array substrate row driving unit is connected to provide a scan signal to the nth horizontal scanning line of the display area;
  • the nth stage array substrate row driving unit further includes:
  • a pull-up control unit including a first thin film transistor, respectively connected to the n-2th stage signal input end, the n-3th stage signal input end, and the second output end, wherein the nth - the peak voltage of the signal of the -3 signal input terminal is twice the peak voltage of the signal of the n-2th stage signal input terminal for pulling up the potential of the second output terminal;
  • a pull-up unit respectively connected to the high-frequency clock signal input end and the first output end, and connected to the second output end together with the pull-up control unit, for the first output end
  • the signal is charged to bring the second output to a higher potential
  • a pull-down control unit respectively connected to the low-level input terminal, the pull-up control unit, and the pull-up unit, for controlling the second output terminal when the signal of the first output terminal is in a non-charging state
  • the first output terminal remains at a low potential
  • a pull-down unit respectively connected to the n+2th stage signal input end, the low level input end, the pull-down control unit, and connected to the pull-up unit and the pull-up control unit a second output for pulling down the potential of the second output.
  • the first thin film transistor has a first gate, a first source, and a first drain;
  • the first gate is electrically connected to the n-3th stage signal input end, and the first source is electrically connected to the n-2th stage signal input end, and the first drain is respectively associated with
  • the pull-down control unit is electrically connected, and is connected to the second output end in common with the pull-down unit and the pull-up unit.
  • the pull-up unit includes a capacitor and a second thin film transistor, and the second thin film transistor has a second gate, a second source, and a second drain, and the capacitor includes a plate and a second plate;
  • the second gate is electrically connected to the pull-up control unit and the first plate of the capacitor through a second output end, and the second source is electrically connected to the high-frequency clock signal input end
  • the second drain is electrically connected to the first output end.
  • the pull-down control unit includes a first pull-down control sub-unit
  • the first pull-down control sub-unit includes a third thin film transistor, and the third thin film transistor has a third gate, a third source, and a third drain;
  • the third gate is connected to the first drain, and the third drain is connected to the low level input terminal;
  • the first pull-down control sub-unit further includes a fourth thin film transistor and a fifth thin film transistor, the fourth thin film transistor has a fourth gate, a fourth source, and a fourth drain, and the fifth thin film transistor has a fifth gate, a fifth source, and a fifth drain;
  • the fourth gate and the fifth gate are connected to the third source, the fourth source and the fifth source are connected to the second plate of the capacitor, and the first output Connected; the fourth drain is connected to the low level input, and the fifth drain is connected to the third gate.
  • the stage array substrate row driving unit further includes a first input end of the low frequency clock signal and a second input end of the low frequency clock signal;
  • the first pull-down control sub-unit further includes a sixth thin film transistor and a seventh thin film transistor, the sixth thin film transistor has a sixth gate, a sixth source, and a sixth drain, and the seventh thin film transistor has a seventh gate, a seventh source, and a seventh drain;
  • the sixth gate, the sixth source and the seventh source are connected to the first input end of the low frequency clock signal, the seventh gate is connected to the second input end of the low frequency clock signal; the sixth drain And a seventh drain connected to the fourth gate.
  • the nth-level array substrate row driving unit further includes a second pull-down control sub-unit
  • the second pull-down control sub-unit includes an eighth thin film transistor, and the eighth thin film transistor has an eighth gate, an eighth source, and an eighth drain;
  • the eighth gate is connected to the first drain, and the eighth drain is connected to the low level input terminal;
  • the second pull-down control sub-unit further includes a ninth thin film transistor having a ninth gate, a ninth source, and a ninth drain, and a tenth thin film transistor having a a ten gate, a tenth source, and a tenth drain;
  • the ninth gate and the tenth gate are connected to the eighth source, and the ninth source and the tenth source are connected to the fourth source and the fifth source, and are connected And to the second output of the capacitor, and connected to the first output; the ninth drain is connected to the low level input, and the tenth drain is connected to the eighth gate.
  • the second pull-down control sub-unit further includes an eleventh thin film transistor and a twelfth thin film transistor, wherein the eleventh thin film transistor has an eleventh gate and an eleventh source And an eleventh drain; the twelfth thin film transistor has a twelfth gate, a twelfth source, and a twelfth drain;
  • the eleventh gate, the eleventh source and the twelfth source are connected to the second input end of the low frequency clock signal, and the twelfth gate is connected to the first input end of the low frequency clock signal;
  • the eleventh drain and the twelfth drain are connected to the ninth gate.
  • the pull-down unit is a thirteenth thin film transistor, and the thirteenth thin film transistor has a thirteenth gate, a thirteenth source, and a thirteenth drain;
  • the thirteenth gate is connected to the n+2th stage signal input end, the thirteenth drain is connected to the low level input end, and the thirteenth source and the second gate are connected Extremely connected.
  • a liquid crystal display device comprising an array substrate row driving circuit, and a display area connected to the array substrate row driving circuit, the array substrate row driving circuit comprising a multi-stage connected array substrate row driving unit;
  • the stage array substrate row driving unit comprises: an n-3th stage signal input end, an n-2th stage signal input end, an n+2th stage signal input end, a first output end, a second output end, and a low level input
  • n is a positive integer greater than 3;
  • n-3th stage signal input end is connected to the second output end of the n-3th stage array substrate row driving unit; the n-2th stage signal input end and the n-2th stage array substrate
  • the first output end of the row driving unit is connected; the n+2th stage signal input end is connected to the first output end of the n+2th array substrate row driving unit; the second output end and the n+3th
  • the n-3th stage signal input end of the array substrate driving unit is connected; the first output end is connected to the n-2th stage signal input end of the n+2th array substrate row driving unit, and
  • the n+th stage signal input end of the n-2 stage array substrate row driving unit is connected to provide a scan signal to the nth horizontal scanning line of the display area;
  • the nth stage array substrate row driving unit further includes:
  • a pull-up control unit including a first thin film transistor, respectively connected to the n-2th stage signal input end, the n-3th stage signal input end, and the second output end, wherein the nth - the peak voltage of the signal of the -3 signal input terminal is twice the peak voltage of the signal of the n-2th stage signal input terminal for pulling up the potential of the second output terminal;
  • a pull-up unit respectively connected to the high-frequency clock signal input end and the first output end, and connected to the second output end together with the pull-up control unit, for the first output end
  • the signal is charged to bring the second output to a higher potential
  • a pull-down control unit respectively connected to the low-level input terminal, the pull-up control unit, and the pull-up unit, for controlling the second output terminal when the signal of the first output terminal is in a non-charging state
  • the first output terminal remains at a low potential
  • a pull-down unit respectively connected to the n+2th stage signal input end, the low level input end, the pull-down control unit, and connected to the pull-up unit and the pull-up control unit a second output for pulling down the potential of the second output.
  • the display area has horizontal scanning lines, and one end of each of the horizontal scanning lines is connected to one of the array substrate row driving units, the horizontal scanning line and the array substrate row driving unit.
  • the first output is connected.
  • the present invention utilizes a pre-stage signal with a higher peak voltage to control the turn-on of the first thin film transistor responsible for signal transmission between the upper and lower stages of the GOA circuit, so that the signal between the upper and lower stages of the GOA circuit
  • the transfer is less affected by the threshold voltage drift of the TFT element than the existing GOA circuit, so that the output of the GOA circuit is less affected by the threshold voltage drift of the TFT element, and the stability of the output of the GOA circuit is improved.
  • FIG. 1 is a schematic structural view of an array substrate row driving circuit provided by the present invention
  • FIG. 2 is a schematic diagram showing driving timing of an array substrate row driving circuit provided by the present invention.
  • FIG. 3 is another schematic structural diagram of an array substrate row driving circuit provided by the present invention.
  • FIG. 4 is a schematic structural view of a liquid crystal display device provided by the present invention.
  • 5a to 5c are schematic diagrams showing the output comparison between the GOA circuit and an existing GOA circuit provided by the present invention.
  • FIG. 1 is a schematic diagram of a first embodiment of an array substrate row driving circuit provided by the present invention.
  • the array substrate row driving circuit of the embodiment includes a plurality of stages of array substrate row driving units, wherein the nth row in the array substrate row driving circuit
  • the stage array substrate row driving unit comprises an n-3th stage signal input end, an n-2th stage signal input end, an n+2th stage signal input end, a first output end, a second output end, and a low level input end
  • n is a positive integer greater than 3;
  • the first output end is configured to provide a scan signal to the nth horizontal scanning line of the display area;
  • the embodiment of the present invention is for the nth The stage array substrate row driving unit, the signal of the n-3th stage signal input end is Q(n-3), and the Q(n-3) is the second stage of the n-3th stage array substrate row driving unit a signal at the output end;
  • the signal of the input signal of the n-2th stage is G(n-2), and the G(n-2) is a signal of the first output end of the row driving unit of the n-2th stage substrate row;
  • the signal of the input signal of the n+2th stage is G(n+2), and the signal of G(n+2) is the signal of the first output end of the row driving unit of the n+2th array substrate;
  • the signal of one output is G(n), the signal of the second output is Q(n), the signal of the low level input is Vss, and the signal of the input end of the high frequency clock signal is CK(n).
  • the nth stage array substrate row driving unit further includes:
  • the pull-up control unit 104 includes a first thin film transistor respectively connected to the n-2th stage signal input end, the n-3th stage signal input end, and the second output end, wherein the The peak voltage of the signal of the n-3 stage signal input end is twice the peak voltage of the signal of the n-2th stage signal input end, and is used for pulling up the potential of the second output end;
  • the pull-up unit 101 is respectively connected to the high-frequency clock signal input end and the first output end, and is connected to the second output end together with the pull-up control unit 104, for the first The signal at the output is charged to bring the second output to a higher potential;
  • the pull-down control unit 103 is respectively connected to the low-level input terminal, the pull-up control unit 104, and the pull-up unit 101, and is configured to control the signal when the signal at the first output end is in a non-charging state.
  • the second output terminal and the first output terminal are kept at a low potential;
  • the pull-down unit 102 is respectively connected to the n+2th stage signal input end, the low level input end, the pull-down control unit 103, and is shared with the pull-up unit 104 and the pull-up control unit 104. Connected to the second output terminal for pulling down the potential of the second output terminal.
  • the n-3th stage signal input end and the n-2th stage signal input end are both for inputting a pulse activation signal
  • the n+2th stage signal input end and the 3rd The first output end of the row of array substrate driving units is connected, and the second output end is connected to the n-3th stage signal input end of the array substrate driving unit of the fourth stage; the first output end and the third output end
  • the n-2th stage signal input end of the array substrate driving unit is connected to provide a scanning signal to the first level horizontal scanning line of the display area; for the same reason, for the second
  • a similar process can be employed for the stage array substrate row drive unit and the third stage array substrate row drive unit, and will not be described in detail herein.
  • the n+2th stage signal input terminal is used to input a pulse activation signal, and the second output end can be set to be left floating, similarly for the second to last and the last 3
  • a similar processing can be employed for the stage array substrate row driving unit, which will not be described in detail herein.
  • the internal connection structures of the pull-up control unit 104, the pull-up unit 101, the pull-down control unit 103, and the pull-down unit 102 are separately analyzed in the following:
  • the pull-up control unit 104 is a first thin film transistor T11, and the first thin film transistor T11 has a first gate, a first source, and a first drain;
  • the first gate is electrically connected to the n-3th stage signal input end, and the first source is electrically connected to the n-2th stage signal input end, and the first drain is respectively associated with
  • the pull-down control unit 103 is electrically connected, and is connected to the second output end in common with the pull-down unit 102 and the pull-up unit 101.
  • the pull-up unit 101 includes a capacitor Cb and a second thin film transistor T21, the second thin film transistor T21 has a second gate, a second source, and a second drain, and the capacitor Cb includes a first plate and Second plate
  • the second gate is electrically connected to the first plate of the pull-up control unit 104 and the capacitor Cb through the second output end, the second source is electrically connected to the high-frequency clock signal input end, and the second The drain is electrically connected to the first output end.
  • the pull-down control unit 103 includes a first pull-down control sub-unit 1031;
  • the first pull-down control sub-unit 1031 includes a third thin film transistor T52, and the third thin film transistor T52 Having a third gate, a third source, and a third drain;
  • the third gate is connected to the first drain, and the third drain is connected to the low level input terminal;
  • the first pull-down control sub-unit 1031 further includes a fourth thin film transistor T32 and a fifth thin film transistor T42, wherein the fourth thin film transistor T32 has a fourth gate, a fourth source, and a fourth drain, The fifth thin film transistor T42 has a fifth gate, a fifth source, and a fifth drain;
  • the fourth gate and the fifth gate are connected to the third source, the fourth source and the fifth source are connected to the second plate of the capacitor Cb, and the first output
  • the fourth drain is connected to the low level input, and the fifth drain is connected to the third gate.
  • the stage array substrate row driving unit further includes a first input end of the low frequency clock signal and a second input end of the low frequency clock signal;
  • the signal of the first input end of the low frequency clock signal is LC1, and the signal of the second input end of the low frequency clock signal is LC2;
  • the first pull-down control sub-unit 1031 further includes a sixth thin film transistor T53 and a seventh thin film transistor T54, wherein the sixth thin film transistor T53 has a sixth gate, a sixth source, and a sixth drain, The seven thin film transistor T54 has a seventh gate, a seventh source, and a seventh drain;
  • the sixth gate, the sixth source and the seventh source are connected to the first input end of the low frequency clock signal, and the seventh gate is connected to the second input end of the low frequency clock signal; A drain and a seventh drain are connected to the fourth gate.
  • the nth stage array substrate row driving unit further includes a second pulldown control subunit 1032;
  • the second pull-down control sub-unit 1032 includes an eighth thin film transistor T62, and the eighth thin film transistor T62 has an eighth gate, an eighth source, and an eighth drain;
  • the eighth gate is connected to the first drain, and the eighth drain is connected to the low level input terminal;
  • the second pull-down control sub-unit 1032 further includes a ninth thin film transistor T33 and a tenth thin film transistor T43, the ninth thin film transistor T33 having a ninth gate, a ninth source, and a ninth drain, the tenth
  • the thin film transistor T43 has a tenth gate, a tenth source, and a tenth drain;
  • the ninth gate and the tenth gate are connected to the eighth source, and the ninth source and the tenth source are connected to the fourth source and the fifth source, and are connected a second plate to the capacitor Cb and connected to the first output; the ninth drain is connected to the low level input, and the tenth drain is connected to the eighth gate.
  • the second pull-down control sub-unit 1032 further includes an eleventh thin film transistor T63 and a twelfth thin film transistor T64, wherein the eleventh thin film transistor T63 has an eleventh gate, an eleventh source, and an eleventh drain
  • the twelfth thin film transistor T64 has a twelfth gate, a twelfth source, and a twelfth drain;
  • the eleventh gate, the eleventh source and the twelfth source are connected to the second input end of the low frequency clock signal, and the twelfth gate is connected to the first input end of the low frequency clock signal;
  • the eleventh drain and the twelfth drain are connected to the ninth gate.
  • the pull-down unit 102 is a thirteenth thin film transistor T41, and the thirteenth thin film transistor T41 has a thirteenth gate, a thirteenth source, and a thirteenth drain;
  • the thirteenth gate is connected to the n+2th stage signal input end, the thirteenth drain is connected to the low level input end, and the thirteenth source and the second gate are connected Extremely connected.
  • each thin film transistor respectively corresponds to the on or off of the current path between the source and the drain thereof.
  • the first thin film transistor T11, the second thin film transistor T21, the third thin film transistor T52, the fourth thin film transistor T32, the fifth thin film transistor T42, and the The sixth thin film transistor T53, the seventh thin film transistor T54, the eighth thin film transistor T62, the ninth thin film transistor T33, the tenth thin film transistor T43, the eleventh thin film transistor T63, the The twelfth thin film transistor T64 and the thirteenth thin film transistor T41 are both N-type thin film transistors.
  • each of the thin film transistors may be a P-type thin film transistor in other embodiments, and the type may be performed according to a specific scene. It is to be understood that the examples herein are not intended to limit the invention.
  • FIG. 1 is an example of a single-stage architecture of the GOA circuit of the present invention, and the single-level GOA circuit is briefly introduced:
  • the single-stage GOA circuit includes a second thin film transistor T21 (corresponding to the pull-up unit 101 shown in FIG. 1) for controlling charging of the n-th horizontal scanning line of the display region, wherein the first output terminal (ie, the G(n) signal The output end is connected to the nth horizontal scanning line, and the second source and the second drain of the second thin film transistor T21 are respectively connected to the first output end and the high frequency clock signal input end (ie, the CK (n) signal input end).
  • the second gate of the second thin film transistor T21 is connected to the second output terminal, and the potential of Q(n) directly affects CK(n) charging G(n); the GOA circuit is further included in G ( n)
  • the thirteenth thin film transistor T41 that discharges Q(n) at the end of charging (corresponding to the pull-down unit 104 of Fig. 1).
  • the pull-down control unit 103 shown in FIG. 1 is a pull-down circuit region of the GOA, and the low potentials of G(n) and Q(n) can be maintained during the non-charging period.
  • the P point and the K point in the pull-down control unit 103 are alternately charged by the first input end of the low frequency clock signal (ie, the LC1 signal input end) and the second input end of the low frequency clock signal (ie, the LC2 signal input end), thereby alternating Controlling the opening of the fourth thin film transistor T32 and the fifth thin film transistor T42, or the ninth thin film transistor T33 and the tenth thin film transistor T43, to alternately maintain the low potentials of G(n) and Q(n) during the non-charging period, thereby Avoid thin film transistors from being affected by gate voltage stress for a long time.
  • the third thin film transistor T52 is connected to the P point and the low level input terminal (ie, the Vss signal input terminal), the eighth thin film transistor T62 is connected to the K point and the low level input terminal, and the third thin film transistor T52 and the first
  • the eight thin film transistor T62 can be turned on when Q(n) is at a high potential and the P point and K point potentials are pulled low to turn off the fourth thin film transistor T32, the fifth thin film transistor T42, the ninth thin film transistor T33, and the tenth thin film transistor T43. It does not affect G(n) charging.
  • the first thin film transistor T11 (corresponding to the pull-up control unit 104 of FIG. 1) can control the signal outputted by the pre-stage GOA circuit to the GOA circuit of the current stage, so that the GOA signal can be transmitted step by step; Q(n) and G(n) A capacitor Cb connected with a bootstrap function can increase the Q(n) potential by the coupling effect of Cb when the G(n) potential is raised, thereby obtaining a higher Q(n) potential and a smaller GOA charging signal. .
  • each switching transistor uses an N-type thin film transistor as an example to analyze the working principle of the single-stage GOA circuit as shown in FIG.
  • FIG. 2 is a schematic diagram of driving timing of the array substrate row driving circuit; the driving timing is divided into three stages, wherein t1 ⁇ t4 are G(n) preparation time before charging, t4 ⁇ t5 For the charging time of G(n), G(n) is discharged after t5.
  • CK(n-3) is high and Q(n-3) is bootstrapped to a high potential, wherein the high potential of the Q(n-3) bootstrap is about twice G(n-2) High potential.
  • G(n-2) is low, and Q(n) is not charged, then Q(n) is low.
  • CK(n-3) is the high frequency clock signal of the row drive unit of the n-3th array substrate row, and when it is high potential, correspondingly Q(n-3) Bootstrap to high potential.
  • CK(n-2) is a high frequency clock signal of the row driving unit of the n-2th stage array substrate.
  • the third thin film transistor T52 and the eighth thin film transistor T62 are turned on, thereby pulling down the P and K point potentials to turn off the fourth thin film transistor T32, the fifth thin film transistor T42, and the ninth.
  • Thin film transistor T33 and tenth thin film transistor T43 so as not to affect G(n) Subsequent charging.
  • the potential of CK(n) starts to rise, the second thin film transistor T21 is turned on, Q(n) boots up to a higher potential and controls the second thin film transistor T21 to charge G(n), and the G(n) potential rises. .
  • the CK(n) potential begins to decrease, and the Q(n) potential is not immediately pulled low.
  • the second thin film transistor T21 remains conductive for a short time after t5, pulling the G(n) potential low.
  • the G(n+2) potential is raised, and the thirteenth thin film transistor T41 is turned on to ensure that Q(n) is pulled to a low potential; the third thin film transistor T52 and the eighth thin film transistor T62 are at Q(n)
  • the switch combination of the fourth thin film transistor T32 and the fifth thin film transistor T42 and the switch combination of the ninth thin film transistor T33 and the tenth thin film transistor T43 can be normally alternately opened to maintain G(n) and Q(n). ) Low potential during non-charging periods.
  • the potentials of the P point and the K point can be affected by the low frequency signals LC1 and LC2.
  • the sixth thin film transistor T53 is turned on and the seventh thin film transistor T54 is turned off, the P point can be high, and the P point is high, the fourth thin film transistor can be turned on.
  • T32 and fifth thin film transistor T42 assuming that LC2 is at a high potential and LC1 is at a low potential, the eleventh thin film transistor T63 is turned on and the twelfth thin film transistor T64 is turned off, the K point can be high, and the K point is high.
  • the ninth thin film transistor T33 and the tenth thin film transistor T43 which function as pull-downs can be turned on.
  • the purpose of this design is to prevent the fourth thin film transistor T32 and the fifth thin film transistor T42, or the ninth thin film transistor T33 and the tenth thin film transistor T43 from being affected by a single gate stress for a long time, thereby prolonging the life of the device.
  • the first thin film transistor T11 responsible for signal transmission between the upper and lower stages in the GOA circuit of the present invention has a first gate, a first drain, and a first source connected to the n-3.
  • Q(n) is to be charged from the first thin film transistor T11, the voltage difference Vgs between the first gate and the first source must be not less than its threshold voltage Vth, that is, Vgs- Vth ⁇ 0.
  • the potential of the Q(n-3) signal of the first gate is about twice that of the G(n-2) high potential VG(n-2) after the bootstrap, that is, 2 VG(n-2) . Therefore, Q(n) can be charged to the VG(n-2) by the first thin film transistor T11, and the potential at which Q(n) can be charged before the bootstrap is less susceptible to the drift of the threshold voltage Vth of the first thin film transistor T11.
  • the peak potential of the gate of the first thin film transistor T11 in the pull control unit 104 is approximately equal to the potential VG(n-2) of G(n-2), so Q(n) can be
  • the potential at which the first thin film transistor T11 is charged is approximately equal to VG(n-2) - Vth, and the potential at which Q(n) can be charged before the bootstrap is susceptible to the drift of the threshold voltage Vth of the first thin film transistor T11.
  • the GOA circuit of the present invention controls the turn-on of the first thin film transistor T11 responsible for signal transmission between the upper and lower stages of the GOA circuit with a Q(n-3) signal having a higher peak voltage, so that the GOA circuit is on the GOA circuit.
  • the signal transmission between the lower stages is less affected by the threshold voltage drift of the TFT element than the existing GOA circuit, so that the output of the GOA circuit is less affected by the threshold voltage drift of the TFT element, and the stability of the output of the GOA circuit is improved.
  • the embodiment of the present invention further provides a liquid crystal display device including an array substrate row driving circuit.
  • the meaning of the noun is the same as that in the above-mentioned array substrate row driving circuit, and the specific implementation details can be referred to the description in the embodiment of the array substrate row driving circuit.
  • Embodiments of the present invention provide a liquid crystal display device including an array substrate row driving circuit, and a display region connected to the array substrate row driving circuit, the array substrate row driving circuit, including a multi-level connected array substrate row driving unit ;
  • the stage array substrate row driving unit comprises an n-3th stage signal input end, an n-2th stage signal input end, an n+2th stage signal input end, a first output end, a second output end, and a low level input end And a high frequency clock signal input end, n is a positive integer greater than 3;
  • n-3th stage signal input end is connected to the second output end of the n-3th stage array substrate row driving unit; the n-2th stage signal input end and the n-2th stage array substrate
  • the first output end of the row driving unit is connected; the n+2th stage signal input end is connected to the first output end of the n+2th array substrate row driving unit; the second output end and the n+3th
  • the n-3th stage signal input end of the array substrate driving unit is connected; the first output end is connected to the n-2th stage signal input end of the n+2th array substrate row driving unit, and
  • the n+th stage signal input end of the n-2 stage array substrate row driving unit is connected to provide a scan signal to the nth horizontal scanning line of the display area;
  • the embodiment of the present invention is for the nth The stage array substrate row driving unit, the signal of the n-3th stage signal input end is Q(n-3), and the Q(n-3) is the second stage of the n-3th stage array substrate row driving unit a signal at the output end;
  • the signal of the input signal of the n-2th stage is G(n-2), and the G(n-2) is a signal of the first output end of the row driving unit of the n-2th stage substrate row;
  • the signal of the input signal of the n+2th stage is G(n+2), and the signal of G(n+2) is the signal of the first output end of the row driving unit of the n+2th array substrate;
  • the signal of one output is G(n), the signal of the second output is Q(n), the signal of the low level input is Vss, and the signal of the input end of the high frequency clock signal is CK(n).
  • the nth stage array substrate row driving unit further includes:
  • the pull-up control unit 104 includes a first thin film transistor respectively connected to the n-2th stage signal input end, the n-3th stage signal input end, and the second output end, wherein the The peak voltage of the signal of the n-3 stage signal input end is twice the peak voltage of the signal of the n-2th stage signal input end, and is used for pulling up the potential of the second output end;
  • the pull-up unit 101 is respectively connected to the high-frequency clock signal input end and the first output end, and is connected to the second output end together with the pull-up control unit 104, for the first The signal at the output is charged to bring the second output to a higher potential;
  • the pull-down control unit 103 is respectively connected to the low-level input terminal, the pull-up control unit 104, and the pull-up unit 101, and is configured to control the signal when the signal at the first output end is in a non-charging state.
  • the second output terminal and the first output terminal are kept at a low potential;
  • the pull-down unit 102 is respectively connected to the n+2th stage signal input end, the low level input end, the pull-down control unit 103, and is shared with the pull-up unit 104 and the pull-up control unit 104. Connected to the second output terminal for pulling down the potential of the second output terminal.
  • FIG. 3 is a schematic diagram of a multi-level connection structure of a GOA circuit according to the present invention.
  • the display area has horizontal scanning lines, and one end of each horizontal scanning line is connected to one of the array substrates.
  • a row driving unit wherein the horizontal scan line is connected to the first output end of the array substrate row driving unit.
  • the GOA circuit can be horizontally scanned from the left and right sides respectively. Line is charged and discharged to achieve a uniform charging effect.
  • the low-frequency clock signals LC1 and LC2, the DC low-voltage Vss, and the metal lines of the four high-frequency clock signals of CK1 to CK4 are placed on the periphery of each level of the GOA circuit.
  • the nth stage GOA circuit accepts one CK signal of LC1, LC2, Vss, CK1 ⁇ CK4, and G(n-2) generated by the n-2th GOA circuit, respectively.
  • the signal, the Q(n-3) signal generated by the n-3th GOA circuit, the G(n+2) signal generated by the n+2th GOA circuit, and the G(n) signal and Q(n) Signal can ensure that the GOA signal can be transmitted step by step, and the GOA circuits of each level can charge and discharge the horizontal scanning lines of the display area from the left and right sides step by step.
  • the pull-up control unit 104 is a first thin film transistor T11, and the first thin film transistor T11 has a first gate, a first source, and a first drain;
  • the first gate is electrically connected to the n-3th stage signal input end, and the first source is electrically connected to the n-2th stage signal input end, and the first drain is respectively associated with
  • the pull-down control unit 103 is electrically connected, and is connected to the second output end in common with the pull-down unit 102 and the pull-up unit 101.
  • the pull-up unit 101 includes a capacitor Cb and a second thin film transistor T21, the second thin film transistor T21 has a second gate, a second source, and a second drain, and the capacitor Cb includes a first plate and Second plate
  • the second gate is electrically connected to the first plate of the pull-up control unit 104 and the capacitor Cb through the second output end, the second source is electrically connected to the high-frequency clock signal input end, and the second The drain is electrically connected to the first output end.
  • the pull-down control unit 103 includes a first pull-down control sub-unit 1031;
  • the first pull-down control sub-unit 1031 includes a third thin film transistor T52, and the third thin film transistor T52 Having a third gate, a third source, and a third drain;
  • the third gate is connected to the first drain, and the third drain is connected to the low level input terminal;
  • the first pull-down control sub-unit 1031 further includes a fourth thin film transistor T32 and a fifth thin film transistor T42, wherein the fourth thin film transistor T32 has a fourth gate, a fourth source, and a fourth drain, The fifth thin film transistor T42 has a fifth gate, a fifth source, and a fifth drain;
  • the fourth gate and the fifth gate are connected to the third source, the fourth source and the fifth source are connected to the second plate of the capacitor Cb, and the first output
  • the fourth drain is connected to the low level input, and the fifth drain is connected to the third gate.
  • the stage array substrate row driving unit further includes a first input end of the low frequency clock signal and a second input end of the low frequency clock signal;
  • the signal of the first input end of the low frequency clock signal is LC1, and the signal of the second input end of the low frequency clock signal is LC2;
  • the first pull-down control sub-unit 1031 further includes a sixth thin film transistor T53 and a seventh thin film transistor T54, wherein the sixth thin film transistor T53 has a sixth gate, a sixth source, and a sixth drain, The seven thin film transistor T54 has a seventh gate, a seventh source, and a seventh drain;
  • the sixth gate, the sixth source and the seventh source are connected to the first input end of the low frequency clock signal, and the seventh gate is connected to the second input end of the low frequency clock signal; A drain and a seventh drain are connected to the fourth gate.
  • the nth stage array substrate row driving unit further includes a second pulldown control subunit 1032;
  • the second pull-down control sub-unit 1032 includes an eighth thin film transistor T62, and the eighth thin film transistor T62 has an eighth gate, an eighth source, and an eighth drain;
  • the eighth gate is connected to the first drain, and the eighth drain is connected to the low level input terminal;
  • the second pull-down control sub-unit 1032 further includes a ninth thin film transistor T33 and a tenth thin film transistor T43, the ninth thin film transistor T33 having a ninth gate, a ninth source, and a ninth drain, the tenth
  • the thin film transistor T43 has a tenth gate, a tenth source, and a tenth drain;
  • the ninth gate and the tenth gate are connected to the eighth source, and the ninth source and the tenth source are connected to the fourth source and the fifth source, and are connected a second plate to the capacitor Cb and connected to the first output; the ninth drain is connected to the low level input, and the tenth drain is connected to the eighth gate.
  • the second pull-down control sub-unit 1032 further includes an eleventh thin film transistor T63 and a twelfth thin film transistor T64, wherein the eleventh thin film transistor T63 has an eleventh gate, an eleventh source, and an eleventh drain
  • the twelfth thin film transistor T64 has a twelfth gate, a twelfth source, and a twelfth drain;
  • the eleventh gate, the eleventh source and the twelfth source are connected to the second input end of the low frequency clock signal, and the twelfth gate is connected to the first input end of the low frequency clock signal;
  • the eleventh drain and the twelfth drain are connected to the ninth gate.
  • the pull-down unit 102 is a thirteenth thin film transistor T41, and the thirteenth thin film transistor T41 has a thirteenth gate, a thirteenth source, and a thirteenth drain;
  • the thirteenth gate is connected to the n+2th stage signal input end, the thirteenth drain is connected to the low level input end, and the thirteenth source and the second gate are connected Extremely connected.
  • t1 ⁇ t4 is the preparation time before G(n) charging
  • t4 ⁇ t5 is the charging time of G(n)
  • G(n) is discharged after t5;
  • CK(n-3) is high and Q(n-3) is bootstrapped to a high potential, wherein the high potential of the Q(n-3) bootstrap is about twice G(n-2) High potential.
  • G(n-2) is low, and Q(n) is not charged, then Q(n) is low.
  • the potential of CK(n-2) rises, G(n-2) Also raised to a high potential, Q(n-3) still maintains a high bootstrap potential (still higher than the high potential of G(n-2)), the first thin film transistor T11 is turned on and charges Q(n), then Q(n) potential is raised. Further, after the Q(n) potential is raised, the third thin film transistor T52 and the eighth thin film transistor T62 are turned on, thereby pulling down the P and K point potentials to turn off the fourth thin film transistor T32, the fifth thin film transistor T42, and the ninth. Thin film transistor T33 and tenth thin film transistor T43 so as not to affect G(n) Subsequent charging.
  • the potential of CK(n) starts to rise, the second thin film transistor T21 is turned on, Q(n) boots up to a higher potential and controls the second thin film transistor T21 to charge G(n), and the G(n) potential rises. .
  • the CK(n) potential begins to decrease, and the Q(n) potential is not immediately pulled low.
  • the second thin film transistor T21 remains conductive for a short time after t5, pulling the G(n) potential low.
  • the G(n+2) potential is raised, and the thirteenth thin film transistor T41 is turned on to ensure that Q(n) is pulled to a low potential; the third thin film transistor T52 and the eighth thin film transistor T62 are at Q(n)
  • the switch combination of the fourth thin film transistor T32 and the fifth thin film transistor T42 and the switch combination of the ninth thin film transistor T33 and the tenth thin film transistor T43 can be normally alternately opened to maintain G(n) and Q(n). ) Low potential during non-charging periods.
  • the GOA circuit controls the connection of the first thin film transistor T11 responsible for signal transmission between the upper and lower stages of the GOA circuit by using a Q(n-3) signal having a higher peak voltage. That is, the output of the GOA circuit of the upper stage can be used as the input of the lower stage driving circuit, and the input of the GOA circuit of the upper stage is the output of the GOA circuit of the upper stage of the previous row, so that the signal transmission between the upper and lower stages of the GOA circuit is subject to the threshold of the TFT element.
  • the effect of voltage drift is smaller than that of the existing GOA circuit, so that the output of the GOA circuit is less affected by the threshold voltage drift of the TFT element, and the stability of the output of the GOA circuit is improved.
  • FIG. 4 is a schematic structural diagram of a liquid crystal display device provided by the present invention.
  • x+c above the display substrate ie, display area 403
  • the board provides drive and control signals for the display substrate.
  • the area of 402 is the display device casing, and the GOA circuit is formed on the left side 401 area and the right side 404 area of the display substrate, and the horizontal scanning line of the display area 403 can be driven from the left and right directions.
  • GOA circuit accepts x+c
  • the input signal of the board and the control signal of the horizontal scanning line are generated step by step, and the pixel in the display area 403 can be controlled to be turned on line by line.
  • the GOA circuit is compared with an existing GOA circuit as follows:
  • FIG. 5a to FIG. 5c are schematic diagrams showing the output comparison between the GOA circuit and the prior art GOA circuit provided by the present invention; for example, a conventional GOA circuit having a gate of the first thin film transistor T11 in the pull-up control unit 104
  • the peak potential of the pole is approximately equal to the potential VG(n-2) of G(n-2)
  • the potential at which Q(n) can be charged by the first thin film transistor T11 is approximately equal to VG(n-2)-Vth; wherein, FIG.
  • FIG. 5a is a drift of the threshold voltage of the TFT in the circuit of the GOA circuit of the present invention and the existing GOA circuit Alignment before and after, where the dotted line is the indication before the BTS, the solid line is the indication after the BTS, which can be found in Figure 5a, in the BTS (bias) Temperature After stress, bias temperature stress, the threshold voltage Vth of the TFT shifts to the right.
  • the electrical parameters of the TFTs before and after the BTS are collected and simulated. Referring to FIG. 5b and FIG. 5c, it can be found from FIG. 5b that the output of the existing GOA circuit after its TFT threshold voltage drift is Q(n) and G(n). ) The variation is large. It can be seen from Fig. 5c that the GOA circuit of the present invention has a small change in its outputs Q(n) and G(n) after its TFT threshold voltage drift.
  • the GOA circuit of the present invention controls the turn-on of the first thin film transistor T11 responsible for signal transmission between the upper and lower stages of the GOA circuit with a Q(n-3) signal having a higher peak voltage, so that the GOA circuit is on the GOA circuit.
  • the signal transmission between the lower stages is less affected by the threshold voltage drift of the TFT element than the existing GOA circuit, so that the output of the GOA circuit is less affected by the threshold voltage drift of the TFT element, and the stability of the output of the GOA circuit is improved.
  • the GOA circuit can be prepared on the substrate of the display panel by using the original process of the flat panel display panel, can replace the external IC to complete the driving of the horizontal scanning lines of each level, simplify the manufacturing process of the display panel, and reduce the cost, and is particularly suitable for the production.

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Abstract

提供了一种阵列基板行驱动电路，包括多级连接的阵列基板行驱动单元，其中，第n级阵列基板行驱动单元包括：第n-3级信号输入端、第n-2级信号输入端及上拉控制单元(104)，上拉控制单元(104)为第一薄膜晶体管(T11)，分别与第n-2级信号输入端和第n-3级信号输入端连接，第n-3级信号输入端的信号的峰值电压为第n-2级信号输入端的信号的峰值电压的两倍，避免阵列基板行驱动电路中TFT元件阈值电压漂移，提高输出的稳定性。

Description

阵列基板行驱动电路及液晶显示装置 技术领域
本发明涉及显示面板技术领域，特别涉及一种阵列基板行驱动电路及液晶显示装置。
 背景技术
传统的显示面板一般采用窄边框设计的技术方案。
传统的窄边框设计的技术方案一般采用多层金属走线或GOA（Gate driver On array）二种技术来实现。其中，多层金属走线的技术方案并不能显著地实现窄边框，相反，其会增加面板短路的几率，使得良率下降以及成本上升。而GOA技术可以使用显示面板的现有制程，将控制水平扫描线的驱动电路制作在面板显示区域周围的基板上，使之替代IC来完成水平扫描线的驱动。GOA技术能简化显示面板的制作工序，降低成本，使显示面板更适合制作窄边框或无边框的显示产品，近年来在平板显示领域受到广泛关注。
在实践中，发明人发现目前大部分的GOA电路也具有一定局限性：比如，组成GOA电路的TFT元件会由于应力阻抗stress效应而出现阈值电压漂移，从而使GOA电路输出的稳定性受到影响。
因此，需解决现有技术GOA电路中，存在的 TFT元件阈值电压漂移，影响GOA电路输出的稳定性的技术问题。
 技术问题
本发明的目的在于提供一种阵列基板行驱动电路及液晶显示装置，其能避免GOA电路中TFT元件阈值电压漂移，从而提高GOA电路输出的稳定性。
技术解决方案
一种阵列基板行驱动电路，包括多级连接的阵列基板行驱动单元，其中对于所述阵列基板行驱动电路中的第n 级阵列基板行驱动单元，包括：
第n-3级信号输入端、第n-2级信号输入端、第n+2级信号输入端、第一输出端、第二输出端、低电平输入端以及高频时钟信号输入端，n为大于3的正整数；
其中，所述第n-3级信号输入端与第n-3级的阵列基板行驱动单元的第二输出端相连；所述第n-2级信号输入端与第n-2级的阵列基板行驱动单元的第一输出端相连；所述第n+2级信号输入端与第n+2级的阵列基板行驱动单元的第一输出端相连；所述第二输出端与第n+3级的阵列基板行驱动单元的第n-3级信号输入端相连；所述第一输出端与第n+2级的阵列基板行驱动单元的第n-2级信号输入端相连，且与第n-2级的阵列基板行驱动单元的第n+2级信号输入端相连，用于向显示区域的第n级水平扫描线提供扫描信号；
所述第n 级阵列基板行驱动单元还包括：
一上拉控制单元，包括一第一薄膜晶体管，所述第一薄膜晶体管具有第一栅极、第一源极及第一漏极，所述第一栅极电性连接至所述第n-3级信号输入端，所述第一源极电性连接至所述第n-2级信号输入端，所述第一漏极与一下拉控制单元电性连接，并与一下拉单元及一上拉单元共同连接于所述第二输出端；其中，所述第n-3级信号输入端的信号的峰值电压为所述第n-2级信号输入端的信号的峰值电压的两倍，用于上拉所述第二输出端的电位；
所述上拉单元，包括一电容和第二薄膜晶体管，所述第二薄膜晶体管具有第二栅极、第二源极及第二漏极，所述电容包括第一极板和第二极板；所述第二栅极与所述上拉控制单元和所述电容的第一极板共同连接于所述第二输出端，所述第二源极与所述高频时钟信号输入端电性连接，所述第二漏极与第一输出端电性连接，用于对所述第一输出端的信号进行充电，以使所述第二输出端达到更高的电位；
所述下拉控制单元，分别与低电平输入端、所述上拉控制单元及所述上拉单元连接，用于在所述第一输出端的信号处于非充电状态时，控制所述第二输出端和所述第一输出端保持低电位；
所述下拉单元，分别与所述第n+2级信号输入端、所述低电平输入端、所述下拉控制单元连接，并与所述上拉单元及所述上拉控制单元共同连接于所述第二输出端，用于下拉所述第二输出端的电位。
在上述阵列基板行驱动电路中，其中所述下拉控制单元包括第一下拉控制子单元；
所述第一下拉控制子单元包括第三薄膜晶体管，所述第三薄膜晶体管具有第三栅极、第三源极及第三漏极；
所述第三栅极与所述第一漏极连接，第三漏极与所述低电平输入端连接；
所述第一下拉控制子单元还包括第四薄膜晶体管和第五薄膜晶体管，所述第四薄膜晶体管具有第四栅极、第四源极及第四漏极，所述第五薄膜晶体管具有第五栅极、第五源极及第五漏极；
所述第四栅极与所述第五栅极连接至所述第三源极，所述第四源极与第五源极连接至所述电容的第二极板，且与第一输出端连接；所述第四漏极与所述低电平输入端连接，所述第五漏极与第三栅极连接。
在上述阵列基板行驱动电路中，其中所述第n 级阵列基板行驱动单元还包括低频时钟信号第一输入端和低频时钟信号第二输入端；
所述第一下拉控制子单元还包括第六薄膜晶体管和第七薄膜晶体管，所述第六薄膜晶体管具有第六栅极、第六源极及第六漏极，所述第七薄膜晶体管具有第七栅极、第七源极及第七漏极；
所述第六栅极、第六源极与第七源极连接至所述低频时钟信号第一输入端，所述第七栅极与所述低频时钟信号第二输入端连接；所述第六漏极与所述第七漏极连接至所述第四栅极。
在上述阵列基板行驱动电路中，其中所述第n 级阵列基板行驱动单元还包括第二下拉控制子单元；
所述第二下拉控制子单元包括第八薄膜晶体管，所述第八薄膜晶体管具有第八栅极、第八源极及第八漏极；
所述第八栅极与所述第一漏极连接，所述第八漏极与所述低电平输入端连接；
所述第二下拉控制子单元还包括第九薄膜晶体管和第十薄膜晶体管，所述第九薄膜晶体管具有第九栅极、第九源极及第九漏极，所述第十薄膜晶体管具有第十栅极、第十源极及第十漏极；
所述第九栅极与所述第十栅极连接至所述第八源极，所述第九源极与第十源极均与所述第四源极和第五源极连接，并连接至所述电容的第二极板，且与所述第一输出端连接；所述第九漏极与所述低电平输入端连接，所述第十漏极与所述第八栅极连接。
在上述阵列基板行驱动电路中，其中所述第二下拉控制子单元还包括第十一薄膜晶体管和第十二薄膜晶体管，所述第十一薄膜晶体管具有第十一栅极、第十一源极及第十一漏极；所述第十二薄膜晶体管具有第十二栅极、第十二源极及第十二漏极；
所述第十一栅极、第十一源极与第十二源极连接至所述低频时钟信号第二输入端，所述第十二栅极与所述低频时钟信号第一输入端连接；所述第十一漏极与所述第十二漏极连接至第九栅极。
在上述阵列基板行驱动电路中，所述下拉单元为一第十三薄膜晶体管，所述第十三薄膜晶体管具有第十三栅极、第十三源极及第十三漏极；
所述第十三栅极与所述第n+2级信号输入端连接，所述第十三漏极与所述低电平输入端连接，所述第十三源极与所述第二栅极连接。
一种阵列基板行驱动电路，包括多级连接的阵列基板行驱动单元，其中，对于所述阵列基板行驱动电路中的第n 级阵列基板行驱动单元，包括第n-3级信号输入端、第n-2级信号输入端、第n+2级信号输入端、第一输出端、第二输出端、低电平输入端以及高频时钟信号输入端，n为大于3的正整数；
其中，所述第n-3级信号输入端与第n-3级的阵列基板行驱动单元的第二输出端相连；所述第n-2级信号输入端与第n-2级的阵列基板行驱动单元的第一输出端相连；所述第n+2级信号输入端与第n+2级的阵列基板行驱动单元的第一输出端相连；所述第二输出端与第n+3级的阵列基板行驱动单元的第n-3级信号输入端相连；所述第一输出端与第n+2级的阵列基板行驱动单元的第n-2级信号输入端相连，且与第n-2级的阵列基板行驱动单元的第n+2级信号输入端相连，用于向显示区域的第n级水平扫描线提供扫描信号；
所述第n 级阵列基板行驱动单元还包括：
上拉控制单元，包括一第一薄膜晶体管，分别与所述第n-2级信号输入端、所述第n-3级信号输入端以及所述第二输出端连接，其中，所述第n-3级信号输入端的信号的峰值电压为所述第n-2级信号输入端的信号的峰值电压的两倍，用于上拉所述第二输出端的电位；
上拉单元，分别与所述高频时钟信号输入端、所述第一输出端连接，并与所述上拉控制单元共同连接于所述第二输出端，用于对所述第一输出端的信号进行充电，以使所述第二输出端达到更高的电位；
下拉控制单元，分别与低电平输入端、所述上拉控制单元及所述上拉单元连接，用于在所述第一输出端的信号处于非充电状态时，控制所述第二输出端和所述第一输出端保持低电位；
下拉单元，分别与所述第n+2级信号输入端、所述低电平输入端、所述下拉控制单元连接，并与所述上拉单元及所述上拉控制单元共同连接于所述第二输出端，用于下拉所述第二输出端的电位。
在上述阵列基板行驱动电路中，所述第一薄膜晶体管具有第一栅极、第一源极及第一漏极；
所述第一栅极电性连接至所述第n-3级信号输入端，所述第一源极电性连接至所述第n-2级信号输入端，所述第一漏极分别与所述下拉控制单元电性连接，并与所述下拉单元及所述上拉单元共同连接于所述第二输出端。
在上述阵列基板行驱动电路中，所述上拉单元包括一电容和第二薄膜晶体管，所述第二薄膜晶体管具有第二栅极、第二源极及第二漏极，所述电容包括第一极板和第二极板；
所述第二栅极通过第二输出端分别与所述上拉控制单元和所述电容的第一极板电性连接，所述第二源极与所述高频时钟信号输入端电性连接，所述第二漏极与第一输出端电性连接。
在上述阵列基板行驱动电路中，所述下拉控制单元包括第一下拉控制子单元；
所述第一下拉控制子单元包括第三薄膜晶体管，所述第三薄膜晶体管具有第三栅极、第三源极及第三漏极；
所述第三栅极与所述第一漏极连接，第三漏极与所述低电平输入端连接；
所述第一下拉控制子单元还包括第四薄膜晶体管和第五薄膜晶体管，所述第四薄膜晶体管具有第四栅极、第四源极及第四漏极，所述第五薄膜晶体管具有第五栅极、第五源极及第五漏极；
所述第四栅极与所述第五栅极连接至所述第三源极，所述第四源极与第五源极连接至所述电容的第二极板，且与第一输出端连接；所述第四漏极与所述低电平输入端连接，所述第五漏极与第三栅极连接。
在上述阵列基板行驱动电路中，所述第n 级阵列基板行驱动单元还包括低频时钟信号第一输入端和低频时钟信号第二输入端；
所述第一下拉控制子单元还包括第六薄膜晶体管和第七薄膜晶体管，所述第六薄膜晶体管具有第六栅极、第六源极及第六漏极，所述第七薄膜晶体管具有第七栅极、第七源极及第七漏极；
所述第六栅极、第六源极与第七源极连接至所述低频时钟信号第一输入端，所述第七栅极与所述低频时钟信号第二输入端连接；第六漏极与第七漏极连接至第四栅极。
在上述阵列基板行驱动电路中，所述第n 级阵列基板行驱动单元还包括第二下拉控制子单元；
所述第二下拉控制子单元包括第八薄膜晶体管，所述第八薄膜晶体管具有第八栅极、第八源极及第八漏极；
所述第八栅极与第一漏极连接，所述第八漏极与所述低电平输入端连接；
所述第二下拉控制子单元还包括第九薄膜晶体管和第十薄膜晶体管，所述第九薄膜晶体管具有第九栅极、第九源极及第九漏极，所述第十薄膜晶体管具有第十栅极、第十源极及第十漏极；
所述第九栅极与所述第十栅极连接至所述第八源极，所述第九源极与第十源极均和所述第四源极与第五源极连接，并连接至所述电容的第二极板，且与第一输出端连接；所述第九漏极与所述低电平输入端连接，所述第十漏极与第八栅极连接。
在上述阵列基板行驱动电路中，所述第二下拉控制子单元还包括第十一薄膜晶体管和第十二薄膜晶体管，所述第十一薄膜晶体管具有第十一栅极、第十一源极及第十一漏极；所述第十二薄膜晶体管具有第十二栅极、第十二源极及第十二漏极；
所述第十一栅极、第十一源极与第十二源极连接至所述低频时钟信号第二输入端，所述第十二栅极与所述低频时钟信号第一输入端连接；第十一漏极与第十二漏极连接至第九栅极。
在上述阵列基板行驱动电路中，所述下拉单元为一第十三薄膜晶体管，所述第十三薄膜晶体管具有第十三栅极、第十三源极及第十三漏极；
所述第十三栅极与所述第n+2级信号输入端连接，所述第十三漏极与所述低电平输入端连接，所述第十三源极与所述第二栅极连接。
一种液晶显示装置，包括阵列基板行驱动电路，以及与所述阵列基板行驱动电路连接的显示区域，所述阵列基板行驱动电路，包括多级连接的阵列基板行驱动单元；
其中对于所述阵列基板行驱动电路中的第n 级阵列基板行驱动单元，包括：第n-3级信号输入端、第n-2级信号输入端、第n+2级信号输入端、第一输出端、第二输出端、低电平输入端以及高频时钟信号输入端，n为大于3的正整数；
其中，所述第n-3级信号输入端与第n-3级的阵列基板行驱动单元的第二输出端相连；所述第n-2级信号输入端与第n-2级的阵列基板行驱动单元的第一输出端相连；所述第n+2级信号输入端与第n+2级的阵列基板行驱动单元的第一输出端相连；所述第二输出端与第n+3级的阵列基板行驱动单元的第n-3级信号输入端相连；所述第一输出端与第n+2级的阵列基板行驱动单元的第n-2级信号输入端相连，且与第n-2级的阵列基板行驱动单元的第n+2级信号输入端相连，用于向显示区域的第n级水平扫描线提供扫描信号；
所述第n 级阵列基板行驱动单元还包括：
上拉控制单元，包括一第一薄膜晶体管，分别与所述第n-2级信号输入端、所述第n-3级信号输入端以及所述第二输出端连接，其中，所述第n-3级信号输入端的信号的峰值电压为所述第n-2级信号输入端的信号的峰值电压的两倍，用于上拉所述第二输出端的电位；
上拉单元，分别与所述高频时钟信号输入端、所述第一输出端连接，并与所述上拉控制单元共同连接于所述第二输出端，用于对所述第一输出端的信号进行充电，以使所述第二输出端达到更高的电位；
下拉控制单元，分别与低电平输入端、所述上拉控制单元及所述上拉单元连接，用于在所述第一输出端的信号处于非充电状态时，控制所述第二输出端和所述第一输出端保持低电位；
下拉单元，分别与所述第n+2级信号输入端、所述低电平输入端、所述下拉控制单元连接，并与所述上拉单元及所述上拉控制单元共同连接于所述第二输出端，用于下拉所述第二输出端的电位。
在上述液晶显示装置中，所述显示区域具有水平扫描线，每条所述水平扫描线的两端各连接一个所述阵列基板行驱动单元，所述水平扫描线与所述阵列基板行驱动单元的第一输出端连接。
 有益效果
相对现有技术，本发明利用一个峰值电压更高的前级信号来控制负责GOA电路的上、下级之间的信号传递的第一薄膜晶体管的接通，使GOA电路上、下级之间的信号传递受TFT元件阈值电压漂移的影响较现有的GOA电路更小，从而使GOA电路的输出受TFT元件阈值电压漂移的影响变小，提高GOA电路输出的稳定性。
 附图说明
图1为本发明提供的阵列基板行驱动电路的结构示意图；
图2为本发明提供的阵列基板行驱动电路的驱动时序示意图；
图3为本发明提供的阵列基板行驱动电路的另一结构示意图；
图4为本发明提供的液晶显示装置的结构示意图；
图5a至图5c为本发明提供的GOA电路与一现有GOA电路的输出对比示意图。
 本发明的最佳实施方式
请参照图式，其中相同的组件符号代表相同的组件，本发明的原理是以实施在一适当的运算环境中来举例说明。以下的说明是基于所例示的本发明具体实施例，其不应被视为限制本发明未在此详述的其它具体实施例。
参考图1，图1为本发明提供的阵列基板行驱动电路的第一实施例的示意图。
本实施例的阵列基板行驱动电路包括多级连接的阵列基板行驱动单元，其中，对于所述阵列基板行驱动电路中的第n 级阵列基板行驱动单元，包括第n-3级信号输入端、第n-2级信号输入端、第n+2级信号输入端、第一输出端、第二输出端、低电平输入端以及高频时钟信号输入端，n为大于3的正整数；
其中，对于所述第n 级阵列基板行驱动单元，所述第n-3级信号输入端与第n-3级的阵列基板行驱动单元的第二输出端相连；所述第n-2级信号输入端与第n-2级的阵列基板行驱动单元的第一输出端相连；所述第n+2级信号输入端与第n+2级的阵列基板行驱动单元的第一输出端相连；所述第二输出端与第n+3级的阵列基板行驱动单元的第n-3级信号输入端相连；所述第一输出端与第n+2级的阵列基板行驱动单元的第n-2级信号输入端相连，且与第n-2级的阵列基板行驱动单元的第n+2级信号输入端相连，所述第一输出端用于向显示区域的第n级水平扫描线提供扫描信号；
可以理解的是，本发明实施例对于第n 级阵列基板行驱动单元，所述第n-3级信号输入端的信号为Q（n-3），同时，所述Q（n-3）为第n-3级阵列基板行驱动单元的第二输出端的信号；所述第n-2级信号输入端的信号为G（n-2），同时所述G（n-2）为第n-2级阵列基板行驱动单元的第一输出端的信号；所述第n+2级信号输入端的信号为G（n+2），同时，所述G（n+2）为第n+2级阵列基板行驱动单元的第一输出端的信号；所述第一输出端的信号为G(n)，所述第二输出端的信号为Q(n)，所述低电平输入端的信号为Vss，所述高频时钟信号输入端的信号为CK（n）。
所述第n 级阵列基板行驱动单元还包括：
上拉控制单元104，包括一第一薄膜晶体管，分别与所述第n-2级信号输入端、所述第n-3级信号输入端以及所述第二输出端连接，其中，所述第n-3级信号输入端的信号的峰值电压为所述第n-2级信号输入端的信号的峰值电压的两倍，用于上拉所述第二输出端的电位；
上拉单元101，分别与所述高频时钟信号输入端、所述第一输出端连接，并与所述上拉控制单元104共同连接于所述第二输出端，用于对所述第一输出端的信号进行充电，以使所述第二输出端达到更高的电位；
下拉控制单元103，分别与所述低电平输入端、所述上拉控制单元104及所述上拉单元101连接，用于在所述第一输出端的信号处于非充电状态时，控制所述第二输出端和所述第一输出端保持低电位；
下拉单元102，分别与所述第n+2级信号输入端、所述低电平输入端、所述下拉控制单元103连接，并与所述上拉单元104及所述上拉控制单元104共同连接于所述第二输出端，用于下拉所述第二输出端的电位。
可以理解的是，对于第1 级阵列基板行驱动单元，所述第n-3级信号输入端和所述第n-2级信号输入端均用于输入一脉冲激活信号，所述第n+2级信号输入端与第3级的阵列基板行驱动单元的第一输出端相连，所述第二输出端与第4级的阵列基板行驱动单元的第n-3级信号输入端相连；所述第一输出端与第3级的阵列基板行驱动单元的第n-2级信号输入端相连，用于向显示区域第1级水平扫描线提供扫描信号；同理，对于第2 级的阵列基板行驱动单元和第3级的阵列基板行驱动单元可以采用类似的处理，此处不作具体描述。
容易想到的是，对于倒数第1级，所述第n+2级信号输入端用于输入一脉冲激活信号，所述第二输出端可以设置为悬空，同理对于倒数第2级和倒数3级的阵列基板行驱动单元可以采用类似的处理，此处不作具体描述。
以下分别对所述上拉控制单元104、所述上拉单元101、所述下拉控制单元103以及所述下拉单元102的内部连接结构进行具体分析：
所述上拉控制单元104为一第一薄膜晶体管T11，所述第一薄膜晶体管T11具有第一栅极、第一源极及第一漏极；
所述第一栅极电性连接至所述第n-3级信号输入端，所述第一源极电性连接至所述第n-2级信号输入端，所述第一漏极分别与所述下拉控制单元103电性连接，并与所述下拉单元102及所述上拉单元101共同连接于所述第二输出端。
所述上拉单元101包括一电容Cb和第二薄膜晶体管T21，所述第二薄膜晶体管T21具有第二栅极、第二源极及第二漏极，所述电容Cb包括第一极板和第二极板；
所述第二栅极通过第二输出端与上拉控制单元104和电容Cb的第一极板电性连接，所述第二源极与所述高频时钟信号输入端电性连接，第二漏极与第一输出端电性连接。
所述下拉控制单元103包括第一下拉控制子单元1031；
所述第一下拉控制子单元1031包括第三薄膜晶体管T52，所述第三薄膜晶体管T52 具有第三栅极、第三源极及第三漏极；
所述第三栅极与第一漏极连接，第三漏极与所述低电平输入端连接；
所述第一下拉控制子单元1031还包括第四薄膜晶体管T32和第五薄膜晶体管T42，所述第四薄膜晶体管T32具有第四栅极、第四源极及第四漏极，所述第五薄膜晶体管T42具有第五栅极、第五源极及第五漏极；
所述第四栅极与所述第五栅极连接至所述第三源极，所述第四源极与第五源极连接至所述电容Cb的第二极板，且与第一输出端连接；所述第四漏极与所述低电平输入端连接，所述第五漏极与第三栅极连接。
如图1所示，所述第n 级阵列基板行驱动单元还包括低频时钟信号第一输入端和低频时钟信号第二输入端；
其中，所述低频时钟信号第一输入端的信号为LC1，所述低频时钟信号第二输入端的信号为LC2；
所述第一下拉控制子单元1031还包括第六薄膜晶体管T53和第七薄膜晶体管T54，所述第六薄膜晶体管T53具有第六栅极、第六源极及第六漏极，所述第七薄膜晶体管T54具有第七栅极、第七源极及第七漏极；
所述第六栅极、第六源极与第七源极连接至所述低频时钟信号第一输入端，所述第七栅极与所述低频时钟信号第二输入端连接；所述第六漏极与第七漏极连接至所述第四栅极。
所述第n 级阵列基板行驱动单元还包括第二下拉控制子单元1032；
所述第二下拉控制子单元1032包括第八薄膜晶体管T62、所述第八薄膜晶体管T62具有第八栅极、第八源极及第八漏极；
所述第八栅极与所述第一漏极连接，所述第八漏极与所述低电平输入端连接；
所述第二下拉控制子单元1032还包括第九薄膜晶体管T33和第十薄膜晶体管T43，所述第九薄膜晶体管T33具有第九栅极、第九源极及第九漏极，所述第十薄膜晶体管T43具有第十栅极、第十源极及第十漏极；
所述第九栅极与所述第十栅极连接至所述第八源极，所述第九源极与第十源极均和所述第四源极与第五源极连接，并连接至所述电容Cb的第二极板，且与所述第一输出端连接；所述第九漏极与所述低电平输入端连接，所述第十漏极与第八栅极连接。
所述第二下拉控制子单元1032还包括第十一薄膜晶体管T63和第十二薄膜晶体管T64，所述第十一薄膜晶体管T63具有第十一栅极、第十一源极及第十一漏极；所述第十二薄膜晶体管T64具有第十二栅极、第十二源极及第十二漏极；
所述第十一栅极、第十一源极与第十二源极连接至所述低频时钟信号第二输入端，所述第十二栅极与所述低频时钟信号第一输入端连接；所述第十一漏极与第十二漏极连接至第九栅极。
所述下拉单元102为一第十三薄膜晶体管T41、所述第十三薄膜晶体管T41具有第十三栅极、第十三源极及第十三漏极；
所述第十三栅极与所述第n+2级信号输入端连接，所述第十三漏极与所述低电平输入端连接，所述第十三源极与所述第二栅极连接。
可以理解的是，各薄膜晶体管的接通或断开分别对应其源极和其漏极之间的电流通道的接通或断开。
进一步的，本发明实施例中，所述第一薄膜晶体管T11、所述第二薄膜晶体管T21、所述第三薄膜晶体管T52、所述第四薄膜晶体管T32、所述第五薄膜晶体管T42、所述第六薄膜晶体管T53、所述第七薄膜晶体管T54、所述第八薄膜晶体管T62、所述第九薄膜晶体管T33、所述第十薄膜晶体管T43、所述第十一薄膜晶体管T63、所述第十二薄膜晶体管T64以及所述第十三薄膜晶体管T41均为N型的薄膜晶体管，显然，上述各薄膜晶体管在其他实施例中还可以为P型的薄膜晶体管，其类型可以根据具体场景进行确定，此处举例不构成对本发明的限定。
为了更好地理解本发明技术方案，以下基于如图1所示的阵列基板行驱动电路（GOA），为本发明GOA电路的单级架构的一个实例，对该单级GOA电路进行简单介绍：
所述单级GOA电路包含控制给显示区域第n级水平扫描线进行充电的第二薄膜晶体管T21（对应图1所示的上拉单元101），其中第一输出端（即G(n)信号输出端）与第n级水平扫描线相连接，第二薄膜晶体管T21的第二源级和第二漏极分别连接第一输出端和高频时钟信号输入端（即CK(n)信号输入端），所述第二薄膜晶体管T21的第二栅极与所述第二输出端相连，Q(n)的电位可直接影响CK(n)对G(n)充电；GOA电路还包含在G(n)充电结束时对Q(n)进行放电的第十三薄膜晶体管T41（对应图1的下拉单元104）。
进一步地，图1所示的下拉控制单元103为GOA的下拉电路区，可以在非充电时期维持G(n)和Q(n)的低电位。下拉控制单元103中P点和K点交替受低频时钟信号第一输入端（即LC1信号输入端）和低频时钟信号第二输入端（即LC2信号输入端）的充电而处于高电位，从而交替控制第四薄膜晶体管T32和第五薄膜晶体管T42，或者，第九薄膜晶体管T33和第十薄膜晶体管T43的打开，以便交替维持G(n)和Q(n)在非充电时期的低电位，从而避免薄膜晶体管长时间受栅极电压应力的影响。
另外，第三薄膜晶体管T52连接P点和低电平输入端（即Vss信号输入端），第八薄膜晶体管T62连接K点和低电平输入端，所述第三薄膜晶体管T52和所述第八薄膜晶体管T62可在Q(n)处于高电位时打开而将P点、K点电位拉低以关闭第四薄膜晶体管T32、第五薄膜晶体管T42、第九薄膜晶体管T33、第十薄膜晶体管T43使之不影响G(n)充电。
第一薄膜晶体管T11（对应图1的上拉控制单元104）可以控制将前级GOA电路输出的信号传递给本级GOA电路，使GOA信号可以逐级传递；Q(n)和G(n)之间连接有自举功能的电容Cb，可在G(n)电位提升时通过Cb的耦合效应使Q(n)电位提升，从而获得更高的Q(n)电位及更小的GOA充电信号。
以下实施例中，各开关管均以N型的薄膜晶体管为例，对如图1所示的单级GOA电路的工作原理进行分析：
可一并参考图2，图2为所述阵列基板行驱动电路的驱动时序示意图；该驱动时序分为三个阶段，其中，t1~t4为G(n)充电前的准备时间，t4~t5为G(n)的充电时间，t5后G(n)被放电。
具体地，t1时，CK(n-3)为高电位，Q(n-3)自举到高电位，其中，Q(n-3)自举的高电位约为两倍G(n-2)的高电位。t1时G(n-2)为低电位，Q(n)未充电，则Q(n)为低电位。
其中，CK(n-3)为第n-3级阵列基板行驱动单元的高频时钟信号，当其为高电位时，对应地Q(n-3) 自举到高电位。
t2时，CK(n-2)的电位抬升，G(n-2) 也抬升为高电位，Q(n-3)仍维持高的自举电位（仍高于G(n-2)的高电位），第一薄膜晶体管T11接通并给Q(n)充电，则Q(n)电位抬升。
其中，CK(n-2)为第n-2级阵列基板行驱动单元的高频时钟信号。
进一步地，Q(n)电位抬升后，可第三薄膜晶体管T52和第八薄膜晶体管T62接通，从而拉低P、K点电位以关闭第四薄膜晶体管T32、第五薄膜晶体管T42、第九薄膜晶体管T33和第十薄膜晶体管T43，使之不影响G(n) 后续充电。
可以理解的是，如果P点或K点是高电位，那么起下拉作用的第四薄膜晶体管T32与第五薄膜晶体管T42的开关组合，或者，第九薄膜晶体管T33与第十薄膜晶体管T43的开关组合就会打开，就会下拉G(n)和Q(n)的电位而影响充电。
t3时，CK(n-3)的电位开始下降，Q(n-3)的电位也下降，G(n-2)维持高电位，Q(n)电位基本保持不变。
t4时，CK(n)的电位开始抬升，第二薄膜晶体管T21接通，Q(n)自举到更高电位并控制第二薄膜晶体管T21给G(n)充电，G(n)电位抬升。
t5时，CK(n)电位开始下降，Q(n)电位并未立即被拉低，第二薄膜晶体管T21在t5后的短时间内仍保持导通，将G(n)电位拉低。
之后，G(n+2)电位抬升，第十三薄膜晶体管T41接通，以确保Q(n)被拉至低电位；所述第三薄膜晶体管T52和第八薄膜晶体管T62在Q(n)电位拉低后关闭，第四薄膜晶体管T32与第五薄膜晶体管T42的开关组合和第九薄膜晶体管T33与第十薄膜晶体管T43的开关组合可正常交替打开，以维持G(n)和Q(n)在非充电时期的低电位。
可以理解的是，在所述第三薄膜晶体管T52和第八薄膜晶体管T62关闭后，P点和K点的电位可以受低频信号LC1和LC2的影响。假设，LC1为高电位而LC2为低电位时，第六薄膜晶体管T53打开而第七薄膜晶体管T54关闭，P点可为高电位，P点为高电位就可打开起下拉作用的第四薄膜晶体管T32与第五薄膜晶体管T42；假设，LC2为高电位而LC1为低电位时，第十一薄膜晶体管T63打开而第十二薄膜晶体管T64关闭，K点可为高电位，K点为高电位就可打开起下拉作用的第九薄膜晶体管T33与第十薄膜晶体管T43。这一设计的目的是避免第四薄膜晶体管T32与第五薄膜晶体管T42，或者第九薄膜晶体管T33与第十薄膜晶体管T43长时间受单一栅极应力的影响，从而可以延长器件的寿命。
需要说明的是，如图1所示本发明GOA电路中负责上、下级间讯号传递的第一薄膜晶体管T11，其第一栅极、第一漏极、第一源极分别连接第n-3级信号输入端（Q(n-3)信号）、第n-2级信号输入端（G(n-2) 信号）、第二输出端（Q(n)信号）。根据半导体器件导通原则，如果要使Q(n)接受到来自第一薄膜晶体管T11的充电，第一栅极和第一源极间的电压差Vgs须不小于其阈值电压Vth，即Vgs-Vth≥0。本发明中第一栅极的Q(n-3)信号在自举后的电位约是G(n-2)高电位VG(n-2)的2倍，即2 VG(n-2) 。因此Q(n)可被第一薄膜晶体管T11充至VG(n-2)，Q(n)在自举前可被充至的电位不易受到第一薄膜晶体管T11阈值电压Vth漂移的影响。而对于目前大部分的GOA电路，如上拉控制单元104中第一薄膜晶体管T11的栅极的峰值电位约等于G(n-2)的电位VG(n-2)，因此Q(n)可被第一薄膜晶体管T11充至的电位约等于VG(n-2)-Vth，Q(n)在自举前可被充至的电位易受到第一薄膜晶体管T11阈值电压Vth漂移的影响。
综上所述，本发明GOA电路用一个峰值电压更高的Q(n-3)信号来控制负责GOA电路的上、下级之间信号传递的第一薄膜晶体管T11的接通，使GOA电路上、下级之间的信号传递受TFT元件阈值电压漂移的影响较现有的GOA电路更小，从而使GOA电路的输出受TFT元件阈值电压漂移的影响变小，提高GOA电路输出的稳定性。
为便于更好的实施本发明实施例提供的阵列基板行驱动电路，本发明实施例还提供一种包含阵列基板行驱动电路的液晶显示装置。其中名词的含义与上述阵列基板行驱动电路中相同，具体实现细节可以参考阵列基板行驱动电路实施例中的说明。
本发明实施例提供一种液晶显示装置，包括阵列基板行驱动电路，以及与所述阵列基板行驱动电路连接的显示区域，所述阵列基板行驱动电路，包括多级连接的阵列基板行驱动单元；
其中，对于所述阵列基板行驱动电路中的第n 级阵列基板行驱动单元，包括第n-3级信号输入端、第n-2级信号输入端、第n+2级信号输入端、第一输出端、第二输出端、低电平输入端以及高频时钟信号输入端，n为大于3的正整数；
其中，所述第n-3级信号输入端与第n-3级的阵列基板行驱动单元的第二输出端相连；所述第n-2级信号输入端与第n-2级的阵列基板行驱动单元的第一输出端相连；所述第n+2级信号输入端与第n+2级的阵列基板行驱动单元的第一输出端相连；所述第二输出端与第n+3级的阵列基板行驱动单元的第n-3级信号输入端相连；所述第一输出端与第n+2级的阵列基板行驱动单元的第n-2级信号输入端相连，且与第n-2级的阵列基板行驱动单元的第n+2级信号输入端相连，用于向显示区域的第n级水平扫描线提供扫描信号；
可以理解的是，本发明实施例对于第n 级阵列基板行驱动单元，所述第n-3级信号输入端的信号为Q（n-3），同时，所述Q（n-3）为第n-3级阵列基板行驱动单元的第二输出端的信号；所述第n-2级信号输入端的信号为G（n-2），同时所述G（n-2）为第n-2级阵列基板行驱动单元的第一输出端的信号；所述第n+2级信号输入端的信号为G（n+2），同时，所述G（n+2）为第n+2级阵列基板行驱动单元的第一输出端的信号；所述第一输出端的信号为G(n)，所述第二输出端的信号为Q(n)，所述低电平输入端的信号为Vss，所述高频时钟信号输入端的信号为CK（n）。
所述第n 级阵列基板行驱动单元还包括：
上拉控制单元104，包括一第一薄膜晶体管，分别与所述第n-2级信号输入端、所述第n-3级信号输入端以及所述第二输出端连接，其中，所述第n-3级信号输入端的信号的峰值电压为所述第n-2级信号输入端的信号的峰值电压的两倍，用于上拉所述第二输出端的电位；
上拉单元101，分别与所述高频时钟信号输入端、所述第一输出端连接，并与所述上拉控制单元104共同连接于所述第二输出端，用于对所述第一输出端的信号进行充电，以使所述第二输出端达到更高的电位；
下拉控制单元103，分别与所述低电平输入端、所述上拉控制单元104及所述上拉单元101连接，用于在所述第一输出端的信号处于非充电状态时，控制所述第二输出端和所述第一输出端保持低电位；
下拉单元102，分别与所述第n+2级信号输入端、所述低电平输入端、所述下拉控制单元103连接，并与所述上拉单元104及所述上拉控制单元104共同连接于所述第二输出端，用于下拉所述第二输出端的电位。
可一并参考图3，图3为本发明的GOA电路的一种多级连接结构示意图，所述显示区域具有水平扫描线，每条所述水平扫描线的两端各连接一个所述阵列基板行驱动单元，所述水平扫描线与所述阵列基板行驱动单元的第一输出端连接。
可以理解的是，GOA电路可以从左右两边分别对水平扫描线gate line进行充电和放电，以获得均匀的充电效果。低频时钟信号LC1和LC2、直流低电压Vss、以及CK1~CK4的4个高频时钟信号的金属线放置于各级GOA电路的外围。第n级GOA电路分别接受LC1、LC2、Vss、CK1~CK4中的1个CK信号、第n-2级GOA电路产生的G(n-2) 信号、第n-3级GOA电路产生的Q(n-3) 信号、第n+2级GOA电路产生的G(n+2) 信号，并产生G(n) 信号和Q(n) 信号。如图3所示的电路多级连接结构可以保证GOA讯号能逐级传递，并且各级GOA电路可以逐级从左、右两边分别对显示区域的水平扫描线进行充电和放电。
以下分别对所述上拉控制单元104、所述上拉单元101、所述下拉控制单元103以及所述下拉单元102的结构进行具体分析：
所述上拉控制单元104为一第一薄膜晶体管T11，所述第一薄膜晶体管T11具有第一栅极、第一源极及第一漏极；
所述第一栅极电性连接至所述第n-3级信号输入端，所述第一源极电性连接至所述第n-2级信号输入端，所述第一漏极分别与所述下拉控制单元103电性连接，并与所述下拉单元102及所述上拉单元101共同连接于所述第二输出端。
所述上拉单元101包括一电容Cb和第二薄膜晶体管T21，所述第二薄膜晶体管T21具有第二栅极、第二源极及第二漏极，所述电容Cb包括第一极板和第二极板；
所述第二栅极通过第二输出端与上拉控制单元104和电容Cb的第一极板电性连接，所述第二源极与所述高频时钟信号输入端电性连接，第二漏极与第一输出端电性连接。
所述下拉控制单元103包括第一下拉控制子单元1031；
所述第一下拉控制子单元1031包括第三薄膜晶体管T52，所述第三薄膜晶体管T52 具有第三栅极、第三源极及第三漏极；
所述第三栅极与第一漏极连接，第三漏极与所述低电平输入端连接；
所述第一下拉控制子单元1031还包括第四薄膜晶体管T32和第五薄膜晶体管T42，所述第四薄膜晶体管T32具有第四栅极、第四源极及第四漏极，所述第五薄膜晶体管T42具有第五栅极、第五源极及第五漏极；
所述第四栅极与所述第五栅极连接至所述第三源极，所述第四源极与第五源极连接至所述电容Cb的第二极板，且与第一输出端连接；所述第四漏极与所述低电平输入端连接，所述第五漏极与第三栅极连接。
如图1所示，所述第n 级阵列基板行驱动单元还包括低频时钟信号第一输入端和低频时钟信号第二输入端；
其中，所述低频时钟信号第一输入端的信号为LC1，所述低频时钟信号第二输入端的信号为LC2；
所述第一下拉控制子单元1031还包括第六薄膜晶体管T53和第七薄膜晶体管T54，所述第六薄膜晶体管T53具有第六栅极、第六源极及第六漏极，所述第七薄膜晶体管T54具有第七栅极、第七源极及第七漏极；
所述第六栅极、第六源极与第七源极连接至所述低频时钟信号第一输入端，所述第七栅极与所述低频时钟信号第二输入端连接；所述第六漏极与第七漏极连接至所述第四栅极。
所述第n 级阵列基板行驱动单元还包括第二下拉控制子单元1032；
所述第二下拉控制子单元1032包括第八薄膜晶体管T62、所述第八薄膜晶体管T62具有第八栅极、第八源极及第八漏极；
所述第八栅极与所述第一漏极连接，所述第八漏极与所述低电平输入端连接；
所述第二下拉控制子单元1032还包括第九薄膜晶体管T33和第十薄膜晶体管T43，所述第九薄膜晶体管T33具有第九栅极、第九源极及第九漏极，所述第十薄膜晶体管T43具有第十栅极、第十源极及第十漏极；
所述第九栅极与所述第十栅极连接至所述第八源极，所述第九源极与第十源极均和所述第四源极与第五源极连接，并连接至所述电容Cb的第二极板，且与所述第一输出端连接；所述第九漏极与所述低电平输入端连接，所述第十漏极与第八栅极连接。
所述第二下拉控制子单元1032还包括第十一薄膜晶体管T63和第十二薄膜晶体管T64，所述第十一薄膜晶体管T63具有第十一栅极、第十一源极及第十一漏极；所述第十二薄膜晶体管T64具有第十二栅极、第十二源极及第十二漏极；
所述第十一栅极、第十一源极与第十二源极连接至所述低频时钟信号第二输入端，所述第十二栅极与所述低频时钟信号第一输入端连接；所述第十一漏极与第十二漏极连接至第九栅极。
所述下拉单元102为一第十三薄膜晶体管T41、所述第十三薄膜晶体管T41具有第十三栅极、第十三源极及第十三漏极；
所述第十三栅极与所述第n+2级信号输入端连接，所述第十三漏极与所述低电平输入端连接，所述第十三源极与所述第二栅极连接。
可一并参考图2，其中，t1~t4为G(n)充电前的准备时间，t4~t5为G(n)的充电时间，t5后G(n)被放电；
具体地，t1时，CK(n-3)为高电位，Q(n-3)自举到高电位，其中，Q(n-3)自举的高电位约为两倍G(n-2)的高电位。t1时G(n-2)为低电位，Q(n)未充电，则Q(n)为低电位。
t2时，CK(n-2)的电位抬升，G(n-2) 也抬升为高电位，Q(n-3)仍维持高的自举电位（仍高于G(n-2)的高电位），第一薄膜晶体管T11接通并给Q(n)充电，则Q(n)电位抬升。进一步地，Q(n)电位抬升后，可第三薄膜晶体管T52和第八薄膜晶体管T62接通，从而拉低P、K点电位以关闭第四薄膜晶体管T32、第五薄膜晶体管T42、第九薄膜晶体管T33和第十薄膜晶体管T43，使之不影响G(n) 后续充电。
t3时，CK(n-3)的电位开始下降，Q(n-3)的电位也下降，G(n-2)维持高电位，Q(n)电位基本保持不变。
t4时，CK(n)的电位开始抬升，第二薄膜晶体管T21接通，Q(n)自举到更高电位并控制第二薄膜晶体管T21给G(n)充电，G(n)电位抬升。
t5时，CK(n)电位开始下降，Q(n)电位并未立即被拉低，第二薄膜晶体管T21在t5后的短时间内仍保持导通，将G(n)电位拉低。
之后，G(n+2)电位抬升，第十三薄膜晶体管T41接通，以确保Q(n)被拉至低电位；所述第三薄膜晶体管T52和第八薄膜晶体管T62在Q(n)电位拉低后关闭，第四薄膜晶体管T32与第五薄膜晶体管T42的开关组合和第九薄膜晶体管T33与第十薄膜晶体管T43的开关组合可正常交替打开，以维持G(n)和Q(n)在非充电时期的低电位。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见上文单级GOA电路的详细描述，此处不再赘述。
可以理解的是，在本实施例中，所述GOA电路用一个峰值电压更高的Q(n-3)信号来控制负责GOA电路的上、下级之间信号传递的第一薄膜晶体管T11的接通；即上级的GOA电路的输出可以用作下级驱动电路的输入，上级的GOA电路的输入为上一行上级的GOA电路的输出，从而使得GOA电路上、下级之间的信号传递受TFT元件阈值电压漂移的影响较现有的GOA电路更小，从而使GOA电路的输出受TFT元件阈值电压漂移的影响变小，提高GOA电路输出的稳定性。
本发明的GOA电路可以利用平板显示面板的原有制程制备在显示面板的基板上，能替代外接IC来完成各级水平扫描线的驱动，尤其适合制作窄边框或无边框的平板显示产品。可一并参考图4，图4为本发明提供的液晶显示装置的结构示意图。其中，显示基板（即显示区域403）上方的x+c board为显示基板提供驱动和控制讯号， 402区域为显示装置外壳，显示基板左边401区域和右边404区域制作GOA电路，可从左、右两个方向驱动显示区域403的水平扫描线。GOA电路接受x+c board的输入讯号并逐级产生水平扫描线的控制讯号，可以控制显示区域403中的pixel逐行打开。
为了更好地理解本发明提供的GOA电路，以下将所述GOA电路与一现有的GOA电路进行对比分析：
可一并参考图5a至图5c为本发明提供的GOA电路与一现有GOA电路的输出对比示意图；比如，一现有的GOA电路，其上拉控制单元104中第一薄膜晶体管T11的栅极的峰值电位约等于G(n-2)的电位VG(n-2)， Q(n)可被第一薄膜晶体管T11充至的电位约等于VG(n-2)-Vth；其中，图5a为本发明的GOA电路和现有GOA电路在电路中TFT的阈值电压发生漂移前后的比对，其中虚线为BTS前的示意，实线为BTS后的示意，由图5a可以发现，在BTS（bias temperature stress，偏压温度应力）后，TFT的阈值电压Vth会发生右移。采集BTS前、后TFT的电性参数并将其进行模拟，可参考图5b和图5c，由图5b可以发现现有GOA电路在其TFT阈值电压漂移后其输出Q(n)和G(n) 的变化较大，由图5c可以发现本发明的GOA电路在其TFT阈值电压漂移后其输出Q(n)和G(n)的变化较小。
综上所述，本发明GOA电路用一个峰值电压更高的Q(n-3)信号来控制负责GOA电路的上、下级之间信号传递的第一薄膜晶体管T11的接通，使GOA电路上、下级之间的信号传递受TFT元件阈值电压漂移的影响较现有的GOA电路更小，从而使GOA电路的输出受TFT元件阈值电压漂移的影响变小，提高GOA电路输出的稳定性。并且，所述GOA电路可以利用平板显示面板的原有制程制备在显示面板的基板上，能替代外接IC来完成各级水平扫描线的驱动，简化显示面板的制作工序，降低成本，尤其适合制作窄边框或无边框的平板显示产品。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见上文相关的详细描述，此处不再赘述。
本领域技术人员将认识到，本文所使用的词语“优选的”意指用作实例、示例或例证。奉文描述为“优选的”任意方面或设计不必被解释为比其他方面或设计更有利。相反，词语“优选的”的使用旨在以具体方式提出概念。如本申请中所使用的术语“或”旨在意指包含的“或”而非排除的“或”。即，除非另外指定或从上下文中清楚，“X使用101或102”意指自然包括排列的任意一个。即，如果X使用101；X使用102;或X使用101和102二者，则“X使用101或102”在前述任一示例中得到满足。
而且，尽管已经相对于一个或多个实现方式示出并描述了本公开，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本公开包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件（例如元件、资源等）执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本公开的示范性实现方式中的功能的公开结构不等同。此外，尽管本公开的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种阵列基板行驱动电路，包括多级连接的阵列基板行驱动单元，其中对于所述阵列基板行驱动电路中的第n 级阵列基板行驱动单元，包括：
    第n-3级信号输入端、第n-2级信号输入端、第n+2级信号输入端、第一输出端、第二输出端、低电平输入端以及高频时钟信号输入端，n为大于3的正整数；
    其中，所述第n-3级信号输入端与第n-3级的阵列基板行驱动单元的第二输出端相连；所述第n-2级信号输入端与第n-2级的阵列基板行驱动单元的第一输出端相连；所述第n+2级信号输入端与第n+2级的阵列基板行驱动单元的第一输出端相连；所述第二输出端与第n+3级的阵列基板行驱动单元的第n-3级信号输入端相连；所述第一输出端与第n+2级的阵列基板行驱动单元的第n-2级信号输入端相连，且与第n-2级的阵列基板行驱动单元的第n+2级信号输入端相连，用于向显示区域的第n级水平扫描线提供扫描信号；
    所述第n 级阵列基板行驱动单元还包括：
    一上拉控制单元，包括一第一薄膜晶体管，所述第一薄膜晶体管具有第一栅极、第一源极及第一漏极，所述第一栅极电性连接至所述第n-3级信号输入端，所述第一源极电性连接至所述第n-2级信号输入端，所述第一漏极与一下拉控制单元电性连接，并与一下拉单元及一上拉单元共同连接于所述第二输出端；其中，所述第n-3级信号输入端的信号的峰值电压为所述第n-2级信号输入端的信号的峰值电压的两倍，用于上拉所述第二输出端的电位；
    所述上拉单元，包括一电容和第二薄膜晶体管，所述第二薄膜晶体管具有第二栅极、第二源极及第二漏极，所述电容包括第一极板和第二极板；所述第二栅极与所述上拉控制单元和所述电容的第一极板共同连接于所述第二输出端，所述第二源极与所述高频时钟信号输入端电性连接，所述第二漏极与第一输出端电性连接，用于对所述第一输出端的信号进行充电，以使所述第二输出端达到更高的电位；
    所述下拉控制单元，分别与低电平输入端、所述上拉控制单元及所述上拉单元连接，用于在所述第一输出端的信号处于非充电状态时，控制所述第二输出端和所述第一输出端保持低电位；
    所述下拉单元，分别与所述第n+2级信号输入端、所述低电平输入端、所述下拉控制单元连接，并与所述上拉单元及所述上拉控制单元共同连接于所述第二输出端，用于下拉所述第二输出端的电位。
  2. 根据权利要求1所述的阵列基板行驱动电路，其中所述下拉控制单元包括第一下拉控制子单元；
    所述第一下拉控制子单元包括第三薄膜晶体管，所述第三薄膜晶体管具有第三栅极、第三源极及第三漏极；
    所述第三栅极与所述第一漏极连接，第三漏极与所述低电平输入端连接；
    所述第一下拉控制子单元还包括第四薄膜晶体管和第五薄膜晶体管，所述第四薄膜晶体管具有第四栅极、第四源极及第四漏极，所述第五薄膜晶体管具有第五栅极、第五源极及第五漏极；
    所述第四栅极与所述第五栅极连接至所述第三源极，所述第四源极与第五源极连接至所述电容的第二极板，且与第一输出端连接；所述第四漏极与所述低电平输入端连接，所述第五漏极与第三栅极连接。
  3. 根据权利要求2所述的阵列基板行驱动电路，其中所述第n 级阵列基板行驱动单元还包括低频时钟信号第一输入端和低频时钟信号第二输入端；
    所述第一下拉控制子单元还包括第六薄膜晶体管和第七薄膜晶体管，所述第六薄膜晶体管具有第六栅极、第六源极及第六漏极，所述第七薄膜晶体管具有第七栅极、第七源极及第七漏极；
    所述第六栅极、第六源极与第七源极连接至所述低频时钟信号第一输入端，所述第七栅极与所述低频时钟信号第二输入端连接；所述第六漏极与所述第七漏极连接至所述第四栅极。
  4. 根据权利要求3所述的阵列基板行驱动电路，其中所述第n 级阵列基板行驱动单元还包括第二下拉控制子单元；
    所述第二下拉控制子单元包括第八薄膜晶体管，所述第八薄膜晶体管具有第八栅极、第八源极及第八漏极；
    所述第八栅极与所述第一漏极连接，所述第八漏极与所述低电平输入端连接；
    所述第二下拉控制子单元还包括第九薄膜晶体管和第十薄膜晶体管，所述第九薄膜晶体管具有第九栅极、第九源极及第九漏极，所述第十薄膜晶体管具有第十栅极、第十源极及第十漏极；
    所述第九栅极与所述第十栅极连接至所述第八源极，所述第九源极与第十源极均与所述第四源极和第五源极连接，并连接至所述电容的第二极板，且与所述第一输出端连接；所述第九漏极与所述低电平输入端连接，所述第十漏极与所述第八栅极连接。
  5. 根据权利要求4所述的阵列基板行驱动电路，其中所述第二下拉控制子单元还包括第十一薄膜晶体管和第十二薄膜晶体管，所述第十一薄膜晶体管具有第十一栅极、第十一源极及第十一漏极；所述第十二薄膜晶体管具有第十二栅极、第十二源极及第十二漏极；
    所述第十一栅极、第十一源极与第十二源极连接至所述低频时钟信号第二输入端，所述第十二栅极与所述低频时钟信号第一输入端连接；所述第十一漏极与所述第十二漏极连接至第九栅极。
  6. 根据权利要求5所述的阵列基板行驱动电路，其中所述下拉单元为一第十三薄膜晶体管，所述第十三薄膜晶体管具有第十三栅极、第十三源极及第十三漏极；
    所述第十三栅极与所述第n+2级信号输入端连接，所述第十三漏极与所述低电平输入端连接，所述第十三源极与所述第二栅极连接。
  7. 一种阵列基板行驱动电路，包括多级连接的阵列基板行驱动单元，其中对于所述阵列基板行驱动电路中的第n 级阵列基板行驱动单元，包括：
    第n-3级信号输入端、第n-2级信号输入端、第n+2级信号输入端、第一输出端、第二输出端、低电平输入端以及高频时钟信号输入端，n为大于3的正整数；
    其中，所述第n-3级信号输入端与第n-3级的阵列基板行驱动单元的第二输出端相连；所述第n-2级信号输入端与第n-2级的阵列基板行驱动单元的第一输出端相连；所述第n+2级信号输入端与第n+2级的阵列基板行驱动单元的第一输出端相连；所述第二输出端与第n+3级的阵列基板行驱动单元的第n-3级信号输入端相连；所述第一输出端与第n+2级的阵列基板行驱动单元的第n-2级信号输入端相连，且与第n-2级的阵列基板行驱动单元的第n+2级信号输入端相连，用于向显示区域的第n级水平扫描线提供扫描信号；
    所述第n 级阵列基板行驱动单元还包括：
    上拉控制单元，包括一第一薄膜晶体管，分别与所述第n-2级信号输入端、所述第n-3级信号输入端以及所述第二输出端连接，其中，所述第n-3级信号输入端的信号的峰值电压为所述第n-2级信号输入端的信号的峰值电压的两倍，用于上拉所述第二输出端的电位；
    上拉单元，分别与所述高频时钟信号输入端、所述第一输出端连接，并与所述上拉控制单元共同连接于所述第二输出端，用于对所述第一输出端的信号进行充电，以使所述第二输出端达到更高的电位；
    下拉控制单元，分别与低电平输入端、所述上拉控制单元及所述上拉单元连接，用于在所述第一输出端的信号处于非充电状态时，控制所述第二输出端和所述第一输出端保持低电位；
    下拉单元，分别与所述第n+2级信号输入端、所述低电平输入端、所述下拉控制单元连接，并与所述上拉单元及所述上拉控制单元共同连接于所述第二输出端，用于下拉所述第二输出端的电位。
  8. 根据权利要求7所述的阵列基板行驱动电路，其中所述第一薄膜晶体管具有第一栅极、第一源极及第一漏极；
    所述第一栅极电性连接至所述第n-3级信号输入端，所述第一源极电性连接至所述第n-2级信号输入端，所述第一漏极分别与所述下拉控制单元电性连接，并与所述下拉单元及所述上拉单元共同连接于所述第二输出端。
  9. 根据权利要求7所述的阵列基板行驱动电路，其中所述上拉单元包括一电容和第二薄膜晶体管，所述第二薄膜晶体管具有第二栅极、第二源极及第二漏极，所述电容包括第一极板和第二极板；
    所述第二栅极通过第二输出端分别与所述上拉控制单元和所述电容的第一极板电性连接，所述第二源极与所述高频时钟信号输入端电性连接，所述第二漏极与第一输出端电性连接。
  10. 根据权利要求8所述的阵列基板行驱动电路，其中所述下拉控制单元包括第一下拉控制子单元；
    所述第一下拉控制子单元包括第三薄膜晶体管，所述第三薄膜晶体管具有第三栅极、第三源极及第三漏极；
    所述第三栅极与所述第一漏极连接，第三漏极与所述低电平输入端连接；
    所述第一下拉控制子单元还包括第四薄膜晶体管和第五薄膜晶体管，所述第四薄膜晶体管具有第四栅极、第四源极及第四漏极，所述第五薄膜晶体管具有第五栅极、第五源极及第五漏极；
    所述第四栅极与所述第五栅极连接至所述第三源极，所述第四源极与第五源极连接至所述电容的第二极板，且与第一输出端连接；所述第四漏极与所述低电平输入端连接，所述第五漏极与第三栅极连接。
  11. 根据权利要求10所述的阵列基板行驱动电路，其中所述第n 级阵列基板行驱动单元还包括低频时钟信号第一输入端和低频时钟信号第二输入端；
    所述第一下拉控制子单元还包括第六薄膜晶体管和第七薄膜晶体管，所述第六薄膜晶体管具有第六栅极、第六源极及第六漏极，所述第七薄膜晶体管具有第七栅极、第七源极及第七漏极；
    所述第六栅极、第六源极与第七源极连接至所述低频时钟信号第一输入端，所述第七栅极与所述低频时钟信号第二输入端连接；所述第六漏极与所述第七漏极连接至所述第四栅极。
  12. 根据权利要求11所述的阵列基板行驱动电路，其中所述第n 级阵列基板行驱动单元还包括第二下拉控制子单元；
    所述第二下拉控制子单元包括第八薄膜晶体管，所述第八薄膜晶体管具有第八栅极、第八源极及第八漏极；
    所述第八栅极与所述第一漏极连接，所述第八漏极与所述低电平输入端连接；
    所述第二下拉控制子单元还包括第九薄膜晶体管和第十薄膜晶体管，所述第九薄膜晶体管具有第九栅极、第九源极及第九漏极，所述第十薄膜晶体管具有第十栅极、第十源极及第十漏极；
    所述第九栅极与所述第十栅极连接至所述第八源极，所述第九源极与第十源极均与所述第四源极和第五源极连接，并连接至所述电容的第二极板，且与所述第一输出端连接；所述第九漏极与所述低电平输入端连接，所述第十漏极与所述第八栅极连接。
  13. 根据权利要求12所述的阵列基板行驱动电路，其中所述第二下拉控制子单元还包括第十一薄膜晶体管和第十二薄膜晶体管，所述第十一薄膜晶体管具有第十一栅极、第十一源极及第十一漏极；所述第十二薄膜晶体管具有第十二栅极、第十二源极及第十二漏极；
    所述第十一栅极、第十一源极与第十二源极连接至所述低频时钟信号第二输入端，所述第十二栅极与所述低频时钟信号第一输入端连接；所述第十一漏极与所述第十二漏极连接至第九栅极。
  14. 根据权利要求13所述的阵列基板行驱动电路，其中所述下拉单元为一第十三薄膜晶体管，所述第十三薄膜晶体管具有第十三栅极、第十三源极及第十三漏极；
    所述第十三栅极与所述第n+2级信号输入端连接，所述第十三漏极与所述低电平输入端连接，所述第十三源极与所述第二栅极连接。
  15. 一种液晶显示装置，包括阵列基板行驱动电路，以及与所述阵列基板行驱动电路连接的显示区域，其中所述阵列基板行驱动电路，包括多级连接的阵列基板行驱动单元，其中，
    对于所述阵列基板行驱动电路中的第n 级阵列基板行驱动单元，包括：第n-3级信号输入端、第n-2级信号输入端、第n+2级信号输入端、第一输出端、第二输出端、低电平输入端以及高频时钟信号输入端，n为大于3的正整数；
    其中，所述第n-3级信号输入端与第n-3级的阵列基板行驱动单元的第二输出端相连；所述第n-2级信号输入端与第n-2级的阵列基板行驱动单元的第一输出端相连；所述第n+2级信号输入端与第n+2级的阵列基板行驱动单元的第一输出端相连；所述第二输出端与第n+3级的阵列基板行驱动单元的第n-3级信号输入端相连；所述第一输出端与第n+2级的阵列基板行驱动单元的第n-2级信号输入端相连，且与第n-2级的阵列基板行驱动单元的第n+2级信号输入端相连，用于向显示区域的第n级水平扫描线提供扫描信号；
    所述第n 级阵列基板行驱动单元还包括：
    上拉控制单元，包括一第一薄膜晶体管，分别与所述第n-2级信号输入端、所述第n-3级信号输入端以及所述第二输出端连接，其中，所述第n-3级信号输入端的信号的峰值电压为所述第n-2级信号输入端的信号的峰值电压的两倍，用于上拉所述第二输出端的电位；
    上拉单元，分别与所述高频时钟信号输入端、所述第一输出端连接，并与所述上拉控制单元共同连接于所述第二输出端，用于对所述第一输出端的信号进行充电，以使所述第二输出端达到更高的电位；
    下拉控制单元，分别与低电平输入端、所述上拉控制单元及所述上拉单元连接，用于在所述第一输出端的信号处于非充电状态时，控制所述第二输出端和所述第一输出端保持低电位；
    下拉单元，分别与所述第n+2级信号输入端、所述低电平输入端、所述下拉控制单元连接，并与所述上拉单元及所述上拉控制单元共同连接于所述第二输出端，用于下拉所述第二输出端的电位。
  16. 根据权利要求15所述的液晶显示装置，其中所述显示区域具有水平扫描线，每条所述水平扫描线的两端各连接一个所述阵列基板行驱动单元，所述水平扫描线与所述阵列基板行驱动单元的第一输出端连接。
PCT/CN2014/079928 2014-05-26 2014-06-16 阵列基板行驱动电路及液晶显示装置 WO2015180214A1 (zh)

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