WO2016101392A1 - Amoled背板的制作方法及其结构 - Google Patents

Amoled背板的制作方法及其结构 Download PDF

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WO2016101392A1
WO2016101392A1 PCT/CN2015/072505 CN2015072505W WO2016101392A1 WO 2016101392 A1 WO2016101392 A1 WO 2016101392A1 CN 2015072505 W CN2015072505 W CN 2015072505W WO 2016101392 A1 WO2016101392 A1 WO 2016101392A1
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drain
source
layer
gate
electrode
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French (fr)
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徐源竣
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method and a structure for fabricating an AMOLED backplane.
  • OLED organic light emitting diodes
  • OLEDs can be classified into passive OLEDs (PMOLEDs) and active OLEDs (AMOLEDs) according to the type of driving.
  • the AMOLED is usually composed of a low temperature poly-Silicon (LTPS) driven backplane and an electroluminescent layer to form a self-illuminating component.
  • LTPS low temperature poly-Silicon
  • electroluminescent layer to form a self-illuminating component.
  • Low-temperature polysilicon has high electron mobility.
  • low-temperature polysilicon material has the advantages of high resolution, fast reaction speed, high brightness, high aperture ratio, and low energy consumption.
  • FIG. 1 The structure of an existing AMOLED backplane is shown in FIG.
  • the manufacturing process of the AMOLED backplane is generally as follows:
  • Step 1 depositing a buffer layer 200 on the substrate 100;
  • Step 2 depositing an amorphous silicon (a-Si) layer on the buffer layer 200, and crystallizing the amorphous silicon layer into a polysilicon (Poly-Si) layer by laser treatment;
  • Step 3 through the yellow light, etching process to pattern the polysilicon layer, forming a first polysilicon segment 301 and a second polysilicon segment 303 arranged at intervals;
  • Step 4 depositing an N-type heavily doped amorphous silicon layer N+a-Si on the buffer layer 200, the first polysilicon segment 301, and the second polysilicon segment 303, and defining a trench by a yellow light process
  • the N-type heavily doped amorphous silicon layer N+a-Si is patterned to form a source/drain 401 on the first polysilicon segment 301 except for the corresponding region of the channel 400.
  • Step 5 depositing and patterning the gate insulating layer 500 on the buffer layer 200, the source/drain 401, and the electrode 403;
  • Step 6 Depositing and patterning a first metal layer on the gate insulating layer 500 to form a gate 601, and a metal electrode 603; the gate 601 is located above the source/drain 401, and partially overlaps the source/drain 401 in the horizontal direction;
  • Step 7 sequentially forming an interlayer insulating layer 700, a metal source/drain 801, a flat layer 900, an anode 1000, and a pixel definition on the gate insulating layer 500, the gate electrode 601, and the metal electrode 603 by a deposition, a yellow light, and an etching process.
  • Layer 1100, and photoresist spacer 1200 sequentially forming an interlayer insulating layer 700, a metal source/drain 801, a flat layer 900, an anode 1000, and a pixel definition on the gate insulating layer 500, the gate electrode 601, and the metal electrode 603 by a deposition, a yellow light, and an etching process.
  • Layer 1100, and photoresist spacer 1200 sequentially forming an interlayer insulating layer 700, a metal source/drain 801, a flat layer 900, an anode 1000, and a pixel definition on the gate insulating layer 500, the gate electrode 601, and the metal electrode 603 by a
  • the metal source/drain 801 is electrically connected to the source/drain 401; the anode 1000 is electrically connected to the metal source/drain 801.
  • the first polysilicon segment 301, the source/drain 401, the gate 601 and the metal source/drain 801 constitute a driving TFT
  • the second polysilicon segment 303, the electrode 403 and the metal electrode 603 constitute a storage capacitor.
  • the driving TFT of the AMOLED backplane shown in FIG. 1 is an NMOS
  • the AMOLED panel is relatively easy to cause image sticking
  • the higher contact impedance between the drain 401 and the first polysilicon segment 301 causes the conduction current of the driving TFT to be lower, and the source/drain 401 and the gate 601 partially overlap in the horizontal direction, which may also cause The driving TFT leakage current is too high.
  • An object of the present invention is to provide a method for fabricating an AMOLED backplane, which can improve the electrical characteristics of the driving TFT, have a high on-current, a low leakage current, reduce image sticking, and improve display quality of the AMOLED.
  • Another object of the present invention is to provide an AMOLED backplane structure, which can improve the electrical characteristics of the driving TFT, make the on current higher, lower the leakage current, reduce image sticking, and improve the display quality of the AMOLED.
  • the present invention provides a method for fabricating an AMOLED backplane, which sequentially deposits a buffer layer and an amorphous silicon layer on the substrate, crystallizes the amorphous silicon layer, converts it into a polysilicon layer, and patterns the polysilicon layer, and then deposits a layer.
  • Layer P-type heavily doped microcrystalline silicon layer followed by a yellow light process to define the position of the channel, and then etching the P-type heavily doped microcrystalline silicon layer to form a source/drain, and subsequently forming a gate insulating layer a gate, an interlayer insulating layer, a metal source/drain, a flat layer, an anode, a pixel defining layer, and a photoresist spacer; the source/drain and the gate do not overlap in the horizontal direction and are spaced apart from each other.
  • the manufacturing method of the AMOLED backplane includes the following steps:
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing an amorphous silicon layer on the buffer layer, and performing an excimer laser annealing treatment on the amorphous silicon layer, so that the amorphous silicon layer is crystallized and converted into a polysilicon layer;
  • Step 3 patterning the polysilicon layer by a yellow light or an etching process to form a first polysilicon segment and a second polysilicon segment arranged at intervals;
  • Step 4 depositing a P-type heavily doped microcrystalline silicon layer on the buffer layer, the first polysilicon segment, and the second polysilicon segment, and then performing a yellow light process to define a position of the channel, and then P The heavily doped microcrystalline silicon layer is etched to pattern the P-type heavily doped microcrystalline silicon layer to form a source/drain on the first polysilicon segment except for the corresponding region of the channel, and located in the second An electrode on the crystalline silicon segment;
  • Step 5 depositing and patterning a gate insulating layer on the buffer layer, the source/drain, and the electrode;
  • Step 6 Depositing and patterning a first metal layer on the gate insulating layer to form a gate electrode and a metal electrode;
  • the gate is located above the channel; the source/drain and the gate are spaced apart from each other by a certain distance in a horizontal direction;
  • Step 7 sequentially forming an interlayer insulating layer, a metal source/drain, a flat layer, an anode, a pixel defining layer, and a photoresist spacer on the gate insulating layer, the gate electrode, and the metal electrode by a deposition, a yellow light, and an etching process. ;
  • the metal source/drain is electrically connected to the source/drain; the anode is electrically connected to the metal source/drain;
  • the first polysilicon segment, the source/drain, the gate and the metal source/drain constitute a driving TFT
  • the second polysilicon segment, the electrode and the metal electrode constitute a storage capacitor
  • a P-type heavily doped microcrystalline silicon layer is deposited by a CVD method.
  • the distance between the source/drain and the gate in the horizontal direction is 0.1 to 0.5 ⁇ m.
  • the material of the gate is a stack combination of one or more of molybdenum, titanium, aluminum, copper.
  • the material of the buffer layer is silicon nitride, silicon oxide, or a combination of the two; the material of the interlayer insulating layer is silicon oxide, silicon nitride, or a combination of the two.
  • the material of the anode is an indium tin oxide/silver/indium tin oxide composite film.
  • the present invention also provides an AMOLED backplane structure, including a substrate, a buffer layer disposed on the substrate, a first polysilicon segment and a second polysilicon segment disposed on the buffer layer, respectively a source/drain and an electrode disposed on the first polysilicon segment and the second polysilicon segment, a gate insulating layer disposed on the buffer layer, the source/drain electrodes, and the electrode, disposed at the a gate electrode and a metal electrode on the gate insulating layer, and an interlayer insulating layer, a metal source/drain, a flat layer, an anode, and a pixel defining layer sequentially disposed on the gate insulating layer, the gate and the metal electrode a photoresist source; the metal source/drain is electrically connected to the source/drain; the anode is electrically connected to the metal source/drain;
  • the material of the source/drain is P-type heavily doped microcrystalline silicon; the source/drain has a channel therebetween; the gate is located above the channel; the source/drain and the gate are horizontal Do not overlap in direction, and are spaced apart from each other;
  • the first polysilicon segment, the source/drain, the gate and the metal source/drain constitute a driving TFT
  • the second polysilicon segment, the electrode and the metal electrode constitute a storage capacitor
  • the distance between the source/drain and the gate in the horizontal direction is 0.1 to 0.5 ⁇ m.
  • the material of the gate is a stack combination of one or more of molybdenum, titanium, aluminum, copper; the material of the buffer layer is silicon nitride, silicon oxide, or a combination of the two; the interlayer insulation The material of the layer is silicon oxide, silicon nitride, or a combination of the two; the material of the anode is an indium tin oxide/silver/indium tin oxide composite film.
  • the present invention also provides an AMOLED backplane structure, including a substrate, a buffer layer disposed on the substrate, a first polysilicon segment and a second polysilicon segment disposed on the buffer layer, respectively a source/drain and an electrode disposed on the first polysilicon segment and the second polysilicon segment, a gate insulating layer disposed on the buffer layer, the source/drain electrodes, and the electrode, disposed at the a gate electrode and a metal electrode on the gate insulating layer, and an interlayer insulating layer, a metal source/drain, a flat layer, an anode, and a pixel defining layer sequentially disposed on the gate insulating layer, the gate and the metal electrode a photoresist source; the metal source/drain is electrically connected to the source/drain; the anode is electrically connected to the metal source/drain;
  • the material of the source/drain is P-type heavily doped microcrystalline silicon; the source/drain has a channel therebetween; the gate is located above the channel; the source/drain and the gate are horizontal Do not overlap in direction, and are spaced apart from each other;
  • the first polysilicon segment, the source/drain, the gate and the metal source/drain constitute a driving TFT, and the second polysilicon segment, the electrode and the metal electrode constitute a storage capacitor;
  • the distance between the source/drain and the gate in the horizontal direction is 0.1 to 0.5 ⁇ m;
  • the material of the gate is a stack combination of one or more of molybdenum, titanium, aluminum, copper;
  • the material of the buffer layer is silicon nitride, silicon oxide, or a combination of the two;
  • the material of the interlayer insulating layer is silicon oxide, silicon nitride, or a combination of the two;
  • the material of the anode is an indium tin oxide/silver/indium tin oxide composite film.
  • the present invention provides a method for fabricating an AMOLED backplane by depositing and patterning a P-type heavily doped microcrystalline silicon layer to form a source/drain, and to make the source/drain and gate at a level
  • the directions are spaced apart from each other, which can reduce the contact resistance between the source/drain and the first polysilicon segment, improve the electrical characteristics of the driving TFT, make the on current higher, lower the leakage current, reduce image sticking, and improve AMOLED.
  • the display quality of the present invention provides an AMOLED backplane structure by disposing a source/drain using P-type heavily doped microcrystalline silicon as a material, and setting the source/drain and the gate to be horizontally spaced from each other. The contact resistance between the source/drain and the first polysilicon segment can be reduced, the electrical characteristics of the driving TFT can be improved, the conduction current is high, the leakage current is low, image residual is reduced, and the display quality of the AMOLED is improved.
  • FIG. 1 is a schematic view of a conventional AMOLED backplane structure
  • FIG. 2 is a flow chart of a method for fabricating an AMOLED backplane according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating an AMOLED backplane according to the present invention
  • step 4 is a schematic diagram of step 4 of a method for fabricating an AMOLED backplane according to the present invention.
  • step 5 is a schematic diagram of step 5 of a method for fabricating an AMOLED backplane according to the present invention.
  • step 6 is a schematic diagram of step 6 of the method for fabricating an AMOLED backplane according to the present invention.
  • FIG. 7 is a schematic diagram of step 7 of the method for fabricating an AMOLED backplane of the present invention and the structure of the AMOLED backplane of the present invention.
  • the present invention provides a method for fabricating an AMOLED backplane, including the following steps:
  • Step 1 A substrate 1 is provided, and a buffer layer 2 is deposited on the substrate 1.
  • the substrate 1 is a transparent substrate.
  • the substrate 1 is a glass substrate or a plastic substrate.
  • the material of the buffer layer 2 is silicon nitride (SiNx), silicon oxide (SiOx), or a combination of both.
  • Step 2 depositing an amorphous silicon layer on the buffer layer 2, and performing an excimer laser annealing treatment on the amorphous silicon layer, so that the amorphous silicon layer is crystallized and converted into a polysilicon layer.
  • Step 3 As shown in FIG. 3, the polysilicon layer is patterned by a yellow light or etching process to form a first polysilicon segment 31 and a second polysilicon segment 33 arranged at intervals.
  • Step 4 as shown in FIG. 4, a P-type heavily doped is deposited on the buffer layer 2, the first polysilicon segment 31, and the second polysilicon segment 33 by a chemical vapor deposition (CVD) method.
  • CVD chemical vapor deposition
  • Step 5 as shown in FIG. 5, a gate insulating layer 5 is deposited and patterned on the buffer layer 2, the source/drain electrodes 41, and the electrodes 43.
  • Step 6 As shown in FIG. 6, a first metal layer is deposited and patterned on the gate insulating layer 5 to form a gate electrode 61 and a metal electrode 63.
  • the gate 61 is located above the channel 40; the source/drain 41 and the gate 61 are spaced apart from each other in the horizontal direction. Further, the distance between the source/drain 41 and the gate 61 in the horizontal direction is 0.1 to 0.5 ⁇ m.
  • the material of the gate electrode 61 and the metal electrode 63 may be a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Step 7 as shown in FIG. 7, the interlayer insulating layer 7, the metal source/drain 81, and the flat layer 9 are sequentially formed on the gate insulating layer 5, the gate electrode 61, and the metal electrode 63 by a deposition, yellow light, and etching process.
  • the metal source/drain 81 is electrically connected to the source/drain 41; the anode 10 is electrically connected to the metal source/drain 81.
  • the material of the interlayer insulating layer 7 is silicon oxide, silicon nitride, or a combination of the two.
  • the material of the anode 10 is an indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO) composite film.
  • the first polysilicon segment 31, the source/drain 41, the gate 61 and the metal source/drain 81 constitute a driving TFT
  • the second polysilicon segment 33, the electrode 43 and the metal electrode 63 constitute a storage capacitor.
  • the source/drain 41 is obtained by depositing and patterning a P-type heavily doped microcrystalline silicon layer P+uc-Si, so that the driving TFT is a P-type TFT, and the P
  • the TFT driving the AMOLED can reduce the image residue and improve the display quality of the AMOLED.
  • the source/drain 41 and the first polysilicon segment 31 are The contact resistance between the electrodes is lowered, the electrical characteristics of the driving TFT are improved, and the on-current is high; the source/drain 41 and the gate 61 are spaced apart from each other in the horizontal direction, and there is no overlapping region, which can reduce leakage of the driving TFT. Current.
  • the present invention further provides an AMOLED backplane structure, including a substrate 1 , a buffer layer 2 disposed on the substrate 1 , and first spaced polysilicon segments disposed on the buffer layer 2 .
  • 31 and the second polysilicon segment 33, the source/drain electrodes 41 and the electrodes 43 respectively disposed on the first polysilicon segment 31 and the second polysilicon segment 33, are disposed on the buffer layer 2, and are provided on the buffer layer 2 a drain insulating layer 5, a gate insulating layer 5 on the electrode 43, a gate electrode 61 and a metal electrode 63 provided on the gate insulating layer 5, and a gate insulating layer 5 and a gate electrode 61 in this order.
  • the metal source/drain 81 is electrically connected to the source/drain electrodes 41.
  • the anode 10 is electrically connected to the metal source/drain 81.
  • the first polysilicon segment 31, the source/drain 41, the gate 61 and the metal source/drain 81 constitute a driving TFT, and the second polysilicon segment 33, the electrode 43 and the metal electrode 63 constitute a storage capacitor.
  • the material of the source/drain 41 is P-type heavily doped microcrystalline silicon (P+uc-Si); the source/drain 41 has a channel 40 therebetween; the gate 61 is located above the channel 40
  • the source/drain electrodes 41 and the gate electrode 61 do not overlap each other in the horizontal direction, and are spaced apart from each other. Further, the distance between the source/drain electrodes 41 and the gate electrodes 61 in the horizontal direction is 0.1 to 0.5 ⁇ m.
  • the substrate 1 is a transparent substrate.
  • the substrate 1 is a glass substrate or a plastic substrate.
  • the material of the gate electrode 61 is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the buffer layer 2 is silicon nitride, silicon oxide, or a combination of the two.
  • the material of the interlayer insulating layer 7 is silicon oxide, silicon nitride, or a combination of the two.
  • the material of the anode 10 is an indium tin oxide/silver/indium tin oxide composite film.
  • the material of the source/drain 41 is P-type heavily doped microcrystalline silicon P+uc-Si, so that the driving TFT is a P-type TFT, and the driving of the AMOLED by the P-type TFT can be reduced.
  • Image retention improves the display quality of the AMOLED; meanwhile, since the material properties of the P-type heavily doped microcrystalline silicon and the polycrystalline silicon are relatively close, the contact resistance between the source/drain 41 and the first polysilicon segment 31 is reduced.
  • the electrical characteristics of the driving TFT are improved, and the on-current is high.
  • the source/drain 41 and the gate 61 are spaced apart from each other in the horizontal direction, and there is no overlapping region, so that the leakage current of the driving TFT can be reduced.
  • the method for fabricating the AMOLED backplane of the present invention forms a source/drain by depositing and patterning a P-type heavily doped microcrystalline silicon layer, and spacing the source/drain and the gate in the horizontal direction.
  • the contact resistance between the source/drain and the first polysilicon segment can be reduced, the electrical characteristics of the driving TFT can be improved, the conduction current is higher, the leakage current is lower, the image residual is reduced, and the display quality of the AMOLED is improved;
  • the AMOLED backplane structure of the present invention can reduce the source/drain with the source/drain of the P-type heavily doped microcrystalline silicon as a material, and the source/drain and the gate are spaced apart from each other in the horizontal direction.
  • the contact resistance between the first polysilicon segments improves the electrical characteristics of the driving TFT, causes higher on-current, lower leakage current, and reduces image sticking, thereby improving the display quality of the AMOLED.

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Abstract

一种AMOLED背板的制作方法及其结构。该AMOLED背板的制作方法为：依次在基板(1)上沉积缓冲层(2)、非晶硅层，使非晶硅层结晶、转变为多晶硅层并图案化多晶硅层，然后沉积一层P型重掺杂微晶硅层(P+ uc-Si)，接着进行黄光制程定义出沟道(40)的位置，再对P型重掺杂微晶硅层(P+ uc-Si)进行蚀刻，形成源/漏极(41)，后续依次形成栅极绝缘层(5)、栅极(61)、层间绝缘层(7)、金属源/漏极(81)、平坦层(9)、阳极(10)、像素定义层(11)、及光阻间隙物(12)；所述源/漏极(41)与栅极(61)在水平方向上不重叠，相互间隔。该方法能够改善驱动TFT的电特性，使导通电流较高、漏电流较低，并减少图像残留，提高AMOLED的显示质量。

Description

AMOLED背板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种AMOLED背板的制作方法及其结构。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示技术已经逐步取代CRT显示器。其中，OLED具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED按照驱动类型可分为无源OLED(PMOLED)和有源OLED(AMOLED)。其中，AMOLED通常是由低温多晶硅(Low Temperature Poly-Silicon，LTPS)驱动背板和电激发光层组成自发光组件。低温多晶硅具有较高的电子迁移率，对AMOLED而言，采用低温多晶硅材料具有高分辨率、反应速度快、高亮度、高开口率、低能耗等优点。
现有的一种AMOLED背板的结构如图1所示。该AMOLED背板的制作过程大体为：
步骤1、在基板100上沉积缓冲层200；
步骤2、在缓冲层200上沉积非晶硅(a-Si)层，经激光(Laser)处理使非晶硅层结晶、转变为多晶硅(Poly-Si)层；
步骤3、通过黄光、蚀刻制程对多晶硅层进行图案化处理，形成间隔排列的第一多晶硅段301与第二多晶硅段303；
步骤4、在所述缓冲层200、第一多晶硅段301、与第二多晶硅段303上沉积N型重掺杂非晶硅层N+a-Si，并用黄光制程定义出沟道400的位置后再进行蚀刻，使N型重掺杂非晶硅层N+a-Si图案化，形成除沟道400对应区域以外位于第一多晶硅段301上的源/漏极401、及位于第二多晶硅段303上的电极403；
步骤5、在所述缓冲层200、源/漏极401、与电极403上沉积并图案化栅极绝缘层500；
步骤6、在所述栅极绝缘层500上沉积并图案化第一金属层，形成栅极 601、及金属电极603；所述栅极601位于源/漏极401上方，并在水平方向上与源/漏极401有部分重叠；
步骤7、通过沉积、黄光、蚀刻制程在栅极绝缘层500、栅极601及金属电极603上依次形成层间绝缘层700、金属源/漏极801、平坦层900、阳极1000、像素定义层1100、及光阻间隙物1200。
金属源/漏极801电性连接于源/漏极401；阳极1000电性连接于金属源/漏极801。
所述第一多晶硅段301、源/漏极401、栅极601与金属源/漏极801构成驱动TFT，所述第二多晶硅段303、电极403与金属电极603构成存储电容。
由于如图1所示的AMOLED背板的驱动TFT为NMOS，AMOLED面板比较容易产生图像残留(Image Sticking)的现象，另外由N型重掺杂非晶硅层N+a-Si形成的源/漏极401与由第一多晶硅段301的接触阻抗较高，会导致驱动TFT的导通电流较低，而源/漏极401与栅极601在水平方向上有部分重叠，还会导致驱动TFT漏电流过高。
发明内容
本发明的目的在于提供一种AMOLED背板的制作方法，能够改善驱动TFT的电特性，使导通电流较高、漏电流较低，并减少图像残留，提高AMOLED的显示质量。
本发明的目的还在于提供一种AMOLED背板结构，能够改善驱动TFT的电特性，使导通电流较高、漏电流较低，并减少图像残留，提高AMOLED的显示质量。
为实现上述目的，本发明提供一种AMOLED背板的制作方法，依次在基板上沉积缓冲层、非晶硅层，使非晶硅层结晶、转变为多晶硅层并图案化多晶硅层，然后沉积一层P型重掺杂微晶硅层，接着进行黄光制程定义出沟道的位置，再对P型重掺杂微晶硅层进行蚀刻，形成源/漏极，后续依次形成栅极绝缘层、栅极、层间绝缘层、金属源/漏极、平坦层、阳极、像素定义层、及光阻间隙物；所述源/漏极与栅极在水平方向上不重叠，相互间隔。
所述AMOLED背板的制作方法，包括如下步骤：
步骤1、提供一基板，在该基板上沉积缓冲层；
步骤2、在缓冲层上沉积非晶硅层，并对非晶硅层进行准分子激光退火处理，使得该非晶硅层结晶、转变为多晶硅层；
步骤3、通过黄光、蚀刻制程对多晶硅层进行图案化处理，形成间隔排列的第一多晶硅段与第二多晶硅段；
步骤4、在所述缓冲层、第一多晶硅段、与第二多晶硅段上沉积P型重掺杂微晶硅层，接着进行黄光制程定义出沟道的位置，再对P型重掺杂微晶硅层进行蚀刻，使P型重掺杂微晶硅层图案化，形成除沟道对应区域以外位于第一多晶硅段上的源/漏极、及位于第二多晶硅段上的电极；
步骤5、在所述缓冲层、源/漏极、与电极上沉积并图案化栅极绝缘层；
步骤6、在所述栅极绝缘层上沉积并图案化第一金属层，形成栅极、及金属电极；
所述栅极位于沟道上方；所述源/漏极与栅极在水平方向上相互间隔一定距离；
步骤7、通过沉积、黄光、蚀刻制程在栅极绝缘层、栅极及金属电极上依次形成层间绝缘层、金属源/漏极、平坦层、阳极、像素定义层、及光阻间隙物；
所述金属源/漏极电性连接于源/漏极；所述阳极电性连接于金属源/漏极；
所述第一多晶硅段、源/漏极、栅极与金属源/漏极构成驱动TFT，所述第二多晶硅段、电极与金属电极构成存储电容。
所述步骤4中采用CVD法沉积P型重掺杂微晶硅层。
所述源/漏极与栅极在水平方向上相互间隔的距离为0.1～0.5μm。
所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述缓冲层的材料为氮化硅、氧化硅、或二者的组合；所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
所述阳极的材料为氧化铟锡/银/氧化铟锡复合薄膜。
本发明还提供一种AMOLED背板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的间隔排列的第一多晶硅段与第二多晶硅段、分别设于所述第一多晶硅段与第二多晶硅段上的源/漏极与电极、设于所述缓冲层、源/漏极、与电极上的栅极绝缘层、设于所述栅极绝缘层上的栅极与金属电极、及依次设于所述栅极绝缘层、栅极与金属电极上的层间绝缘层、金属源/漏极、平坦层、阳极、像素定义层、光阻间隙物；所述金属源/漏极电性连接于源/漏极；所述阳极电性连接于金属源/漏极；
所述源/漏极的材料为P型重掺杂微晶硅；所述源/漏极之间具有沟道；所述栅极位于沟道上方；所述源/漏极与栅极在水平方向上不重叠，相互间隔；
所述第一多晶硅段、源/漏极、栅极与金属源/漏极构成驱动TFT，所述第二多晶硅段、电极与金属电极构成存储电容。
所述源/漏极与栅极在水平方向上相互间隔的距离为0.1～0.5μm。
所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层的材料为氮化硅、氧化硅、或二者的组合；所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述阳极的材料为氧化铟锡/银/氧化铟锡复合薄膜。
本发明还提供一种AMOLED背板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的间隔排列的第一多晶硅段与第二多晶硅段、分别设于所述第一多晶硅段与第二多晶硅段上的源/漏极与电极、设于所述缓冲层、源/漏极、与电极上的栅极绝缘层、设于所述栅极绝缘层上的栅极与金属电极、及依次设于所述栅极绝缘层、栅极与金属电极上的层间绝缘层、金属源/漏极、平坦层、阳极、像素定义层、光阻间隙物；所述金属源/漏极电性连接于源/漏极；所述阳极电性连接于金属源/漏极；
所述源/漏极的材料为P型重掺杂微晶硅；所述源/漏极之间具有沟道；所述栅极位于沟道上方；所述源/漏极与栅极在水平方向上不重叠，相互间隔；
所述第一多晶硅段、源/漏极、栅极与金属源/漏极构成驱动TFT，所述第二多晶硅段、电极与金属电极构成存储电容；
其中，所述源/漏极与栅极在水平方向上相互间隔的距离为0.1～0.5μm；
其中，所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层的材料为氮化硅、氧化硅、或二者的组合；所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述阳极的材料为氧化铟锡/银/氧化铟锡复合薄膜。
本发明的有益效果：本发明提供的一种AMOLED背板的制作方法，通过沉积并图案化P型重掺杂微晶硅层形成源/漏极，并使源/漏极与栅极在水平方向上相互间隔，能够降低源/漏极与第一多晶硅段之间的接触阻抗，改善驱动TFT的电特性，使导通电流较高、漏电流较低，并减少图像残留，提高AMOLED的显示质量；本发明提供的一种AMOLED背板结构，通过设置以P型重掺杂微晶硅为材料的源/漏极，并设置源/漏极与栅极在水平方向上相互间隔，能够降低源/漏极与第一多晶硅段之间的接触阻抗，改善驱动TFT的电特性，使导通电流较高、漏电流较低，并减少图像残留，提高AMOLED的显示质量。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有的AMOLED背板结构的示意图；
图2为本发明AMOLED背板制作方法的流程图；
图3为本发明AMOLED背板制作方法的步骤3的示意图；
图4为本发明AMOLED背板制作方法的步骤4的示意图；
图5为本发明AMOLED背板制作方法的步骤5的示意图；
图6为本发明AMOLED背板制作方法的步骤6的示意图；
图7为本发明AMOLED背板制作方法的步骤7暨本发明AMOLED背板结构的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图2至图7，本发明提供一种AMOLED背板的制作方法，包括如下步骤：
步骤1、提供一基板1，在该基板1上沉积缓冲层2。
所述基板1为透明基板，优选的，所述基板1为玻璃基板或塑料基板。
所述缓冲层2的材料为氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。
步骤2、在缓冲层2上沉积非晶硅层，并对非晶硅层进行准分子激光退火处理，使得该非晶硅层结晶、转变为多晶硅层。
步骤3、如图3所示，通过黄光、蚀刻制程对多晶硅层进行图案化处理，形成间隔排列的第一多晶硅段31与第二多晶硅段33。
步骤4、如图4所示，采用化学气相沉积(Chemical Vapor Deposition，CVD)法在所述缓冲层2、第一多晶硅段31、与第二多晶硅段33上沉积P型重掺杂微晶硅(P+micro-crystallized Si)层P+uc-Si，接着进行黄光制程定义出沟道40的位置，再对P型重掺杂微晶硅层P+uc-Si进行蚀刻，使P型重掺杂微晶硅层P+uc-Si图案化，形成除沟道40对应区域以外位于第一多晶硅段31上的源/漏极41、及位于第二多晶硅段33上的电极43。
步骤5、如图5所示，在所述缓冲层2、源/漏极41、与电极43上沉积并图案化栅极绝缘层5。
步骤6、如图6所示，在所述栅极绝缘层5上沉积并图案化第一金属层，形成栅极61、及金属电极63。
所述栅极61位于沟道40上方；所述源/漏极41与栅极61在水平方向上相互间隔一定距离。进一步的，所述源/漏极41与栅极61在水平方向上相互间隔的距离为0.1～0.5μm。
所述栅极61及金属电极63的材料可为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
步骤7、如图7所示，通过沉积、黄光、蚀刻制程在栅极绝缘层5、栅极61及金属电极63上依次形成层间绝缘层7、金属源/漏极81、平坦层9、阳极10、像素定义层11、及光阻间隙物12。
所述金属源/漏极81电性连接于源/漏极41；所述阳极10电性连接于金属源/漏极81。
所述层间绝缘层7的材料为氧化硅、氮化硅、或二者的组合。所述阳极10的材料为氧化铟锡/银/氧化铟锡(ITO/Ag/ITO)复合薄膜。
所述第一多晶硅段31、源/漏极41、栅极61与金属源/漏极81构成驱动TFT，所述第二多晶硅段33、电极43与金属电极63构成存储电容。
上述AMOLED背板的制作方法中，所述源/漏极41通过沉积并图案化P型重掺杂微晶硅层P+uc-Si得到，从而所述驱动TFT为P型TFT，由该P型TFT驱动AMOLED可以减少图像残留，提高AMOLED的显示质量；同时，由于P型重掺杂微晶硅与多晶硅的材料特性较为接近，所述源/漏极41与第一多晶硅段31之间的接触阻抗得以降低，改善了驱动TFT的电特性，使导通电流较高；所述源/漏极41与栅极61在水平方向上相互间隔，没有重叠区域，能够降低驱动TFT的漏电流。
请参阅图7，本发明还提供一种AMOLED背板结构，包括基板1、设于所述基板1上的缓冲层2、设于所述缓冲层2上的间隔排列的第一多晶硅段31与第二多晶硅段33、分别设于所述第一多晶硅段31与第二多晶硅段33上的源/漏极41与电极43、设于所述缓冲层2、源/漏极41、与电极43上的栅极绝缘层5、设于所述栅极绝缘层5上的栅极61与金属电极63、及依次设于所述栅极绝缘层5、栅极61与金属电极63上的层间绝缘层7、金属源/漏极81、平坦层9、阳极10、像素定义层11、光阻间隙物12。
所述金属源/漏极81电性连接于源/漏极41。所述阳极10电性连接于金属源/漏极81。所述第一多晶硅段31、源/漏极41、栅极61与金属源/漏极81构成驱动TFT，所述第二多晶硅段33、电极43与金属电极63构成存储电容。
所述源/漏极41的材料为P型重掺杂微晶硅(P+uc-Si)；所述源/漏极41之间具有沟道40；所述栅极61位于沟道40上方；所述源/漏极41与栅极61在水平方向上不重叠，相互间隔，进一步的，所述源/漏极41与栅极61在水平方向上相互间隔的距离为0.1～0.5μm。
具体的，所述基板1为透明基板，优选的，所述基板1为玻璃基板或塑料基板。所述栅极61的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。所述缓冲层2的材料为氮化硅、氧化硅、或二者的组合。所述层间绝缘层7的材料为氧化硅、氮化硅、或二者的组合。所述阳极10的材料为氧化铟锡/银/氧化铟锡复合薄膜。
上述AMOLED背板结构，设置所述源/漏极41的材料为P型重掺杂微晶硅P+uc-Si，从而所述驱动TFT为P型TFT，由该P型TFT驱动AMOLED可以减少图像残留，提高AMOLED的显示质量；同时，由于P型重掺杂微晶硅与多晶硅的材料特性较为接近，所述源/漏极41与第一多晶硅段31之间的接触阻抗得以降低，改善了驱动TFT的电特性，使导通电流较高；设置所述源/漏极41与栅极61在水平方向上相互间隔，没有重叠区域，能够降低驱动TFT的漏电流。
综上所述，本发明的AMOLED背板的制作方法，通过沉积并图案化P型重掺杂微晶硅层形成源/漏极，并使源/漏极与栅极在水平方向上相互间隔，能够降低源/漏极与第一多晶硅段之间的接触阻抗，改善驱动TFT的电特性，使导通电流较高、漏电流较低，并减少图像残留，提高AMOLED的显示质量；本发明的AMOLED背板结构，通过设置以P型重掺杂微晶硅为材料的源/漏极，并设置源/漏极与栅极在水平方向上相互间隔，能够降低源/漏极与第一多晶硅段之间的接触阻抗，改善驱动TFT的电特性，使导通电流较高、漏电流较低，并减少图像残留，提高AMOLED的显示质量。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种AMOLED背板的制作方法，依次在基板上沉积缓冲层、非晶硅层，使非晶硅层结晶、转变为多晶硅层并图案化多晶硅层，然后沉积一层P型重掺杂微晶硅层，接着进行黄光制程定义出沟道的位置，再对P型重掺杂微晶硅层进行蚀刻，形成源/漏极，后续依次形成栅极绝缘层、栅极、层间绝缘层、金属源/漏极、平坦层、阳极、像素定义层、及光阻间隙物；所述源/漏极与栅极在水平方向上不重叠，相互间隔。
  2. 如权利要求1所述的AMOLED背板的制作方法，其中，包括如下步骤：
    步骤1、提供一基板，在该基板上沉积缓冲层；
    步骤2、在缓冲层上沉积非晶硅层，并对非晶硅层进行准分子激光退火处理，使得该非晶硅层结晶、转变为多晶硅层；
    步骤3、通过黄光、蚀刻制程对多晶硅层进行图案化处理，形成间隔排列的第一多晶硅段与第二多晶硅段；
    步骤4、在所述缓冲层、第一多晶硅段、与第二多晶硅段上沉积P型重掺杂微晶硅层，接着进行黄光制程定义出沟道的位置，再对P型重掺杂微晶硅层进行蚀刻，使P型重掺杂微晶硅层图案化，形成除沟道对应区域以外位于第一多晶硅段上的源/漏极、及位于第二多晶硅段上的电极；
    步骤5、在所述缓冲层、源/漏极、与电极上沉积并图案化栅极绝缘层；
    步骤6、在所述栅极绝缘层上沉积并图案化第一金属层，形成栅极、及金属电极；
    所述栅极位于沟道上方；所述源/漏极与栅极在水平方向上相互间隔一定距离；
    步骤7、通过沉积、黄光、蚀刻制程在栅极绝缘层、栅极及金属电极上依次形成层间绝缘层、金属源/漏极、平坦层、阳极、像素定义层、及光阻间隙物；
    所述金属源/漏极电性连接于源/漏极；所述阳极电性连接于金属源/漏极；
    所述第一多晶硅段、源/漏极、栅极与金属源/漏极构成驱动TFT，所述第二多晶硅段、电极与金属电极构成存储电容。
  3. 如权利要求2所述的AMOLED背板的制作方法，其中，所述步骤4中采用CVD法沉积P型重掺杂微晶硅层。
  4. 如权利要求2所述的AMOLED背板的制作方法，其中，所述源/漏极与栅极在水平方向上相互间隔的距离为0.1～0.5μm。
  5. 如权利要求2所述的AMOLED背板的制作方法，其中，所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  6. 如权利要求2所述的AMOLED背板的制作方法，其中，所述缓冲层的材料为氮化硅、氧化硅、或二者的组合；所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
  7. 如权利要求2所述的AMOLED背板的制作方法，其中，所述阳极的材料为氧化铟锡/银/氧化铟锡复合薄膜。
  8. 一种AMOLED背板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的间隔排列的第一多晶硅段与第二多晶硅段、分别设于所述第一多晶硅段与第二多晶硅段上的源/漏极与电极、设于所述缓冲层、源/漏极、与电极上的栅极绝缘层、设于所述栅极绝缘层上的栅极与金属电极、及依次设于所述栅极绝缘层、栅极与金属电极上的层间绝缘层、金属源/漏极、平坦层、阳极、像素定义层、光阻间隙物；所述金属源/漏极电性连接于源/漏极；所述阳极电性连接于金属源/漏极；
    所述源/漏极的材料为P型重掺杂微晶硅；所述源/漏极之间具有沟道；所述栅极位于沟道上方；所述源/漏极与栅极在水平方向上不重叠，相互间隔；
    所述第一多晶硅段、源/漏极、栅极与金属源/漏极构成驱动TFT，所述第二多晶硅段、电极与金属电极构成存储电容。
  9. 如权利要求8所述的AMOLED背板结构，其中，所述源/漏极与栅极在水平方向上相互间隔的距离为0.1～0.5μm。
  10. 如权利要求8所述的AMOLED背板结构，其中，所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层的材料为氮化硅、氧化硅、或二者的组合；所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述阳极的材料为氧化铟锡/银/氧化铟锡复合薄膜。
  11. 一种AMOLED背板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的间隔排列的第一多晶硅段与第二多晶硅段、分别设于所述第一多晶硅段与第二多晶硅段上的源/漏极与电极、设于所述缓冲层、源/漏极、与电极上的栅极绝缘层、设于所述栅极绝缘层上的栅极与金属电极、及依次设于所述栅极绝缘层、栅极与金属电极上的层间绝缘层、金属源/漏极、平坦层、阳极、像素定义层、光阻间隙物；所述金属源/漏极电性连接于源/漏极；所述阳极电性连接于金属源/漏极；
    所述源/漏极的材料为P型重掺杂微晶硅；所述源/漏极之间具有沟道；所述栅极位于沟道上方；所述源/漏极与栅极在水平方向上不重叠，相互间隔；
    所述第一多晶硅段、源/漏极、栅极与金属源/漏极构成驱动TFT，所述第二多晶硅段、电极与金属电极构成存储电容；
    其中，所述源/漏极与栅极在水平方向上相互间隔的距离为0.1～0.5μm；
    其中，所述栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层的材料为氮化硅、氧化硅、或二者的组合；所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述阳极的材料为氧化铟锡/银/氧化铟锡复合薄膜。
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