WO2016065834A1 - 移位寄存器单元及其驱动方法、移位寄存器电路、及显示装置 - Google Patents
移位寄存器单元及其驱动方法、移位寄存器电路、及显示装置 Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/061—Details of flat display driving waveforms for resetting or blanking
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/061—Details of flat display driving waveforms for resetting or blanking
- G09G2310/063—Waveforms for resetting the whole screen at once
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Definitions
- the present invention relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a shift register circuit, and a display device.
- the GOA Gate Drive on Array
- the GOA circuit includes a plurality of GOA units, and each GOA unit corresponds to one gate drive output, thereby realizing the function of the gate drive circuit IC.
- the technical problem to be solved by the present invention is how to avoid erroneous operations caused by the reset terminal in the GOA unit.
- a shift register unit including:
- a charging module connected to the gate start end, the first clock end, and the storage capacitor, for storing the memory under the control of the gate start end and the first clock end
- the storage capacitor is charged to a high level
- An output control module coupled to the second clock terminal, the storage capacitor, and the gate output terminal for outputting a level signal of the second clock terminal to the Gate output terminal;
- a reset module comprising a second transistor, a fourth transistor and a fifth transistor, a gate of the second transistor being connected to the reset terminal, a source being connected to the first end of the storage capacitor, and a drain and the first a gate of a five transistor, a gate of the fourth transistor is connected to the reset terminal, a source is connected to the gate output terminal, a drain is connected to the low level terminal, and a source of the fifth transistor a pole connected to the first end of the storage capacitor, a drain connected to the low level end; the second transistor and the fifth transistor being configured to connect the first end of the storage capacitor with the control of the reset terminal The low level terminal is connected, and the fourth transistor is configured to connect the gate output terminal to the low level end under the control of the reset terminal.
- the gate turn-on voltage of the fifth transistor is greater than the gate turn-on voltage of the second transistor.
- the charging module includes a first transistor and a sixth transistor, a gate and a source of the first transistor are connected to the gate start end, and a drain is connected to the first end of the storage capacitor. Charging the storage capacitor when the gate start terminal is at a high level, the gate of the sixth transistor is connected to the first clock terminal, the source is connected to the gate start terminal, and the drain is A first end of the storage capacitor is coupled to charge the storage capacitor when the gate enable terminal and the first clock terminal are at a high level.
- the output control module includes a third transistor, a gate of the third transistor is connected to a first end of the storage capacitor, a source is connected to the second clock terminal, and a drain and the gate are connected An output terminal, the gate output terminal and the storage capacitor The second terminal is configured to output a level signal of the second clock terminal to the gate output terminal when the first end of the storage capacitor is at a high level.
- the present invention also provides a driving method of the above shift register unit, comprising:
- a high level is applied to the gate start end and the first clock end, and a low level is applied to the second clock end, so that the charging module is at the gate start end and the first clock Charging the storage capacitor to a high level under the control of the terminal, and causing the gate output terminal to output the low level of the second clock terminal specifically includes:
- a low level is applied to the gate start end and the first clock end
- a high level is applied to the second clock end
- the output control module controls the gate while the storage capacitor remains at a high level.
- the output terminal outputs a high level of the second clock terminal, which specifically includes:
- the present invention also provides a shift register circuit comprising a plurality of cascaded shift register units for feeding back a gate output signal of a shift register unit of a next stage to a reset terminal of a shift register unit of a previous stage.
- the present invention also provides a display device comprising the above shift register circuit.
- 1 is a schematic structural diagram of a shift register circuit
- FIG. 2 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention.
- FIG. 3 is a timing chart showing the operation of the shift register unit of FIG. 2.
- the present invention provides a shift register unit including: a gate start terminal STV, a first clock terminal CLKB, a second clock terminal CLK, a reset terminal Reset, a low level terminal VSS, and a gate output terminal.
- a gate start terminal STV a gate start terminal STV
- a first clock terminal CLKB a first clock terminal CLKB
- a second clock terminal CLK a reset terminal Reset
- a low level terminal VSS a gate output terminal.
- OUT storage capacitor C1, charging module, output control module and reset module.
- the charging module is connected to the gate start terminal STV, the first clock terminal CLKB and the storage capacitor C1 for charging the storage capacitor C1 to a high level under the control of the gate start terminal STV and the first clock terminal CLKB. That is, the node PU in FIG. 2 is at a high level.
- the output control module is connected to the second clock terminal CLK, the storage capacitor C1 and the gate output terminal OUT for using the second clock terminal when the storage capacitor C1 is at a high level A level signal of CLK is output to the gate output terminal OUT.
- the reset module is connected to the reset terminal Reset, the low level terminal VSS, the storage capacitor C1 device and the gate output terminal OUT for connecting both ends of the storage capacitor C1 and the gate under the control of the reset terminal Reset
- the pole output terminal OUT is connected to the low level terminal VSS.
- the reset module includes a second transistor M2, a fourth transistor M4, and a fifth transistor M5.
- the gate of the second transistor M2 is connected to the reset terminal Reset, the source is connected to the first end of the storage capacitor C1, and the drain is connected to the gate of the fifth transistor M5.
- the gate of the fourth transistor M4 is connected to the reset terminal Reset, the source is connected to the gate output terminal OUT, and the drain is connected to the low-level terminal VSS.
- the source of the fifth transistor M5 is connected to the first end of the storage capacitor C1, and the drain is connected to the low level terminal VSS.
- the second transistor M2 and the fifth transistor M5 are configured to connect the first end of the storage capacitor C1 to the low level terminal VSS under the control of the reset terminal Reset.
- the fourth transistor M4 is configured to connect the gate output terminal OUT to the low level terminal VSS under the control of the reset terminal Reset.
- the second transistor M2 When the Reset signal is unstable and fluctuates, the second transistor M2 is in a micro-on state, and the voltage of the node P1 is insufficient to turn on the fifth transistor M5. At this time, the first end of the storage capacitor C1, that is, the voltage of the node PU does not It is pulled to the low level terminal VSS, so the shift register unit does not cause an erroneous reset operation due to the instability of the Reset signal.
- the charging module includes a first transistor M1 and a sixth transistor M6.
- the gate and the source of the first transistor M1 are connected to the gate start terminal STV, and the drain is connected to the first end of the storage capacitor C1 for using the gate start terminal STV at a high level.
- the storage capacitor C1 is charged.
- the gate of the sixth transistor M6 is connected to the first clock terminal CLKB, the source is connected to the gate start terminal STV, and the drain is connected to the first end of the storage capacitor C1 for the gate.
- the storage capacitor C1 is charged when the start terminal STV and the first clock terminal CLKB are at a high level.
- the output control module includes a third transistor M3.
- a gate of the third transistor M3 is connected to a first end of the storage capacitor C1, a source is connected to the second clock terminal CLK, a drain is connected to the gate output terminal OUT, and a gate output terminal OUT With the stated The second end of the storage capacitor C1 is connected.
- the third transistor M3 is configured to output a level signal of the second clock terminal CLK to the gate output terminal OUT when the first end of the storage capacitor C1 is at a high level.
- a gate turn-on voltage of the fifth transistor M5 is greater than a gate turn-on voltage of the second transistor M2. This ensures that the voltage of the node P1 cannot turn on the fifth transistor M5 when the second transistor M2 is micro-conducting.
- phase 1 the STV terminal and the CLKB terminal are at a high level, and the CLK terminal is at a low level.
- the transistors M1 and M6 are turned on, and the voltage of the node PU is pulled high to charge the storage capacitor C1.
- Transistor M3 is turned on, and the OUT terminal outputs a low level at the CLK terminal.
- phase 2 the STV terminal and the CLKB terminal are at a low level, the CLK terminal is at a high level, the storage capacitor C1 maintains a high level of the node PU, the transistor M3 is turned on, and the OUT terminal outputs a high level at the CLK terminal.
- phase 3 when the high level of the OUT terminal of the next stage shift register unit is fed back to the current stage shift register unit, that is, the Reset terminal is at a high level, and at this time, the transistor M2 is turned on, and the voltage of the node P1 is pulled high. At the same time, the transistor M5 is turned on, and the voltage of the node PU is pulled to the low level of the VSS terminal to realize the reset of the shift register unit. At the same time, the transistor M4 is turned on, and the voltage at the OUT terminal is pulled to the low level of the VSS terminal, and the output of the shift register unit is turned off, that is, the OUT terminal stops outputting the high level.
- the transistor M2 when the Reset signal is unstable and fluctuates, the transistor M2 is in a micro-on state, and the voltage of the node P1 is insufficient to turn on the transistor M5. At this time, the voltage of the node PU is not pulled to the VSS, so The bit register unit does not cause an erroneous reset operation due to the instability of the Reset signal. That is, only when the transistor M2 and the transistor M5 are simultaneously turned on, the shift register unit can complete the correct reset operation.
- the invention also provides a driving method of the above shift register unit, which comprises the following three stages:
- Phase 1 applying a high level to the gate start terminal STV and the first clock terminal CLKB, Applying a low level to the second clock terminal CLK, causing the charging module to charge the storage capacitor C1 to a high level under the control of the gate start terminal STV and the first clock terminal CLKB, and to make the gate output terminal OUT outputs a low level of the second clock terminal CLK.
- a high level is applied to the gate start terminal STV and the first clock terminal CLKB, and the first transistor M1 and the sixth transistor M6 are turned on to charge the first end of the storage capacitor C1 to a high level.
- the three transistors M3 are turned on.
- a low level is applied to the second clock terminal CLK, and a low level of the second clock terminal CLK is output to the gate output terminal OUT.
- Phase 2 applying a low level to the gate start terminal STV and the first clock terminal CLKB, and applying a high level to the second clock terminal CLK to enable the output control module to control the gate output while the storage capacitor C1 is maintained at a high level.
- the terminal OUT outputs a high level of the second clock terminal CLK.
- a low level is applied to the gate start terminal STV and the first clock terminal CLKB, the first transistor M1 and the sixth transistor M6 are turned off, and the first end of the storage capacitor C1 is kept at a high level, so that the third transistor M3 is turned off. Turn on.
- a high level is applied to the second clock terminal CLK, and a high level of the second clock terminal CLK is output to the gate output terminal OUT through the third transistor M3.
- Phase 3 applying a high level to the reset terminal Reset, the second transistor M2 is turned on, and transmitting the high level of the first end of the storage capacitor C1 to the gate of the fifth transistor M5, so that the fifth transistor M5 is turned on, The first end of the storage capacitor C1 is pulled low.
- the fourth transistor M4 is turned on, so that the gate output terminal OUT outputs a low level.
- the present invention also provides a shift register circuit comprising a plurality of cascaded shift register units.
- the gate output signal of the next stage shift register unit is fed back to the reset terminal of the shift register unit of the previous stage.
- the present invention also provides a display device comprising the above-described shift register circuit.
- the display device can be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
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Abstract
一种移位寄存器单元电路,包括:栅极启动端(STV)、第一时钟端(CLKB)、第二时钟端(CLK)、复位端(Reset)、低电平端(VSS)、栅极输出端(OUT)、存储电容(C1)、充电模块、输出控制模块及复位模块。还公开了移位寄存器、驱动方法及显示装置。在移位寄存器单元电路中,由于第二晶体管(M2)和第五晶体管(M5)一起作用控制复位端(Reset),即使复位端(Reset)信号出现的不稳定的情况,也不会出现错误的复位操作。
Description
本发明涉及显示技术领域,具体涉及移位寄存器单元及其驱动方法、移位寄存器电路、及显示装置。
GOA(Gate Drive on Array)技术是将栅极驱动电路IC的功能形成在阵列基板上,从而提高了液晶显示面板的集成度,降低了材料成本和制作工艺成本。如图1所示,GOA电路包括多个GOA单元,每个GOA单元对应一个栅极驱动输出,从而实现栅极驱动电路IC的功能。
但是GOA单元存在一个问题,在复位信号本身可能会出现不稳定的情况,导致GOA单元中与该复位信号连接的晶体管误导通,从而出现错误的复位操作。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是:如何避免GOA单元中的复位端引起的误操作。
(二)技术方案
为解决上述技术问题,本发明提供了一种移位寄存器单元,包括:
栅极启动端;
第一时钟端;
存储电容器;
充电模块,与所述栅极启动端、所述第一时钟端和所述存储电容器连接,用于在所述栅极启动端和所述第一时钟端的控制下将所述存
储电容器充电至高电平;
第二时钟端;
栅极输出端;
输出控制模块,与所述第二时钟端、所述存储电容器和所述栅极输出端连接,用于在所述存储电容器为高电平时将所述第二时钟端的电平信号输出至所述栅极输出端;
复位端;
低电平端;以及
复位模块,包括第二晶体管、第四晶体管和第五晶体管,所述第二晶体管的栅极与所述复位端连接,源极与所述存储电容器的第一端连接,漏极与所述第五晶体管的栅极连接,所述第四晶体管的栅极与所述复位端连接,源极与所述栅极输出端连接,漏极与所述低电平端连接,所述第五晶体管的源极与所述存储电容器的第一端连接,漏极与所述低电平端连接;所述第二晶体管和第五晶体管用于在复位端的控制下将所述存储电容器的第一端与所述低电平端连接,所述第四晶体管用于在复位端的控制下将所述栅极输出端与所述低电平端连接。
优选地,所述第五晶体管的栅极开启电压大于所述第二晶体管的栅极开启电压。
优选地,所述充电模块包括第一晶体管和第六晶体管,所述第一晶体管的栅极和源极与所述栅极启动端连接,漏极与所述存储电容器的第一端连接,用于在栅极启动端为高电平时对所述存储电容器充电,所述第六晶体管的栅极与所述第一时钟端连接,源极与所述栅极启动端连接,漏极与所述存储电容器的第一端连接,用于在栅极启动端和第一时钟端为高电平时对所述存储电容器充电。
优选地,所述输出控制模块包括第三晶体管,所述第三晶体管的栅极与所述存储电容器的第一端连接,源极与所述第二时钟端连接、漏极与所述栅极输出端连接,所述栅极输出端与所述存储电容器的第
二端连接,所述第三晶体管用于在所述存储电容器的第一端为高电平时将所述第二时钟端的电平信号输出至所述栅极输出端。
本发明还提供了一种上述移位寄存器单元的驱动方法,包括:
对所述栅极启动端和第一时钟端施加高电平,对所述第二时钟端施加低电平,使所述充电模块在所述栅极启动端和第一时钟端的控制下将所述存储电容器充电至高电平,且使栅极输出端输出第二时钟端的低电平;
对所述栅极启动端和所述第一时钟端施加低电平,对所述第二时钟端施加高电平,在存储电容器保持高电平的同时使输出控制模块控制栅极输出端输出第二时钟端的高电平;并且
对复位端施加高电平,使第二晶体管导通,同时存储电容器的第一端的高电平传输至第五晶体管的栅极,使第五晶体管导通,并且存储电容器的第一端被拉至低电平,同时第四晶体管导通,使栅极输出端输出低电平。
优选地,对所述栅极启动端和所述第一时钟端施加高电平,对所述第二时钟端施加低电平,使所述充电模块在所述栅极启动端和第一时钟端的控制下将所述存储电容器充电至高电平,且使栅极输出端输出第二时钟端的低电平具体包括:
对所述栅极启动端和所述第一时钟端施加高电平,使第一晶体管和第六晶体管导通,所述存储电容器的第一端被充电至高电平,并且第三晶体管导通;同时对第二时钟端施加低电平,使第二时钟端的低电平输出至所述栅极输出端。
优选地,对所述栅极启动端和所述第一时钟端施加低电平,对所述第二时钟端施加高电平,在存储电容器保持高电平的同时使输出控制模块控制栅极输出端输出第二时钟端的高电平具体包括:
对所述栅极启动端和所述第一时钟端施加低电平,使第一晶体管和第六晶体管截止,存储电容器的第一端保持高电平,并且第三晶体
管导通;同时对第二时钟端施加高电平,使得通过所述第三晶体管将第二时钟端的高电平输出至所述栅极输出端。
本发明还提供了一种移位寄存器电路,包括多个级联的上述移位寄存器单元,将下一级移位寄存器单元的栅极输出端信号反馈至上一级移位寄存器单元的复位端。
本发明还提供了一种显示装置,包括上述移位寄存器电路。
(三)有益效果
在本发明的移位寄存器单元中,由于第二晶体管和第五晶体管一起作用来控制复位操作,即使复位端信号出现的不稳定的情况,也不会出现错误的复位操作。
图1是移位寄存器电路的结构示意图;
图2是本发明实施例的移位寄存器单元的结构示意图;
图3是图2中移位寄存器单元的工作时序图。
下面结合附图和实施例,对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明,但不用来限制本发明的范围。
如图2所示,本发明提供了一种移位寄存器单元,包括:栅极启动端STV、第一时钟端CLKB、第二时钟端CLK、复位端Reset、低电平端VSS、栅极输出端OUT、存储电容器C1、充电模块、输出控制模块及复位模块。
所述充电模块与栅极启动端STV、第一时钟端CLKB和存储电容器C1与连接,用于在所述栅极启动端STV和第一时钟端CLKB的控制下将存储电容器C1充电至高电平,即,图2中节点PU为高电平。
所述输出控制模块与所述第二时钟端CLK、存储电容器C1和栅极输出端OUT连接,用于在所述存储电容器C1为高电平时将所述第二时钟端
CLK的电平信号输出至所述栅极输出端OUT。
所述复位模块与所述复位端Reset、低电平端VSS、存储电容器C1器和栅极输出端OUT连接,用于在所述复位端Reset的控制下将所述存储电容器C1的两端和栅极输出端OUT连接至所述低电平端VSS。具体地,复位模块包括第二晶体管M2、第四晶体管M4和第五晶体管M5。所述第二晶体管M2的栅极与所述复位端Reset连接,源极与所述存储电容器C1的第一端连接,漏极与所述第五晶体管M5的栅极连接。所述第四晶体管M4的栅极与所述复位端Reset连接,源极与所述栅极输出端OUT连接,漏极与所述低电平端VSS连接。所述第五晶体管M5的源极与所述存储电容器C1的第一端连接,漏极与所述低电平端VSS连接。所述第二晶体管M2和第五晶体管M5用于在复位端Reset的控制下将所述存储电容器C1第一端连接至所述低电平端VSS。所述第四晶体管M4用于在复位端Reset的控制下将所述栅极输出端OUT连接至所述低电平端VSS。
当Reset信号不稳定而发生波动时,第二晶体管M2处于微导通状态,节点P1电压不足以使第五晶体管M5导通,这时存储电容器C1的第一端,即节点PU的电压不会被拉到低电平端VSS,所以移位寄存器单元不会因为Reset信号的不稳定而发生错误的复位操作。
本实施例中,所述充电模块包括第一晶体管M1和第六晶体管M6。所述第一晶体管M1的栅极和源极与所述栅极启动端STV连接,漏极与所述存储电容器C1的第一端连接,用于在栅极启动端STV为高电平时对所述存储电容器C1充电。所述第六晶体管M6的栅极与所述第一时钟端CLKB连接,源极与所述栅极启动端STV连接,漏极与所述存储电容器C1的第一端连接,用于在栅极启动端STV和第一时钟端CLKB为高电平时对所述存储电容器C1充电。
其中,所述输出控制模块包括第三晶体管M3。所述第三晶体管M3的栅极与所述存储电容器C1的第一端连接,源极与所述第二时钟端CLK连接、漏极与所述栅极输出端OUT连接,栅极输出端OUT与所述
存储电容器C1的第二端连接。所述第三晶体管M3用于在所述存储电容器C1的第一端为高电平时将所述第二时钟端CLK的电平信号输出至所述栅极输出端OUT。
进一步地,所述第五晶体管M5的栅极开启电压大于所述第二晶体管M2的栅极开启电压。这样更能保证在第二晶体管M2微导通时,节点P1的电压无法使第五晶体管M5导通。
本实施例的移位寄存器单元的工作时序如图3所示,其具体工作原理如下:
在阶段1,STV端和CLKB端为高电平,CLK端为低电平,此时晶体管M1和M6导通,节点PU的电压被拉高,对存储电容器C1充电。晶体管M3导通,OUT端输出为CLK端的低电平。
在阶段2,STV端和CLKB端为低电平,CLK端为高电平,存储电容器C1保持节点PU的高电平,晶体管M3导通,OUT端输出为CLK端的高电平。
在阶段3,当下一级移位寄存器单元的OUT端的高电平反馈到当前级移位寄存器单元时,即Reset端为高电平,此时晶体管M2导通,将节点P1的电压拉高,同时晶体管M5导通,将节点PU的电压拉到VSS端的低电平,实现移位寄存器单元的Reset。同时晶体管M4导通,将OUT端的电压拉到VSS端的低电平,关闭移位寄存器单元的输出,即OUT端停止输出高电平。
本实施例中,当Reset信号不稳定而发生波动时,晶体管M2处于微导通状态,节点P1的电压不足以使晶体管M5导通,这时节点PU的电压不会被拉到VSS,所以移位寄存器单元不会因为Reset信号的不稳定而发生错误复位操作。即只有晶体管M2和晶体管M5同时处于导通状态时,移位寄存器单元才能完成正确的复位操作。
本发明还提供了一种上述移位寄存器单元的驱动方法,包括以下三个阶段:
阶段一:对所述栅极启动端STV和第一时钟端CLKB施加高电平,
对第二时钟端CLK施加低电平,使所述充电模块在所述栅极启动端STV和第一时钟端CLKB的控制下将所述存储电容器C1充电至高电平,且使栅极输出端OUT输出第二时钟端CLK的低电平。具体地,对所述栅极启动端STV和第一时钟端CLKB施加高电平,第一晶体管M1和第六晶体管M6导通,将所述存储电容器C1的第一端充电至高电平,第三晶体管M3导通。同时对第二时钟端CLK施加低电平,使第二时钟端CLK的低电平输出至所述栅极输出端OUT。
阶段二:对所述栅极启动端STV和第一时钟端CLKB施加低电平,第二时钟端CLK施加高电平,在存储电容器C1保持高电平的同时使输出控制模块控制栅极输出端OUT输出第二时钟端CLK的高电平。具体地,对所述栅极启动端STV和第一时钟端CLKB施加低电平,第一晶体管M1和第六晶体管M6截止,存储电容器C1的第一端保持高电平,使第三晶体管M3导通。同时对第二时钟端CLK施加高电平,通过所述第三晶体管M3将第二时钟端CLK的高电平输出至所述栅极输出端OUT。
阶段三:对复位端Reset施加高电平,第二晶体管M2导通,将存储电容器C1的第一端的高电平传输至第五晶体管M5的栅极,使第五晶体管M5导通,将存储电容器C1的第一端拉至低电平。同时第四晶体管M4导通,使栅极输出端OUT输出低电平。
本发明还提供了一种移位寄存器电路,包括多个级联的上述移位寄存器单元。下一级移位寄存器单元的栅极输出端信号被反馈至上一级移位寄存器单元的复位端。
本发明还提供了一种显示装置,包括上述的移位寄存器电路。该显示装置可以为:液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本发明,而并非对本发明的限制,有关技术领域的普通技术人员,在不脱离本发明的精神和范围的情况下,还可以做出各种变化和变型,因此所有等同的技术方案也属于本发明
的范畴,本发明的专利保护范围应由权利要求限定。
Claims (9)
- 一种移位寄存器单元,包括:栅极启动端;第一时钟端;存储电容器;充电模块,与所述栅极启动端、所述第一时钟端和所述存储电容器连接,用于在所述栅极启动端和所述第一时钟端的控制下将所述存储电容器充电至高电平;第二时钟端;栅极输出端;输出控制模块,与所述第二时钟端、所述存储电容器和所述栅极输出端连接,用于在所述存储电容器为高电平时将所述第二时钟端的电平信号输出至所述栅极输出端;复位端;低电平端;以及复位模块,包括第二晶体管、第四晶体管和第五晶体管,所述第二晶体管的栅极与所述复位端连接,源极与所述存储电容器的第一端连接,漏极与所述第五晶体管的栅极连接,所述第四晶体管的栅极与所述复位端连接,源极与所述栅极输出端连接,漏极与所述低电平端连接,所述第五晶体管的源极与所述存储电容器的第一端连接,漏极与所述低电平端连接;所述第二晶体管和第五晶体管用于在复位端的控制下将所述存储电容器的第一端与所述低电平端连接,所述第四晶体管用于在复位端的控制下将所述栅极输出端与所述低电平端连接。
- 如权利要求1所述的移位寄存器单元,其中,所述第五晶体管的栅极开启电压大于所述第二晶体管的栅极开启电压。
- 如权利要求1或2所述的移位寄存器单元,其中,所述充电模块包括第一晶体管和第六晶体管,所述第一晶体管的栅极和源极与所述栅 极启动端连接,漏极与所述存储电容器的第一端连接,用于在栅极启动端为高电平时对所述存储电容器充电,所述第六晶体管的栅极与所述第一时钟端连接,源极与所述栅极启动端连接,漏极与所述存储电容器的第一端连接,用于在栅极启动端和第一时钟端为高电平时对所述存储电容器充电。
- 如权利要求3所述的移位寄存器单元,其中,所述输出控制模块包括第三晶体管,所述第三晶体管的栅极与所述存储电容器的第一端连接,源极与所述第二时钟端连接、漏极与所述栅极输出端连接,所述栅极输出端与所述存储电容器的第二端连接,所述第三晶体管用于在所述存储电容器的第一端为高电平时将所述第二时钟端的电平信号输出至所述栅极输出端。
- 一种如权利要求4所述的移位寄存器单元的驱动方法,包括:对所述栅极启动端和第一时钟端施加高电平,对所述第二时钟端施加低电平,使所述充电模块在所述栅极启动端和第一时钟端的控制下将所述存储电容器充电至高电平,且使栅极输出端输出第二时钟端的低电平;对所述栅极启动端和所述第一时钟端施加低电平,对所述第二时钟端施加高电平,在存储电容器保持高电平的同时使输出控制模块控制栅极输出端输出第二时钟端的高电平;并且对复位端施加高电平,使第二晶体管导通,同时存储电容器的第一端的高电平传输至第五晶体管的栅极,使第五晶体管导通,并且存储电容器的第一端被拉至低电平,同时第四晶体管导通,使栅极输出端输出低电平。
- 如权利要求5所述的驱动方法,其中,对所述栅极启动端和所述第一时钟端施加高电平,对所述第二时钟端施加低电平,使所述充电模块在所述栅极启动端和第一时钟端的控制下将所述存储电容器充电至高电平,且使栅极输出端输出第二时钟端的低电平具体包括:对所述栅极启动端和所述第一时钟端施加高电平,使第一晶体管和第六晶体管导通,所述存储电容器的第一端被充电至高电平,并且第三晶体管导通;同时对第二时钟端施加低电平,使第二时钟端的低电平输出至所述栅极输出端。
- 如权利要求5所述的驱动方法,其中,对所述栅极启动端和所述第一时钟端施加低电平,对所述第二时钟端施加高电平,在存储电容器保持高电平的同时使输出控制模块控制栅极输出端输出第二时钟端的高电平具体包括:对所述栅极启动端和所述第一时钟端施加低电平,使第一晶体管和第六晶体管截止,存储电容器的第一端保持高电平,并且第三晶体管导通;同时对第二时钟端施加高电平,使得通过所述第三晶体管将第二时钟端的高电平输出至所述栅极输出端。
- 一种移位寄存器电路,包括多个级联的如权利要求1~4中任一项所述的移位寄存器单元,其中,将下一级移位寄存器单元的栅极输出端信号反馈至上一级移位寄存器单元的复位端。
- 一种显示装置,包括如权利要求8所述的移位寄存器电路。
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Application Number | Priority Date | Filing Date | Title |
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EP15777857.2A EP3038099B1 (en) | 2014-10-29 | 2015-03-27 | Shift register unit and driving method therefor, shift register circuit and display device |
US14/785,689 US9741304B2 (en) | 2014-10-29 | 2015-03-27 | Shift register unit and driving method thereof, shift register circuit, and display apparatus |
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CN106652872B (zh) | 2016-12-30 | 2019-12-31 | 深圳市华星光电技术有限公司 | Goa驱动电路及显示装置 |
CN106952614B (zh) * | 2017-03-20 | 2019-02-22 | 昆山国显光电有限公司 | 驱动电路、阵列基板、显示屏及其初始化方法 |
US11253508B2 (en) | 2017-04-03 | 2022-02-22 | Coherus Biosciences, Inc. | PPARy agonist for treatment of progressive supranuclear palsy |
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WO2020205027A1 (en) | 2019-04-02 | 2020-10-08 | Christos Mantzoros | Compositions and methods to treat non-alcoholic fatty liver diseases (nafld) |
US20220288054A1 (en) | 2019-04-04 | 2022-09-15 | Coherus Biosciences, Inc. | Compositions and methods to treat non-alcoholic fatty liver diseases (nafld) |
US20220288053A1 (en) | 2019-04-04 | 2022-09-15 | Coherus Biosciences, Inc. | Compositions and methods to treat non-alcoholic fatty liver diseases (nafld) |
US20220175758A1 (en) | 2019-04-04 | 2022-06-09 | Coherus Biosciences, Inc. | Compositions and methods to treat non-alcoholic fatty liver diseases (nafld) |
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EP3038099B1 (en) | 2019-05-08 |
CN104299589A (zh) | 2015-01-21 |
EP3038099A1 (en) | 2016-06-29 |
US9741304B2 (en) | 2017-08-22 |
US20160260398A1 (en) | 2016-09-08 |
CN104299589B (zh) | 2016-05-25 |
EP3038099A4 (en) | 2017-02-01 |
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