WO2016056889A1 - Convertisseur analogique-numérique à approximations successives et son procédé d'étalonnage - Google Patents

Convertisseur analogique-numérique à approximations successives et son procédé d'étalonnage Download PDF

Info

Publication number
WO2016056889A1
WO2016056889A1 PCT/MY2015/050116 MY2015050116W WO2016056889A1 WO 2016056889 A1 WO2016056889 A1 WO 2016056889A1 MY 2015050116 W MY2015050116 W MY 2015050116W WO 2016056889 A1 WO2016056889 A1 WO 2016056889A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
adc
test
under
dac
Prior art date
Application number
PCT/MY2015/050116
Other languages
English (en)
Inventor
Kong Yew Tan
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Publication of WO2016056889A1 publication Critical patent/WO2016056889A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H03M1/1038—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by storing corrected or correction values in one or more digital look-up tables
    • H03M1/1042—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by storing corrected or correction values in one or more digital look-up tables the look-up table containing corrected values for replacing the original digital values
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array

Definitions

  • the present invention relates to a Successive Approximation Analog to Digital Converter (SA-ADC).
  • SA-ADC Successive Approximation Analog to Digital Converter
  • SA-ADC Successive Approximation Analog to Digital Converter
  • DAC digital to analog converter
  • SAR successive approximation register
  • comparator to perform a binary search operation to convert an analog input into its digital representation.
  • the DAC block used in the SA-ADC architecture includes passive elements such as an array of capacitors with binary weighted values.
  • passive elements such as an array of capacitors with binary weighted values.
  • the performance of these passive elements might be restricted due to capacitance mismatch resulting from deviation from original manufacturing design of these elements. This mismatch impacts the accuracy of a high resolution SA-ADC.
  • conventional high resolution (>10 bits) SA-ADC require calibration to compensate for mismatch in the passive elements.
  • the SA-ADC operates in two cycles, namely a calibration cycle and a conversion cycle.
  • a calibration cycle a high accuracy calibration DAC is used along with the functional DAC of the SA-ADC to convert the passive (usually capacitor) mismatch to residual voltage by pre-charging the capacitors to be calibrated and detecting residual voltage through charge redistribution. The residual voltage is then measured to compute error voltages for each of these capacitors. The error voltage is thereafter stored in digital memory.
  • the corresponding error voltage is then subtracted from the functional DAC output according to the digital input code of the functional DAC.
  • the conventional technique of calibration which is performed by measuring residual voltage requires a high accuracy calibration DAC to measure the capacitance mismatch and a digital memory or storage to store the measured voltages.
  • each SA-ADC operation requires two cycles, that is the calibration cycle followed by the conversion cycle and the overhead of performing mathematical calculation i.e. subtracting the error voltage from the output of the functional DAC during the conversion cycle, there is a slowdown in the conversion rate of the ADC.
  • the SA-ADC includes a Digital to Analog Converter (DAC) comprising at least one array of binary weighted capacitors, wherein each capacitor of the arrays has a top plate and bottom plate; a plurality of switches coupled to each of the binary weighted capacitors; a Successive Approximation Register (SAR) control logic to control the switches to enable the DAC to switch between a calibration cycle and a conversion cycle; a comparator coupled between the DAC and the SAR control logic; and at least one capacitance measuring circuit connected to each binary weighted capacitor in the array at a time for performing frequency based capacitance measurement for calibrating the SA-ADC.
  • DAC Digital to Analog Converter
  • SAR Successive Approximation Register
  • the SAR control logic in the calibration cycle connects the capacitance measuring circuit to the array and selects at least one capacitor at a time from the array as a capacitor-under-test, and the capacitance measuring circuit detects the frequency of the output obtained by applying a constant current to individually charge and discharge each capacitor-under-test to determine a true weight of that capacitor.
  • the SAR control logic in the conversion cycle connects the comparator to the DAC array for performing a successive approximation operation to determine preliminary conversion digital bits.
  • the SAR control logic at the end of each conversion cycle multiplies each preliminary conversion digital bit by the true weight of its corresponding capacitor to obtain an equivalent digital signal for the corresponding analog signal.
  • the capacitance measuring circuit includes at least two current sources alternately connected for each capacitor-under-test; at least two comparators, wherein each comparator has one terminal connected to the capacitor-under-test and other terminal connected to a discrete threshold voltage; and a flip flop configured to receive the output of the two comparators, wherein the two current sources alternately charge and discharge the capacitor-under-test to facilitate detection of the frequency obtained from the output of flip flop which is set and/or reset by the two comparators.
  • a calibration cycle is only activated once either when the SA- ADC circuit is powered on or during reset.
  • the calibration cycle precedes the conversion cycle whereby during calibration the capacitance measurement circuit(s) is activated to determine true weights for each of the capacitors and to save the determined true weights for use in the conversion cycle.
  • normal analog to digital conversion cycle is initiated which then utilizes the saved true weights of each of the capacitors for performing the conversion.
  • FIGURE 1 is a block diagram of a self-calibrating Successive Approximation Analog to Digital Converter (SA-ADC) in accordance with this invention
  • FIGURE 2 is a block diagram of an exemplary design of a DAC sub-block of the SA- ADC
  • FIGURE 3 is a block diagram of a capacitance measurement circuit for calibrating a SA- ADC in accordance with this invention
  • FIGURE 4 is a flowchart showing the steps involved in calibrating a SA-ADC in accordance with this invention.
  • SA-ADC Successive Approximation Analog to Digital Converters
  • the proposed SA-ADC performs calibration or capacitance mismatch compensation by measuring true weight of each capacitor in the DAC sub-block of the SA-ADC.
  • the present invention does not measure the residual voltage for capacitance mismatch compensation and hence does not require a high accuracy calibration DAC.
  • the SA-ADC of the present invention includes a capacitance measurement circuit which facilitates in measurement of true weight of capacitors in the DAC for calibrating the SA- ADC.
  • the capacitor based DAC block of the SA-ADC is disconnected from its normal path and connected to the capacitance measurement circuit.
  • the capacitance measurement circuit determines an absolute value of the true weight for each capacitor in the DAC by performing frequency based capacitance measurement. This frequency based capacitance measurement approach involves translation of sensed capacitance values to frequencies or digital pulses using oscillator circuits present in the capacitance measurement circuit.
  • the capacitance measurement circuit converts the measured true weight as a radix and stores it in a digital format for that particular capacitor (bit). Once the true weight of all capacitors in the binary weighted sub-DAC has been determined, the capacitance measurement circuit is disengaged and the binary weighted DAC is connected back to the comparator (normal path) of the SA-ADC.
  • the true weight of the capacitors is then repeatedly used in the conversion cycles, consequently improving the conversion rate. Moreover, as no mathematical calculation (e.g. subtraction) is to be done for every conversion, the rate of conversion is further improved.
  • FIGURE 1 discloses a block diagram of the self-calibrating SA-ADC (100) in accordance with this invention.
  • the self-calibrating SA- ADC (100) includes at least one Digital to Analog Converter (DAC), a Successive Approximation Register, SAR control logic (106), a comparator (108) and at least one capacitance measuring circuit (200).
  • DAC Digital to Analog Converter
  • SAR control logic 106
  • comparator 108
  • capacitance measuring circuit 200
  • the DAC of the SA-ADC (100) is a conventional capacitor based DAC which includes at least one array of binary weighted capacitors in one or more configurations.
  • FIGURE 2 shows a schematic of a differential capacitor based DAC circuit configured in accordance with an embodiment of the present invention.
  • the design of the capacitor based DAC includes a first array (102) and at least a second array (104) of binary weighted capacitors.
  • the present invention is described and depicted in the figures by a differential capacitor based DAC, the scope of the present invention is not limited to a particular type or design of the capacitor based DAC. Other types or designs of capacitor based DAC circuits and devices are within the scope of this invention.
  • each of the binary weighted capacitors in the arrays (102,104) is connected to a top plate and bottom plate and is further coupled to a plurality of switches. These switches are controlled by the SAR control logic (106) to enable the DAC (102, 104) to switch between a calibration cycle and a conversion cycle.
  • the SAR control logic (106) also controls operation of the SA-ADC along with performing a successive approximation operation for converting an analog signal into its digital representation.
  • the comparator (108) is coupled between the DAC (102, 104) and the SAR control logic (106) and performs the binary search operation for facilitating the successive approximation operation.
  • the capacitance measuring circuit (200) is connected for determining the true weight of each of the capacitors in the DAC.
  • the calibration cycle is activated only once initially either when the SA-ADC circuit is powered on or during reset.
  • the SAR control logic (106) disconnects the DAC block (102, 104) from the comparator (108) and connects it to the capacitance measuring circuit (200) via interchanging the connection of the switches coupled to the DAC (102, 104).
  • the SAR control logic (106) connects the capacitance measurement circuit (200) to the top plate of the first array (102) and the top plate of the second array (104).
  • the SAR control logic (106) selects at least one capacitor at a time from the arrays (102, 104) as a capacitor-under-test.
  • the true weight of the capacitor-under-test is then determined by using frequency based capacitance measurement technique.
  • the frequency based approach involves translation of sensed capacitance values to frequencies or digital pulses. These pulses are further converted and stored in a digital format in a register as a radix for that particular capacitor (bit).
  • the calibration cycle is continued in this manner until the true weight of each capacitor in the arrays (102, 104) has been determined and stored in a discrete location corresponding to that capacitor in the register.
  • the capacitance measuring circuit (200) is disengaged and the DAC block (102, 104) is connected to its normal path in SA-ADC (100) and the conversion cycle is initiated.
  • the comparator's (108) positive input is connected to the first capacitor array (102) for receiving a positive analogue signal, a negative input connected to the second capacitor array (104) for receiving a negative analogue signal for performing a binary search on the analog inputs sampled by the DAC (102, 104).
  • the iterative results of the binary search are used by the successive approximation register to determine preliminary conversion digital bits.
  • an accurate digital equivalent for an input analog signal is obtained by multiplying each corresponding preliminary conversion digital bit by its equivalent true binary weight (i.e. radix).
  • the proposed SA-ADC (100) eliminates the need for repeatedly calibrating the DAC block and thereby improves the conversion rate.
  • the binary-weighted capacitor array representing the DAC consists of 2 * n weighted capacitors (CNP 1 to CNP").
  • the present invention measures capacitance mismatch of these weighted capacitors by determining the voltages VP and VN. In accordance with this invention, these voltages are expressed in terms of capacitor weights with error term for any mismatch. According to the present invention if correct capacitor weights are determined then an accurate digital signal equivalent to the analog input can be obtained.
  • the basis for determining true weight for overcoming capacitance mismatch for accurate conversion is provided hereinafter. Taking mismatch into account, the actual value of each pair of capacitor can be modelled as follows: wherein, C 0 is the unit capacitor and and are the deviation factors of the
  • weight of each capacitor is expressed as follows:
  • FIGURE 3 discloses a block diagram of the capacitance measuring circuit (200) for performing the frequency based capacitance measurement.
  • the capacitance measuring circuit (200) includes at least two current sources (202, 204) alternately connected for each capacitor-under-test, wherein one current source is connected for charging the capacitor-under-test and the other current source is connected to discharge the capacitor-under-test.
  • the charging and discharging of the capacitor-under-test is implemented using transistors which represent the controlled current sources (202, 204).
  • the capacitance value (voltage) which is measured by charging and discharging the capacitor-under-test is input to two comparators (206, 208).
  • the two comparators include a first comparator (206) with hysteresis and an inverting input and a second comparator (208) with hysteresis and a non-inverting input. Both the comparators (206, 208) have different reference threshold voltages (V tr _ and V tr+ ). The two comparators compare potential across the capacitor-under-test with the reference threshold voltages by alternately switching the capacitor-under-test between the two current sources (202, 204). The output terminal of the comparators (206, 208) is connected to a flip flop (210) whose state is set or reset dependent upon whether the output of the comparators is high or low.
  • the capacitance measuring circuit (200) of the present invention maps a capacitance range of 10 f F - 100 pF to a frequency span of 300 Hz - 3 MHz.
  • the output frequency (f osc ) is used to determine absolute value (real binary weights) for each capacitor used in the sub-DAC.
  • the absolute value is converted and stored in digital format as a radix for that particular capacitor (bit) in a register (not shown in the Figures).
  • TABLE 1 shows exemplary radix values computed for each of the capacitors of the sub- DAC.
  • the radix values (which represent the true weight of a particular capacitor) as seen in TABLE 1 are multiplied with each preliminary digital conversion bit to arrive at the correct output code for that particular conversion, as seen below:
  • sum of the above computation gives the correct value for the digital equivalent of the analog input voltage.
  • the sum is shown in decimal form however during implementation the decimal numbers are represented in 2's complement digital logic.
  • SA-ADC Successive Approximation Analog to Digital Converter
  • SA-ADC includes a Digital to Analog Converter, DAC; a Successive Approximation Register, SAR control logic (106) and a comparator (108).
  • the method as seen in FIGURE 4 comprises the following steps: connecting a capacitance measuring circuit (200) to an array of binary weighted capacitors representing the DAC, (1000); selecting at least one binary weighted capacitor from the array as a capacitor-under-test, (1002); determining a true weight of the capacitor-under-test by performing frequency based capacitance measurement, (1004); disconnecting the capacitance measuring circuit (200) if the true weight of each individual capacitor in the array has been determined, (1006); connecting the comparator (108) to the array representing the DAC, (1008); performing successive approximation operation to determine preliminary conversion digital bits, (1010); and multiplying each preliminary conversion digital bit by the true weight of its corresponding capacitor to obtain an equivalent digital signal for the particular analog input, (1012).
  • the step of determining a true weight of the capacitor-under-test by performing frequency based capacitance measurement includes: connecting the weighted capacitors to input terminals of two comparators of the capacitance measuring circuit (200), wherein the two comparators have different threshold voltages; applying a constant current to charge or discharge each capacitor-under-test by alternatively connecting each capacitor-under-test to at least two current sources; detecting the frequency of an output obtained from a flip flop which is set or reset by the two comparators to determine the true weight of each individual capacitor; and storing the true weight as register bits corresponding to the capacitor-under-test.
  • the capacitance measuring circuit of the present invention eliminates the need for employing a high accuracy calibration DAC or tuning capacitor for measuring residual voltage to overcome capacitor mismatch errors. Moreover, the present invention requires calibration to be done initially only once and thereafter the true value of each capacitor can be used repeatedly in normal conversion mode. Furthermore, the capacitance measuring circuit of the present invention does not slow down the conversion time as no mathematical calculation (e.g. subtraction) is to be done for every conversion.
  • example apparatus represents only one functionally descriptive example of many potential implementations. Accordingly, division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would be necessarily be divided, omitted, or included in embodiments of the present invention. Unless contrary to physical possibility, the inventors envision the methods described herein: (i) may be performed in any sequence and/or in any combination; and (ii) the components of respective embodiments may be combined in any manner.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

L'invention porte sur un convertisseur analogique-numérique à approximations successives (CAN-AS) (100) et son procédé d'étalonnage. Le CAN-AS (100) comprend un circuit de mesure de capacité (200) qui effectue une mesure de capacité à base de fréquence pour étalonner le CAN-AS (100). Le circuit de mesure de capacité (200) est connecté à un convertisseur numérique-analogique (CNA) du CAN-AS (100) une fois seulement, et ensuite la valeur de capacité à base de fréquence de condensateurs est utilisée de façon répétée dans des cycles de conversion. Ainsi, le circuit de mesure de capacité (200) améliore la fréquence de conversion de convertisseurs analogique-numérique à approximations successives classiques et élimine la nécessité d'un CNA de grande précision requis dans un CAN-AS classique.
PCT/MY2015/050116 2014-10-10 2015-10-08 Convertisseur analogique-numérique à approximations successives et son procédé d'étalonnage WO2016056889A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI2014002905A MY184557A (en) 2014-10-10 2014-10-10 A successive approximation analog to digital converter and method for calibrating thereof
MYPI2014002905 2014-10-10

Publications (1)

Publication Number Publication Date
WO2016056889A1 true WO2016056889A1 (fr) 2016-04-14

Family

ID=55653419

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/MY2015/050116 WO2016056889A1 (fr) 2014-10-10 2015-10-08 Convertisseur analogique-numérique à approximations successives et son procédé d'étalonnage

Country Status (2)

Country Link
MY (1) MY184557A (fr)
WO (1) WO2016056889A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110474643A (zh) * 2018-05-09 2019-11-19 德州仪器公司 具有反冲线性化的逐次逼近寄存器模/数转换器
CN110995264A (zh) * 2019-12-26 2020-04-10 上海贝岭股份有限公司 Cdac的电容失配的校准系统和逐次逼近型adc
CN111614354A (zh) * 2020-05-14 2020-09-01 和芯星通（上海）科技有限公司 一种模数转换器的电容权重的校准电路
CN112290945A (zh) * 2020-09-30 2021-01-29 西安电子科技大学 单通道高速高精度sar adc的数字后台自校准电路结构及方法
CN114696825A (zh) * 2022-06-01 2022-07-01 浙江地芯引力科技有限公司 模数转换器及电容权重校准方法和装置
CN115913229A (zh) * 2022-12-15 2023-04-04 江苏润石科技有限公司 Sar adc的比较器的动态配置方法、电路、sar adc和芯片
CN115940949A (zh) * 2022-12-14 2023-04-07 合肥健天电子有限公司 分裂电容结构逐次逼近模数转换器校准电路及方法
CN117375611A (zh) * 2023-05-31 2024-01-09 中国移动通信有限公司研究院 Adc芯片、电容偏差调整方法、装置及系统

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5012241A (en) * 1988-09-30 1991-04-30 Siemens Aktiengesellschaft Method for determining and processing correction values for self-calibrating A/D and D/A converters, and calculating register for performing the method
JPH05167449A (ja) * 1991-12-12 1993-07-02 Toshiba Corp 逐次比較型アナログデジタル変換器
JPH0786947A (ja) * 1993-09-09 1995-03-31 Hitachi Ltd Ａ／ｄ変換器
JPH08237125A (ja) * 1995-02-23 1996-09-13 Fujitsu Ltd アナログ−デジタル変換器
EP1018806A2 (fr) * 1999-01-08 2000-07-12 Nec Corporation Convertisseur analogique-numérique avec circuit d'économie d'énergie et procédé de commande de celui
JP2011166240A (ja) * 2010-02-04 2011-08-25 Tokai Rika Co Ltd 静電容量検出方式および静電容量検出装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5012241A (en) * 1988-09-30 1991-04-30 Siemens Aktiengesellschaft Method for determining and processing correction values for self-calibrating A/D and D/A converters, and calculating register for performing the method
JPH05167449A (ja) * 1991-12-12 1993-07-02 Toshiba Corp 逐次比較型アナログデジタル変換器
JPH0786947A (ja) * 1993-09-09 1995-03-31 Hitachi Ltd Ａ／ｄ変換器
JPH08237125A (ja) * 1995-02-23 1996-09-13 Fujitsu Ltd アナログ−デジタル変換器
EP1018806A2 (fr) * 1999-01-08 2000-07-12 Nec Corporation Convertisseur analogique-numérique avec circuit d'économie d'énergie et procédé de commande de celui
JP2011166240A (ja) * 2010-02-04 2011-08-25 Tokai Rika Co Ltd 静電容量検出方式および静電容量検出装置

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110474643A (zh) * 2018-05-09 2019-11-19 德州仪器公司 具有反冲线性化的逐次逼近寄存器模/数转换器
CN110474643B (zh) * 2018-05-09 2023-08-18 德州仪器公司 具有反冲线性化的逐次逼近寄存器模/数转换器
CN110995264B (zh) * 2019-12-26 2023-04-28 上海贝岭股份有限公司 Cdac的电容失配的校准系统和逐次逼近型adc
CN110995264A (zh) * 2019-12-26 2020-04-10 上海贝岭股份有限公司 Cdac的电容失配的校准系统和逐次逼近型adc
CN111614354A (zh) * 2020-05-14 2020-09-01 和芯星通（上海）科技有限公司 一种模数转换器的电容权重的校准电路
CN111614354B (zh) * 2020-05-14 2023-03-24 芯与物(上海)技术有限公司 一种模数转换器的电容权重的校准电路
CN112290945A (zh) * 2020-09-30 2021-01-29 西安电子科技大学 单通道高速高精度sar adc的数字后台自校准电路结构及方法
CN112290945B (zh) * 2020-09-30 2023-03-28 西安电子科技大学 单通道高速高精度sar adc的数字后台自校准电路结构及方法
CN114696825A (zh) * 2022-06-01 2022-07-01 浙江地芯引力科技有限公司 模数转换器及电容权重校准方法和装置
CN115940949A (zh) * 2022-12-14 2023-04-07 合肥健天电子有限公司 分裂电容结构逐次逼近模数转换器校准电路及方法
CN115913229A (zh) * 2022-12-15 2023-04-04 江苏润石科技有限公司 Sar adc的比较器的动态配置方法、电路、sar adc和芯片
CN115913229B (zh) * 2022-12-15 2023-10-03 江苏润石科技有限公司 Sar adc的比较器的动态配置方法、电路、sar adc和芯片
CN117375611A (zh) * 2023-05-31 2024-01-09 中国移动通信有限公司研究院 Adc芯片、电容偏差调整方法、装置及系统

Also Published As

Publication number Publication date
MY184557A (en) 2021-04-02

Similar Documents

Publication Publication Date Title
WO2016056889A1 (fr) Convertisseur analogique-numérique à approximations successives et son procédé d'étalonnage
US9030346B2 (en) Method and apparatus for self-test of successive approximation register (SAR) A/D converter
US10581443B2 (en) Method and apparatus for offset correction in SAR ADC with reduced capacitor array DAC
EP3059867B1 (fr) Circuit et procédé pour la détection d'erreurs de non-concordance dans un convertisseur numérique-analogique et pour leur correction dans un convertisseur analogique-numérique
US7705765B1 (en) Systems and methods for characterizing component ratios and generating a digital representation of same
EP3557766A1 (fr) Convertisseur analogique-numérique (adc) doté d'un étalonnage
US7755521B1 (en) A-D convert apparatus, D-A convert apparatus and adjustment method
CN105811976A (zh) 模拟数字转换器电路
US10432213B1 (en) Successive approximation register (SAR) analog to digital converter (ADC) with overlapping reference voltage ranges
US10236900B1 (en) Capacitive mismatch measurement
US8902092B2 (en) Analog-digital conversion circuit and method
US9191018B2 (en) Analog-digital converter
TWI462489B (zh) 校正電容不匹配的逐漸逼近類比至數位轉換器及其方法
US10461767B1 (en) Successive approximation register (SAR) analog to digital converter (ADC) with switchable reference voltage
EP3607659B1 (fr) Registre d'approximation successive (sar) analogique à l'extension de la gamme dynamique du convertisseur numérique (adc)
US9166608B1 (en) Method and circuit for bandwidth mismatch estimation in an A/D converter
CN112290945B (zh) 单通道高速高精度sar adc的数字后台自校准电路结构及方法
TWI703830B (zh) 類比數位轉換裝置及其電容調整方法
JP6131102B2 (ja) 逐次比較型ａ／ｄ変換器及びその駆動方法
US9007253B2 (en) Successive-approximation-register analog-to-digital converter and method thereof
US10735017B2 (en) Efficient successive approximation register analog to digital converter
CN109802680B (zh) 一种基于分数基准的电容阵列及模数转换器
Zhou et al. A calibration technique for mismatch of capacitor arrays in A/D and D/A converters
CN113114263A (zh) Sar模数转换器
CN117318714A (zh) 一种基于电容失配随机化非线性消除技术的高精度sar adc

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15848619

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15848619

Country of ref document: EP

Kind code of ref document: A1