WO2016051473A1 - 演算増幅回路 - Google Patents
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- WO2016051473A1 WO2016051473A1 PCT/JP2014/075939 JP2014075939W WO2016051473A1 WO 2016051473 A1 WO2016051473 A1 WO 2016051473A1 JP 2014075939 W JP2014075939 W JP 2014075939W WO 2016051473 A1 WO2016051473 A1 WO 2016051473A1
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- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 34
- 238000010586 diagram Methods 0.000 description 19
- 238000000034 method Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 230000006866 deterioration Effects 0.000 description 4
- 230000014509 gene expression Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
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- H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
- H03F3/301—CMOS common drain output SEPP amplifiers
- H03F3/3011—CMOS common drain output SEPP amplifiers with asymmetrical driving of the end stage
- H03F3/3013—CMOS common drain output SEPP amplifiers with asymmetrical driving of the end stage using a common drain driving stage, i.e. follower stage
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- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45224—Complementary Pl types having parallel inputs and being supplied in parallel
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
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- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H03F2203/30006—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor the push and the pull stages of the SEPP amplifier are both current mirrors
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- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45281—One SEPP output stage being added to the differential amplifier
Definitions
- the present invention relates to an operational amplifier circuit, and more particularly to an operational amplifier circuit having a class AB push-pull type source follower circuit as an output amplifier stage.
- Non-Patent Document 1 A technology for operating the output amplifier stage of the operational amplifier circuit as a class AB as a technology that makes it possible to suppress the current consumption in the bias state of the operational amplifier circuit and increase the maximum output current when driving the load.
- An operational amplifier circuit having a class AB output there is an operational amplifier circuit using a push-pull type source follower circuit.
- a conventional operational amplifier circuit using a push-pull type source follower circuit has a problem that a range of an output voltage is narrowed and a problem that a frequency characteristic is deteriorated.
- CMOS Analog Circuit Design Second Edition p. 224, P.I. E. Allen, D.C. R. Holberg, Oxford
- An object of the present invention is to provide an operational amplifier circuit that suppresses deterioration of frequency characteristics and suppresses a narrowing of an output voltage range.
- the operational amplifier circuit includes an output amplifier stage that amplifies the first voltage of the differential amplifier stage that outputs the first voltage and outputs the amplified voltage from the output terminal.
- the output amplification stage includes: A first nMOSFET having a first p-well formed, a shorted gate and drain connected to a first node, and a source connected to a second node; A second nMOSFET having a second p-well formed, a gate connected to the first node, a drain connected to a first reference terminal, and a source connected to the output terminal; A first pMOSFET having a first n-well formed, a shorted gate and drain connected to a third node, and a source connected to the second node; A second n-well is formed, a second pMOSFET having a gate connected to the third node, a drain connected to a second reference terminal, and a source connected to the output terminal.
- the first p well and the second p well are: Connected to the fourth node,
- the first n well and the second n well are: Connected to the fifth node, At least one of the fourth node and the fifth node is: Connected to the output terminal.
- FIG. 3 is a diagram of the operational amplifier circuit 200 in the first embodiment.
- FIG. FIG. 3 is a diagram of the operational amplifier circuit 210 in the first embodiment.
- FIG. 3 is a diagram of the first embodiment, and is a circuit diagram of an operational amplifier circuit 200-1.
- FIG. 3 is a diagram of the first embodiment, and is a basic circuit diagram including a configuration of an output amplification stage 202-1.
- FIG. 3 is a diagram of the first embodiment and shows an example of the layout shape of the first pMOSFET 107 and the second pMOSFET 108 of the operational amplifier circuit 200-1.
- FIG. 8 is a diagram of the first embodiment and shows another example of the layout shape of the first pMOSFET 107 and the second pMOSFET 108 of the operational amplifier circuit 200-1.
- FIG. 5 is a diagram of the first embodiment and shows an example of a layout shape of the first nMOSFET 109 and the second nMOSFET 110 of the operational amplifier circuit 200-1.
- FIG. 10 is a diagram of the first embodiment and shows another example of the layout shape of the first nMOSFET 109 and the second nMOSFET 110 of the operational amplifier circuit 200-1.
- FIG. 3 is a diagram of Embodiment 1, and is a circuit diagram of an operational amplifier circuit 200-2.
- Embodiment 1 the operational amplifier circuit 200 and the operational amplifier circuit 200-1 will be described.
- the voltage is expressed as a voltage ⁇ VOUT>
- the terminal is expressed as a terminal VOUT.
- the voltage ⁇ VOUT> means the voltage at the terminal VOUT.
- the terminal voltage has the same meaning as the terminal potential.
- FIG. 1 shows a circuit configuration of an operational amplifier circuit 200 having a push-pull type source follower circuit, which is a premise of the operational amplifier circuit 200-1 of the first embodiment.
- the push-pull type source follower circuit corresponds to the range 202A of the output amplification stage 202 of FIG.
- the operational amplifier circuit 200 includes a differential input terminal VIP that is a non-inverting input terminal, a differential input terminal VIM that is an inverting input terminal, a bias input terminal VBIAS, and an output terminal VOUT.
- the operational amplifier circuit 200 includes a differential amplifier stage 201 and an output amplifier stage 202.
- the differential amplifier stage 201 amplifies the potential difference between the differential input terminal VIP and the differential input terminal VIM, and outputs a first voltage ⁇ VA>.
- the output amplification stage 202 amplifies the first voltage ⁇ VA> output from the differential amplification stage 201, and outputs the amplified voltage from the output terminal VOUT as an output voltage ⁇ VOUT> that is a second voltage.
- the differential amplification stage 201 includes an nMOSFET 100, a differential pair 211, and an active load 221.
- the nMOSFET 100 receives a bias voltage input from the bias input terminal VBIAS at its gate and generates a bias current.
- the differential pair 211 includes an nMOSFET 101 and an nMOSFET 102.
- the active load 221 includes a pMOSFET 103 and a pMOSFET 104.
- the output amplification stage 202 includes a first nMOSFET 109, a second nMOSFET 110, a first pMOSFET 107, a second pMOSFET 108, a third nMOSFET 105, and a third pMOSFET 106.
- the sources of the second nMOSFET 110 and the second pMOSFET 108 are connected to the output terminal VOUT.
- the first nMOSFET 109 is a replica of the second nMOSFET 110.
- the first pMOSFET 107 is a replica of the second pMOSFET 108.
- the third pMOSFET 106 receives and amplifies the first voltage ⁇ VA> output from the differential amplification stage 201 at the gate.
- the third nMOSFET 105 receives a bias voltage input from the bias input terminal VBIAS at its gate and generates a bias current.
- the gate terminal VGN of the first nMOSFET 109 is connected to the drain of the first nMOSFET 109 and the drain of the third pMOSFET 106.
- the gate terminal VGP of the first pMOSFET 107 is connected to the drain of the first pMOSFET 107 and the drain of the third nMOSFET 105.
- the sources of the first nMOSFET 109 and the first pMOSFET 107 are connected to each other.
- the second nMOSFET 110 and the second pMOSFET 108 have a source connected to the output terminal VOUT, a gate connected to the gate terminal VGN and the gate terminal VGP, and a drain connected to the power supply terminal VDD and the ground terminal VSS, respectively.
- the well potentials of the first nMOSFET 109 and the second nMOSFET 110 are supplied from the ground terminal VSS.
- the well potentials of the first pMOSFET 107 and the second pMOSFET 108 are supplied from the power supply terminal VDD.
- the gate widths of the first pMOSFET 107, the second pMOSFET 108, the first nMOSFET 109, and the second nMOSFET 110 are W107, W108, W109, and W110, respectively, and the gate lengths are L107, L108, L109, and L110, respectively.
- the current flowing through the second nMOSFET 110 and the second pMOSFET 108 in the bias state is N times the current flowing through the first nMOSFET 109 and the first pMOSFET 107.
- the well potentials of the first pMOSFET 107 and the second pMOSFET 108 of the output amplification stage 202 are connected to the power supply terminal VDD, and the well potentials of the first nMOSFET 109 and the second nMOSFET 110 are the ground potential. It is connected to the ground terminal VSS.
- the source potential of the first pMOSFET 107, the second pMOSFET 108, the first nMOSFET 109, and the second nMOSFET 110 is a value between the ground potential and the power supply potential.
- the pn junction between the source and well of the first pMOSFET 107, the second pMOSFET 108, the first nMOSFET 109, and the second nMOSFET 110 is biased in the reverse direction, so that the source-well voltage is so-called zero.
- the absolute value of the threshold voltage increases due to the substrate bias effect as compared to the bias.
- FIG. 2 is a circuit diagram of the operational amplifier circuit 210.
- the arithmetic circuit 210 is different from the output amplification stage 202 of FIG.
- the source and well of the first pMOSFET 107, the second pMOSFET 108, the first nMOSFET 109, and the second nMOSFET 110 are connected as in the output amplification stage 203 shown in FIG. It is effective to make the potential difference between the source and the well zero.
- the parasitic characteristics of the pn junction portion of the well bottom surface and the outer peripheral portion are connected to the source terminal, so that the frequency characteristics are deteriorated.
- an increase in the parasitic capacitance of the source terminals of the first pMOSFET 107 and the first nMOSFET 109 becomes a cause of deterioration of the frequency characteristics of the output amplification stage 202.
- FIG. 3 shows an example of the operational amplifier circuit 200-1 that suppresses the narrowing of the output voltage range that occurs in the operational amplifier circuit 200 of FIG. 1 and that suppresses the deterioration of the frequency characteristics that occurs in the operational amplifier circuit 210 of FIG. The configuration is shown.
- FIG. 3 is a circuit diagram of the operational amplifier circuit 200-1.
- the operational amplifier circuit 200-1 amplifies the first voltage ⁇ VA> of the differential amplifier stage 201 that outputs the first voltage ⁇ VA>, and outputs the amplified voltage from the output terminal VOUT as the second voltage.
- the output amplification stage 202-1 is provided.
- the push-pull type source follower circuit corresponds to the range 202A-1 of the output amplifier stage 202-1.
- the operational amplifier circuit 200-1 is different in the configuration of the output amplifier stage 202-1 from the operational amplifier circuit 200 of FIG.
- the connection state of the well which is a feature of the output amplification stage 202-1, is indicated by a thick line.
- the output amplification stage 202-1 is characterized in that the n wells of the first pMOSFET 107 and the second pMOSFET 108 are connected to the output terminal VOUT, and the p wells of the first nMOSFET 109 and the second nMOSFET 110 are connected to the output terminal VOUT.
- An electric potential is supplied to the n well and the p well.
- the output amplification stage 202-1 shown in FIG. 3 is one specific example, and FIG. 4 shows a basic circuit configuration including the configuration of the output amplification stage 202-1 of FIG.
- FIG. 4 shows a basic circuit configuration including the configuration of the output amplification stage 202-1.
- FIG. 4 is a diagram showing a well potential supply method. The configuration of the output amplification stage 202-1 will be described with reference to FIG.
- the first pMOSFET 107, the second pMOSFET 108, the first nMOSFET 109, the second nMOSFET 110, the third nMOSFET 105, and the third pMOSFET 106 are indicated by solid lines, and the wirings are indicated by broken lines.
- the output amplification stage 202-1 shown in FIG. 4 includes a first pMOSFET 107, a second pMOSFET 108, a first nMOSFET 109, a second nMOSFET 110, a third nMOSFET 105, and a third pMOSFET 106. I have.
- a first p-well PW1 is formed in the first nMOSFET 109.
- the first nMOSFET 109 has a short-circuited gate and drain connected to the first node N (1) and a source connected to the second node N (2).
- the first node N (1) corresponds to the gate terminal VGN of the first nMOSFET 109
- the second node N (2) corresponds to the source terminal of the first nMOSFET 109, for example.
- a second p-well PW2 is formed in the second nMOSFET 110.
- the second nMOSFET 110 has a gate connected to the first node N (1), a drain connected to the first reference terminal 231 and a source connected to the output terminal VOUT.
- the first reference terminal 231 corresponds to the power supply terminal VDD.
- the first n-type well NW1 is formed in the first pMOSFET 107.
- the shorted gate and drain are connected to the third node N (3), and the source is connected to the second node N (2).
- the third node N (3) corresponds to the gate terminal VGP of the first pMOSFET 107.
- the second pMOSFET 108 the second n-well NW2 is formed.
- the second pMOSFET 108 has a gate connected to the third node N (3), a drain connected to the second reference terminal 232, and a source connected to the output terminal VOUT.
- the second reference terminal 232 corresponds to the ground terminal VSS.
- the fourth node N (4) and the fifth node N (5) correspond to the output terminal VOUT.
- the first p well PW1 and the second p well PW2 are connected to the fourth node N (4), and the first n well NW1 and the second n well NW2 Connected to node N (5).
- At least one of the fourth node N (4) and the fifth node N (5) is connected to the output terminal VOUT. That is, in the case of FIG.
- the fourth node N (4) and the fifth node N (5) are connected to the output terminal VOUT, but this connection is an example, and the fourth node N (4 ) And the fifth node N (5) may be connected to the output terminal VOUT.
- the fifth node N (5) may be connected to the power supply terminal VDD as shown in FIG.
- the fourth node N (4) may be connected to the ground terminal VSS as shown in FIG. (7)
- the third pMOSFET 106 has a gate connected to the sixth node N (6), a drain connected to the first node N (1), and a source connected to the first reference terminal 231.
- the sixth node N (6) corresponds to, for example, the drain terminal of the pMOOSFET 103.
- the third nMOSFET 105 has a gate connected to the seventh node N (7), a drain connected to the third node N (3), and a source connected to the second reference terminal 232.
- the seventh node N (7) corresponds to the bias input terminal VBIAS.
- One of the sixth node N (6) and the seventh node N (7) is supplied with the first voltage ⁇ VA>, and the sixth node N (6), The other of the node N (7) is supplied with a bias voltage ⁇ VBIAS>.
- the first voltage ⁇ VA> is supplied to the sixth node N (6) and the bias voltage ⁇ VBIAS> is supplied to the seventh node N (7), but this supply is an example.
- the bias voltage ⁇ VBIAS> may be supplied to the sixth node N (6), and the first voltage ⁇ VA> may be supplied to the seventh node N (7). This configuration will be described later with reference to FIG.
- Equation (2) holds for the gate width and gate length of each of the first pMOSFET 107, the second pMOSFET 108, the first nMOSFET 109, and the second nMOSFET 110 in the operational amplifier circuit 200-1 shown in FIG. Expressions (3) and (4) hold.
- ⁇ VGS107> to ⁇ VGS110> are gate-source voltages of the first pMOSFET 107, the second pMOSFET 108, the first nMOSFET 109, and the second nMOSFET 110, respectively. If the potential of the node to which the source of the first pMOSFET 107 that is a replica and the first nMOSFET 109 that is a replica is connected is ⁇ VS>, Expression (5) is established from Expression (3) and Expression (4).
- ⁇ VOUT> is the voltage of the output terminal VOUT.
- ⁇ VS> ⁇ VOUT> Formula (5) That is, the source potentials of the first pMOSFET 107, the second pMOSFET 108, the first nMOSFET 109, and the second nMOSFET 110 are all equal to the voltage of the output terminal VOUT.
- the parasitic capacitances existing at the well bottom surface and the outer pn junction of the first pMOSFET 107 and the first n109 are not connected to the source terminals of the first pMOSFET 107 and the first nMOSFET 109.
- Good frequency characteristics can be obtained. That is, according to the configuration of the operational amplifier circuit 200-1 shown in FIG. 3, in the output amplifier stage 202-1, the n-well of the first pMOSFET 107 and the p-well of the first nMOSFET 109 are connected to the output terminal VOUT. In this configuration, no parasitic capacitance is connected to the source terminals of one pMOSFET 107 and the first nMOSFET 109.
- the threshold voltage is lowered by reducing the source-well voltage of the first pMOSFET 107, the second pMOSFET 108, the first nMOSFET 109, and the second nMOSFET 110 without deteriorating the frequency characteristics. It is possible to widen the output voltage range.
- FIG. 5 shows a configuration method of the well layout of the first pMOSFET 107 and the second pMOSFET 108.
- the first n well NW 1 and the second n well NW 2 formed on the p-type substrate are separated from each other and connected to the fifth node N (5) by the wiring layer 240. .
- the fifth node N (5) is connected to the output terminal VOUT.
- the first pMOSFET 107 and the second pMOSFET 108 are formed on the first n-well NW1 and the second n-well NW2 that are electrically isolated from each other.
- a second pMOSFET 108 can be realized.
- the potentials of the first n well NW1 and the second n well NW2 are determined by connecting both the first n well NW1 and the second n well NW2 to the output terminal VOUT using the wiring layer 240. , Supplied from the output terminal VOUT.
- FIG. 6 shows a configuration method in which n-wells are unified.
- the first n well NW1 and the second n well NW2 shown in FIG. 5 are formed as a single region by a single n well NW, Connected to node N (5).
- the fifth node N (5) is connected to the output terminal VOUT.
- the first pMOSFET 107 and the second pMOSFET 108 are formed on a single n-well NW, and the potential of the well is set to a single n-well NW at the output terminal VOUT using the wiring layer 240. It may be configured to be connected and supplied from the output terminal VOUT.
- nMOSFET can be realized by forming an n-type buried layer or an epitaxial layer and forming a p-well electrically isolated from the p-type substrate thereon. Therefore, n and p may be replaced with p and n in the descriptions of n and p in FIGS. 5 and 6 and the descriptions of n and p in the description regarding FIGS. 5 and 6.
- FIG. 7 is a diagram showing a configuration method of the well layout of the first nMOSFET 109 and the second nMOSFET 110, and corresponds to FIG.
- FIG. 3 is a diagram in which n and p are replaced with p and n.
- the first p well PW1 and the second p well PW2 are separated from each other by a third n well NW3, and the first p well PW1 and the second p well PW2 are separated from each other. Is separated from the p-type substrate by the third n-well NW3.
- the first p well PW1 and the second p well PW2 are connected to the fourth node N (4) by the wiring layer 240. Note that the fourth node N (4) is connected to the output terminal VOUT.
- FIG. 8 is a diagram showing a case where the first nMOSFET 109 and the second nMOSFET 110 are formed on a single p-well PW with respect to the layout method of the wells of the first nMOSFET 109 and the second nMOSFET 110.
- the first p well PW1 and the second p well PW2 shown in FIG. 7 are formed as a single region by a single p well PW.
- the single p-well PW is separated from the p-type substrate by the third p-well PW3.
- the single p-well PW is connected to the fourth node N (4) by the wiring layer 240.
- the fourth node N (4) is connected to the output terminal VOUT.
- the potential may be supplied from the output terminal VOUT to only one of the nMOSFET and pMOSFET wells. This configuration is as described in the description of FIG.
- one set of the first nMOSFET 109 and the second nMOSFET 110 which are nMOSFETs and the first pMOSFET 107 and the second pMOSFET 108 which are pMOSFETs is replaced with a bipolar transistor, and the other set is output to the well of the MOSFET.
- a potential may be supplied from the terminal VOUT.
- the operational amplifier circuit 200-1 uses an nMOSFET for the differential pair 211 of the differential amplifier stage 201
- the third pMOSFET 106 of the output amplifier stage 202-1 is an amplifier MOSFET
- the third nMOSFET 105 is a current source MOSFET. It was. That is, in FIG. 3, the differential amplifier stage 201 includes a differential pair 211 having two nMOSFETs. However, it is not limited to this configuration.
- FIG. 9 is a circuit diagram of the operational amplifier circuit 200-2. That is, as in the operational amplifier circuit 200-2 shown in FIG. 9, the differential amplifier stage 201-1 includes a differential pair 211-1 having two pMOSFETs.
- the polarity of the MOSFET of the differential amplification stage 201-1 is opposite to that of the differential amplification stage 201 of FIG.
- the differential amplifier stage 201-1 has a configuration in which the nMOSFET of the differential amplifier stage 201 in FIG. 3 is replaced with a pMOSFET, the pMOSFET is replaced with an nMOSFET, and the top and bottom are inverted.
- the configuration in which the top and bottom are inverted is a configuration in which the connection is turned upside down with respect to the power supply terminal VDD and the ground terminal VSS.
- the gate of the third nMOSFET 105 may receive the output voltage ⁇ VA>
- the gate of the third pMOSFET 106 may receive the bias voltage ⁇ VBIAS>.
- N (1) first node, N (2) second node, N (3) third node, N (4) fourth node, N (5) fifth node, N (6) th 6 nodes, N (7), 7th node, NW1 1st n-well, NW2 2nd n-well, PW1 1st p-well, PW2 2nd p-well, VBIAS bias input terminal, VIP, VIM difference Input terminal, VOUT output terminal, VGP gate terminal, VGN gate terminal, VDD power supply terminal, VSS ground terminal, ⁇ VS> first output voltage, 200, 200-1, 200-2, 210 operational amplifier circuit, 201, 201-1 differential amplification stage, 202, 202-1, 203 output amplification stage, 211, 211-1, differential pair, 221, 221-1 active load, 231 first reference terminal, 232 second Reference terminal, 240 wiring layer, 100, 101, 102 nMOSFET, 103, 104 nMOSFET, 105 third nMOSFET, 106 third pMOSF
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Abstract
Description
ここで、前記出力増幅段は、
第1のpウェルが形成され、短絡されたゲートとドレインとが第1のノードに接続され、ソースが第2のノードに接続された第1のnMOSFETと、
第2のpウェルが形成され、ゲートが前記第1のノードに接続され、ドレインが第1の基準端子に接続され、ソースが前記出力端子に接続された第2のnMOSFETと、
第1のnウェルが形成され、短絡されたゲートとドレインとが第3のノードに接続され、ソースが前記第2のノードに接続された第1のpMOSFETと、
第2のnウェルが形成され、ゲートが前記第3のノードに接続され、ドレインが第2の基準端子に接続され、ソースが前記出力端子に接続された第2のpMOSFETと
を備える。
前記第1のpウェルと前記第2のpウェルとは、
第4のノードに接続され、
前記第1のnウェルと前記第2のnウェルとは、
第5のノードに接続され、
前記第4のノードと前記第5のノードとのうち少なくとも一方は、
前記出力端子に接続される。
以下では演算増幅回路200,演算増幅回路200-1を説明する。以下の説明では電圧を電圧<VOUT>のように表記し、端子を端子VOUTのように表記する。電圧<VOUT>は端子VOUTの電圧を意味する。また、端子の電圧は、端子の電位と同じ意味である。
図1は、実施の形態1の演算増幅回路200-1の前提となる、プッシュプル型ソースフォロワ回路を有する演算増幅回路200の回路構成を示す。プッシュプル型ソースフォロワ回路は図1の出力増幅段202の範囲202Aが対応する。演算増幅回路200は、非反転入力端子である差動入力端子VIP及び反転入力端子である差動入力端子VIM、バイアス入力端子VBIAS、出力端子VOUTを有する。演算増幅回路200は、差動増幅段201と、出力増幅段202とを備える。差動増幅段201は、差動入力端子VIPと差動入力端子VIMとの電位差を増幅し、第1の電圧<VA>を出力する。出力増幅段202は、差動増幅段201の出力する第1の電圧<VA>を増幅し、増幅した電圧を、出力端子VOUTから第2の電圧である出力電圧<VOUT>として出力する。
(2)第2のnMOSFET110及び第2のpMOSFET108は、ソースが出力端子VOUTに接続されている。
(3)第1のnMOSFET109は、第2のnMOSFET110のレプリカである。
(4)第1のpMOSFET107は、第2のpMOSFET108のレプリカである。
(5)第3のpMOSFET106は、差動増幅段201が出力する第1の電圧<VA>をゲートに受けて増幅する。
(6)第3のnMOSFET105は、バイアス入力端子VBIASから入力されるバイアス電圧をゲートに受けてバイアス電流を生成する。
(2)第1のpMOSFET107のゲート端子VGPは、第1のpMOSFET107のドレイン及び第3のnMOSFET105のドレインと接続される。
(3)第1のnMOSFET109及び第1のpMOSFET107のソースは、互いに接続される。
(4)第2のnMOSFET110及び第2のpMOSFET108は、ソースが出力端子VOUTに接続され、ゲートがゲート端子VGN及びゲート端子VGPに接続され、ドレインが、それぞれ電源端子VDD及び接地端子VSSに接続される。
(5)また、第1のnMOSFET109及び第2のnMOSFET110のウェル電位は、接地端子VSSから供給される。
(6)第1のpMOSFET107及び第2のpMOSFET108のウェル電位は、電源端子VDDから供給される。
<VG>=<VGN>-<VGP> 式(1)
すなわち、第1のnMOSFET109及び第1のpMOSFET107は、第2のnMOSFET110及び第2のpMOSFET108のレプリカとして機能することで、AB級動作を実現する。ここで、第1のpMOSFET107、第2のpMOSFET108、第1のnMOSFET109、第2のnMOSFET110のゲート幅をそれぞれW107、W108、W109、W110とし、ゲート長をそれぞれL107、L108、L109、L110とする。そして、以下に示す式(2)が成り立つ場合には、バイアス状態における第2のnMOSFET110及び第2のpMOSFET108に流れる電流は、第1のnMOSFET109及び第1のpMOSFET107に流れる電流のN倍となる。
(W108/L108)/(W107/L107)
=(W110/L110)/(W109/L109)
=N 式(2)
図3は、演算増幅回路200-1の回路図である。演算増幅回路200-1は、第1の電圧<VA>を出力する差動増幅段201の第1の電圧<VA>を増幅し、出力端子VOUTから増幅された電圧を第2の電圧として出力する出力増幅段202-1を備えている。図3の演算増幅回路200-1では、プッシュプル型ソースフォロワ回路は出力増幅段202-1の範囲202A-1が対応する。
(2)第2のnMOSFET110は第2のpウェルPW2が形成されている。第2のnMOSFET110は、ゲートが第1のノードN(1)に接続され、ドレインが第1の基準端子231に接続され、ソースが出力端子VOUTに接続される。図3では、第1の基準端子231は電源端子VDDが対応する。
(3)第1のpMOSFET107は第1のnウェルNW1が形成されている。第1のpMOSFET107は、短絡されたゲートとドレインとが第3のノードN(3)に接続され、ソースが第2のノードN(2)に接続されている。図3では、第3のノードN(3)は第1のpMOSFET107のゲート端子VGPが対応する。
(4)第2のpMOSFET108は第2のnウェルNW2が形成されている。第2のpMOSFET108は、ゲートが第3のノードN(3)に接続され、ドレインが第2の基準端子232に接続され、ソースが出力端子VOUTに接続されている。図3では、第2の基準端子232は接地端子VSSが対応する。図3では、第4のノードN(4)及び第5のノードN(5)は、出力端子VOUTが対応する。
(5)第1のpウェルPW1と第2のpウェルPW2とは、第4のノードN(4)に接続され、第1のnウェルNW1と第2のnウェルNW2とは、第5のノードN(5)に接続されている。
(6)第4のノードN(4)と第5のノードN(5)とのうち少なくとも一方は、出力端子VOUTに接続される。つまり、図3の場合は、第4のノードN(4)及び第5のノードN(5)は出力端子VOUTに接続しているが、この接続は例であり、第4のノードN(4)と第5のノードN(5)とのうち少なくとも一方が出力端子VOUTに接続すればよい。第4のノードN(4)のみが出力端子VOUTに接続する場合は、第5のノードN(5)は図1のように電源端子VDDに接続すればよい。一方、第5のノードN(5)のみが出力端子VOUTに接続する場合は、第4のノードN(4)は図1のように接地端子VSSに接続すればよい。
(7)第3のpMOSFET106は、ゲートが第6のノードN(6)に接続され、ドレインが第1のノードN(1)に接続され、ソースが第1の基準端子231に接続される。
図3では、第6のノードN(6)は、例えばpMOOSFET103のドレイン端子が対応する。
(8)第3のnMOSFET105は、ゲートが第7のノードN(7)に接続され、ドレインが第3のノードN(3)に接続され、ソースが第2の基準端子232に接続される。図3では、第7のノードN(7)は、バイアス入力端子VBIASが対応する。
(9)第6のノードN(6)と、第7のノードN(7)との一方は、第1の電圧<VA>が供給され、第6のノードN(6)と、第7のノードN(7)との他方は、バイアス電圧<VBIAS>が供給される。図3では、第6のノードN(6)に第1の電圧<VA>が供給され、第7のノードN(7)にバイアス電圧<VBIAS>が供給されるけれども、この供給は一例である。第6のノードN(6)にバイアス電圧<VBIAS>が供給され、第7のノードN(7)に第1の電圧<VA>が供給される構成でも構わない。この構成は図9で後述する。
図3に示す演算増幅回路200-1における第1のpMOSFET107、第2のpMOSFET108、第1のnMOSFET109、第2のnMOSFET110のそれぞれのゲート幅及びゲート長について式(2)が成り立つとすると、次の式(3)、式(4)が成り立つ。
|<VGS107>|=|<VGS108>| 式(3)
|<VGS109>|=|<VGS110>| 式(4)
ここで、<VGS107>~<VGS110>は、それぞれ、第1のpMOSFET107、第2のpMOSFET108、第1のnMOSFET109、第2のnMOSFET110のゲート―ソース間電圧である。レプリカである第1のpMOSFET107、レプリカである第1のnMOSFET109のソースが接続されるノードの電位を<VS>とすると、式(3)、式(4)より、式(5)が成り立つ。ここで<VOUT>は出力端子VOUTの電圧である。
<VS>=<VOUT> 式(5)
つまり、第1のpMOSFET107、第2のpMOSFET108、第1のnMOSFET109、第2のnMOSFET110のソース電位はいずれも出力端子VOUTの電圧に等しくなる。
したがって、第1のpMOSFET107と第2のpMOSFET108とのnウェルと、第1のnMOSFET109と第2のnMOSFET110とのpウェルとを出力端子VOUTに接続して電位を供給した場合、ソース―ウェル間の電位差はゼロとなるため、基板バイアス効果による閾値電圧の増加は抑制される。このため、図3に示す実施の形態1の演算増幅回路200-1は、図1の演算増幅回路200に対し、広い出力電圧範囲を有する。
次に、第1のpMOSFET107、第2のpMOSFET108、第1のnMOSFET109、第2のnMOSFET110のウェルのレイアウトの構成方法を示す。まず、第1のpMOSFET107及び第2のpMOSFET108の場合を説明する。
図9は、演算増幅回路200-2の回路図である。つまり、図9に示す演算増幅回路200-2のように、差動増幅段201-1は2つのpMOSFETを有する差動対211-1を備える構成とする。これに伴い、差動増幅段201-1は図3の差動増幅段201に対してMOSFETの極性が反対になっている。例えば図9では、図3の差動増幅段201のnMOSFET100に対して、対応するpMOSFETをpMOSFET100-1とした。このように差動増幅段201-1は図3の差動増幅段201のnMOSFETをpMOSFETに置き換え、pMOSFETをnMOSFETに置き換え、上下を反転した構成である。上下を反転した構成とは、言い換えれば、電源端子VDDと接地端子VSSとに関して、接続を上下逆にした構成である。図9に示すように、第3のnMOSFET105のゲートは出力電圧<VA>を受け、第3のpMOSFET106のゲートはバイアス電圧<VBIAS>を受ける構成としてもよい。
Claims (8)
- 第1の電圧を出力する差動増幅段の前記第1の電圧を増幅し、出力端子から増幅された電圧を出力する出力増幅段を備えた演算増幅回路において、
前記出力増幅段は、
第1のpウェルが形成され、短絡されたゲートとドレインとが第1のノードに接続され、ソースが第2のノードに接続された第1のnMOSFETと、
第2のpウェルが形成され、ゲートが前記第1のノードに接続され、ドレインが第1の基準端子に接続され、ソースが前記出力端子に接続された第2のnMOSFETと、
第1のnウェルが形成され、短絡されたゲートとドレインとが第3のノードに接続され、ソースが前記第2のノードに接続された第1のpMOSFETと、
第2のnウェルが形成され、ゲートが前記第3のノードに接続され、ドレインが第2の基準端子に接続され、ソースが前記出力端子に接続された第2のpMOSFETと
を備え、
前記第1のpウェルと前記第2のpウェルとは、
第4のノードに接続され、
前記第1のnウェルと前記第2のnウェルとは、
第5のノードに接続され、
前記第4のノードと前記第5のノードとのうち少なくとも一方は、
前記出力端子に接続された演算増幅回路。 - 前記出力増幅段は、さらに、
ゲートが第6のノードに接続され、ドレインが前記第1のノードに接続され、ソースが前記第1の基準端子に接続された第3のpMOSFETと、
ゲートが第7のノードに接続され、ドレインが前記第3のノードに接続され、ソースが前記第2の基準端子に接続された第3のnMOSFETと
を備え、
前記第6のノードと、前記第7のノードとの一方は、
前記第1の電圧が供給され、
前記第6のノードと、前記第7のノードとの他方は、
バイアス電圧が供給される請求項1に記載の演算増幅回路。 - 前記第1のnウェルと前記第2のnウェルとは、
互いに分離され、配線層によって前記第5のノードに接続された請求項1または2に記載の演算増幅回路。 - 前記第1のnウェルと前記第2のnウェルとは、
単一のnウェルによって単一の領域として形成され、配線層によって前記第5のノードに接続された請求項1または2に記載の演算増幅回路。 - 前記第1のpウェルと前記第2のpウェルとは、
第3のnウェルにより互いに分離され、配線層によって前記第4のノードに接続された請求項1~4のいずれか一項に記載の演算増幅回路。 - 前記第1のpウェルと前記第2のpウェルとは、
単一のpウェルによって単一の領域として形成され、配線層によって前記第4のノードに接続された請求項1~4のいずれか一項に記載の演算増幅回路。 - 前記差動増幅段は、
2つのnMOSFETを有する差動対を備えた請求項1~6のいずれか一項に記載の演算増幅回路。 - 前記差動増幅段は、
2つのpMOSFETを有する差動対を備えた請求項1~6のいずれか一項に記載の演算増幅回路。
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PCT/JP2014/075939 WO2016051473A1 (ja) | 2014-09-29 | 2014-09-29 | 演算増幅回路 |
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US (1) | US9953980B2 (ja) |
JP (1) | JP6320546B2 (ja) |
DE (1) | DE112014007000B4 (ja) |
WO (1) | WO2016051473A1 (ja) |
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DE102018212957B3 (de) | 2018-08-02 | 2020-01-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Übertragung von daten von einem benutzerendgerät zu einem anderen gerät |
US20200194459A1 (en) * | 2018-12-18 | 2020-06-18 | Vanguard International Semiconductor Corporation | Semiconductor devices and methods for fabricating the same |
DE102019206848B3 (de) * | 2019-05-10 | 2020-08-27 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Abstimmung eines elektromagnetischen Schwingkreises einer Konfigurationsschnittstelle eines Teilnehmers eines Kommunikationssystems |
JP7222847B2 (ja) * | 2019-08-26 | 2023-02-15 | 株式会社東芝 | 半導体装置 |
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JPS62125709A (ja) * | 1985-11-26 | 1987-06-08 | Hitachi Ltd | 半導体集積回路 |
IT1185935B (it) | 1985-09-18 | 1987-11-18 | Sgs Microelettronica Spa | Stradio di uscita cmos a grande escursione di tensione e con stabilizzazione della corrente di rifoso |
JPS6450603A (en) * | 1987-08-21 | 1989-02-27 | Toshiba Corp | Current amplifying circuit |
JPH01141407A (ja) * | 1987-11-28 | 1989-06-02 | Mitsubishi Electric Corp | 演算増幅器 |
US5187429A (en) * | 1992-02-20 | 1993-02-16 | Northern Telecom Limited | Reference voltage generator for dynamic random access memory |
FR2691306B1 (fr) * | 1992-05-18 | 1994-08-12 | Sgs Thomson Microelectronics | Amplificateur avec limitation de courant de sortie. |
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JP3403242B2 (ja) * | 1994-03-31 | 2003-05-06 | 新日本無線株式会社 | 電圧ホロワ回路 |
JP3799775B2 (ja) * | 1997-10-07 | 2006-07-19 | ソニー株式会社 | 出力バッファ回路 |
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US6727758B2 (en) * | 2002-05-28 | 2004-04-27 | Koninklijke Philips Electronics N.V. | Fast cascaded class AB bipolar output stage |
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EP2472723B1 (en) * | 2011-01-04 | 2015-12-16 | ams AG | Amplifier with non-linear current mirror |
JP5528378B2 (ja) | 2011-03-07 | 2014-06-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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2014
- 2014-09-29 DE DE112014007000.9T patent/DE112014007000B4/de active Active
- 2014-09-29 JP JP2016551360A patent/JP6320546B2/ja active Active
- 2014-09-29 US US15/329,433 patent/US9953980B2/en active Active
- 2014-09-29 WO PCT/JP2014/075939 patent/WO2016051473A1/ja active Application Filing
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US20060132177A1 (en) * | 2000-09-11 | 2006-06-22 | Broadcom Corporation | Linear buffer |
JP2004173264A (ja) * | 2002-11-08 | 2004-06-17 | Semiconductor Energy Lab Co Ltd | 表示装置 |
Also Published As
Publication number | Publication date |
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DE112014007000B4 (de) | 2021-05-20 |
US20170213831A1 (en) | 2017-07-27 |
JPWO2016051473A1 (ja) | 2017-04-27 |
US9953980B2 (en) | 2018-04-24 |
DE112014007000T5 (de) | 2017-06-29 |
JP6320546B2 (ja) | 2018-05-09 |
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