WO2016030963A1 - TRANSISTOR BIPOLAIRE À GRILLE ISOLÉE AU 4h-SiC, SON PROCÉDÉ DE FABRICATION, ET DISPOSITIF DE CONVERSION DE COURANT - Google Patents

TRANSISTOR BIPOLAIRE À GRILLE ISOLÉE AU 4h-SiC, SON PROCÉDÉ DE FABRICATION, ET DISPOSITIF DE CONVERSION DE COURANT Download PDF

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WO2016030963A1
WO2016030963A1 PCT/JP2014/072288 JP2014072288W WO2016030963A1 WO 2016030963 A1 WO2016030963 A1 WO 2016030963A1 JP 2014072288 W JP2014072288 W JP 2014072288W WO 2016030963 A1 WO2016030963 A1 WO 2016030963A1
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region
silicide
bipolar transistor
insulated gate
gate bipolar
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PCT/JP2014/072288
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English (en)
Japanese (ja)
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広行 吉元
渡辺　直樹
翼 森塚
耕司 藤崎
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株式会社日立製作所
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Priority to PCT/JP2014/072288 priority Critical patent/WO2016030963A1/fr
Priority to JP2016545120A priority patent/JP6268298B2/ja
Publication of WO2016030963A1 publication Critical patent/WO2016030963A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a power conversion device using a 4h-SiC semiconductor element and a manufacturing method thereof, and more particularly to a manufacturing method and structure of an insulated gate bipolar transistor using 4h-SiC as a semiconductor of the element, and a power conversion device using the same.
  • SiC Silicon carbide
  • SiC has a wider band gap than silicon and a dielectric breakdown electric field strength about 10 times higher than that of silicon, and thus has been applied to various semiconductor devices such as power semiconductors.
  • Many types of SiC are known, such as 3C-SiC, 4h-SiC, and 6h-SiC, but 4h-SiC has a large band gap of about 3.2eV, and the fabrication of the substrate is relative to other structures. Widely used because it is easy to make.
  • 4h-SiC semiconductor devices include unipolar device Schottky barrier diodes and power MOSFETs (Metal Oxide Field Effect Transistors), PN diodes for bipolar devices and insulated gate bipolar transistors (IGBT: Insulated Gate Bipolar Transistors), etc. There is.
  • SiC devices can reduce power device loss by replacing the Si elements with unipolar element SiC-MOSFETs or bipolar element SiC-IGBTs for different breakdown voltages.
  • the loss of power devices can be expected by replacing Si elements with SiC-MOSFETs up to about 4.5 kV withstand voltage.
  • SiC bipolar devices have a built-in voltage of about 2.7V and about three times that of Si, so conduction loss is higher than other devices up to about 4.5KV.
  • the withstand voltage exceeds 6.5 kV
  • the drift layer resistance will not increase even if the withstand voltage increases, so the conduction loss of SiC-IGBT can be expected to be smaller than that of Si-IGBT and SiC-MOSFET.
  • Such power devices with an ultra-high breakdown voltage exceeding 6.5 kV can be expected to be used in transformers, power transmission networks or SST (Solid Transformer) in high-speed railways.
  • Patent Document 1 Such a bipolar element using SiC is described in Patent Document 1, Patent Document 2, and the like.
  • n-type Si-IGBT with a p-layer collector region is used, but a SiC-IGBT can also be a p-type IGBT whose impurity polarity is opposite to that of the n-type IGBT.
  • SiC the mobility of electrons is about 1000 cm 2 / Vs, whereas holes are as low as 100 cm 2 / Vs. Therefore, p-type is easier to latch up than n-type, and There is a disadvantage that loss is bad.
  • ⁇ N-type SiC-IGBT does not have the disadvantages of p-type.
  • n-type SiC-IGBT has a problem due to the p-layer in the back collector region.
  • the SiC collector p-layer requires a technology different from n-type to form ohmic contacts.
  • Patent Document 1 describes that a p-layer is formed on an n-type substrate by epitaxial growth, an n-type bulk substrate is later ground to expose the p region, and then heat treatment is performed to form an ohmic electrode. Is done.
  • Patent Document 2 describes that after forming a p-type SiC epitaxial layer on an n-type SiC substrate, removing the substrate, an ohmic contact portion is formed on the exposed p-type SiC by laser annealing, and the like. .
  • the hole injection efficiency of the completed IGBT depends on the thickness and concentration of the p + layer left during grinding and the minority carrier lifetime in the p + layer, regardless of the manufacturing method. Is controlled.
  • An object of the present invention is to provide a semiconductor device manufacturing method and structure capable of appropriately controlling performance such as hole injection efficiency of an IGBT after completion, and a power converter using the same.
  • the thickness of the backside silicide region containing Al in contact with the backside collector electrode of the SiC-IGBT is configured to be thinner than the surface silicide region, so that the SiC semiconductor at the time of backside silicide formation, particularly p +
  • laser annealing is used when forming a silicide layer, and laser irradiation conditions are selected.
  • FIG. 4 is a cross-sectional view of a principal part showing an example of a 4h-SiC n type IGBT according to an embodiment of the present invention.
  • Conceptual graph showing the trade-off between IGBT conduction loss and switching loss.
  • the principal part sectional view showing the silicide layer and electrode formation process of the embodiment of the present invention.
  • the principal part sectional view showing the silicide layer and electrode formation process of the embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of a main part showing another example of the 4h-SiC n type IGBT according to the embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of a main part showing another example of the 4h-SiC n type IGBT according to the embodiment of the present invention.
  • the block diagram which shows an example of the power converter device which applied this invention 4h-SiC n type IGBT.
  • notations such as “first”, “second”, and “third” are attached to identify the constituent elements, and do not necessarily limit the number or order.
  • a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.
  • FIG. 1 shows a schematic cross-sectional view of an n-type SiC-IGBT which is an example of the present invention.
  • the IGBT is a three-terminal switching device having a collector electrode 1, an emitter electrode 12, a gate insulating film 9, and a gate electrode 10.
  • the collector electrode 1 on the back side of the device is different from the MOSFET structure in that a p + collector region 3 exists across a silicide region 2.
  • the p + collector region 3, the n + buffer region 4, and the n ⁇ drift region 5 are all formed by normal epitaxial growth.
  • the p + body region 6 on the device surface and the p + layer 8 and n + layer 7 on the emitter region are often formed by impurity implantation.
  • the emitter regions 7 and 8 on the device surface are silicided at the portion where the SiC and the emitter electrode 12 are in contact with each other in the same manner as the source electrode of the SiC-MOSFET, thereby forming the silicide layer 11 to reduce the contact resistance.
  • Reference numeral 13 denotes an interelectrode insulating film.
  • the drift region 5 accumulates electrons and holes whose density is higher than the carrier density determined by the impurity concentration of the substrate, called the minority carrier accumulation effect or conductivity modulation effect, and the drift region 5 is low during conduction. Make resistance. Since the IGBT uses this conductivity modulation effect, it is possible to achieve a higher breakdown voltage than the MOSFET by reducing the concentration of the drift region 5.
  • IGBTs are designed so that the loss during conduction and switching is appropriate by controlling the amount of accumulation of electrons and holes in the drift region 5 by the flow-out design of electrons and holes. For example, if the accumulation ratio of electrons and holes in the drift region 5 is too high, the drift resistance decreases and the conduction loss also decreases, but the switching loss deteriorates because it is necessary to discharge the accumulated charge during switching. Conversely, if the rate of accumulation is too low, the loss during conduction deteriorates. Therefore, it is important to control these characteristics when creating a device.
  • Figure 2 shows the relationship between switching loss and on-voltage trade-off.
  • hole injection from the back collector affects low-resistance operation.
  • the characteristics shown in Fig. 2 depend on the amount of holes injected from the back surface, and the control of the amount of hole injection can be adjusted by designing the front and back surfaces of the device. On the back side of the device, it can be adjusted by changing the concentration and thickness of the p + collector region 3 and n + buffer region 4 in FIG. 1 and the minority carrier lifetime in each layer.
  • the thickness and density of the p + layer, further by minority carrier lifetime in p + layer, hole injection efficiency of the completed IGBT is controlled.
  • high thermal load during silicide layer 2 is formed to be formed between the back surface of the collector electrode 1 and the collector p + region 3, the SiC film thickness is eroded during silicide layer 2 is formed is increased, in the p + layer
  • the minority carrier lifetime may be deteriorated due to crystal defects and the characteristics may be varied.
  • the collector p + region 3 is sufficiently thick so that the thermal load during formation of the silicide layer 2 does not affect the n + buffer 4 region and the drift region 5, the cost increases due to the thick substrate. In addition, hole injection control by the thickness of the collector p + region 3 cannot be performed.
  • the area of the collector electrode 1 on the back surface of the device is larger than that of the emitter electrode 12 on the surface, an increase in contact resistance that is about the electrode area ratio with the surface emitter region is allowed. Further, since the carriers injected from the surface emitter region are electrons, the silicide layer on the surface of the device does not have a problem such as deterioration of conduction due to hole injection.
  • the present invention adopts the idea of making the silicide layer 2 of the back collector electrode as thin as possible by such examination. Specifically, a configuration is adopted in which the silicide layer 2 of the back collector electrode is made thinner than the silicide layer 11 of the front surface emitter electrode.
  • the thickness of the backside collector electrode and the backside silicide region containing Al in contact with the backside collector electrode is thinner than that of the front surface silicide layer, so that the SiC eroded by silicidation is reduced.
  • the thermal load at the time of silicide formation is small, it is possible to provide a device in which the minority carrier lifetime in the collector p + collector region due to silicide formation is small and reliability is not deteriorated such as deterioration of energization.
  • laser annealing that can be locally heat-treated as a manufacturing process that does not affect other parts of the device when the backside silicide is formed.
  • specific configurations of conditions, materials, etc. suitable for the manufacturing process are proposed.
  • FIG. 1 is a conceptual diagram showing a cross-sectional structure of a 4h-SiC n-type IGBT according to the first embodiment of the present invention.
  • the 4h-SiC trench type power MOSFET according to the present embodiment includes a collector electrode 1, a backside silicide region 2, a p + collector region 3, an n + buffer region 4, an n ⁇ drift region 5 and a p + body region 6.
  • the first emitter region 7, the second emitter region 8, the gate insulating film 9, the gate electrode 10, the surface side silicide region 11 and the emitter electrode 12 are included.
  • the collector electrode 1 is a sputtered electrode region of a metal such as Al, Ti, Ni, Au, Ag.
  • the backside silicide region 2 is a region of a silicide layer in which a metal containing Si and Al is bonded.
  • the p + collector region 3 is a p-type SiC region containing p-type impurities such as Al: aluminum and B: boron.
  • the n + buffer region 4 is an n-type SiC region containing n-type impurities such as N: nitrogen and P: phosphorus.
  • the n ⁇ drift region 5 is an n-type SiC region containing n-type impurities such as N and P, for example. Note that the n-type impurity concentration of the n ⁇ drift region 5 is always lower than that of the n + buffer region, for example, the concentration of the n + buffer region 4 is less than 1 ⁇ 10 19 cm ⁇ 3 , and the concentration of the n ⁇ drift region 5 is 2 ⁇ 10 15 less than cm- 3 .
  • the bulk substrate is ground, or formed by epitaxially growing the n ⁇ drift region 5, n + buffer region 4, and p + collector region 3 in this order on the n or p layer bulk substrate and then grinding the bulk substrate. .
  • the p + body region 6 is a p-type SiC region formed on the drift layer by, for example, impurity implantation or epitaxial growth of p-type impurities such as Al and B.
  • the first emitter region 7 is an n-type SiC region formed by, for example, implanting an n-type impurity such as N or P at a high concentration such as 1 ⁇ 10 19 cm ⁇ 3 or more.
  • the second emitter region 8 is a p-type SiC region formed by, for example, implanting a p-type impurity such as Al or B at a high concentration such as 1 ⁇ 10 19 cm ⁇ 3 or more.
  • the gate insulating film 9 is an insulating film layer formed so as to straddle the n ⁇ drift region 5, the p + body region 6, and the first emitter region 7.
  • the gate insulating film 9 is formed by, for example, wet oxidation, dry oxidation, or CVD (Chemical Vapor Deposition) of SiO 2 oxide film.
  • the gate electrode 10 is an electrode region formed by, after forming the gate insulating film 9, immediately after the CVD of polysilicon or CVD of amorphous silicon, it is transformed into polysilicon by heat treatment.
  • the surface side silicide region 11 is a silicide region formed by combining Si formed so as to straddle the first emitter region and the second emitter region and a metal such as Ni.
  • the emitter electrode 12 is an electrode region in which a metal such as Al, Ti, or Ni is sputtered so as to cover the surface side silicide region 11 and the front surface of the device.
  • the backside silicide region 2 is formed by laser annealing after sputtering, for example, a metal containing Al on the p-type collector region 3. As a result, only the outermost surface in contact with the p-type collector region 3 of the sputtered metal is silicided, and the silicide layer is formed thinner than the surface-side silicide region 11.
  • the collector electrode 1 is formed.
  • the backside silicide region 2 and the collector electrode 1 may be formed before or after the device (circuit) portion is formed, but there is less possibility that the device will be affected before the device is formed.
  • FIG. 3 shows the back collector electrode 1 side of FIG. 1, and explains the process of forming the silicide region 2.
  • FIG. 3C a back surface metal layer 13 containing Al exists between the back surface collector electrode 1 and the back surface silicide region 2, and the other structure is the same as the structure of FIG.
  • a metal 300 containing Al is sputtered on the p + collector region 3, and then annealed by laser 310 irradiation (FIG. 3A).
  • FIG. 3B shows the backside silicide region 2 bonded to Si and the backside metal layer 13 left unreacted are simultaneously formed (FIG. 3B).
  • the composition of Si, C, Al, etc. at the contact surface between the backside metal layer 13 containing Al and the backside silicide region 2 is the same.
  • the collector electrode layer 1 is formed of Al, Ti, Ni, Au, Ag or the like (FIG. 3C).
  • Patent Document 1 the process described in Patent Document 1, Patent Document 2, etc. may be applied to the process until the p + collector region 3 is formed.
  • the n-type SiC substrate was removed by mechanical or chemical polishing to expose the p + collector region 3.
  • the surface of the metal 300 containing Al with a substance other than Al, for example, Ti, Ni, TiN, etc. in order to adjust the reflectance.
  • a substance other than Al for example, Ti, Ni, TiN, etc.
  • Ti, Ni, and TiN are also present in the back surface metal layer 13 and the back surface silicide region 2.
  • the third embodiment according to the present invention is characterized in that, in the 4h-SiC insulated gate bipolar transistor of the first and second embodiments, the backside silicide region 2 contains Al and the depth (thickness) is less than 20 nm.
  • N-type SiC-IGBT can adjust the hole injection efficiency by changing the film thickness and concentration of the back collector p + region 3 and the minority carrier lifetime.
  • concentration is too low, there is a concern that the contact resistance at the time of electrode formation will increase, and there is a concern that the lifetime control by a method such as adding a defect to the crystal will impair the reliability.
  • the film thickness of the collector p + region 3 can be controlled without such a problem.
  • switching loss and loss during conduction are generally in a trade-off relationship. If the thickness of collector p + region 3 is reduced, hole injection efficiency decreases and switching loss decreases. Loss increases. This balance is determined by the intended use, such as the actual device switching frequency. The effect of the film thickness adjustment for reducing the hole injection efficiency is noticeable when the film thickness of the collector p + region 3 is reduced to, for example, less than 2 ⁇ m.
  • the collector p + region 3 is thin, it is more strongly affected by the characteristic fluctuation due to the film thickness fluctuation caused by the heat treatment accompanying silicidation, and further by the reliability deterioration described above.
  • the hole injection efficiency can be adjusted by the film thickness of the collector p + region 3.
  • the collector p + region 3 has a thickness of about 100 nm in the Si-IGBT that has been commercialized prior to the SiC-IGBT, the same thickness is applied to the SiC-IGBT. It is desirable that the film thickness can be adjusted.
  • the depth of the backside silicide region 2 is preferably less than 20 nm.
  • the backside silicide region 2 is formed by, for example, laser annealing as in the first and second embodiments.
  • the depth of the backside silicide region 2 is desirably 5 nm or more for the operation of the collector electrode 1.
  • both layers are made of at least a part of the same kind of material (for example, Ti, Ni, TiN, etc.) other than Al and Al. It will contain.
  • FIG. 4 illustrates a fourth embodiment of the present invention.
  • the fourth embodiment of the present invention has basically the same configuration as the 4h-SiC-insulated gate bipolar transistor of the first to third embodiments.
  • the surface silicide region is divided into a surface first silicide region 19 and a surface second silicide region 20 as shown in FIG.
  • the surface first silicide region 19 is on the first emitter region side which is an n-type SiC region.
  • the surface second silicide region 20 is on the second emitter region 8 side which is a p-type SiC region.
  • the surface first silicide region 19 is formed of Ni silicide
  • the surface second silicide region 20 is formed of silicide containing Al.
  • the thickness of the backside silicide region 2 is smaller than that of the front surface first silicide region 19 and the front surface second silicide region 20.
  • the effect of the present embodiment on the back collector region side is the same as that of the first to third embodiments.
  • the surface second silicide region 20 with silicide containing Al, it is possible to reduce the contact resistance of holes when flowing from the emitter electrode 12 to the second emitter region 8. Become.
  • the fifth embodiment according to the present invention relates to a configuration when a silicide layer containing Al is formed by laser annealing in the first to fourth embodiments of the present invention.
  • a silicide layer containing Al is formed by laser annealing in the first to fourth embodiments of the present invention.
  • the silicide region 2 is formed in the p + collector region 3 (p-type SiC substrate 21) in the configuration of FIG. 1 will be described as an example.
  • Al—22 is sputtered on a p-type SiC substrate 21, and then a metal film 23 such as Ti, Ni, and TiN is sputtered to cover the surface of the sputtered Al 22 (upside down from FIG. Is drawn on).
  • the material may be a single metal or an alloy of these metals.
  • the metal film 23 is irradiated with laser, the SiC of the metal film 23, the aluminum 22, and the substrate 21 is annealed, and a silicide metal layer 24 containing aluminum and an unreacted metal layer 25 are formed.
  • Figure 6 shows another example.
  • the positional relationship between the Al 22 and the metal film 23 may be a laminated structure of the aluminum 22 and another metal 23 as shown in FIG.
  • Fig. 7 shows another example.
  • the lowermost layer may be the metal film 23 as shown in FIG.
  • the metal and SiC react as shown in FIG. 5 to form a silicide layer 24 and an unreacted metal layer 25.
  • the outermost surface is the metal film 23.
  • Al has a high reflectivity with respect to laser light over a wide range of wavelengths and the effect of laser irradiation is lost, so that the outermost surface is preferably a metal that absorbs or transmits laser light.
  • the total film thickness is desirably 10 nm or more, and if it is too thick, reaction of Al adjacent to SiC is hindered, so it is desirably less than 1 um.
  • the lowermost surface of the metal film 23 in contact with the p-type SiC substrate 21 preferably has a thickness of less than 100 nm in order to prevent the reaction between Al and SiC from being hindered.
  • the laser irradiation conditions be less than 400 nm in order to make the energy equivalent to the SiC band gap or more.
  • the laser irradiation intensity and scan speed are less than 400 nm because the contact resistance is reduced by C deposited on the silicide surface from SiC if Al does not react with SiC if the annealing conditions are too weak and if it is too strong.
  • the sixth embodiment according to the present invention relates to a formation process when a silicide layer containing Al in the surface second silicide region 20 is formed by laser annealing in the configuration of FIG. 4 of the present invention.
  • a Ni layer 80 is formed on the p + SiC layer 8 and the n + SiC layer 7 by sputtering or the like. At this time, the thickness of the Ni layer 80 is increased to such an extent that, even if direct laser irradiation is performed, the interface with SiC is not affected.
  • the Ni layer 80 is selectively removed only on the p + SiC layer 8 by a method such as wet etching or dry etching.
  • the Ni layer 80 is selectively irradiated with a laser and annealed to form a Ni-silicide layer 19.
  • Al 90 is sputtered on the p + SiC layer 8 forming the Ni silicide layer 19 and the Al silicide layer.
  • Al 90 is selectively removed only on the p + SiC layer 8 by a method such as wet etching or dry etching.
  • the Ni silicide layer 19 has a thickness capable of protecting the Ni silicide layer, and the p + SiC layer 8 has a thickness necessary for forming the Al silicide layer.
  • the film thickness of Al is increased to such an extent that, for example, direct laser irradiation does not affect the interface with SiC.
  • the region where the Al silicide layer is not formed is represented by the n + SiC layer 7, but this may be another structure such as the gate electrode 10 in FIG.
  • a metal film 91 other than aluminum is formed only on Al 90 on the p + SiC layer 8 to prevent reflection.
  • Al may be formed by a method such as etching without leaving the desired film thickness at the first time, without applying the method of once etching with the p + SiC layer 8 and then sputtering again. . Thereafter, when laser annealing according to the fifth embodiment of the present invention is performed, the laser is reflected at the portion where the surface is the Al layer, and no thermal load is applied, and only the p + SiC layer 8 is silicided, and the Al silicide is formed. Layer 20 and unreacted metal layer 92 are formed. As described in the second embodiment, the unreacted metal layer 92 improves the adhesion between the Al silicide layer 20 and the emitter electrode layer 12, and can prevent deterioration in reliability due to film peeling.
  • the gate insulating film 9 and the gate electrode 10 are formed after the formation of the surface first silicide region 19 and the surface second silicide region 20, the metal at the time of silicide formation is formed in the insulating film.
  • the surface first silicide region 19 and the surface second silicide region 20 are preferably formed after the formation of the gate insulating film 9, the gate electrode 10, and the like.
  • FIG. 10 is a conceptual diagram showing a cross-sectional structure of a 4h-SiC n-type IGBT according to the seventh embodiment of the present invention.
  • the same components as those shown in FIG. 1 are denoted by the same reference numerals.
  • the shapes of the gate insulating film 9b, the gate electrode 10b, and the emitter electrode 12b are different from the example of FIG. 1, but operate according to the same principle as the configuration of FIG.
  • the configurations described in the first to sixth embodiments can be applied to the structure and manufacturing method of the front surface silicide region 11 and the back surface silicide region 2, and similar effects can be obtained.
  • the eighth embodiment according to the present invention relates to a power converter to which the n-type SiC-IGBT according to the above-described embodiment is applied.
  • the power conversion device including the power conversion device according to the present invention can be used for, for example, a railway vehicle.
  • a three-phase motor system applied to this railway vehicle will be described with reference to FIG.
  • FIG. 11 is a block diagram showing an example of a three-phase motor system applied to a railway vehicle. Electric power is supplied to the railway vehicle from the overhead line RT via the panda graph PG.
  • the high voltage AC voltage of the overhead line RT is, for example, 25 kV or 15 kV.
  • This high-voltage AC voltage is stepped down to an AC voltage of, for example, 3.3 kV by the insulated main transformer MTR.
  • the stepped-down AC voltage is forward converted to a DC voltage of 3.3 kV by the converter AC / DC.
  • the DC voltage is converted into an AC voltage by the inverter DC / AC via the capacitor CL, and a desired three-phase AC voltage is output to the three-phase motor MO3, thereby driving the three-phase motor MO3.
  • the symbol WHL indicates a wheel.
  • the n-type SiC-IGBT of the present invention can be applied to the converter AC / DC and the inverter DC / AC constituting the three-phase motor system of the railway vehicle.
  • the SiC-IGBT of the present invention has a larger drive current than the SiC-MOSFET with the same breakdown voltage, and the breakdown voltage per device is higher than the Si-IGBT, reducing the number of parts.
  • the converter circuit portion and the inverter circuit portion can be made highly reliable by the effect of the present invention.
  • the floor of the railway vehicle can be reduced by downsizing the underfloor parts including the three-phase motor system.
  • a storage battery SB can be newly installed in a part of the railway vehicle. Therefore, when the vehicle is not traveling, power is transferred to the overhead line RT via the wheels WHL. The electric power can be stored in the storage battery SB without returning. As a result, the regeneration efficiency of the railway vehicle can be improved. In other words, the life cycle cost of the railway system can be reduced.
  • the present invention is not limited to the above-described embodiment, and includes various modifications.
  • a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment.
  • Electrode and “wiring” do not functionally limit these components.
  • an “electrode” may be used as part of a “wiring” and vice versa.
  • the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

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Abstract

La présente invention concerne une structure qui rend possible de produire un dispositif ayant une plus faible variation de la durée de vie des porteurs minoritaires due à la formation de siliciure dans une zone de collecteur p+, et aucune dégradation de fiabilité, telle qu'une dégradation de conduction, étant donné que l'épaisseur de film d'une zone de siliciure de surface arrière en contact avec une électrode de collecteur de surface arrière est inférieure à celle d'une couche de siliciure de surface avant, ladite zone de siliciure de surface arrière contenant Al, moins de SiC est à éroder du fait de la siliciuration, et la charge thermique appliquée pendant la formation de siliciure est faible.
PCT/JP2014/072288 2014-08-26 2014-08-26 TRANSISTOR BIPOLAIRE À GRILLE ISOLÉE AU 4h-SiC, SON PROCÉDÉ DE FABRICATION, ET DISPOSITIF DE CONVERSION DE COURANT WO2016030963A1 (fr)

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JP2016545120A JP6268298B2 (ja) 2014-08-26 2014-08-26 ４ｈ−ＳｉＣ絶縁ゲートバイポーラトランジスタおよびその製造方法

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JP2021082753A (ja) * 2019-11-21 2021-05-27 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
WO2021261203A1 (fr) * 2020-06-26 2021-12-30 株式会社日立製作所 Dispositif semi-conducteur et son procédé de fabrication

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WO2017158747A1 (fr) * 2016-03-16 2017-09-21 株式会社日立製作所 Procédé de fabrication de substrat épitaxial et procédé de fabrication de dispositif à semi-conducteurs
JP2021082753A (ja) * 2019-11-21 2021-05-27 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
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JP7478604B2 (ja) 2020-06-26 2024-05-07 株式会社日立製作所 半導体装置およびその製造方法

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