WO2016030963A1 - 4h-SiC INSULATED GATE BIPOLAR TRANSISTOR, METHOD FOR MANUFACTURING SAME, AND POWER CONVERSION DEVICE - Google Patents

4h-SiC INSULATED GATE BIPOLAR TRANSISTOR, METHOD FOR MANUFACTURING SAME, AND POWER CONVERSION DEVICE Download PDF

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WO2016030963A1
WO2016030963A1 PCT/JP2014/072288 JP2014072288W WO2016030963A1 WO 2016030963 A1 WO2016030963 A1 WO 2016030963A1 JP 2014072288 W JP2014072288 W JP 2014072288W WO 2016030963 A1 WO2016030963 A1 WO 2016030963A1
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region
silicide
bipolar transistor
insulated gate
gate bipolar
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PCT/JP2014/072288
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French (fr)
Japanese (ja)
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広行 吉元
渡辺　直樹
翼 森塚
耕司 藤崎
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株式会社日立製作所
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Priority to PCT/JP2014/072288 priority Critical patent/WO2016030963A1/en
Priority to JP2016545120A priority patent/JP6268298B2/en
Publication of WO2016030963A1 publication Critical patent/WO2016030963A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a power conversion device using a 4h-SiC semiconductor element and a manufacturing method thereof, and more particularly to a manufacturing method and structure of an insulated gate bipolar transistor using 4h-SiC as a semiconductor of the element, and a power conversion device using the same.
  • SiC Silicon carbide
  • SiC has a wider band gap than silicon and a dielectric breakdown electric field strength about 10 times higher than that of silicon, and thus has been applied to various semiconductor devices such as power semiconductors.
  • Many types of SiC are known, such as 3C-SiC, 4h-SiC, and 6h-SiC, but 4h-SiC has a large band gap of about 3.2eV, and the fabrication of the substrate is relative to other structures. Widely used because it is easy to make.
  • 4h-SiC semiconductor devices include unipolar device Schottky barrier diodes and power MOSFETs (Metal Oxide Field Effect Transistors), PN diodes for bipolar devices and insulated gate bipolar transistors (IGBT: Insulated Gate Bipolar Transistors), etc. There is.
  • SiC devices can reduce power device loss by replacing the Si elements with unipolar element SiC-MOSFETs or bipolar element SiC-IGBTs for different breakdown voltages.
  • the loss of power devices can be expected by replacing Si elements with SiC-MOSFETs up to about 4.5 kV withstand voltage.
  • SiC bipolar devices have a built-in voltage of about 2.7V and about three times that of Si, so conduction loss is higher than other devices up to about 4.5KV.
  • the withstand voltage exceeds 6.5 kV
  • the drift layer resistance will not increase even if the withstand voltage increases, so the conduction loss of SiC-IGBT can be expected to be smaller than that of Si-IGBT and SiC-MOSFET.
  • Such power devices with an ultra-high breakdown voltage exceeding 6.5 kV can be expected to be used in transformers, power transmission networks or SST (Solid Transformer) in high-speed railways.
  • Patent Document 1 Such a bipolar element using SiC is described in Patent Document 1, Patent Document 2, and the like.
  • n-type Si-IGBT with a p-layer collector region is used, but a SiC-IGBT can also be a p-type IGBT whose impurity polarity is opposite to that of the n-type IGBT.
  • SiC the mobility of electrons is about 1000 cm 2 / Vs, whereas holes are as low as 100 cm 2 / Vs. Therefore, p-type is easier to latch up than n-type, and There is a disadvantage that loss is bad.
  • ⁇ N-type SiC-IGBT does not have the disadvantages of p-type.
  • n-type SiC-IGBT has a problem due to the p-layer in the back collector region.
  • the SiC collector p-layer requires a technology different from n-type to form ohmic contacts.
  • Patent Document 1 describes that a p-layer is formed on an n-type substrate by epitaxial growth, an n-type bulk substrate is later ground to expose the p region, and then heat treatment is performed to form an ohmic electrode. Is done.
  • Patent Document 2 describes that after forming a p-type SiC epitaxial layer on an n-type SiC substrate, removing the substrate, an ohmic contact portion is formed on the exposed p-type SiC by laser annealing, and the like. .
  • the hole injection efficiency of the completed IGBT depends on the thickness and concentration of the p + layer left during grinding and the minority carrier lifetime in the p + layer, regardless of the manufacturing method. Is controlled.
  • An object of the present invention is to provide a semiconductor device manufacturing method and structure capable of appropriately controlling performance such as hole injection efficiency of an IGBT after completion, and a power converter using the same.
  • the thickness of the backside silicide region containing Al in contact with the backside collector electrode of the SiC-IGBT is configured to be thinner than the surface silicide region, so that the SiC semiconductor at the time of backside silicide formation, particularly p +
  • laser annealing is used when forming a silicide layer, and laser irradiation conditions are selected.
  • FIG. 4 is a cross-sectional view of a principal part showing an example of a 4h-SiC n type IGBT according to an embodiment of the present invention.
  • Conceptual graph showing the trade-off between IGBT conduction loss and switching loss.
  • the principal part sectional view showing the silicide layer and electrode formation process of the embodiment of the present invention.
  • the principal part sectional view showing the silicide layer and electrode formation process of the embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of a main part showing another example of the 4h-SiC n type IGBT according to the embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of a main part showing another example of the 4h-SiC n type IGBT according to the embodiment of the present invention.
  • the block diagram which shows an example of the power converter device which applied this invention 4h-SiC n type IGBT.
  • notations such as “first”, “second”, and “third” are attached to identify the constituent elements, and do not necessarily limit the number or order.
  • a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.
  • FIG. 1 shows a schematic cross-sectional view of an n-type SiC-IGBT which is an example of the present invention.
  • the IGBT is a three-terminal switching device having a collector electrode 1, an emitter electrode 12, a gate insulating film 9, and a gate electrode 10.
  • the collector electrode 1 on the back side of the device is different from the MOSFET structure in that a p + collector region 3 exists across a silicide region 2.
  • the p + collector region 3, the n + buffer region 4, and the n ⁇ drift region 5 are all formed by normal epitaxial growth.
  • the p + body region 6 on the device surface and the p + layer 8 and n + layer 7 on the emitter region are often formed by impurity implantation.
  • the emitter regions 7 and 8 on the device surface are silicided at the portion where the SiC and the emitter electrode 12 are in contact with each other in the same manner as the source electrode of the SiC-MOSFET, thereby forming the silicide layer 11 to reduce the contact resistance.
  • Reference numeral 13 denotes an interelectrode insulating film.
  • the drift region 5 accumulates electrons and holes whose density is higher than the carrier density determined by the impurity concentration of the substrate, called the minority carrier accumulation effect or conductivity modulation effect, and the drift region 5 is low during conduction. Make resistance. Since the IGBT uses this conductivity modulation effect, it is possible to achieve a higher breakdown voltage than the MOSFET by reducing the concentration of the drift region 5.
  • IGBTs are designed so that the loss during conduction and switching is appropriate by controlling the amount of accumulation of electrons and holes in the drift region 5 by the flow-out design of electrons and holes. For example, if the accumulation ratio of electrons and holes in the drift region 5 is too high, the drift resistance decreases and the conduction loss also decreases, but the switching loss deteriorates because it is necessary to discharge the accumulated charge during switching. Conversely, if the rate of accumulation is too low, the loss during conduction deteriorates. Therefore, it is important to control these characteristics when creating a device.
  • Figure 2 shows the relationship between switching loss and on-voltage trade-off.
  • hole injection from the back collector affects low-resistance operation.
  • the characteristics shown in Fig. 2 depend on the amount of holes injected from the back surface, and the control of the amount of hole injection can be adjusted by designing the front and back surfaces of the device. On the back side of the device, it can be adjusted by changing the concentration and thickness of the p + collector region 3 and n + buffer region 4 in FIG. 1 and the minority carrier lifetime in each layer.
  • the thickness and density of the p + layer, further by minority carrier lifetime in p + layer, hole injection efficiency of the completed IGBT is controlled.
  • high thermal load during silicide layer 2 is formed to be formed between the back surface of the collector electrode 1 and the collector p + region 3, the SiC film thickness is eroded during silicide layer 2 is formed is increased, in the p + layer
  • the minority carrier lifetime may be deteriorated due to crystal defects and the characteristics may be varied.
  • the collector p + region 3 is sufficiently thick so that the thermal load during formation of the silicide layer 2 does not affect the n + buffer 4 region and the drift region 5, the cost increases due to the thick substrate. In addition, hole injection control by the thickness of the collector p + region 3 cannot be performed.
  • the area of the collector electrode 1 on the back surface of the device is larger than that of the emitter electrode 12 on the surface, an increase in contact resistance that is about the electrode area ratio with the surface emitter region is allowed. Further, since the carriers injected from the surface emitter region are electrons, the silicide layer on the surface of the device does not have a problem such as deterioration of conduction due to hole injection.
  • the present invention adopts the idea of making the silicide layer 2 of the back collector electrode as thin as possible by such examination. Specifically, a configuration is adopted in which the silicide layer 2 of the back collector electrode is made thinner than the silicide layer 11 of the front surface emitter electrode.
  • the thickness of the backside collector electrode and the backside silicide region containing Al in contact with the backside collector electrode is thinner than that of the front surface silicide layer, so that the SiC eroded by silicidation is reduced.
  • the thermal load at the time of silicide formation is small, it is possible to provide a device in which the minority carrier lifetime in the collector p + collector region due to silicide formation is small and reliability is not deteriorated such as deterioration of energization.
  • laser annealing that can be locally heat-treated as a manufacturing process that does not affect other parts of the device when the backside silicide is formed.
  • specific configurations of conditions, materials, etc. suitable for the manufacturing process are proposed.
  • FIG. 1 is a conceptual diagram showing a cross-sectional structure of a 4h-SiC n-type IGBT according to the first embodiment of the present invention.
  • the 4h-SiC trench type power MOSFET according to the present embodiment includes a collector electrode 1, a backside silicide region 2, a p + collector region 3, an n + buffer region 4, an n ⁇ drift region 5 and a p + body region 6.
  • the first emitter region 7, the second emitter region 8, the gate insulating film 9, the gate electrode 10, the surface side silicide region 11 and the emitter electrode 12 are included.
  • the collector electrode 1 is a sputtered electrode region of a metal such as Al, Ti, Ni, Au, Ag.
  • the backside silicide region 2 is a region of a silicide layer in which a metal containing Si and Al is bonded.
  • the p + collector region 3 is a p-type SiC region containing p-type impurities such as Al: aluminum and B: boron.
  • the n + buffer region 4 is an n-type SiC region containing n-type impurities such as N: nitrogen and P: phosphorus.
  • the n ⁇ drift region 5 is an n-type SiC region containing n-type impurities such as N and P, for example. Note that the n-type impurity concentration of the n ⁇ drift region 5 is always lower than that of the n + buffer region, for example, the concentration of the n + buffer region 4 is less than 1 ⁇ 10 19 cm ⁇ 3 , and the concentration of the n ⁇ drift region 5 is 2 ⁇ 10 15 less than cm- 3 .
  • the bulk substrate is ground, or formed by epitaxially growing the n ⁇ drift region 5, n + buffer region 4, and p + collector region 3 in this order on the n or p layer bulk substrate and then grinding the bulk substrate. .
  • the p + body region 6 is a p-type SiC region formed on the drift layer by, for example, impurity implantation or epitaxial growth of p-type impurities such as Al and B.
  • the first emitter region 7 is an n-type SiC region formed by, for example, implanting an n-type impurity such as N or P at a high concentration such as 1 ⁇ 10 19 cm ⁇ 3 or more.
  • the second emitter region 8 is a p-type SiC region formed by, for example, implanting a p-type impurity such as Al or B at a high concentration such as 1 ⁇ 10 19 cm ⁇ 3 or more.
  • the gate insulating film 9 is an insulating film layer formed so as to straddle the n ⁇ drift region 5, the p + body region 6, and the first emitter region 7.
  • the gate insulating film 9 is formed by, for example, wet oxidation, dry oxidation, or CVD (Chemical Vapor Deposition) of SiO 2 oxide film.
  • the gate electrode 10 is an electrode region formed by, after forming the gate insulating film 9, immediately after the CVD of polysilicon or CVD of amorphous silicon, it is transformed into polysilicon by heat treatment.
  • the surface side silicide region 11 is a silicide region formed by combining Si formed so as to straddle the first emitter region and the second emitter region and a metal such as Ni.
  • the emitter electrode 12 is an electrode region in which a metal such as Al, Ti, or Ni is sputtered so as to cover the surface side silicide region 11 and the front surface of the device.
  • the backside silicide region 2 is formed by laser annealing after sputtering, for example, a metal containing Al on the p-type collector region 3. As a result, only the outermost surface in contact with the p-type collector region 3 of the sputtered metal is silicided, and the silicide layer is formed thinner than the surface-side silicide region 11.
  • the collector electrode 1 is formed.
  • the backside silicide region 2 and the collector electrode 1 may be formed before or after the device (circuit) portion is formed, but there is less possibility that the device will be affected before the device is formed.
  • FIG. 3 shows the back collector electrode 1 side of FIG. 1, and explains the process of forming the silicide region 2.
  • FIG. 3C a back surface metal layer 13 containing Al exists between the back surface collector electrode 1 and the back surface silicide region 2, and the other structure is the same as the structure of FIG.
  • a metal 300 containing Al is sputtered on the p + collector region 3, and then annealed by laser 310 irradiation (FIG. 3A).
  • FIG. 3B shows the backside silicide region 2 bonded to Si and the backside metal layer 13 left unreacted are simultaneously formed (FIG. 3B).
  • the composition of Si, C, Al, etc. at the contact surface between the backside metal layer 13 containing Al and the backside silicide region 2 is the same.
  • the collector electrode layer 1 is formed of Al, Ti, Ni, Au, Ag or the like (FIG. 3C).
  • Patent Document 1 the process described in Patent Document 1, Patent Document 2, etc. may be applied to the process until the p + collector region 3 is formed.
  • the n-type SiC substrate was removed by mechanical or chemical polishing to expose the p + collector region 3.
  • the surface of the metal 300 containing Al with a substance other than Al, for example, Ti, Ni, TiN, etc. in order to adjust the reflectance.
  • a substance other than Al for example, Ti, Ni, TiN, etc.
  • Ti, Ni, and TiN are also present in the back surface metal layer 13 and the back surface silicide region 2.
  • the third embodiment according to the present invention is characterized in that, in the 4h-SiC insulated gate bipolar transistor of the first and second embodiments, the backside silicide region 2 contains Al and the depth (thickness) is less than 20 nm.
  • N-type SiC-IGBT can adjust the hole injection efficiency by changing the film thickness and concentration of the back collector p + region 3 and the minority carrier lifetime.
  • concentration is too low, there is a concern that the contact resistance at the time of electrode formation will increase, and there is a concern that the lifetime control by a method such as adding a defect to the crystal will impair the reliability.
  • the film thickness of the collector p + region 3 can be controlled without such a problem.
  • switching loss and loss during conduction are generally in a trade-off relationship. If the thickness of collector p + region 3 is reduced, hole injection efficiency decreases and switching loss decreases. Loss increases. This balance is determined by the intended use, such as the actual device switching frequency. The effect of the film thickness adjustment for reducing the hole injection efficiency is noticeable when the film thickness of the collector p + region 3 is reduced to, for example, less than 2 ⁇ m.
  • the collector p + region 3 is thin, it is more strongly affected by the characteristic fluctuation due to the film thickness fluctuation caused by the heat treatment accompanying silicidation, and further by the reliability deterioration described above.
  • the hole injection efficiency can be adjusted by the film thickness of the collector p + region 3.
  • the collector p + region 3 has a thickness of about 100 nm in the Si-IGBT that has been commercialized prior to the SiC-IGBT, the same thickness is applied to the SiC-IGBT. It is desirable that the film thickness can be adjusted.
  • the depth of the backside silicide region 2 is preferably less than 20 nm.
  • the backside silicide region 2 is formed by, for example, laser annealing as in the first and second embodiments.
  • the depth of the backside silicide region 2 is desirably 5 nm or more for the operation of the collector electrode 1.
  • both layers are made of at least a part of the same kind of material (for example, Ti, Ni, TiN, etc.) other than Al and Al. It will contain.
  • FIG. 4 illustrates a fourth embodiment of the present invention.
  • the fourth embodiment of the present invention has basically the same configuration as the 4h-SiC-insulated gate bipolar transistor of the first to third embodiments.
  • the surface silicide region is divided into a surface first silicide region 19 and a surface second silicide region 20 as shown in FIG.
  • the surface first silicide region 19 is on the first emitter region side which is an n-type SiC region.
  • the surface second silicide region 20 is on the second emitter region 8 side which is a p-type SiC region.
  • the surface first silicide region 19 is formed of Ni silicide
  • the surface second silicide region 20 is formed of silicide containing Al.
  • the thickness of the backside silicide region 2 is smaller than that of the front surface first silicide region 19 and the front surface second silicide region 20.
  • the effect of the present embodiment on the back collector region side is the same as that of the first to third embodiments.
  • the surface second silicide region 20 with silicide containing Al, it is possible to reduce the contact resistance of holes when flowing from the emitter electrode 12 to the second emitter region 8. Become.
  • the fifth embodiment according to the present invention relates to a configuration when a silicide layer containing Al is formed by laser annealing in the first to fourth embodiments of the present invention.
  • a silicide layer containing Al is formed by laser annealing in the first to fourth embodiments of the present invention.
  • the silicide region 2 is formed in the p + collector region 3 (p-type SiC substrate 21) in the configuration of FIG. 1 will be described as an example.
  • Al—22 is sputtered on a p-type SiC substrate 21, and then a metal film 23 such as Ti, Ni, and TiN is sputtered to cover the surface of the sputtered Al 22 (upside down from FIG. Is drawn on).
  • the material may be a single metal or an alloy of these metals.
  • the metal film 23 is irradiated with laser, the SiC of the metal film 23, the aluminum 22, and the substrate 21 is annealed, and a silicide metal layer 24 containing aluminum and an unreacted metal layer 25 are formed.
  • Figure 6 shows another example.
  • the positional relationship between the Al 22 and the metal film 23 may be a laminated structure of the aluminum 22 and another metal 23 as shown in FIG.
  • Fig. 7 shows another example.
  • the lowermost layer may be the metal film 23 as shown in FIG.
  • the metal and SiC react as shown in FIG. 5 to form a silicide layer 24 and an unreacted metal layer 25.
  • the outermost surface is the metal film 23.
  • Al has a high reflectivity with respect to laser light over a wide range of wavelengths and the effect of laser irradiation is lost, so that the outermost surface is preferably a metal that absorbs or transmits laser light.
  • the total film thickness is desirably 10 nm or more, and if it is too thick, reaction of Al adjacent to SiC is hindered, so it is desirably less than 1 um.
  • the lowermost surface of the metal film 23 in contact with the p-type SiC substrate 21 preferably has a thickness of less than 100 nm in order to prevent the reaction between Al and SiC from being hindered.
  • the laser irradiation conditions be less than 400 nm in order to make the energy equivalent to the SiC band gap or more.
  • the laser irradiation intensity and scan speed are less than 400 nm because the contact resistance is reduced by C deposited on the silicide surface from SiC if Al does not react with SiC if the annealing conditions are too weak and if it is too strong.
  • the sixth embodiment according to the present invention relates to a formation process when a silicide layer containing Al in the surface second silicide region 20 is formed by laser annealing in the configuration of FIG. 4 of the present invention.
  • a Ni layer 80 is formed on the p + SiC layer 8 and the n + SiC layer 7 by sputtering or the like. At this time, the thickness of the Ni layer 80 is increased to such an extent that, even if direct laser irradiation is performed, the interface with SiC is not affected.
  • the Ni layer 80 is selectively removed only on the p + SiC layer 8 by a method such as wet etching or dry etching.
  • the Ni layer 80 is selectively irradiated with a laser and annealed to form a Ni-silicide layer 19.
  • Al 90 is sputtered on the p + SiC layer 8 forming the Ni silicide layer 19 and the Al silicide layer.
  • Al 90 is selectively removed only on the p + SiC layer 8 by a method such as wet etching or dry etching.
  • the Ni silicide layer 19 has a thickness capable of protecting the Ni silicide layer, and the p + SiC layer 8 has a thickness necessary for forming the Al silicide layer.
  • the film thickness of Al is increased to such an extent that, for example, direct laser irradiation does not affect the interface with SiC.
  • the region where the Al silicide layer is not formed is represented by the n + SiC layer 7, but this may be another structure such as the gate electrode 10 in FIG.
  • a metal film 91 other than aluminum is formed only on Al 90 on the p + SiC layer 8 to prevent reflection.
  • Al may be formed by a method such as etching without leaving the desired film thickness at the first time, without applying the method of once etching with the p + SiC layer 8 and then sputtering again. . Thereafter, when laser annealing according to the fifth embodiment of the present invention is performed, the laser is reflected at the portion where the surface is the Al layer, and no thermal load is applied, and only the p + SiC layer 8 is silicided, and the Al silicide is formed. Layer 20 and unreacted metal layer 92 are formed. As described in the second embodiment, the unreacted metal layer 92 improves the adhesion between the Al silicide layer 20 and the emitter electrode layer 12, and can prevent deterioration in reliability due to film peeling.
  • the gate insulating film 9 and the gate electrode 10 are formed after the formation of the surface first silicide region 19 and the surface second silicide region 20, the metal at the time of silicide formation is formed in the insulating film.
  • the surface first silicide region 19 and the surface second silicide region 20 are preferably formed after the formation of the gate insulating film 9, the gate electrode 10, and the like.
  • FIG. 10 is a conceptual diagram showing a cross-sectional structure of a 4h-SiC n-type IGBT according to the seventh embodiment of the present invention.
  • the same components as those shown in FIG. 1 are denoted by the same reference numerals.
  • the shapes of the gate insulating film 9b, the gate electrode 10b, and the emitter electrode 12b are different from the example of FIG. 1, but operate according to the same principle as the configuration of FIG.
  • the configurations described in the first to sixth embodiments can be applied to the structure and manufacturing method of the front surface silicide region 11 and the back surface silicide region 2, and similar effects can be obtained.
  • the eighth embodiment according to the present invention relates to a power converter to which the n-type SiC-IGBT according to the above-described embodiment is applied.
  • the power conversion device including the power conversion device according to the present invention can be used for, for example, a railway vehicle.
  • a three-phase motor system applied to this railway vehicle will be described with reference to FIG.
  • FIG. 11 is a block diagram showing an example of a three-phase motor system applied to a railway vehicle. Electric power is supplied to the railway vehicle from the overhead line RT via the panda graph PG.
  • the high voltage AC voltage of the overhead line RT is, for example, 25 kV or 15 kV.
  • This high-voltage AC voltage is stepped down to an AC voltage of, for example, 3.3 kV by the insulated main transformer MTR.
  • the stepped-down AC voltage is forward converted to a DC voltage of 3.3 kV by the converter AC / DC.
  • the DC voltage is converted into an AC voltage by the inverter DC / AC via the capacitor CL, and a desired three-phase AC voltage is output to the three-phase motor MO3, thereby driving the three-phase motor MO3.
  • the symbol WHL indicates a wheel.
  • the n-type SiC-IGBT of the present invention can be applied to the converter AC / DC and the inverter DC / AC constituting the three-phase motor system of the railway vehicle.
  • the SiC-IGBT of the present invention has a larger drive current than the SiC-MOSFET with the same breakdown voltage, and the breakdown voltage per device is higher than the Si-IGBT, reducing the number of parts.
  • the converter circuit portion and the inverter circuit portion can be made highly reliable by the effect of the present invention.
  • the floor of the railway vehicle can be reduced by downsizing the underfloor parts including the three-phase motor system.
  • a storage battery SB can be newly installed in a part of the railway vehicle. Therefore, when the vehicle is not traveling, power is transferred to the overhead line RT via the wheels WHL. The electric power can be stored in the storage battery SB without returning. As a result, the regeneration efficiency of the railway vehicle can be improved. In other words, the life cycle cost of the railway system can be reduced.
  • the present invention is not limited to the above-described embodiment, and includes various modifications.
  • a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment.
  • Electrode and “wiring” do not functionally limit these components.
  • an “electrode” may be used as part of a “wiring” and vice versa.
  • the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

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Abstract

A structure of the present invention makes it possible to provide a device having less minority carrier lifetime change due to silicide formation in a collector p+ collector region, and no reliability degradation, such as conduction degradation, since the film thickness of a rear-surface silicide region in contact with a rear-surface collector electrode is less than that of a front-surface silicide layer, said rear-surface silicide region containing Al, less SiC is to be eroded due to silicidation, and a thermal load applied during the silicide formation is small.

Description

４ｈ－ＳｉＣ　絶縁ゲートバイポーラトランジスタ、その製造方法、および電力変換装置4h-SiC insulated gate bipolar transistor, manufacturing method thereof, and power conversion device
　本発明は4h-SiC半導体素子を用いた電力変換装置ならびにその製造方法に関し，特に素子の半導体に4h-SiCを用いた絶縁ゲートバイポーラトランジスタの製造方法、構造およびそれを用いた電力変換装置に関する。 The present invention relates to a power conversion device using a 4h-SiC semiconductor element and a manufacturing method thereof, and more particularly to a manufacturing method and structure of an insulated gate bipolar transistor using 4h-SiC as a semiconductor of the element, and a power conversion device using the same.
　炭化けい素 (SiC)はバンドギャップがシリコンよりも大きく，絶縁破壊電界強度がシリコンより10倍程度高いために，パワー半導体を中心とした半導体素子への様々な応用がなされている。このSiCには3C-SiC，4h-SiC，6h-SiCなど数々の種類が知られているが，4h-SiCはバンドギャップが約3.2eVと大きくまた基板の作製が他の構造より相対的に作りやすいために，広く用いられている。 Silicon carbide (SiC) has a wider band gap than silicon and a dielectric breakdown electric field strength about 10 times higher than that of silicon, and thus has been applied to various semiconductor devices such as power semiconductors. Many types of SiC are known, such as 3C-SiC, 4h-SiC, and 6h-SiC, but 4h-SiC has a large band gap of about 3.2eV, and the fabrication of the substrate is relative to other structures. Widely used because it is easy to make.
　4h-SiCの半導体素子への応用先は，ユニポーラデバイスのショットキーバリアダイオードやパワーMOSFET　(Metal Oxide Field Effect Transistor)，またバイポーラデバイスのPNダイオードや絶縁ゲートバイポーラトランジスタ(IGBT: Insulated Gate Bipolar Transistor)などがある。 Applications for 4h-SiC semiconductor devices include unipolar device Schottky barrier diodes and power MOSFETs (Metal Oxide Field Effect Transistors), PN diodes for bipolar devices and insulated gate bipolar transistors (IGBT: Insulated Gate Bipolar Transistors), etc. There is.
　これらSiCデバイスはSi素子を，異なる耐圧ごとにユニポーラ素子のSiC-MOSFETやバイポーラ素子のSiC-IGBTで置き換えることで，パワーデバイスの低損失化を図ることができる。4.5 kV耐圧未満程度まではSi素子をSiC-MOSFETで置き換えることによりパワーデバイスの低損失化が見込める。一方SiCバイポーラデバイスは2.7 V程度とSiの約3倍のビルトイン電圧をもつために，4.5 kV耐圧程度未満までは他の素子よりも導通損失は高くなる。しかし耐圧が6.5 kV程度を超えると耐圧が上がってもドリフト層抵抗の増大が少ないために，SiC-IGBTの導通損失はSi-IGBT，SiC-MOSFETと比較しても小さくなることが見込める。このような6.5 kVを超える超高耐圧でのパワーデバイスは，高速鉄道における変圧器や送電網あるいはSST（Solid State Transformer）などでの利用が期待できる。 These SiC devices can reduce power device loss by replacing the Si elements with unipolar element SiC-MOSFETs or bipolar element SiC-IGBTs for different breakdown voltages. The loss of power devices can be expected by replacing Si elements with SiC-MOSFETs up to about 4.5 kV withstand voltage. On the other hand, SiC bipolar devices have a built-in voltage of about 2.7V and about three times that of Si, so conduction loss is higher than other devices up to about 4.5KV. However, if the withstand voltage exceeds 6.5 kV, the drift layer resistance will not increase even if the withstand voltage increases, so the conduction loss of SiC-IGBT can be expected to be smaller than that of Si-IGBT and SiC-MOSFET. Such power devices with an ultra-high breakdown voltage exceeding 6.5 kV can be expected to be used in transformers, power transmission networks or SST (Solid Transformer) in high-speed railways.
　このようなSiCを用いたバイポーラ素子については、特許文献１、特許文献２等に記載がある。 Such a bipolar element using SiC is described in Patent Document 1, Patent Document 2, and the like.
特開2012-230964号公報JP 2012-230964 US2008/0296771US2008 / 0296771
　通常Si-IGBTはコレクタ領域がp層のn型が用いられているが，SiC-IGBTではn型IGBTとは不純物の極性が逆のp型IGBTも可能である。ただしSiCでは電子の移動度が約1000 cm2/Vs程度に対して正孔が100 cm2/Vsと低いために，p型はn型と比較するとラッチアップがおき易いことや，ターンオフ時の損失が悪いといった欠点がある。 Normally, an n-type Si-IGBT with a p-layer collector region is used, but a SiC-IGBT can also be a p-type IGBT whose impurity polarity is opposite to that of the n-type IGBT. However, in SiC, the mobility of electrons is about 1000 cm 2 / Vs, whereas holes are as low as 100 cm 2 / Vs. Therefore, p-type is easier to latch up than n-type, and There is a disadvantage that loss is bad.
　n型のSiC-IGBTにはp型のような欠点は生じない。しかしn型のSiC-IGBTは裏面コレクタ領域がp層であることによる課題が存在する。SiCのコレクタp層はオーミックなコンタクトを形成するためにn型とは異なる技術が必要となる点である。 ¡N-type SiC-IGBT does not have the disadvantages of p-type. However, n-type SiC-IGBT has a problem due to the p-layer in the back collector region. The SiC collector p-layer requires a technology different from n-type to form ohmic contacts.
　p型SiC-IGBTはn型バルク基板上に形成するため，裏面の電極形成はSiC-MOSFETと同様の電極形成方法を適用できる。一方，n型SiC-IGBTは高品質なp型バルク基板の作製は困難である。特許文献１には，n型基板上にp層をエピタキシャル成長で形成し，後にn型バルク基板を研削することでp領域を露出させてから，熱処理を行ってオーミック電極を形成すること等が記載される。特許文献２には、n型SiC基板上にp型SiCエピタキシャル層を形成し、基板を除去した後で、露出したp型SiC上にレーザアニールによりオーミック接触部を形成すること等が記載される。 Since p-type SiC-IGBT is formed on an n-type bulk substrate, the electrode formation method similar to that for SiC-MOSFET can be applied to the backside electrode formation. On the other hand, n-type SiC-IGBT is difficult to fabricate high-quality p-type bulk substrates. Patent Document 1 describes that a p-layer is formed on an n-type substrate by epitaxial growth, an n-type bulk substrate is later ground to expose the p region, and then heat treatment is performed to form an ohmic electrode. Is done. Patent Document 2 describes that after forming a p-type SiC epitaxial layer on an n-type SiC substrate, removing the substrate, an ohmic contact portion is formed on the exposed p-type SiC by laser annealing, and the like. .
　n型のSiC-IGBTでは、いずれの製造方法によるとしても，研削時に残したp+層の厚さや濃度，さらにはp+層中の少数キャリアライフタイムによって，完成後のIGBTの正孔注入効率がコントロールされる。 For n-type SiC-IGBT, the hole injection efficiency of the completed IGBT depends on the thickness and concentration of the p + layer left during grinding and the minority carrier lifetime in the p + layer, regardless of the manufacturing method. Is controlled.
　本発明の課題は、完成後のIGBTの正孔注入効率等の性能を適切にコントロールできる半導体装置の製造方法、構造およびそれを用いた電力変換装置を提供することにある。 An object of the present invention is to provide a semiconductor device manufacturing method and structure capable of appropriately controlling performance such as hole injection efficiency of an IGBT after completion, and a power converter using the same.
　本発明の一つの側面では，SiC-IGBTの裏面コレクタ電極に接するAlを含む裏面シリサイド領域の膜厚を，表面シリサイド領域よりも薄く構成することにより、裏面シリサイド形成時のSiC 半導体，特にp+層への影響を低減する半導体装置の製造方法と構造、およびそれを用いた電力変換装置を提供する。 In one aspect of the present invention, the thickness of the backside silicide region containing Al in contact with the backside collector electrode of the SiC-IGBT is configured to be thinner than the surface silicide region, so that the SiC semiconductor at the time of backside silicide formation, particularly p + Provided are a method and a structure for manufacturing a semiconductor device, and a power conversion device using the same.
　また、本発明の好ましい態様としては、シリサイド層形成時にレーザアニリングを使用し、レーザの照射条件を選択する。 Also, as a preferred embodiment of the present invention, laser annealing is used when forming a silicide layer, and laser irradiation conditions are selected.
　上記した以外の本発明のさらなる課題、構成、及び効果は、以下の実施形態の説明により明らかにされる。 Further problems, configurations, and effects of the present invention other than those described above will be clarified by the following description of embodiments.
　信頼性悪化を招かずにp+コレクタ領域の厚さによりIGBT正孔注入効率をコントロールすることが容易になる。 It becomes easy to control the IGBT hole injection efficiency by the thickness of the p + collector region without causing deterioration of reliability.
本発明の実施形態の4h-SiC n型IGBTの一例を示す要部断面図。FIG. 4 is a cross-sectional view of a principal part showing an example of a 4h-SiC n type IGBT according to an embodiment of the present invention. IGBTの導通損失-スイッチング損失のトレードオフを示す概念グラフ図 。Conceptual graph showing the trade-off between IGBT conduction loss and switching loss. 本発明の実施形態のシリサイド層と電極形成工程を示す要部断面図。The principal part sectional view showing the silicide layer and electrode formation process of the embodiment of the present invention. 本発明の実施形態のシリサイド層と電極形成工程を示す要部断面図。The principal part sectional view showing the silicide layer and electrode formation process of the embodiment of the present invention. 本発明の実施形態のシリサイド層と電極形成工程を示す要部断面図。The principal part sectional view showing the silicide layer and electrode formation process of the embodiment of the present invention. 本発明の実施形態の4h-SiC n型IGBTの他の例を示す要部断面図。FIG. 6 is a cross-sectional view of a main part showing another example of the 4h-SiC n type IGBT according to the embodiment of the present invention. 本発明の実施形態のレーザーアニールによるAlを含むシリサイド層形成プロセス説明する断面図。Sectional drawing explaining the silicide layer formation process containing Al by laser annealing of embodiment of this invention. 本発明の実施形態のレーザーアニールによるAlを含むシリサイド層形成前の金属の積層構造を説明する断面図。Sectional drawing explaining the laminated structure of the metal before formation of the silicide layer containing Al by laser annealing of embodiment of this invention. 本発明の実施形態のレーザーアニールによるAlを含むシリサイド層形成前の金属の積層構造を説明する断面図。Sectional drawing explaining the laminated structure of the metal before formation of the silicide layer containing Al by laser annealing of embodiment of this invention. 本発明の実施形態の表面側シリサイド領域の製造工程を示す断面図。Sectional drawing which shows the manufacturing process of the surface side silicide area | region of embodiment of this invention. 本発明の実施形態の表面側シリサイド領域の製造工程を示す断面図（続き）。Sectional drawing which shows the manufacturing process of the surface side silicide area | region of embodiment of this invention (continuation). 本発明の実施形態の4h-SiC n型IGBTの他の例を示す要部断面図。FIG. 6 is a cross-sectional view of a main part showing another example of the 4h-SiC n type IGBT according to the embodiment of the present invention. 本発明4h-SiC n型IGBTを適用した電力変換装置の一例を示すブロック図。The block diagram which shows an example of the power converter device which applied this invention 4h-SiC n type IGBT.
　実施の形態について、図面を用いて詳細に説明する。ただし、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。本発明の思想ないし趣旨から逸脱しない範囲で、その具体的構成を変更し得ることは当業者であれば容易に理解される。 Embodiments will be described in detail with reference to the drawings. However, the present invention is not construed as being limited to the description of the embodiments below. Those skilled in the art will readily understand that the specific configuration can be changed without departing from the spirit or the spirit of the present invention.
　以下に説明する発明の構成において、同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、重複する説明は省略することがある。 In the structure of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and redundant description may be omitted.
　本明細書等における「第１」、「第２」、「第３」などの表記は、構成要素を識別するために付するものであり、必ずしも、数または順序を限定するものではない。また、構成要素の識別のための番号は文脈毎に用いられ、一つの文脈で用いた番号が、他の文脈で必ずしも同一の構成を示すとは限らない。また、ある番号で識別された構成要素が、他の番号で識別された構成要素の機能を兼ねることを妨げるものではない。 In this specification and the like, notations such as “first”, “second”, and “third” are attached to identify the constituent elements, and do not necessarily limit the number or order. In addition, a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.
　図面等において示す各構成の位置、大きさ、形状、範囲などは、発明の理解を容易にするため、実際の位置、大きさ、形状、範囲などを表していない場合がある。このため、本発明は、必ずしも、図面等に開示された位置、大きさ、形状、範囲などに限定されない。 The position, size, shape, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, shape, range, etc. in order to facilitate understanding of the invention. For this reason, the present invention is not necessarily limited to the position, size, shape, range, and the like disclosed in the drawings and the like.
　本明細書で引用した刊行物、特許および特許出願は、そのまま本明細書の説明の一部を構成する。 The publications, patents and patent applications cited in this specification form a part of the description of this specification as they are.
　本明細書において単数形で表される構成要素は、特段文脈で明らかに示されない限り、複数形を含むものとする。 In this specification, a component expressed in the singular shall include the plural unless specifically indicated otherwise.
　図1に本発明の一例であるn型SiC-IGBTの断面模式図を示す。IGBTはコレクタ電極1，エミッタ電極12，ゲート絶縁膜9ならびにゲート電極10を持つ3端子のスイッチングデバイスである。デバイス裏面のコレクタ電極1にはシリサイド領域2をはさんでp+コレクタ領域3が存在する点がMOSFETの構造とは異なる。このp+コレクタ領域3，n+バッファ領域4，ならびにn-ドリフト領域5は全て通常エピタキシャル成長によって形成する。またデバイス表面のp+ボディ領域6やエミッタ領域のp+層8, n+層7は多くの場合不純物注入によって形成する。またデバイス表面のエミッタ領域7，8はSiC-MOSFETのソース電極と同じように，SiCとエミッタ電極12が接する部分をシリサイド化し，シリサイド層11を形成することでコンタクト抵抗を下げている。13は電極間絶縁膜である。 FIG. 1 shows a schematic cross-sectional view of an n-type SiC-IGBT which is an example of the present invention. The IGBT is a three-terminal switching device having a collector electrode 1, an emitter electrode 12, a gate insulating film 9, and a gate electrode 10. The collector electrode 1 on the back side of the device is different from the MOSFET structure in that a p + collector region 3 exists across a silicide region 2. The p + collector region 3, the n + buffer region 4, and the n − drift region 5 are all formed by normal epitaxial growth. The p + body region 6 on the device surface and the p + layer 8 and n + layer 7 on the emitter region are often formed by impurity implantation. In addition, the emitter regions 7 and 8 on the device surface are silicided at the portion where the SiC and the emitter electrode 12 are in contact with each other in the same manner as the source electrode of the SiC-MOSFET, thereby forming the silicide layer 11 to reduce the contact resistance. Reference numeral 13 denotes an interelectrode insulating film.
　このSiC-IGBTのゲート電極10に電圧が印加されたオン状態の下でコレクタ-エミッタ電極間にビルトイン電圧よりも高い電圧を印加すると，デバイス表面のエミッタ領域7，8からゲート絶縁膜9下のチャネルを通って電子が流入し，かつコレクタ領域3からは正孔が流入する。この結果，ドリフト領域5には少数キャリア蓄積効果，または伝導度変調効果と呼ばれる，基板の不純物濃度で決まるキャリア密度よりも高い密度の電子と正孔の蓄積がおき，導通時にはドリフト領域5が低抵抗化する。IGBTは，この伝導度変調効果を利用するためドリフト領域5の濃度を低くすることでMOSFETよりも高耐圧化を図ることができる。 When a voltage higher than the built-in voltage is applied between the collector and the emitter electrode under the ON state in which a voltage is applied to the gate electrode 10 of this SiC-IGBT, the emitter regions 7 and 8 on the device surface Electrons flow through the channel, and holes flow from the collector region 3. As a result, the drift region 5 accumulates electrons and holes whose density is higher than the carrier density determined by the impurity concentration of the substrate, called the minority carrier accumulation effect or conductivity modulation effect, and the drift region 5 is low during conduction. Make resistance. Since the IGBT uses this conductivity modulation effect, it is possible to achieve a higher breakdown voltage than the MOSFET by reducing the concentration of the drift region 5.
　なお，エミッタ領域7，8から流入した電子はコレクタ領域3から流出し，コレクタ領域3から流入した正孔はエミッタ領域7，8から流出する。IGBTは一般にこの電子と正孔の流出入設計で電子，正孔のドリフト領域5中の蓄積量をコントロールして導通時およびスイッチング時における損失が適切になるように設計を行っている。例えばドリフト領域5への電子と正孔の蓄積割合が高すぎると，ドリフト抵抗は下がり導通損失も下がるが，スイッチング時に蓄積した電荷を排出する必要が生じるためスイッチング損失は悪化する。逆に蓄積の割合が低すぎると導通時の損失が悪化する。従って、デバイス作成時に，これらの特性をコントロールすることが重要である。 Note that electrons flowing from the emitter regions 7 and 8 flow out from the collector region 3, and holes flowing from the collector region 3 flow out from the emitter regions 7 and 8. In general, IGBTs are designed so that the loss during conduction and switching is appropriate by controlling the amount of accumulation of electrons and holes in the drift region 5 by the flow-out design of electrons and holes. For example, if the accumulation ratio of electrons and holes in the drift region 5 is too high, the drift resistance decreases and the conduction loss also decreases, but the switching loss deteriorates because it is necessary to discharge the accumulated charge during switching. Conversely, if the rate of accumulation is too low, the loss during conduction deteriorates. Therefore, it is important to control these characteristics when creating a device.
　図2にスイッチング損失とオン電圧のトレードオフの関係を示す。図1に示すIGBTでは，裏面コレクタからの正孔注入が，低抵抗動作に影響する。図2の特性は、裏面からの正孔注入量に依存し、正孔注入量のコントロールはデバイスの表面，裏面両面の設計で調整することができる。デバイス裏面では図1のp+コレクタ領域3，n+バッファ領域4の濃度，厚さならびに各層における少数キャリアライフタイムを変えることで調整できる。 Figure 2 shows the relationship between switching loss and on-voltage trade-off. In the IGBT shown in Fig. 1, hole injection from the back collector affects low-resistance operation. The characteristics shown in Fig. 2 depend on the amount of holes injected from the back surface, and the control of the amount of hole injection can be adjusted by designing the front and back surfaces of the device. On the back side of the device, it can be adjusted by changing the concentration and thickness of the p + collector region 3 and n + buffer region 4 in FIG. 1 and the minority carrier lifetime in each layer.
　図1に示したIGBTでは，p+層の厚さや濃度，さらにはp+層中の少数キャリアライフタイムによって，完成後のIGBTの正孔注入効率がコントロールされる。このとき，裏面のコレクタ電極1とコレクタp+領域3の間に形成するシリサイド層2形成時の熱負荷が大きく，シリサイド層2形成時に侵食されるSiC膜厚が厚くなると，p+層中の結晶欠陥に起因する少数キャリアライフタイムの劣化ならびに特性ばらつきを引き起こす懸念がある。また熱負荷による，欠陥生成での通電劣化や耐性低下の懸念もある。 In the IGBT shown in FIG. 1, the thickness and density of the p + layer, further by minority carrier lifetime in p + layer, hole injection efficiency of the completed IGBT is controlled. At this time, high thermal load during silicide layer 2 is formed to be formed between the back surface of the collector electrode 1 and the collector p + region 3, the SiC film thickness is eroded during silicide layer 2 is formed is increased, in the p + layer There is a concern that the minority carrier lifetime may be deteriorated due to crystal defects and the characteristics may be varied. In addition, there is a concern of deterioration of energization and resistance reduction due to defect generation due to heat load.
　一方でシリサイド層2形成時の熱負荷がn+バッファ4領域やドリフト領域5付近に影響を与えないほどにコレクタp+領域3を充分に厚くすると，基板が厚くなることによるコストの増大を招きかつコレクタp+領域3の厚さによる正孔注入コントロールもできなくなる。 On the other hand, if the collector p + region 3 is sufficiently thick so that the thermal load during formation of the silicide layer 2 does not affect the n + buffer 4 region and the drift region 5, the cost increases due to the thick substrate. In addition, hole injection control by the thickness of the collector p + region 3 cannot be performed.
　一方で，デバイス裏面のコレクタ電極1の面積は表面のエミッタ電極12よりも大きいため表面エミッタ領域との電極面積比程度の，コンタクト抵抗の増大は許容される。また表面エミッタ領域から注入されるキャリアは電子のためにデバイス表面のシリサイド層には正孔注入による通電劣化のような課題は発生しない。 On the other hand, since the area of the collector electrode 1 on the back surface of the device is larger than that of the emitter electrode 12 on the surface, an increase in contact resistance that is about the electrode area ratio with the surface emitter region is allowed. Further, since the carriers injected from the surface emitter region are electrons, the silicide layer on the surface of the device does not have a problem such as deterioration of conduction due to hole injection.
　本発明は，このような検討により，裏面コレクタ電極のシリサイド層2をできるだけ薄くする思想を採用する。具体的には、表面エミッタ電極のシリサイド層11より裏面コレクタ電極のシリサイド層2を薄くする構成を採用する。 The present invention adopts the idea of making the silicide layer 2 of the back collector electrode as thin as possible by such examination. Specifically, a configuration is adopted in which the silicide layer 2 of the back collector electrode is made thinner than the silicide layer 11 of the front surface emitter electrode.
　このような構造によれば、裏面コレクタ電極と裏面コレクタ電極に接するAlを含む裏面シリサイド領域の膜厚が表面シリサイド層よりも薄いので，シリサイド化により侵食されるSiCが少なくなる。またシリサイド形成時の熱負荷も少ないために，シリサイド形成によるコレクタp+コレクタ領域中の少数キャリアライフタイムの変化が少なく通電劣化などの信頼性悪化のないデバイスを提供できる。さらには上述のように信頼性悪化を招かずにp+コレクタ領域の厚さによりIGBT正孔注入効率をコントロールすることが可能となる。 According to such a structure, the thickness of the backside collector electrode and the backside silicide region containing Al in contact with the backside collector electrode is thinner than that of the front surface silicide layer, so that the SiC eroded by silicidation is reduced. In addition, since the thermal load at the time of silicide formation is small, it is possible to provide a device in which the minority carrier lifetime in the collector p + collector region due to silicide formation is small and reliability is not deteriorated such as deterioration of energization. Furthermore, as described above, it is possible to control the IGBT hole injection efficiency by the thickness of the p + collector region without causing deterioration of reliability.
　また、裏面シリサイド形成時に，デバイスの他の部分に影響を与えない製造プロセスとして，局所的に熱処理が可能なレーザアニリングを用いることが望ましい。実施例中では，当該製造プロセスに好適な条件，材料等についての具体構成を提案するものである。 Also, it is desirable to use laser annealing that can be locally heat-treated as a manufacturing process that does not affect other parts of the device when the backside silicide is formed. In the examples, specific configurations of conditions, materials, etc. suitable for the manufacturing process are proposed.
第１の実施形態First embodiment
　以下，本発明の実施の形態について，図面を参照して詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
　図1は本発明の第1実施形態による4h-SiC n型IGBTの断面構造を示す概念図である。図1において，本実施形態による4h-SiCトレンチ型パワーMOSFETは，コレクタ電極1と裏面シリサイド領域2とp+コレクタ領域3とn+バッファ領域4とn-ドリフト領域5とp+ボディ領域6と第1エミッタ領域7と第2エミッタ領域8とゲート絶縁膜9とゲート電極10と表面側シリサイド領域11とエミッタ電極12からなる。 FIG. 1 is a conceptual diagram showing a cross-sectional structure of a 4h-SiC n-type IGBT according to the first embodiment of the present invention. In FIG. 1, the 4h-SiC trench type power MOSFET according to the present embodiment includes a collector electrode 1, a backside silicide region 2, a p + collector region 3, an n + buffer region 4, an n − drift region 5 and a p + body region 6. The first emitter region 7, the second emitter region 8, the gate insulating film 9, the gate electrode 10, the surface side silicide region 11 and the emitter electrode 12 are included.
　コレクタ電極1はAl, Ti, Ni, Au, Agなどの金属のスパッタされた電極領域である。裏面シリサイド領域2はSiとAlを含む金属が結合したシリサイド層の領域である。p+コレクタ領域3は例えばAl:アルミニウムやB:ホウ素などp型不純物を含むp型SiCの領域である。 The collector electrode 1 is a sputtered electrode region of a metal such as Al, Ti, Ni, Au, Ag. The backside silicide region 2 is a region of a silicide layer in which a metal containing Si and Al is bonded. The p + collector region 3 is a p-type SiC region containing p-type impurities such as Al: aluminum and B: boron.
　n+バッファ領域4は例えばN:窒素やP:リンなどn型不純物を含むn型SiCの領域である。n-ドリフト領域5は例えばNやPなどn型不純物を含むn型SiCの領域である。なおn-ドリフト領域5のn型不純物濃度はn+バッファ領域よりも常に低く，たとえばn+バッファ領域4の濃度は1×1019cm-3未満n-ドリフト領域5の濃度は2×1015cm-3未満である。 The n + buffer region 4 is an n-type SiC region containing n-type impurities such as N: nitrogen and P: phosphorus. The n − drift region 5 is an n-type SiC region containing n-type impurities such as N and P, for example. Note that the n-type impurity concentration of the n − drift region 5 is always lower than that of the n + buffer region, for example, the concentration of the n + buffer region 4 is less than 1 × 10 19 cm −3 , and the concentration of the n − drift region 5 is 2 × 10 15 less than cm- 3 .
　p+コレクタ領域3，n+バッファ領域4，n-ドリフト領域5は，例えばnまたはp層のバルク基板上にp+コレクタ領域3，n+バッファ領域4，n-ドリフト領域5の順番でエピタキシャル成長した後にバルク基板を研削するあるいは，nまたはp層のバルク基板上にn-ドリフト領域5，n+バッファ領域4，p+コレクタ領域3の順番でエピタキシャル成長した後にバルク基板を研削することで形成する。 p + collector region 3, n + buffer region 4, n - drift region 5, for example, n or p + collector region in the bulk substrate of the p layer 3, n + buffer region 4, n - epitaxial growth in the order of the drift region 5 After forming the substrate, the bulk substrate is ground, or formed by epitaxially growing the n − drift region 5, n + buffer region 4, and p + collector region 3 in this order on the n or p layer bulk substrate and then grinding the bulk substrate. .
　p+ボディ領域6は例えばAlやBなどp型不純物を不純物注入またはエピタキシャル成長などでドリフト層上に形成したp型SiCの領域である。第1エミッタ領域7は例えばNやPなどのn型不純物を例えば1×1019cm-3以上など高濃度に注入するなどして形成したn型SiCの領域である。第2エミッタ領域8は例えばAlやBなどのp型不純物を例えば1×1019cm-3以上など高濃度に注入するなどして形成したp型SiCの領域である。 The p + body region 6 is a p-type SiC region formed on the drift layer by, for example, impurity implantation or epitaxial growth of p-type impurities such as Al and B. The first emitter region 7 is an n-type SiC region formed by, for example, implanting an n-type impurity such as N or P at a high concentration such as 1 × 10 19 cm −3 or more. The second emitter region 8 is a p-type SiC region formed by, for example, implanting a p-type impurity such as Al or B at a high concentration such as 1 × 10 19 cm −3 or more.
　ゲート絶縁膜9はn-ドリフト領域5，p+ボディ領域6，第1エミッタ領域7の上にまたがるように形成された絶縁膜の層である。このゲート絶縁膜9は例えばウェット酸化，ドライ酸化あるいはSiO2酸化膜のCVD(Chemical Vapor Deposition)などによって形成される。ゲート電極10はゲート絶縁膜9の形成後，その直上にポリシリコンのCVD またはアモルファスシリコンのCVD後，熱処理でポリシリコンに変性させるなどで形成した電極領域である。 The gate insulating film 9 is an insulating film layer formed so as to straddle the n − drift region 5, the p + body region 6, and the first emitter region 7. The gate insulating film 9 is formed by, for example, wet oxidation, dry oxidation, or CVD (Chemical Vapor Deposition) of SiO 2 oxide film. The gate electrode 10 is an electrode region formed by, after forming the gate insulating film 9, immediately after the CVD of polysilicon or CVD of amorphous silicon, it is transformed into polysilicon by heat treatment.
　表面側シリサイド領域11は第1エミッタ領域と第2エミッタ領域上にまたがるように形成したSiと例えばNiなどの金属が結合してできたシリサイド領域である。エミッタ電極12は表面側シリサイド領域11ならびにデバイス前面を覆うようにAl, Ti, Niなどの金属がスパッタされた電極領域である。裏面シリサイド領域2は例えばAlを含む金属をp型コレクタ領域3にスパッタ後にレーザーアニールで形成する。これによりスパッタした金属のうちp型コレクタ領域3に接する最表面のみをシリサイド化して，シリサイド層を表面側シリサイド領域11よりも薄く形成する。これによりp+コレクタ領域3における少数キャリアライフタイムの劣化ならびに特性ばらつき耐性ならびに通電劣化耐性を向上させる。レーザーアニールは，所望の領域のみをアニールできるので，例えばRTA (Rapid Thermal Annealing )のように、デバイス全体を加熱する方法に比べてデバイスの信頼性維持に利点がある。裏面シリサイド領域2形成後，コレクタ電極1を形成する。なお、裏面シリサイド領域2，コレクタ電極1の形成は、デバイス（回路）部分の作成前でも後でもよいが、作成前のほうが素子に影響を与えるおそれが少ない。 The surface side silicide region 11 is a silicide region formed by combining Si formed so as to straddle the first emitter region and the second emitter region and a metal such as Ni. The emitter electrode 12 is an electrode region in which a metal such as Al, Ti, or Ni is sputtered so as to cover the surface side silicide region 11 and the front surface of the device. The backside silicide region 2 is formed by laser annealing after sputtering, for example, a metal containing Al on the p-type collector region 3. As a result, only the outermost surface in contact with the p-type collector region 3 of the sputtered metal is silicided, and the silicide layer is formed thinner than the surface-side silicide region 11. This improves minority carrier lifetime degradation, characteristic variation tolerance, and current degradation resistance in the p + collector region 3. Since laser annealing can anneal only a desired region, there is an advantage in maintaining device reliability as compared to a method of heating the entire device, such as RTA (Rapid Thermal Annealing). After the backside silicide region 2 is formed, the collector electrode 1 is formed. The backside silicide region 2 and the collector electrode 1 may be formed before or after the device (circuit) portion is formed, but there is less possibility that the device will be affected before the device is formed.
第２の実施形態Second embodiment
　図3で本発明による第2実施形態を説明する。図3は，図1の裏面コレクタ電極1側を示し、シリサイド領域2の作成過程を説明するものである。作成された素子構造は、図3Cに示すようにAlを含む裏面金属層13が裏面コレクタ電極1と裏面シリサイド領域2の間に存在し，それ以外の構造は図1の構成と同一である。これを作成するには，たとえばAlを含む金属300をp+コレクタ領域3上にスパッタ後，レーザ310照射によりアニール処理をする（図3A）。このとき、Siと結合した裏面シリサイド領域2と未反応で残された裏面金属層13が同時に形成される（図3B）。この場合には、Alを含む裏面金属層13と裏面シリサイド領域2の接触面におけるSi, C, Alなどの組成は互いに同一となる。その後Al, Ti, Ni, Au, Ag等によりコレクタ電極層1を形成する（図3C）。この構造により裏面シリサイド層2とコレクタ電極層1の密着性を向上し，膜はがれによる信頼性劣化を防ぐことが可能となる。 A second embodiment according to the present invention will be described with reference to FIG. FIG. 3 shows the back collector electrode 1 side of FIG. 1, and explains the process of forming the silicide region 2. FIG. In the fabricated device structure, as shown in FIG. 3C, a back surface metal layer 13 containing Al exists between the back surface collector electrode 1 and the back surface silicide region 2, and the other structure is the same as the structure of FIG. In order to create this, for example, a metal 300 containing Al is sputtered on the p + collector region 3, and then annealed by laser 310 irradiation (FIG. 3A). At this time, the backside silicide region 2 bonded to Si and the backside metal layer 13 left unreacted are simultaneously formed (FIG. 3B). In this case, the composition of Si, C, Al, etc. at the contact surface between the backside metal layer 13 containing Al and the backside silicide region 2 is the same. Thereafter, the collector electrode layer 1 is formed of Al, Ti, Ni, Au, Ag or the like (FIG. 3C). With this structure, the adhesion between the backside silicide layer 2 and the collector electrode layer 1 can be improved, and reliability deterioration due to film peeling can be prevented.
　なお、p+コレクタ領域3を形成するまでの工程は、特許文献１、特許文献２等に記載されている手法を適用すればよく、n型SiC基板上にp型SiC層を形成し、その後n型SiC基板を機械的または化学的研磨により除去してp+コレクタ領域3を露出した。 In addition, the process described in Patent Document 1, Patent Document 2, etc. may be applied to the process until the p + collector region 3 is formed. After forming the p-type SiC layer on the n-type SiC substrate, The n-type SiC substrate was removed by mechanical or chemical polishing to expose the p + collector region 3.
　後に図6，図7で説明するように、Alを含む金属300の表面には、反射率を調整するためにAl以外の物質，例えばTi, Ni, TiN等を被覆することが望ましい。この場合には、レーザアニールの結果，裏面金属層13と裏面シリサイド領域2には、Ti, Ni, TiNも存在することになる。 As will be described later with reference to FIGS. 6 and 7, it is desirable to coat the surface of the metal 300 containing Al with a substance other than Al, for example, Ti, Ni, TiN, etc. in order to adjust the reflectance. In this case, as a result of laser annealing, Ti, Ni, and TiN are also present in the back surface metal layer 13 and the back surface silicide region 2.
第３の実施形態Third embodiment
　本発明による第3実施形態は，第1、第2の実施形態の4h-SiC 絶縁ゲートバイポーラトランジスタにおいて，裏面シリサイド領域2がAlを含み， 深さ（厚さ）が20nm未満であることを特徴とする。 The third embodiment according to the present invention is characterized in that, in the 4h-SiC insulated gate bipolar transistor of the first and second embodiments, the backside silicide region 2 contains Al and the depth (thickness) is less than 20 nm. And
　N型SiC-IGBTは裏面コレクタp+領域3の膜厚や濃度，少数キャリアライフタイムを変えることで正孔の注入効率を調整できる。しかし，濃度は下げすぎると電極形成時のコンタクト抵抗を増大させる懸念があり，また結晶に欠陥を加えるなどの方法によるライフタイムのコントロールは信頼性を損ねる懸念がある。一方コレクタp+領域3の膜厚はこのような課題なくコントロール可能である。 N-type SiC-IGBT can adjust the hole injection efficiency by changing the film thickness and concentration of the back collector p + region 3 and the minority carrier lifetime. However, if the concentration is too low, there is a concern that the contact resistance at the time of electrode formation will increase, and there is a concern that the lifetime control by a method such as adding a defect to the crystal will impair the reliability. On the other hand, the film thickness of the collector p + region 3 can be controlled without such a problem.
　図2の概念図に示すように一般にスイッチング損失と，導通時の損失はトレードオフ関係にあり，コレクタp+領域3の膜厚を薄くすると正孔注入効率が下がりスイッチング損失が下がる一方で，導通損失は増大する。このバランスは実際のデバイスのスイッチング周波数など，使用用途によって決まる。この正孔注入効率を下げるための膜厚調整による効果は，コレクタp+領域3の膜厚を例えば2μm未満程度に薄くすると，顕著に現れる。 As shown in the conceptual diagram in Fig. 2, switching loss and loss during conduction are generally in a trade-off relationship. If the thickness of collector p + region 3 is reduced, hole injection efficiency decreases and switching loss decreases. Loss increases. This balance is determined by the intended use, such as the actual device switching frequency. The effect of the film thickness adjustment for reducing the hole injection efficiency is noticeable when the film thickness of the collector p + region 3 is reduced to, for example, less than 2 μm.
　しかしコレクタp+領域3が薄いとシリサイド化に伴う熱処理による膜厚変動による特性変動，さらには上述した信頼性劣化の影響をより強く受ける。本実施例による薄い裏面シリサイド領域2の形成によりこのような懸念がなく，コレクタp+領域3の膜厚で正孔注入効率を調整することが可能になる。コレクタp+領域3の膜厚は，SiC-IGBTに先行して製品化されているSi-IGBTで100nm程度の厚さで使用されていることを考慮すると，SiC-IGBTにおいても同様の膜厚まで膜厚調整が可能であることが望ましい。この目的のためには裏面シリサイド領域2の深さは20nm未満であることが望ましい。この裏面シリサイド領域2の形成は例えば第1, 第2の実施形態と同じくレーザーアニールで形成する。また、裏面シリサイド領域2の深さは，コレクタ電極1の動作のためには5nm以上が望ましい。 However, if the collector p + region 3 is thin, it is more strongly affected by the characteristic fluctuation due to the film thickness fluctuation caused by the heat treatment accompanying silicidation, and further by the reliability deterioration described above. By forming the thin backside silicide region 2 according to the present embodiment, there is no such concern, and the hole injection efficiency can be adjusted by the film thickness of the collector p + region 3. In consideration of the fact that the collector p + region 3 has a thickness of about 100 nm in the Si-IGBT that has been commercialized prior to the SiC-IGBT, the same thickness is applied to the SiC-IGBT. It is desirable that the film thickness can be adjusted. For this purpose, the depth of the backside silicide region 2 is preferably less than 20 nm. The backside silicide region 2 is formed by, for example, laser annealing as in the first and second embodiments. The depth of the backside silicide region 2 is desirably 5 nm or more for the operation of the collector electrode 1.
　なお，この裏面シリサイド領域2とコレクタ電極1の間に第2の実施形態と同様のAlを含む裏面金属層13が存在すると，第2の実施形態と同様の信頼性劣化を防ぐ効果がある。第2の実施形態のように、レーザでシリサイド層と金属層を同時に形成すると，両方の層はともにその少なくとも一部に，AlとAl以外の同種の物質（例えばTi, Ni, TiNなど）を含有することになる。 It should be noted that the presence of a back metal layer 13 containing Al similar to that in the second embodiment between the back silicide region 2 and the collector electrode 1 has the effect of preventing the same deterioration in reliability as in the second embodiment. When the silicide layer and the metal layer are simultaneously formed by laser as in the second embodiment, both layers are made of at least a part of the same kind of material (for example, Ti, Ni, TiN, etc.) other than Al and Al. It will contain.
第４の実施形態Fourth embodiment
　図4で本発明の第4実施例を説明する。本発明による第4実施形態は，第1-第3の実施形態の4h-SiC 絶縁ゲートバイポーラトランジスタと基本的に同様の構成である。さらなる特徴として，表面シリサイド領域が，図4のように表面第1シリサイド領域19と表面第2シリサイド領域20に分かれている。表面第1シリサイド領域19は，n型SiCの領域である第1エミッタ領域側にある。表面第2シリサイド領域20は，p型SiCの領域である第2エミッタ領域8側にある。表面第1シリサイド領域19がNiシリサイドで形成され，表面第2シリサイド領域20がAlを含むシリサイドで形成される。ここで，裏面シリサイド領域2の膜厚が表面第1シリサイド領域19と表面第2シリサイド領域20よりも薄いことを特徴とする。裏面コレクタ領域側についての本実施例の効果は第1-第3の実施形態と同一である。本実施例にあるように，表面第2シリサイド領域20をAlを含むシリサイドで形成することにより，エミッタ電極12から第2エミッタ領域8に流出する際の正孔のコンタクト抵抗を下げることが可能になる。 FIG. 4 illustrates a fourth embodiment of the present invention. The fourth embodiment of the present invention has basically the same configuration as the 4h-SiC-insulated gate bipolar transistor of the first to third embodiments. As a further feature, the surface silicide region is divided into a surface first silicide region 19 and a surface second silicide region 20 as shown in FIG. The surface first silicide region 19 is on the first emitter region side which is an n-type SiC region. The surface second silicide region 20 is on the second emitter region 8 side which is a p-type SiC region. The surface first silicide region 19 is formed of Ni silicide, and the surface second silicide region 20 is formed of silicide containing Al. Here, the thickness of the backside silicide region 2 is smaller than that of the front surface first silicide region 19 and the front surface second silicide region 20. The effect of the present embodiment on the back collector region side is the same as that of the first to third embodiments. As in the present embodiment, by forming the surface second silicide region 20 with silicide containing Al, it is possible to reduce the contact resistance of holes when flowing from the emitter electrode 12 to the second emitter region 8. Become.
第５の実施形態Fifth embodiment
　本発明による第5実施形態は，本発明の第1-第4の実施形態でAlを含むシリサイド層をレーザーアニールで形成する際の構成に関する。具体例として、図1の構成において、p+コレクタ領域3（p型SiC基板21）にシリサイド領域2を形成する場合を例に説明する。 The fifth embodiment according to the present invention relates to a configuration when a silicide layer containing Al is formed by laser annealing in the first to fourth embodiments of the present invention. As a specific example, the case where the silicide region 2 is formed in the p + collector region 3 (p-type SiC substrate 21) in the configuration of FIG. 1 will be described as an example.
　図5に示すように，まずp型SiC基板21にAl 22をスパッタし，その後スパッタしたAl 22の表面を覆うようにTi, Ni, TiNなどの金属膜23をスパッタする（図1と上下逆に描かれている）。材料はこれらの金属単独でもよいし、合金としてもよい。その後，レーザを金属膜23に照射すると，金属膜23とアルミ22と基板21のSiCがアニリングされて，アルミを含むシリサイド金属層24と未反応金属層25が形成される。 As shown in FIG. 5, first, Al—22 is sputtered on a p-type SiC substrate 21, and then a metal film 23 such as Ti, Ni, and TiN is sputtered to cover the surface of the sputtered Al 22 (upside down from FIG. Is drawn on). The material may be a single metal or an alloy of these metals. Thereafter, when the metal film 23 is irradiated with laser, the SiC of the metal film 23, the aluminum 22, and the substrate 21 is annealed, and a silicide metal layer 24 containing aluminum and an unreacted metal layer 25 are formed.
　図6に別の例を示す。Al 22と金属膜23の位置関係は，図6のようにアルミ22と他の金属23の積層構造になっていてもよい。 Figure 6 shows another example. The positional relationship between the Al 22 and the metal film 23 may be a laminated structure of the aluminum 22 and another metal 23 as shown in FIG.
　図7はさらに他の例を示す。図7のように一番下の層が金属膜23になっていてもよい。 Fig. 7 shows another example. The lowermost layer may be the metal film 23 as shown in FIG.
　図6あるいは図7の多層構造であっても、レーザアニリング後は、図5のように金属とSiCが反応し、シリサイド層24と未反応金属層25が形成される。 6 or 7, after laser annealing, the metal and SiC react as shown in FIG. 5 to form a silicide layer 24 and an unreacted metal layer 25.
　多層構造では最表面は金属膜23であることが望ましい。これは，Alが広域の波長にわたってレーザ光に対する反射率が高くレーザ照射の効果がなくなるため，最表面はレーザ光を吸収または透過する金属にすることが望ましいからである。またAlはシリサイド化反応させる必要があるため合計膜厚は10nm以上あることが望ましく，また厚すぎるとSiCと近接するAlの反応を妨げるので1um未満であることが望ましい。また金属膜23は図7のようにp型SiC基板21と接する最下層の面はAlとSiCの反応が妨げられることを防ぐために100nm未満の膜厚であることが望ましい。 In the multilayer structure, it is desirable that the outermost surface is the metal film 23. This is because Al has a high reflectivity with respect to laser light over a wide range of wavelengths and the effect of laser irradiation is lost, so that the outermost surface is preferably a metal that absorbs or transmits laser light. Also, since Al needs to undergo silicidation reaction, the total film thickness is desirably 10 nm or more, and if it is too thick, reaction of Al adjacent to SiC is hindered, so it is desirably less than 1 um. Further, as shown in FIG. 7, the lowermost surface of the metal film 23 in contact with the p-type SiC substrate 21 preferably has a thickness of less than 100 nm in order to prevent the reaction between Al and SiC from being hindered.
　またレーザの照射条件はSiCのバンドギャップ相当以上のエネルギーにするために400nm未満であることが望ましい。またレーザの照射強度ならびにスキャン速度は，アニールの条件が弱すぎると，AlがSiCと反応せずまた強すぎるとSiCからシリサイド面表面に析出したCによりコンタクト抵抗が下がるために波長が400nm未満100nm以上のとき照射強度は1.8J以上3.5J未満，スキャン速度が5mm/s以上100mm/s未満のレーザーアニールでの形成が望ましい。 Also, it is desirable that the laser irradiation conditions be less than 400 nm in order to make the energy equivalent to the SiC band gap or more. Also, the laser irradiation intensity and scan speed are less than 400 nm because the contact resistance is reduced by C deposited on the silicide surface from SiC if Al does not react with SiC if the annealing conditions are too weak and if it is too strong. In these cases, it is desirable to form by laser annealing with an irradiation intensity of 1.8 J or more and less than 3.5 J and a scanning speed of 5 mm / s or more and less than 100 mm / s.
第６の実施形態Sixth embodiment
　本発明による第6実施形態は，本発明の図4の構成で，表面第2シリサイド領域20におけるAlを含むシリサイド層をレーザーアニールで形成する際の形成プロセスに関する。 The sixth embodiment according to the present invention relates to a formation process when a silicide layer containing Al in the surface second silicide region 20 is formed by laser annealing in the configuration of FIG. 4 of the present invention.
　図8に示すようにまず， p+　SiC層8とn+　SiC層7にNi層80をスパッタ等で形成する。このときのNi層80の膜厚は例えば，直接レーザ照射してもSiCとの界面に影響が出ない程度に厚くしておく。 As shown in FIG. 8, first, a Ni layer 80 is formed on the p + SiC layer 8 and the n + SiC layer 7 by sputtering or the like. At this time, the thickness of the Ni layer 80 is increased to such an extent that, even if direct laser irradiation is performed, the interface with SiC is not affected.
　次に，ウェットエッチまたはドライエッチなどの方法によりNi層80をp+　SiC層8上のみ選択的に除去する。 Next, the Ni layer 80 is selectively removed only on the p + SiC layer 8 by a method such as wet etching or dry etching.
　次に、Ni層80に選択的にレーザ照射してアニリングを行い、Ni シリサイド層19を形成する。 Next, the Ni layer 80 is selectively irradiated with a laser and annealed to form a Ni-silicide layer 19.
　図9で引き続き説明する。Ni シリサイド層19とAlシリサイド層を形成するp+　SiC層8の上にAl 90をスパッタする。 The description will be continued with reference to FIG. Al 90 is sputtered on the p + SiC layer 8 forming the Ni silicide layer 19 and the Al silicide layer.
　次に、ウェットエッチまたはドライエッチなどの方法により，Al 90 をp+　SiC層8上のみ選択的に除去する。 Next, Al 90 is selectively removed only on the p + SiC layer 8 by a method such as wet etching or dry etching.
　その後、Al 90を全体にスパッタし、Al膜厚を調整する。Ni シリサイド層19上ではNi シリサイド層を保護できる膜厚とし、p+　SiC層8上では、Alシリサイド層を形成するために必要な膜厚とする。 Thereafter, Al 90 is sputtered to adjust the Al film thickness. The Ni silicide layer 19 has a thickness capable of protecting the Ni silicide layer, and the p + SiC layer 8 has a thickness necessary for forming the Al silicide layer.
　このときのAlの膜厚は例えば，直接レーザ照射してもSiCとの界面に影響が出ない程度に厚くしておく。なお図9においてAlシリサイド層を形成しない領域をn+　SiC層7で代表させたが，これは例えば図1におけるゲート電極10のように他の構造であってもよい。その後，アルミ以外の金属膜91を反射防止のために，p+　SiC層8上のAl 90の上のみ形成する。 At this time, the film thickness of Al is increased to such an extent that, for example, direct laser irradiation does not affect the interface with SiC. In FIG. 9, the region where the Al silicide layer is not formed is represented by the n + SiC layer 7, but this may be another structure such as the gate electrode 10 in FIG. Thereafter, a metal film 91 other than aluminum is formed only on Al 90 on the p + SiC layer 8 to prevent reflection.
　なお，Alは p+　SiC層8でいったん全てエッチングしてから再度スパッタする方法は適用せずに，例えば始めの1回で所望の膜厚を残してエッチングするなどの方法で形成してもよい。この後本発明の第5実施形態によるレーザーアニールをすると，表面がAl層である部分ではレーザーは反射されて熱負荷がかかることなく，p+　SiC層8の上のみがシリサイド化され，Alシリサイド層20と未反応金属層92が形成される。第2の実施形態で説明したのと同様に，未反応金属層92はAlシリサイド層20とエミッタ電極層12の密着性を向上し，膜はがれによる信頼性劣化を防ぐことが可能となる。 Note that Al may be formed by a method such as etching without leaving the desired film thickness at the first time, without applying the method of once etching with the p + SiC layer 8 and then sputtering again. . Thereafter, when laser annealing according to the fifth embodiment of the present invention is performed, the laser is reflected at the portion where the surface is the Al layer, and no thermal load is applied, and only the p + SiC layer 8 is silicided, and the Al silicide is formed. Layer 20 and unreacted metal layer 92 are formed. As described in the second embodiment, the unreacted metal layer 92 improves the adhesion between the Al silicide layer 20 and the emitter electrode layer 12, and can prevent deterioration in reliability due to film peeling.
　本発明の-第4の実施形態における，表面第1シリサイド領域19，表面第2シリサイド領域20の形成後にゲート絶縁膜9，ゲート電極10などを形成すると，絶縁膜中にシリサイド形成時の金属が混入しデバイスの不具合の原因となることが懸念される。このために，表面第1シリサイド領域19，表面第2シリサイド領域20はゲート絶縁膜9，ゲート電極10などの形成後に形成することが好ましい。本実施形態を適用することにより他の領域に熱負荷がかかることなく表面第2シリサイド領域20のみをシリサイド化することが可能となる。 In the fourth embodiment of the present invention, when the gate insulating film 9 and the gate electrode 10 are formed after the formation of the surface first silicide region 19 and the surface second silicide region 20, the metal at the time of silicide formation is formed in the insulating film. There is a concern that it may be mixed and cause a malfunction of the device. Therefore, the surface first silicide region 19 and the surface second silicide region 20 are preferably formed after the formation of the gate insulating film 9, the gate electrode 10, and the like. By applying this embodiment, only the surface second silicide region 20 can be silicided without applying a thermal load to other regions.
第７の実施形態Seventh embodiment
　図10は本発明の第7実施形態による4h-SiC n型IGBTの断面構造を示す概念図である。図1で示した構造と同様の構成は同じ符号を付している。図10の構成では，ゲート絶縁膜9b，ゲート電極10b，エミッタ電極12bの形状が図1の例とは異なるが、図1の構成と同様の原理で動作する。 FIG. 10 is a conceptual diagram showing a cross-sectional structure of a 4h-SiC n-type IGBT according to the seventh embodiment of the present invention. The same components as those shown in FIG. 1 are denoted by the same reference numerals. In the configuration of FIG. 10, the shapes of the gate insulating film 9b, the gate electrode 10b, and the emitter electrode 12b are different from the example of FIG. 1, but operate according to the same principle as the configuration of FIG.
　図10の構成においても、表面シリサイド領域11と裏面シリサイド領域2の構造および製法については，第1～６の実施形態で説明した構成が適用でき，同様の効果をえることができる。 In the configuration of FIG. 10 as well, the configurations described in the first to sixth embodiments can be applied to the structure and manufacturing method of the front surface silicide region 11 and the back surface silicide region 2, and similar effects can be obtained.
第８の実施形態Eighth embodiment
　本発明による第8実施形態は，先に述べた実施形態によるn型SiC-IGBTを適用した電力変換機に関する。 The eighth embodiment according to the present invention relates to a power converter to which the n-type SiC-IGBT according to the above-described embodiment is applied.
　本発明による電力変換装置を備える電力変換装置は例えば，鉄道車両に用いることができる。この鉄道車両に適用される三相モータシステムを図11を用いて説明する。 The power conversion device including the power conversion device according to the present invention can be used for, for example, a railway vehicle. A three-phase motor system applied to this railway vehicle will be described with reference to FIG.
　図11は，鉄道車両に適用される三相モータシステムの一例を示すブロック図である。鉄道車両には架線RTからパンダグラフPGを介して電力が供給される。架線ＲＴの高圧交流電圧は，例えば25kVまたは15kVである。この高圧交流電圧は，絶縁型の主変圧器MTRによって，例えば3.3kVの交流電圧に降圧される。降圧された交流電圧は，コンバータAC/DCによって直流電圧3.3kVに順変換される。その後，この直流電圧はキャパシタCLを介してインバータDC/ACによって交流電圧に変換され，三相モータMO3に所望の三相交流電圧が出力されて，三相モータMO3が駆動する。なお図11中，符号WHLは車輪を示す。 FIG. 11 is a block diagram showing an example of a three-phase motor system applied to a railway vehicle. Electric power is supplied to the railway vehicle from the overhead line RT via the panda graph PG. The high voltage AC voltage of the overhead line RT is, for example, 25 kV or 15 kV. This high-voltage AC voltage is stepped down to an AC voltage of, for example, 3.3 kV by the insulated main transformer MTR. The stepped-down AC voltage is forward converted to a DC voltage of 3.3 kV by the converter AC / DC. Thereafter, the DC voltage is converted into an AC voltage by the inverter DC / AC via the capacitor CL, and a desired three-phase AC voltage is output to the three-phase motor MO3, thereby driving the three-phase motor MO3. In FIG. 11, the symbol WHL indicates a wheel.
　このように，鉄道車両の三相モータシステムを構成するコンバータAC/DCおよびインバータDC/ACに，本発明のn型SiC-IGBTを適用することができる。本発明のn型SiC-IGBTを適用すると， SiC-IGBTは同じ耐圧のSiC-MOSFETと比較すると駆動電流量が大きくかつSi-IGBTと比較すると1デバイスあたりの耐圧が高いので部品点数を少なくすることができ，かつ本発明の効果によりコンバータ回路部およびインバータ回路部の高信頼化を図ることができる。また本発明の効果により損失の小さなSiC-IGBTの設計が可能となるために放熱フィン等の削減が可能となり三相モータシステムの体積を小さくすることができる。これにより，例えば三相モータシステムを含む床下部品の小型化による鉄道車両の低床化を図ることができる。また，例えば床下部品の小型化によって鉄道車両の一部に蓄電池SBを新たに設置できるスペースを確保することができるので，車両が走行していない場合，車輪WHLを経由して電力を架線RTに戻さずに，蓄電池SBに電力を蓄積することができる。その結果，鉄道車両の回生効率を向上させることができる。言い換えれば，鉄道システムのライフサイクルコストを低減することができる。 As described above, the n-type SiC-IGBT of the present invention can be applied to the converter AC / DC and the inverter DC / AC constituting the three-phase motor system of the railway vehicle. When the n-type SiC-IGBT of the present invention is applied, the SiC-IGBT has a larger drive current than the SiC-MOSFET with the same breakdown voltage, and the breakdown voltage per device is higher than the Si-IGBT, reducing the number of parts. In addition, the converter circuit portion and the inverter circuit portion can be made highly reliable by the effect of the present invention. In addition, because of the effect of the present invention, it is possible to design a SiC-IGBT with a small loss, so that the number of heat radiation fins can be reduced and the volume of the three-phase motor system can be reduced. As a result, for example, the floor of the railway vehicle can be reduced by downsizing the underfloor parts including the three-phase motor system. In addition, for example, by downsizing the underfloor parts, it is possible to secure a space where a storage battery SB can be newly installed in a part of the railway vehicle. Therefore, when the vehicle is not traveling, power is transferred to the overhead line RT via the wheels WHL. The electric power can be stored in the storage battery SB without returning. As a result, the regeneration efficiency of the railway vehicle can be improved. In other words, the life cycle cost of the railway system can be reduced.
　本発明は上記した実施形態に限定されるものではなく、様々な変形例が含まれる。例えば、ある実施例の構成の一部を他の実施例の構成に置き換えることが可能であり、また、ある実施例の構成に他の実施例の構成を加えることが可能である。また、各実施例の構成の一部について、他の実施例の構成の追加・削除・置換をすることが可能である。 The present invention is not limited to the above-described embodiment, and includes various modifications. For example, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace the configurations of other embodiments with respect to a part of the configurations of the embodiments.
　本明細書等において「電極」や「配線」の用語は、これらの構成要素を機能的に限定するものではない。例えば、「電極」は「配線」の一部として用いられることがあり、その逆もまた同様である。さらに、「電極」や「配線」の用語は、複数の「電極」や「配線」が一体となって形成されている場合なども含む。 In this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.
　絶縁ゲートバイポーラトランジスタおよびこれを適用した電力変換装置に利用可能である。 It can be used for an insulated gate bipolar transistor and a power conversion device using the same.
1,  コレクタ電極 
2,  裏面シリサイド領域 
3. p+コレクタ領域 
4. n+バッファ領域 
5. n-ドリフト領域 
6. p+ボディ領域 
7 第1エミッタ領域
8 第2エミッタ領域
9 ゲート絶縁膜 
10 ゲート電極 
11. 表面側シリサイド領域 
12. エミッタ電極 
13. Alを含む裏面金属領域 
19.表面第1シリサイド領域 
20.表面第2シリサイド領域 
21. p+　SiC基板 
22. Al
23. 表面金属膜  1, collector electrode
2, Backside silicide region
3.p + collector area
4.n + buffer area
5. n - drift region
6.p + body region
7 First emitter region
8 Second emitter region
9 Gate insulation film
10 Gate electrode
11. Surface side silicide region
12. Emitter electrode
13. Backside metal region containing Al
19.Surface first silicide region
20.Surface second silicide region
21.p + SiC substrate
22. Al
23. Surface metal film

Claims (15)

  1. 　裏面コレクタ電極と，
    　前記裏面コレクタ電極に電気的に接続されるAlを含む裏面シリサイド領域と，
    　前記裏面シリサイド領域に電気的に接続される第2導電型のコレクタ領域と，
    　前記第2導電型のコレクタ領域に電気的に接続される第1導電型のバッファ領域と，
    　前記バッファ領域に電気的に接続される第1導電型のドリフト領域と，
    　前記第1導電型のドリフト領域に電気的に接続される第2導電型のボディ領域と，
    　前記第2導電型のボディ領域に電気的に接続される第1導電型の第1エミッタ領域と，
    　前記第1導電型の第1エミッタ領域に隣接し、前記第2導電型のボディ領域に電気的に接続される第2導電型の第2エミッタ領域と，
    　前記第1導電型の第1エミッタ領域，前記ドリフト領域，および前記ボディ領域に跨り、これらの少なくとも一部を覆うゲート絶縁膜と，
    　前記ゲート絶縁膜上に配置されたゲート電極と，
    　前記第1導電型の第1エミッタ領域と第2導電型の第2エミッタ領域に電気的に接続される表面シリサイド領域と，
    　前記表面シリサイド領域に電気的に接続されるエミッタ電極からなり，
    　前記裏面シリサイド領域の厚さが前記表面シリサイド領域の厚さよりも薄いことを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタ。     A back collector electrode;
    A backside silicide region comprising Al electrically connected to the backside collector electrode;
    A second conductivity type collector region electrically connected to the backside silicide region;
    A first conductivity type buffer region electrically connected to the second conductivity type collector region;
    A first conductivity type drift region electrically connected to the buffer region;
    A second conductivity type body region electrically connected to the first conductivity type drift region;
    A first conductivity type first emitter region electrically connected to the second conductivity type body region;
    A second conductivity type second emitter region adjacent to the first conductivity type first emitter region and electrically connected to the second conductivity type body region;
    A gate insulating film covering at least a portion of the first conductivity type first emitter region, the drift region, and the body region; and
    A gate electrode disposed on the gate insulating film;
    A surface silicide region electrically connected to the first conductivity type first emitter region and the second conductivity type second emitter region;
    An emitter electrode electrically connected to the surface silicide region;
    4h-SiC insulated gate bipolar transistor, wherein the thickness of the backside silicide region is thinner than the thickness of the frontside silicide region.
  2. 　前記，請求項1の4h-SiC 絶縁ゲートバイポーラトランジスタにおいて，
    　Alを含む金属層が前記コレクタ電極と前記コレクタ領域の間に存在することを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタ。     In the 4h-SiC insulated gate bipolar transistor of claim 1,
    A 4h-SiC insulated gate bipolar transistor, wherein a metal layer containing Al exists between the collector electrode and the collector region.
  3. 　前記，請求項1の4h-SiC 絶縁ゲートバイポーラトランジスタにおいて，
    　前記裏面シリサイド領域の深さが20nm未満であることを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタ。     In the 4h-SiC insulated gate bipolar transistor of claim 1,
    4h-SiC insulated gate bipolar transistor, characterized in that the depth of the backside silicide region is less than 20 nm.
  4. 　前記，請求項1の4h-SiC 絶縁ゲートバイポーラトランジスタにおいて，
    　前記コレクタ電極と前記コレクタ領域の間には，
    　前記裏面シリサイド領域を構成する厚さ20nm未満5nm以上のシリサイド層と、金属層が存在し，
    　前記シリサイド層と金属層は，ともにその少なくとも一部にAlとAl以外の同種の物質を含有することを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタ。     In the 4h-SiC insulated gate bipolar transistor of claim 1,
    Between the collector electrode and the collector region,
    A silicide layer having a thickness of less than 20 nm and 5 nm or more constituting the backside silicide region, and a metal layer,
    The 4h-SiC insulated gate bipolar transistor, wherein both the silicide layer and the metal layer contain at least a part of the same kind of material other than Al and Al.
  5. 　前記，請求項4の4h-SiC 絶縁ゲートバイポーラトランジスタにおいて，
    　前記Al以外の同種の物質は，Ti, Ni, TiNから選ばれる少なくとも一つであることを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタ。     In the 4h-SiC insulated gate bipolar transistor of claim 4,
    4h-SiC insulated gate bipolar transistor characterized in that the same kind of material other than Al is at least one selected from Ti, Ni and TiN.
  6. 　前記，請求項1の4h-SiC 絶縁ゲートバイポーラトランジスタにおいて，
    　前記コレクタ電極から前記コレクタ領域に至る部分の構造は，
    　Al, Ti, Ni, Au, Agから選択された少なくとも一つを含む前記コレクタ電極と，
    　前記コレクタ電極に接するAlを含有する金属層と，
    　前記金属層に接する前記裏面シリサイド領域と，
    　前記裏面シリサイド領域に接する前記コレクタ領域からなる，
    　4h-SiC 絶縁ゲートバイポーラトランジスタ。     In the 4h-SiC insulated gate bipolar transistor of claim 1,
    The structure of the part from the collector electrode to the collector region is:
    The collector electrode comprising at least one selected from Al, Ti, Ni, Au, Ag;
    A metal layer containing Al in contact with the collector electrode;
    The backside silicide region in contact with the metal layer;
    Consisting of the collector region in contact with the backside silicide region,
    4h-SiC insulated gate bipolar transistor.
  7. 　前記，請求項1の4h-SiC 絶縁ゲートバイポーラトランジスタにおいて，
    　前記表面シリサイド領域が，前記第1導電型の第1エミッタ領域に電気的に接続されるNiシリサイドで形成された表面第1シリサイド領域と，前記第2導電型の第2エミッタ領域に電気的に接続されるAlを含むシリサイドで形成された表面第2シリサイド領域からなり，
    　前記裏面シリサイド領域の膜厚が前記表面第1シリサイド領域と表面第2シリサイド領域よりも薄いことを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタ。     In the 4h-SiC insulated gate bipolar transistor of claim 1,
    The surface silicide region is electrically connected to the surface first silicide region formed of Ni silicide and electrically connected to the first conductivity type first emitter region, and to the second conductivity type second emitter region. It consists of a surface second silicide region made of silicide containing Al to be connected,
    4h-SiC insulated gate bipolar transistor, wherein the thickness of the backside silicide region is thinner than that of the first surface silicide region and the second surface silicide region.
  8. 　第2導電型のコレクタ領域と，
    　前記コレクタ領域と電気的に接続される第1導電型のドリフト領域と，
    　前記ドリフト領域と電気的に接続される第2導電型のエミッタ領域と，
    　前記コレクタ領域と第1のシリサイド領域を介して電気的に接続されるコレクタ電極と，
    　前記エミッタ電極と第2のシリサイド領域を介して電気的に接続されるエミッタ電極と，
    　を備える4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法であって、
    　前記第1のシリサイド領域の厚さを前記第2のシリサイド領域の厚さよりも薄く形成することを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法。     A second conductivity type collector region;
    A first conductivity type drift region electrically connected to the collector region;
    A second conductivity type emitter region electrically connected to the drift region;
    A collector electrode electrically connected to the collector region via a first silicide region;
    An emitter electrode electrically connected to the emitter electrode via a second silicide region;
    A method of manufacturing a 4h-SiC insulated gate bipolar transistor comprising:
    A method of manufacturing a 4h-SiC insulated gate bipolar transistor, characterized in that the thickness of the first silicide region is formed thinner than the thickness of the second silicide region.
  9. 　前記，請求項8の4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法において，
    　前記第1のシリサイド領域を波長400nm未満のレーザーアニールで形成することを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法。     In the method of manufacturing a 4h-SiC insulated gate bipolar transistor according to claim 8,
    A method of manufacturing a 4h-SiC insulated gate bipolar transistor, wherein the first silicide region is formed by laser annealing with a wavelength of less than 400 nm.
  10. 　前記，請求項9の4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法において，
    　前記第1のシリサイド領域を照射強度が1.8J以上3.5J未満のレーザーアニールで形成することを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法。     In the method of manufacturing a 4h-SiC insulated gate bipolar transistor according to claim 9,
    A method of manufacturing a 4h-SiC insulated gate bipolar transistor, wherein the first silicide region is formed by laser annealing with an irradiation intensity of 1.8 J or more and less than 3.5 J.
  11. 　前記，請求項9の4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法において，
    　前記第1のシリサイド領域をスキャン速度が5mm/s以上100mm/s未満のレーザーアニールで形成することを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法。     In the method of manufacturing a 4h-SiC insulated gate bipolar transistor according to claim 9,
    A method of manufacturing a 4h-SiC insulated gate bipolar transistor, wherein the first silicide region is formed by laser annealing with a scan speed of 5 mm / s or more and less than 100 mm / s.
  12. 　前記，請求項8の4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法において，
    　前記第1のシリサイド領域の深さが20nm未満であることを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法。     In the method of manufacturing a 4h-SiC insulated gate bipolar transistor according to claim 8,
    A method of manufacturing a 4h-SiC insulated gate bipolar transistor, wherein the depth of the first silicide region is less than 20 nm.
  13. 　前記，請求項8の4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法において，
    　前記第1のシリサイド領域は，アルミニウムを含む第1の金属層にアルミニウム以外の金属を含む第2の金属層を積層し、前記第2の金属層側からレーザを照射し、前記第1および第2の金属層およびSiCを反応させて前記第1のシリサイド領域を形成することを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法。     In the method of manufacturing a 4h-SiC insulated gate bipolar transistor according to claim 8,
    The first silicide region is formed by laminating a second metal layer containing a metal other than aluminum on a first metal layer containing aluminum, irradiating a laser from the second metal layer side, and A method of manufacturing a 4h-SiC insulated gate bipolar transistor, comprising reacting two metal layers and SiC to form the first silicide region.
  14. 　前記，請求項13の4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法において，
    　前記第1および第2の金属層およびSiCを反応させて前記第1のシリサイド領域を形成する際に、シリサイド化されない金属層を同時に形成することを特徴とする，4h-SiC 絶縁ゲートバイポーラトランジスタの製造方法。     In the method of manufacturing a 4h-SiC insulated gate bipolar transistor according to claim 13,
    In the 4h-SiC insulated gate bipolar transistor, the first and second metal layers and SiC are reacted to form the first silicide region, and a metal layer that is not silicided is simultaneously formed. Production method.
  15. 　第2導電型のコレクタ領域と，
    　前記コレクタ領域と電気的に接続される第1導電型のドリフト領域と，
    　前記ドリフト領域と電気的に接続される第2導電型のエミッタ領域と，
    　前記コレクタ領域と第1のシリサイド領域を介して電気的に接続されるコレクタ電極と，
    　前記エミッタ電極と第2のシリサイド領域を介して電気的に接続されるエミッタ電極とを備え、
    　前記第1のシリサイド領域の厚さを前記第2のシリサイド領域の厚さよりも薄く形成される4h-SiC 絶縁ゲートバイポーラトランジスタを，
    　コンバータ回路部およびインバータ回路の少なくとも一つに用い、
    　直流・交流間の変換を行う4h-SiC 絶縁ゲートバイポーラトランジスタを適用した電力変換装置。     A second conductivity type collector region;
    A first conductivity type drift region electrically connected to the collector region;
    A second conductivity type emitter region electrically connected to the drift region;
    A collector electrode electrically connected to the collector region via a first silicide region;
    An emitter electrode electrically connected via the emitter electrode and a second silicide region;
    A 4h-SiC insulated gate bipolar transistor formed so that the thickness of the first silicide region is smaller than the thickness of the second silicide region;
    Used for at least one of converter circuit and inverter circuit,
    A power converter using a 4h-SiC insulated gate bipolar transistor that converts between DC and AC.
PCT/JP2014/072288 2014-08-26 2014-08-26 4h-SiC INSULATED GATE BIPOLAR TRANSISTOR, METHOD FOR MANUFACTURING SAME, AND POWER CONVERSION DEVICE WO2016030963A1 (en)

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