WO2016015538A1 - 具有时序控制功能的掉电检测电路 - Google Patents

具有时序控制功能的掉电检测电路 Download PDF

Info

Publication number
WO2016015538A1
WO2016015538A1 PCT/CN2015/082965 CN2015082965W WO2016015538A1 WO 2016015538 A1 WO2016015538 A1 WO 2016015538A1 CN 2015082965 W CN2015082965 W CN 2015082965W WO 2016015538 A1 WO2016015538 A1 WO 2016015538A1
Authority
WO
WIPO (PCT)
Prior art keywords
output end
comparator
switch tube
gate
detecting circuit
Prior art date
Application number
PCT/CN2015/082965
Other languages
English (en)
French (fr)
Inventor
李有慧
徐小丽
Original Assignee
无锡华润上华半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华半导体有限公司 filed Critical 无锡华润上华半导体有限公司
Priority to US15/327,956 priority Critical patent/US10254353B2/en
Publication of WO2016015538A1 publication Critical patent/WO2016015538A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/04—Voltage dividers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16538—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
    • G01R19/16552—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies in I.C. power supplies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision

Definitions

  • the present invention relates to the field of power supply control technologies, and in particular, to a power failure detection circuit having a timing control function.
  • the traditional brown out detector (BOD) is relatively simple.
  • the working principle is shown in Figure 1.
  • the output Bout of the BOD is high.
  • the power supply voltage Vcc is below a certain threshold value Vth, Bout immediately becomes a low level.
  • the conventional BOD is sensitive to the noise and interference of the power supply voltage, especially when the difference between the threshold value Vth and the power supply voltage Vcc is small and the noise and interference make Vcc lower than the threshold value Vth, even if the duration of noise and interference is short, Bout is also It will go low, making the system less resistant to noise and interference.
  • a power failure detecting circuit with a timing control function includes a voltage divider, a reference voltage source, a comparator and a timing control module, one end of the voltage divider is connected to an external power source, and the other end of the voltage divider is a forward input terminal of the comparator, the reference voltage source being coupled to an inverting input of the comparator, the timing control module being coupled to an output of the comparator, an output of the timing control module For the output end of the power-down detection circuit, when the duration of the power supply voltage lower than the reference voltage is not shorter than the preset time, the timing control module controls the output of the power-down detection circuit to go from a high level to a low level. Flip.
  • the above-mentioned power-down detection circuit with timing control function is provided with a timing control module, and when the power supply voltage is lower than the reference voltage only for a preset time due to noise and interference, the timing control module does not react to the power-down behavior.
  • the output of this circuit will not be flipped from high level to low level, that is, the circuit's ability to resist noise and interference is enhanced.
  • FIG. 1 is a schematic diagram showing the working principle of a conventional power-down detection circuit
  • FIG. 2 is a block diagram of a power failure detecting circuit with a timing control function according to an embodiment
  • FIG. 3 is a circuit schematic diagram of the timing control module of FIG. 2;
  • FIG. 4 is a schematic diagram showing the working principle of the power-down detecting circuit with timing control function shown in FIG. 2.
  • FIG. 4 is a schematic diagram showing the working principle of the power-down detecting circuit with timing control function shown in FIG. 2.
  • FIG. 2 it is a block diagram of a power failure detecting circuit having a timing control function according to an embodiment.
  • the power-down detection circuit with timing control function includes a voltage divider 110, a reference voltage source 120, a comparator 130, and a timing control module 140.
  • One end of the voltage divider 110 is connected to the external power source Vcc, the other end of the voltage divider 110 is connected to the forward input terminal of the comparator 130, the reference voltage source 120 is connected to the inverting input terminal of the comparator 130, and the timing control module 140
  • the output end of the comparator 130 is connected, and the output end of the timing control module 140 serves as an output end of the power-down detecting circuit.
  • the timing control module 140 controls the output of the brownout detection circuit by The high level flips to a low level.
  • the reference voltage of the reference voltage source 120 is the BGR reference voltage Vth, that is, generated by a BGR circuit (Bandgap reference circuits).
  • the BGR reference voltage Vth does not substantially vary with supply voltage and temperature variations.
  • the preset time is 2 microseconds. It can be understood that in other embodiments, the preset time may also be set according to actual needs, such as 3 microseconds, which is not limited herein.
  • the comparator 130 is a hysteresis comparator.
  • the hysteresis comparator is a comparator with hysteretic loopback transmission characteristics.
  • a positive feedback network is introduced on the basis of the inverting input single threshold voltage comparator, and an inverting input hysteresis comparator having a double threshold value of the upper threshold voltage Vbod+ and the lower threshold voltage Vbod- is formed.
  • the upper threshold voltage Vbod+ and the lower threshold voltage Vbod- are added and then divided by 2 to be equal to the BGR reference voltage Vth.
  • the width of the hysteresis window can be changed by adjusting the ratio of the load current source of the hysteresis comparator (the width of the hysteresis window is the difference between the upper threshold voltage Vbod+ and the lower threshold voltage Vbod-). If the width of the hysteresis window is too small, the ability to suppress noise and interference will be weak. If the width of the hysteresis window is too large, the response to the change in the power supply voltage will be slower. Typically, the value of the hysteresis window is on the order of 50 to 100 mV.
  • timing control module 140 a specific circuit schematic of the timing control module 140 is provided. Specifically, please refer to FIG. 3.
  • the timing control module 140 includes a NOT gate F1, a NAND gate F2, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a Schmitt trigger H1, a first switch transistor Q1, and a second switch. Tube Q2.
  • the output end of the comparator 130 is connected to the input end of the NOT gate F1, the output end of the NOT gate F1 is connected to the first input end of the NAND gate F2, and the first resistor R1 is connected to the output end of the NOT gate F1 and the NAND gate F2.
  • the control end of the first switch tube Q1 is connected to the output end of the comparator 130, and the input end of the first switch tube Q1 is connected to the output end of the NOT gate F1 through the first resistor R1, the first switch The output end of the tube Q1 is grounded, and the first capacitor C1 is connected between the input end and the output end of the first switching tube Q1.
  • the output end of the NAND gate F2 is connected to the control end of the second switch tube Q2, the input end of the second switch tube Q2 is connected to the power source, the output end of the second switch tube Q2 is grounded through the second resistor R2, and the second capacitor C2 is connected in parallel. Both ends of the second resistor R2, the input end of the Schmitt trigger H1 is connected to the output end of the second switch tube Q2.
  • the Schmitt trigger H1 functions as a level inversion unit, and the first resistor R1 and the second resistor R2 function as a first impedance element and a second impedance element, respectively. It can be understood that in other embodiments, when the power supply environment is better, the Schmitt trigger H1 can be replaced by a non-gate. Here, the Schmitt trigger H1 can further improve the anti-noise and interference capability of the circuit.
  • the first resistor R1 and the second resistor R2 may be replaced by two MOS transistors operating in a linear region, and the two types are the same.
  • the first capacitor C1 and the second capacitor C2 may be MIM (Metal-Insulator-Metal), PIP (Polysilicon-Insulator-Polysilicon) capacitors, and MOS. Any of (Metal-Oxide-Semiconductor, metal-oxide-semiconductor) capacitors.
  • the first switch tube Q1 and the second switch tube Q2 are respectively an NMOS tube and a PMOS tube, and the control end, the input end, and the output end of the first switch tube Q1 respectively correspond to the gate of the NMOS tube.
  • the first switch tube Q1 and the second switch tube Q2 can also adopt other functionally similar components.
  • the output of the comparator 130 that is, point A is a low level, and the low level passes through the non-gate F1 and becomes a high level.
  • the high level is used as the input of the first input terminal of the NAND gate F2, and on the other hand, the first capacitor C1 is charged by the first resistor R1, and the voltage of the second input terminal of the NAND gate is gradually increased.
  • the first switching transistor Q1 is turned off, and the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 are respectively R 1 and C 1 , and the charging time constant of the first capacitor C1 is 1/1.
  • R 1 C 1 the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 are respectively R 1 and C 1 , and the charging time constant of the first capacitor C1 is 1/1.
  • R 1 C 1 the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 are respectively R 1 and C 1 , and the charging time constant of the first capacitor C
  • the preset time is determined by the resistance value R 1 , the capacitance value C 1 and the inverted voltage of the NAND gate F2, which is 2 microseconds in this embodiment
  • the voltage of the second input terminal of the NAND gate F2 is reversed, and the output voltage of the NAND gate F2 is turned lower, and the second switching transistor is turned on.
  • the point B becomes a high level, and the high level is triggered by the Schmitt.
  • H1 becomes low, that is, the circuit output Bout is low.
  • the output A of the comparator 130 is at a high level, and the low level passes through the NOT gate F1 and becomes a low level.
  • the low level is used as the input of the first input terminal of the NAND gate F2.
  • the first switching transistor Q1 is turned on, and the second input terminal of the NAND gate F2 is pulled low, so that the output of the NAND gate F2 is made.
  • the second switch Q2 is turned off.
  • the function of the first switching transistor Q1 is to remove the cumulative effect of charging several short-time low pulses on point C to charge C1.
  • the electric charge on the second capacitor C2 is discharged through the second resistor R2, and the resistance value of the second resistor R2 and the capacitance value of the second capacitor C2 are respectively R 2 and C 2 , and the discharge of the second capacitor C2 is The time constant is 1/R 2 C 2 .
  • the voltage at point B will slowly decrease.
  • the voltage at point B is lower than the trigger level of the Schmitt trigger (the voltage at point B changes from high to the trigger level of the Schmitt trigger) by the resistance value R 2
  • the capacitance value C 2 and the trigger level of the Schmitt trigger H1 are determined together, which is set to 2 microseconds in this embodiment, and the Schmitt trigger output is high level, that is, the circuit output Bout is also high. level.
  • the schematic diagram of the specific working principle of the circuit is shown in Figure 4.
  • the above-mentioned power-down detection circuit with timing control function is provided with a timing control module, and when the power supply voltage is lower than the reference voltage only for a preset time due to noise and interference, the timing control module does not react to the power-down behavior.
  • the output of this circuit will not be flipped from high level to low level, that is, the circuit's ability to resist noise and interference is enhanced.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Electronic Switches (AREA)

Abstract

一种具有时序控制功能的掉电检测电路，包括分压器（110）、参考电压源（120）、比较器（130）及时序控制模块（140），分压器（110）的一端与外部电源连接，分压器（110）的另一端与比较器（130）的正向输入端连接，参考电压源（120）与比较器（130）的反向输入端连接，时序控制模块（140）与比较器（130）的输出端连接，时序控制模块（140）的输出端为所述掉电检测电路的输出端，当电源电压低于参考电压的持续时间不短于预设时间时，时序控制模块（140）控制所述掉电检测电路的输出由高电平向低电平翻转。

Description

具有时序控制功能的掉电检测电路 技术领域
本发明涉及电源控制技术领域，特别是涉及一种具有时序控制功能的掉电检测电路。
背景技术
传统的掉电检测电路(BOD，brown out detector)都比较简单，其工作原理如图1所示：当电源电压Vcc正常工作时，BOD的输出Bout为高电平。当电源电压Vcc低于某个阈值Vth时，Bout立即变为低电平。
然而，传统BOD对电源电压的噪声和干扰很敏感，尤其是当阈值Vth跟电源电压Vcc差别比较小且噪声和干扰使得Vcc低于阈值Vth时，即使噪声和干扰的持续时间很短，Bout也会变成低电平，从而使得系统抗噪声和干扰的能力就会很弱。
发明内容
基于此，有必要提供一种抗噪声和干扰的能力强的具有时序控制功能的掉电检测电路。
一种具有时序控制功能的掉电检测电路，包括分压器、参考电压源、比较器及时序控制模块，所述分压器的一端与外部电源连接，所述分压器的另一端与所述比较器的正向输入端连接，所述参考电压源与所述比较器的反向输入端连接，所述时序控制模块与所述比较器的输出端连接，所述时序控制模块的输出端为所述掉电检测电路的输出端，当电源电压低于参考电压的持续时间不短于预设时间，所述时序控制模块控制所述掉电检测电路的输出由高电平向低电平翻转。
上述具有时序控制功能的掉电检测电路设置了时序控制模块，当因噪声和干扰使得电源电压只是在预设时间内低于参考电压时，所述时序控制模块不会对掉电行为产生反应，这样电路的输出不会由高电平向低电平翻转，即电路抗噪声和干扰能力增强了。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为传统掉电检测电路的工作原理示意图；
图2为一实施例的具有时序控制功能的掉电检测电路模块图；
图3为图2中时序控制模块的电路原理图；
图4为图2所示的具有时序控制功能的掉电检测电路的工作原理示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参照图2，为一实施例具有时序控制功能的掉电检测电路模块图。
该具有时序控制功能的掉电检测电路包括分压器110、参考电压源120、比较器130及时序控制模块140。
分压器110的一端与外部电源Vcc连接，分压器110的另一端与比较器130的正向输入端连接，参考电压源120与比较器130的反向输入端连接，时序控制模块140与比较器130的输出端连接，时序控制模块140的输出端作为该掉电检测电路的输出端，当电源Vcc的电压低于参考电压源120的持续时间不短于预设时间时，时序控制模块140控制该掉电检测电路的输出由 高电平向低电平翻转。
在本实施例中，参考电压源120的参考电压为BGR参考电压Vth，即由BGR电路(Bandgap reference circuits，带隙参考电路)产生。BGR参考电压Vth基本不随电源电压和温度变化而变化。所述预设时间为2微秒，可以理解，在其他实施例中，所述预设时间还可以根据实际需要进行设置，如3微秒，这里不作限制。
在本实施例中，比较器130为迟滞比较器。迟滞比较器是一个具有迟滞回环传输特性的比较器。在反相输入单门限电压比较器的基础上引入正反馈网络，就组成了具有上门限电压Vbod+和下门限电压Vbod-的双门限值的反相输入迟滞比较器。上门限电压Vbod+和下门限电压Vbod-相加后再除以2的值等于BGR参考电压Vth。
一般情况下，通过调整迟滞比较器的负载电流源的比例，可以改变迟滞窗口的宽度(迟滞窗口的宽度为上门限电压Vbod+与下门限电压Vbod-的差值)。迟滞窗口的宽度太小的话，对噪声和干扰的抑制能力会比较弱。迟滞窗口的宽度太大的话，对电源电压的变化反应会比较慢。通常，迟滞窗口的值在50～100mV的量级上。
在一个实施例中，提供了时序控制模块140的具体电路原理图，具体请结合图3。
时序控制模块140包括非门F1、与非门F2、第一电阻R1、第二电阻R2、第一电容C1、第二电容C2、施密特触发器H1、第一开关管Q1以及第二开关管Q2。
比较器130的输出端与非门F1的输入端连接，非门F1的输出端与与非门F2的第一输入端连接，第一电阻R1连接在非门F1的输出端与与非门F2的第二输入端之间，第一开关管Q1的控制端与比较器130的输出端连接，第一开关管Q1的输入端通过第一电阻R1与非门F1的输出端连接，第一开关管Q1的输出端接地，第一电容C1连接在第一开关管Q1的输入端与输出端之间。
与非门F2的输出端与第二开关管Q2的控制端连接，第二开关管Q2的输入端接电源，第二开关管Q2的输出端通过第二电阻R2接地，第二电容C2并联在第二电阻R2两端，施密特触发器H1的输入端与第二开关管Q2的输出端连接。
在本实施例中，施密特触发器H1作为电平翻转单元，第一电阻R1和第二电阻R2分别作为第一阻抗元件和第二阻抗元件。可以理解，在其他实施例中，当电源环境比较好的情况下，施密特触发器H1可以用一个非门来代替。这里采用施密特触发器H1可以进一步提高电路的抗噪声和干扰能力。
在其他实施例中，第一电阻R1和第二电阻R2可以用两个工作在线性区的MOS管来代替，且两者类型相同。在本实施例中，第一电容C1和第二电容C2可以为MIM(Metal-Insulator-Metal，金属-绝缘体-金属)电容、PIP(Polysilicon-Insulator-Polysilicon，多晶硅-绝缘体-多晶硅)电容和MOS(Metal-Oxide-Semiconductor，金属-氧化物-半导体)电容中的任一种。
另外，在本实施例中，第一开关管Q1和第二开关管Q2分别为NMOS管和PMOS管，第一开关管Q1的控制端、输入端、输出端分别对应所述NMOS管的栅极、漏极、源极；第二开关管Q2的控制端、输入端、输出端分别对应所述PMOS管的栅极、源极、漏极。可以理解，在其他实施例中，第一开关管Q1和第二开关管Q2还可以采用其他功能相似的元器件。
以下结合图2和图3说明上述电路的工作原理。
当电源电压Vcc低于下门限电压Vbod-时，比较器130的输出即A点为低电平，该低电平通过非门F1后变为高电平。该高电平一方面作为与非门F2第一输入端的输入，另一方面还会通过第一电阻R1对第一电容C1进行充电，这时与非门第二输入端的电压会慢慢升高，此时第一开关管Q1是关断的，设第一电阻R1的电阻值和第一电容C1的电容值分别为R1、C1，则第一电容C1的充电的时间常数为1/R1C1。当A点低电平的持续时间达到预设时间(预设时间由电阻值R1、电容值C1以及与非门F2的反转电压共同决定，本实施例中为2微秒)时，与非门F2第二输入端的电压反转，与非门F2的输 出电压会变低，将第二开关管导通，此时B点变成高电平，该高电平经施密特触发器H1变成低电平，即电路输出Bout为低电平。
当电源电压Vcc高于上门限电压Vbod+时，比较器130的输出A点为高电平，该低电平通过非门F1后变为低电平。该低电平一方面作为与非门F2第一输入端的输入，此时第一开关管Q1导通，与非门F2第二输入端被拉成低电平，从而使得与非门F2的输出为高电平，将第二开关管Q2关断。这里第一开关管Q1的作用是清除由A点连续几个短时低脉冲对C1充电的累积效应。此时，第二电容C2上的电荷会通过第二电阻R2放电，设第二电阻R2的电阻值和第二电容C2的电容值分别为R2、C2，则第二电容C2的放电的时间常数为1/R2C2。B点的电压会慢慢降低，当B点的电压低于施密特触发器的触发电平时(B点的电压由高变为施密特触发器的触发电平的时间由电阻值R2、电容值C2以及施密特触发器H1的触发电平共同决定，在本实施例中设为2微秒)，施密特触发器输出为高电平，即电路输出Bout也为高电平。该电路的具体工作原理示意图如图4所示。
上述具有时序控制功能的掉电检测电路设置了时序控制模块，当因噪声和干扰使得电源电压只是在预设时间内低于参考电压时，所述时序控制模块不会对掉电行为产生反应，这样电路的输出不会由高电平向低电平翻转，即电路抗噪声和干扰能力增强了。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种具有时序控制功能的掉电检测电路，其特征在于，包括分压器、参考电压源、比较器及时序控制模块，所述分压器的一端与外部电源连接，所述分压器的另一端与所述比较器的正向输入端连接，所述参考电压源与所述比较器的反向输入端连接，所述时序控制模块与所述比较器的输出端连接，所述时序控制模块的输出端为所述掉电检测电路的输出端，当电源电压低于参考电压的持续时间不短于预设时间时，所述时序控制模块控制所述掉电检测电路的输出由高电平向低电平翻转。
  2. 根据权利要求1所述的掉电检测电路，其特征在于，所述时序控制模块包括非门、与非门、第一阻抗元件、第二阻抗元件、第一电容、第二电容、电平翻转单元、第一开关管以及第二开关管；
    所述比较器的输出端与所述非门的输入端连接，所述非门的输出端与所述与非门的第一输入端连接，所述第一阻抗元件连接在所述非门的输出端与所述与非门的第二输入端之间，所述第一开关管的控制端与所述比较器的输出端连接，所述第一开关管的输入端通过所述第一阻抗元件与所述非门的输出端连接，所述第一开关管的输出端接地，所述第一电容连接在所述第一开关管的输入端与输出端之间；
    所述与非门的输出端与所述第二开关管的控制端连接，所述第二开关管的输入端接电源，所述第二开关管的输出端通过所述第二阻抗元件接地，所述第二电容并联在所述第二阻抗元件两端，所述电平翻转单元的输入端与所述第二开关管的输出端连接。
  3. 根据权利要求2所述的掉电检测电路，其特征在于，所述电平翻转单元包括非门。
  4. 根据权利要求2所述的掉电检测电路，其特征在于，所述电平翻转单元包括施密特触发器。
  5. 根据权利要求2所述的掉电检测电路，其特征在于，所述第一阻抗元 件包括电阻，所述第二阻抗元件包括电阻。
  6. 根据权利要求2所述的掉电检测电路，其特征在于，所述第一阻抗元件包括工作在线性区的MOS管，所述第二阻抗元件包括工作在线性区的MOS管。
  7. 根据权利要求2所述的掉电检测电路，其特征在于，所述第一开关管和所述第二开关管分别为NMOS管和PMOS管，所述第一开关管的控制端、输入端、输出端分别对应所述NMOS管的栅极、漏极、源极；所述第二开关管的控制端、输入端、输出端分别对应所述PMOS管的栅极、源极、漏极。
  8. 根据权利要求2所述的掉电检测电路，其特征在于，所述第一电容包括MIM电容、PIP电容和MOS电容中的一种。
  9. 根据权利要求2所述的掉电检测电路，其特征在于，所述第二电容包括MIM电容、PIP电容和MOS电容中的一种。
  10. 根据权利要求1所述的掉电检测电路，其特征在于，所述预设时间为2微秒。
  11. 根据权利要求1所述的掉电检测电路，其特征在于，所述参考电压源的参考电压由BGR电路产生。
  12. 根据权利要求1所述的掉电检测电路，其特征在于，所述比较器为迟滞比较器。
PCT/CN2015/082965 2014-07-28 2015-06-30 具有时序控制功能的掉电检测电路 WO2016015538A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/327,956 US10254353B2 (en) 2014-07-28 2015-06-30 Brown out detector having sequential control function

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410364548.4A CN105445529B (zh) 2014-07-28 2014-07-28 具有时序控制功能的掉电检测电路
CN201410364548.4 2014-07-28

Publications (1)

Publication Number Publication Date
WO2016015538A1 true WO2016015538A1 (zh) 2016-02-04

Family

ID=55216746

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/082965 WO2016015538A1 (zh) 2014-07-28 2015-06-30 具有时序控制功能的掉电检测电路

Country Status (3)

Country Link
US (1) US10254353B2 (zh)
CN (1) CN105445529B (zh)
WO (1) WO2016015538A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114839425A (zh) * 2022-06-29 2022-08-02 圣邦微电子（北京）股份有限公司 欠压检测器及包含该欠压检测器的电源系统

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106483758B (zh) 2015-09-02 2019-08-20 无锡华润上华科技有限公司 光学邻近效应修正方法和系统
CN106653842B (zh) 2015-10-28 2019-05-17 无锡华润上华科技有限公司 一种具有静电释放保护结构的半导体器件
CN106816468B (zh) 2015-11-30 2020-07-10 无锡华润上华科技有限公司 具有resurf结构的横向扩散金属氧化物半导体场效应管
CN107465983B (zh) 2016-06-03 2021-06-04 无锡华润上华科技有限公司 Mems麦克风及其制备方法
CN107515328A (zh) * 2016-06-15 2017-12-26 中芯国际集成电路制造(上海)有限公司 电压发生单元的检测电路及检测方法
CN107390063B (zh) * 2017-08-03 2020-11-06 恒宝股份有限公司 一种掉电测试方法及装置
KR102419173B1 (ko) * 2018-03-08 2022-07-11 에스케이하이닉스 주식회사 저전압 감지 회로 및 이를 포함하는 메모리 장치
CN108471228A (zh) * 2018-04-23 2018-08-31 四川协诚智达科技有限公司 一种dc/dc变换模块输出电压快速泄放电路及其实现方法
CN110308891B (zh) * 2019-08-21 2023-05-09 上海南芯半导体科技股份有限公司 一种除法器电路及其实现方法
CN111865273A (zh) * 2020-07-29 2020-10-30 Oppo广东移动通信有限公司 掉电提醒电路及cpe设备
CN113484589A (zh) * 2021-06-30 2021-10-08 杭州加速科技有限公司 一种带有磁滞功能的掉电检测电路及控制系统
CN113839656B (zh) * 2021-08-13 2023-08-11 苏州浪潮智能科技有限公司 一种服务器电源时序放电电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999030173A1 (en) * 1997-12-12 1999-06-17 Scenix Semiconductor, Inc. System and method for programmable brown-out detection and differentiation
CN200962514Y (zh) * 2006-10-25 2007-10-17 深圳桑达国际电子器件有限公司 一种掉电检测装置
CN201222222Y (zh) * 2008-07-18 2009-04-15 珠海中慧微电子有限公司 电源监控芯片
CN102116822A (zh) * 2010-12-30 2011-07-06 易事特电力系统技术有限公司 三相不间断电源的电网掉电检测方法
CN103138716A (zh) * 2013-01-31 2013-06-05 深圳威迈斯电源有限公司 一种掉电触发的单稳态保护电路
CN103529281A (zh) * 2013-10-24 2014-01-22 郑鲲鲲 一种全覆盖实时自我诊断的电压检测电路、电子设备及汽车

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5564010A (en) * 1993-05-24 1996-10-08 Thomson Consumer Electronics, Inc. Reset signal generator, for generating resets of multiple duration
CN1282050C (zh) * 2000-06-19 2006-10-25 国际整流器有限公司 用于镇流控制集成电路中的电路
US6894544B2 (en) * 2003-06-02 2005-05-17 Analog Devices, Inc. Brown-out detector
US7589568B2 (en) * 2007-05-04 2009-09-15 Microchip Technology Incorporated Variable power and response time brown-out-reset circuit
CN101470501B (zh) * 2007-12-26 2010-12-15 珠海中慧微电子有限公司 一种延时复位控制电路及方法
CN101216788B (zh) * 2008-01-21 2010-06-09 珠海中慧微电子有限公司 复位监控芯片及方法
JP5343393B2 (ja) * 2008-04-28 2013-11-13 富士電機株式会社 スイッチング電源制御用半導体装置
CN101819261B (zh) * 2009-08-28 2013-02-20 深圳威迈斯电源有限公司 一种三相电源缺相掉电检测电路
US8253453B2 (en) * 2010-10-28 2012-08-28 Freescale Semiconductor, Inc. Brown-out detection circuit
CN102759655B (zh) * 2011-04-29 2016-03-16 飞兆半导体公司 多电源电压的检测电路及检测方法
US8692593B1 (en) * 2012-09-14 2014-04-08 Nxp B.V. Zero or ultra-low DC current consumption power-on and brown-out detector
KR20140079008A (ko) * 2012-12-18 2014-06-26 삼성전기주식회사 파워 온 리셋 회로

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999030173A1 (en) * 1997-12-12 1999-06-17 Scenix Semiconductor, Inc. System and method for programmable brown-out detection and differentiation
CN200962514Y (zh) * 2006-10-25 2007-10-17 深圳桑达国际电子器件有限公司 一种掉电检测装置
CN201222222Y (zh) * 2008-07-18 2009-04-15 珠海中慧微电子有限公司 电源监控芯片
CN102116822A (zh) * 2010-12-30 2011-07-06 易事特电力系统技术有限公司 三相不间断电源的电网掉电检测方法
CN103138716A (zh) * 2013-01-31 2013-06-05 深圳威迈斯电源有限公司 一种掉电触发的单稳态保护电路
CN103529281A (zh) * 2013-10-24 2014-01-22 郑鲲鲲 一种全覆盖实时自我诊断的电压检测电路、电子设备及汽车

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114839425A (zh) * 2022-06-29 2022-08-02 圣邦微电子（北京）股份有限公司 欠压检测器及包含该欠压检测器的电源系统
CN114839425B (zh) * 2022-06-29 2022-10-14 圣邦微电子（北京）股份有限公司 欠压检测器及包含该欠压检测器的电源系统

Also Published As

Publication number Publication date
US10254353B2 (en) 2019-04-09
US20170205470A1 (en) 2017-07-20
CN105445529A (zh) 2016-03-30
CN105445529B (zh) 2018-06-15

Similar Documents

Publication Publication Date Title
WO2016015538A1 (zh) 具有时序控制功能的掉电检测电路
KR101926000B1 (ko) 파워 온 리셋 회로 및 리셋 방법
JP5225876B2 (ja) パワーオンリセット回路
KR101646910B1 (ko) 파워 온 리셋 회로를 포함하는 반도체 소자
JPS62217714A (ja) 高電圧検出回路
JPH04139914A (ja) パワーオンリセット回路
US20080084232A1 (en) Negative voltage detector
TWI808173B (zh) 電壓偵測器
US20110317319A1 (en) Electrostatic discharge protection circuit
US9660651B2 (en) Level shift circuit
US4071784A (en) MOS input buffer with hysteresis
JP3732841B2 (ja) 遅延回路
US5252909A (en) Constant-voltage generating circuit
KR102572587B1 (ko) 콤퍼레이터 및 발진 회로
TWI641219B (zh) 電源啟動控制電路以及輸入／出控制電路
US11249118B2 (en) Current sensing circuit
JP2002016484A (ja) 半導体回路
JP2848235B2 (ja) 半導体記憶装置用電源回路
JPH02143608A (ja) 半導体集積回路
US5926009A (en) Voltage monitoring circuit in an integrated circuit
JPH0697796A (ja) パワーオンリセット回路
KR101859118B1 (ko) 마이크로 컨트롤러의 파워 온 리셋 회로
JPH03210815A (ja) Ｃｍｏｓ型出力回路
WO2013128802A1 (ja) 電圧検出回路
CN113783557A (zh) 芯片上电复位电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15828141

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 15327956

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15828141

Country of ref document: EP

Kind code of ref document: A1