WO2015182678A1 - 配線基板 - Google Patents

配線基板 Download PDF

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Publication number
WO2015182678A1
WO2015182678A1 PCT/JP2015/065316 JP2015065316W WO2015182678A1 WO 2015182678 A1 WO2015182678 A1 WO 2015182678A1 JP 2015065316 W JP2015065316 W JP 2015065316W WO 2015182678 A1 WO2015182678 A1 WO 2015182678A1
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WIPO (PCT)
Prior art keywords
substrate body
conductor
wiring board
conductor layer
layer
Prior art date
Application number
PCT/JP2015/065316
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English (en)
French (fr)
Inventor
貞浩 西村
Original Assignee
日本特殊陶業株式会社
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Publication date
Application filed by 日本特殊陶業株式会社 filed Critical 日本特殊陶業株式会社
Priority to CN201580028142.1A priority Critical patent/CN106463465B/zh
Priority to JP2015551890A priority patent/JP5957151B2/ja
Priority to US15/312,709 priority patent/US9881861B2/en
Publication of WO2015182678A1 publication Critical patent/WO2015182678A1/ja

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Definitions

  • the present invention relates to a wiring board that is securely coated with a plating film.
  • At least one of a plurality of pads and a single long pad in which all of them are short-circuited is formed on the side surface of the insulating base, and a plurality of external lead terminals erected from the same frame are brought into contact with these pads.
  • a metal plating film is coated by electrolytic plating on each surface of the plurality of metallization layers for wiring that are electrically connected to the pads individually and provided on the bottom surface side of the cavity that opens on the surface of the insulating base.
  • Ni is in a state in which a pointed electrode pin is in point contact with the surface of the metallized layer or the surface of the non-conductive pad.
  • a plating film and an Au plating film are also sequentially coated by electrolytic plating.
  • the contact portion is inadvertently displaced and the metallized layer or the surface of the pad is scratched.
  • the electrode pins may come off and electrolytic plating may not be performed.
  • a separate electrode conductor for contacting the electrode pins is provided on the surface of the substrate body outside the metallized layer, the size of the substrate body is increased.
  • the present invention solves the problems described in the background art, and opens on the surface of the substrate body, which is not electrically connected to the external connection conductor on the surface of the substrate body made of ceramic. Even if there are surface conductors that are not electrically connected to the external connection conductor on the bottom side of the cavity, these surfaces are securely covered with a metal plating film by electrolytic plating, and contact with the electrode pins It is an object of the present invention to provide a wiring board in which scratches are not noticeable and the board body can be reduced in size.
  • the present invention provides an electroplating conductor in which an opening into which an electrode pin can be inserted is formed on at least one of the front and back surfaces of a ceramic substrate body, and a part of the opening is exposed on the bottom surface. It is conceived that the layer and the surface conductor portion that needs to be coated with the metal plating film can be electrically connected.
  • a first wiring board according to the present invention is made of ceramic, and has a substrate body having a front surface and a back surface, and a side surface positioned between the front surface and the back surface, a surface of the substrate body, and A surface conductor portion formed on at least one of the back surfaces and coated with a metal plating film on the surface, formed inside the substrate body, one end electrically connected to the surface conductor portion, and the other end of the substrate body
  • An electroplating conductor layer which is formed on the front surface or the back surface of the substrate and is electrically independent of a conductor portion different from the surface conductor portion and spaced from the side surface of the substrate body.
  • An opening for exposing at least a part of the electroplating conductor layer is formed on at least one of the front surface and the back surface of the substrate body.
  • one end is electrically connected to the surface conductor portion
  • the other end is formed on the front or back surface of the substrate body, and is different from the surface conductor portion.
  • the electroplating conductor layer that is electrically independent of the conductor portion and spaced from the side surface of the substrate body is “formed inside the substrate body, and one end is electrically connected to the surface conductor portion.
  • a conductive layer for electroplating the other end of which is formed on the front or back surface of the substrate body and is not electrically connected to a conductor portion different from the surface conductor portion and is not exposed to the side surface of the substrate body ” It can also be expressed.
  • the surface conductor portion is electrically connected to one end portion of the electroplating conductor layer that is partially exposed to an opening formed on at least one of the front surface or the back surface of the substrate body. . Therefore, for example, even if the surface of the substrate body is widely occupied by another conductor portion, the surface conductor portion can be conducted through the electroplating conductor layer and the via conductor, etc.
  • the tip of the electrode pin for electrolytic plating from the part and contacting with the part of the conductive layer for electrolytic plating exposed at the opening, Ni, Au, etc.
  • the metal plating film is coated. Therefore, the wiring board is obtained by reliably coating the surface of the surface conductor portion that is electrically independent from another conductor layer such as an external connection conductor during use.
  • the tip of the electrode pin for electroplating inserted into the opening is not easily displaced or removed from the opening. Even if scratches such as indentations due to the pins occur, the scratches can be made inconspicuous because they are located on the bottom surface side of the opening. Furthermore, the electroplating conductor layer is formed inside the substrate body and part of the opening is exposed to the opening, thereby preventing a conventional inadvertent short circuit and facilitating the downsizing of the substrate body. Become.
  • the ceramic is a high-temperature fired ceramic such as alumina, mullite, or aluminum nitride, or a low-temperature fired ceramic such as glass-ceramic.
  • the substrate main body may have a cavity opened to the surface on the center side of the surface, as will be described later.
  • the surface conductor portion is a non-conductive conductor portion that is electrically independent from another conductor layer such as an external connection terminal that is electrically connected to a terminal formed on the motherboard in use, for example, Metal frame for sealing the cavity and frame metallization layer for mounting the metal lid (metallization layer for cavity sealing) and non-conductive external connection terminals that are electrically independent from other conductor layers Etc. are exemplified.
  • the another conductor portion is a conductor portion that is electrically connected to a terminal of the motherboard when in use.
  • the ceramic of the substrate body is a high-temperature fired ceramic
  • the ceramic of the substrate body is a low-temperature fired ceramic, Ag or Cu is applied.
  • a portion (exposed surface) of the electroplating conductor layer exposed on the bottom surface of the opening is a power supply pin for supplying an electroplating current to the surface of the surface conductor portion.
  • the pointed tip is abutted in the form of a dot. Further, the opening is formed through the outermost ceramic layer forming the front surface or the back surface of the substrate body, or the ceramic layer and a ceramic adjacent thereto in the thickness direction.
  • the metal plating film include Ni and Au plating films.
  • the surface conductor portion may be a frame-shaped metallization layer for sealing the cavity formed along the opening of the cavity opened on the surface of the substrate body, or the surface of the substrate body or A wiring board (Claim 2) which is a part of the external connection conductor formed on the back surface is also included.
  • the surface of the electrolytic layer is not electrolyzed. It is possible to provide a wiring board that reliably coats a required metal plating film through the plating conductor layer and the conductor portion that is conductive to the plating conductor layer.
  • the external connection conductor does not flow current when in use, for example, a dummy pad that forms part of a pattern used for image processing, and a dummy element for stabilizing the posture of an element to be mounted It is used as a mounting pad or an alignment mark for positioning a wiring board.
  • the substrate body has a cavity opened on the surface thereof, and a non-conductive pad as the surface conductor portion is formed on the bottom surface side of the cavity (Claim 3). Is also included. According to this, even when the area of the non-conductive (dummy) pad is relatively small, for example, when the area is relatively smaller than an element mounting pad such as an electronic component to be mounted, In addition, a wiring board that reliably covers a required metal plating film can be obtained through the electrolytic plating conductor and a conductor that is conductive to the conductor.
  • the bottom surface side of the cavity includes a horizontal surface of a step portion relatively close to the periphery of the bottom surface in addition to the bottom surface of the cavity.
  • a single element mounting pad such as an electronic component to be mounted in the cavity is formed at the center of the bottom surface of the cavity, and the mounting pad has a relatively large surface area. In the case, it is not included in the surface conductor portion in the present invention. However, when the non-conductive (dummy) element mounting pad is included in a part of the plurality of element mounting pads, the non-conductive element mounting pad is included in the surface conductor portion.
  • the present invention also provides a wiring board (Claim 4), wherein the surface conductor portion and the electroplating conductor layer can be electrically connected via at least one of a via conductor and a connection wiring. included.
  • a wiring board (Claim 4)
  • the surface conductor portion and the electroplating conductor layer can be electrically connected via at least one of a via conductor and a connection wiring. included.
  • connection wirings (wiring layers) formed on the inside, the front surface, or the back surface of the substrate body. It may be possible to conduct through.
  • the present invention includes a wiring board (Claim 5) in which the opening is a bottomed hole, and a part of the conductive layer for electrolytic plating is exposed on the bottom surface of the bottomed hole. .
  • the tip of the electrode pin for electrolytic plating is inserted through the opening and is easily brought into contact with a part of the electroplating conductor layer (plating surface electrode) exposed at the bottom of the bottomed hole. be able to.
  • the electrode pin is displaced in the radial direction of the bottomed hole, the contact state between the tip portion and the exposed surface of the electroplating conductor layer can be easily maintained.
  • the bottomed hole to be the opening has a circular shape in plan view and a cylindrical shape as a whole, an elliptical shape in plan view and an elliptical column shape as a whole, an oval shape in plan view and a long cylindrical shape as a whole.
  • the bottom side of the bottomed hole has a narrow inverted cone shape, an inverted elliptical cone shape, an inverted long cone shape, or a shape in which the plan view has a polygonal shape that is a triangle or more and the whole is a triangular prism shape or more, etc. A flat part of the electroplating conductor is exposed on these bottom surfaces.
  • the present invention also includes a wiring board (invention 6) in which a wall surface conductor layer electrically connected to the electroplating conductor layer is formed on the inner wall surface of the bottomed hole. According to this, for example, even when the electrode pin is displaced in the radial direction of the bottomed hole due to an inadvertent external force, the tip end portion reliably contacts the wall surface conductor layer. It can be set as the wiring board which covered the metal plating film reliably.
  • the surface conductor portion and the electroplating conductor layer are electrically connected via connection wiring formed on the front surface or the back surface of the substrate body and the wall surface conductor layer.
  • a wiring board (claim 7) is also included. According to this, for example, on the front surface or the back surface of the substrate body, the surface conductor portion and the electrolysis are connected via the relatively narrow connection wiring and the wall surface conductor layer formed on the inner wall surface of the bottomed hole. Conductivity can be established between the conductor layer for plating. Therefore, by forming the connection wiring between the other conductors on the front surface or the back surface of the substrate body or at an arbitrary position on the back surface, the occupied volume (region) inside the substrate body is minimized, and the surface conductor is formed. It is possible to provide a wiring board in which a required metal plating film is reliably coated on the surface of the portion.
  • FIG. 2 is a partial vertical sectional view taken along the line XX in FIG.
  • FIG. 2 is a partial vertical sectional view taken along line YY in FIG. 1.
  • A) is a partial top view which shows the vicinity of the bottomed hole of a different form in the said wiring board
  • (B) is a partial top view which shows the vicinity of the bottomed hole of a further different form.
  • the partial vertical sectional view which shows the vicinity of the bottomed hole of another form.
  • the partial vertical sectional view which shows the vicinity of the bottomed hole of an application form.
  • FIG. 9 is a partial vertical sectional view visually in the direction of arrow Z in FIG. 8. The same partial vertical sectional view as FIG. 9 which shows the different form of the said wiring board.
  • FIG. 10 is a partial vertical cross-sectional view similar to FIG. 9 showing a further different form of the wiring board.
  • FIG. 1 is a plan view showing a wiring board 1 according to an embodiment of the present invention
  • FIG. 2 is a partial cross-sectional view taken along the line XX in FIG. 1, and FIG. It is a fragmentary sectional view in alignment with the arrow of Y line.
  • the wiring board 1 includes a board body 2 having a plate shape as a whole, a frame-shaped metallized layer (surface conductor portion) 15 formed on the surface 3 of the board body 2, a board, An electroplating conductor layer 16 formed inside the main body 2 and a bottomed hole (opening) 19 formed near the upper right corner of the surface 3 of the substrate main body 2 are provided.
  • the substrate body 2 has a front surface 3 and a rear surface 4 that are square (rectangular) in a plan view, and four side surfaces 5 positioned between the periphery of the front surface 3 and the rear surface 4, and the ceramic layers C1 to C4 are provided. They are laminated together.
  • the ceramic constituting the ceramic layers C1 to C4 is a high-temperature fired ceramic such as alumina, or a low-temperature fired ceramic such as glass-ceramic.
  • a cavity 6 having a square shape in plan view is opened on the center side of the surface of the substrate body 2.
  • the cavity 6 has a bottom surface 7 having a square shape in plan view, a side surface 9 which is erected from the periphery thereof and has a quadrangular prism shape as a whole, and is close to the bottom surface 7 side of the side surface 9 and has a rectangular frame shape in plan view.
  • the step part 8 is provided on the bottom surface 7, a single element mounting pad 10 having a rectangular shape in plan view is formed on almost the entire surface excluding its peripheral portion.
  • the semiconductor element 20 and the like are mounted on the upper surface of the element mounting pad 10 by adhesion.
  • a plurality of element connection terminals (another conductor portion) 11 are formed on the surface (horizontal plane) of the step portion 8.
  • the element connection terminal 11 and the semiconductor element 20 can be made conductive via a plurality of bonding wires wi later.
  • the frame-shaped metallization layer 15 is formed along the vicinity of the opening of the cavity 6.
  • a plurality of external connection conductors (another conductor portions) 14 having a rectangular shape in plan view with one side exposed to each side surface 5 are formed on the peripheral side of the surface 3 of the substrate body 2. As shown in FIG. 1, the tips of the plurality of leads Li are joined individually by brazing or the like on each of the external connection conductors 14.
  • a part of the element connection terminal 11 and the wiring layer 12 are formed between the ceramic layers C2 to C4, and between these and the external connection conductor 14 are ceramic layers. They are electrically connected to each other via via conductors 13 that individually penetrate C3 and C4. The remaining part of the element connection terminal 11 and a part of the external connection conductor 14 may be electrically independent.
  • the bottomed hole 19 having a circular shape in plan view is opened in the vicinity of the upper right corner of the surface 3 of the substrate body 2.
  • a part (plating electrode surface) 18 on the other end side of the electroplating conductor layer 16 formed between the ceramic layers C3 and C4 is exposed.
  • One end side of the electroplating conductor layer 16 is connected to a via conductor 17 connected to the lower surface of the frame-shaped metallized layer 15 near the upper right corner. Moreover, as shown in FIGS. 1 and 3, the electroplating conductor layer 16 is separated from the side surface 5 so as not to be exposed on all the side surfaces 5 including the upper side and the right side of the substrate body 2. Further, the electroplating conductor layer 16 is electrically independent of the element connection terminal (another conductor portion) 11 and the external connection conductor (another conductor portion) 14.
  • the element mounting pad 10, the element connection terminal 11, the wiring layer 12, the via conductors 13 and 17, the external connection terminal 14, the frame-shaped metallized layer 15, and the electroplating conductor layer 16 are made of the ceramic layers C1 to C4.
  • the ceramic constituting the ceramic is made of a high-temperature fired ceramic such as alumina, it is mainly made of W or Mo or an alloy based on one of them, and is made of a low-temperature fired ceramic such as glass-ceramic. Is mainly made of Cu, Ag, or an alloy based on any one of these.
  • the element mounting pad 10, the tip end side of the element connection terminal 11 (the element mounting pad 10 side), the external connection conductor 14, the frame-shaped metallized layer 15, and the part 18 of the electrolytic plating conductor layer 16 are provided outside.
  • the exposed surface is successively covered with two layers of a Ni plating film and an Au plating film (metal plating film: not shown) having a required thickness.
  • the wiring board 1 as described above is generally produced as follows. For example, four green sheets containing alumina powder, etc. are prepared in advance. For each required position of the green sheet, punching processing, pattern printing of conductive paste containing W powder, etc. and filling in through holes are performed. After these, the four green sheets are laminated and pressure-bonded, and then fired at a predetermined temperature range to obtain a fired wiring board 1 that is substantially the same as shown in FIGS. It was. Next, as shown by a two-dot chain line in FIG. 3, the tip of the tip of the electrode pin Pi that is L-shaped as a whole when viewed from the side is connected to the inside of the bottomed hole 19 from the surface 3 side of the substrate body 2.
  • the surface of the portion 18 of the electroplating conductor layer 16 exposed on the bottom surface of the bottomed hole 19 was brought into point contact with a slight pressure. At this time, a part 18 of the conductor layer 16 becomes a plating electrode surface.
  • the wiring board 1 was immersed in an electrolytic Ni plating bath and an electrolytic Au plating bath (not shown) together with the electrode pins Pi, and electrolytic Ni plating and electrolytic Au plating were sequentially applied.
  • the Ni plating film and the Au plating film could be sequentially coated on the surface of the frame-shaped metallized layer 15 which is a surface conductor portion that is not electrically connected to the other conductor layers 11 and 14.
  • another electrode pin Pi is brought into contact with the surface of the element mounting pad 10 having a relatively large area, and further on the front end side of the element connection terminal 11 which is another conductor portion and on the surface of the external connection conductor 14.
  • the same electrolytic metal plating as described above was performed simultaneously with the above by bringing another electrode pin Pi into contact with any of these.
  • the wiring board 1 as described above was obtained.
  • the frame-shaped metallized layer 15 which is a surface conductor portion, is partly exposed in the bottomed hole (opening) 19 formed in the surface 3 of the substrate body 2.
  • the conductor layer 16 is electrically connected to one end of the conductor layer 16 via the via conductor 17. Therefore, the peripheral side of the surface 3 of the substrate body 2 is widely occupied by the external connection terminal (another conductor portion) 14, and the frame-shaped metallized layer 15 has a narrow width and a small area. Even when it is difficult to make direct contact, the surface of the frame-shaped metallized layer 15 can be conducted through the electroplating conductor layer 16 and the via conductor 17.
  • the tip of the electrode pin Pi for electroplating is inserted from the opening of the bottomed hole 19 and is in contact with a part (plating electrode surface) 18 of the electroplating conductor layer 16 exposed in the bottomed hole 19.
  • the surface of the frame-shaped metallized layer 15 is surely covered with a metal plating film of Ni and Au. Therefore, the wiring board 1 is such that the metal plating film is reliably coated on the surface of the frame-shaped metallized layer 15 that is not electrically connected to the other conductors 11 and 14 in use.
  • the tip of the electrode pin Pi inserted into the bottomed hole 19 is misaligned, or the bottomed hole 19
  • the scratch is less noticeable because it is located at the bottom of the bottomed hole 19.
  • the electroplating conductor layer 16 is formed inside the substrate body 2 and a part 18 is exposed on the bottom surface of the bottomed hole 19, so that an inadvertent short circuit can be prevented and the substrate body 2 can be prevented. It is easy to downsize the entire wiring board 1 including the above.
  • FIG. 4A is a partial plan view showing the vicinity of a bottomed hole 19r of a different form in the wiring board 1.
  • the bottomed hole 19r has an elliptical shape having a major axis along a diagonal line passing through the center of the surface 3 in the vicinity of one corner of the surface 3 of the substrate body 2 in plan view. Further, a plating electrode surface (part) 18 of the electroplating conductor layer 16 is exposed in an elliptical shape.
  • the bottomed hole 19r may have an oval shape in plan view.
  • the major axis of the bottomed hole 19r on the surface 3 may be along an arbitrary direction.
  • the bottomed hole 19s has a rectangular shape having a pair of long sides along a diagonal line passing through the center of the surface 3 in the vicinity of one corner of the surface 3 of the substrate body 2 in plan view.
  • a plating electrode surface (part) 18 of the electroplating conductor layer 16 is exposed in a rectangular shape on the bottom surface.
  • the bottomed hole 19s may have a square shape in plan view.
  • each long side and each side of the bottomed hole 19s on the surface 3 may be along an arbitrary direction.
  • FIG. 5 is a partial vertical sectional view showing the vicinity of a differently-shaped bottomed hole 19 t in the wiring board 1.
  • the bottomed hole 19t is directed from the surface 3 side of the substrate body 2 toward the plating electrode surface (part) 18 of the electroplating conductor layer 16 located between the ceramic layers C3 and C4. It has an inclined inner wall surface (tapered surface) that gradually narrows. Therefore, the bottomed hole 19t has a conical shape when the plan view is circular, an elliptical cone shape or a long cone shape when the plan view is elliptical or oval, and a rectangular or square shape when viewed from the top. In this case, a quadrangular pyramid shape is exhibited.
  • the bottomed holes 19r to 19t as described above can achieve the same effect as the bottomed hole 19, and particularly in the case of the bottomed hole 19t having an inclined inner wall surface, as shown in FIG. In addition, it is easy to insert the tip of the electrode pin Pi.
  • FIG. 6 is a partial vertical sectional view showing the vicinity of the bottomed hole 19 of the applied form in the wiring board 1.
  • a cylindrical wall conductor layer 21 having a bottom surface connected to the plating electrode surface 18 of the electrolytic plating conductor layer 16 is further formed.
  • the bottomed hole 19 having the wall surface conductor layer 21 even if the tip end of the electrode pin Pi is inadvertently detached from the plating electrode surface 18, it contacts the inner peripheral surface of the wall surface conductor layer 21 by point contact. Therefore, the electrical connection between the electrode pin Pi and the electroplating conductor layer 16 can be ensured.
  • the wall surface conductor layer 21 may be formed by further adding to the inner wall surfaces of the bottomed holes 19r to 19t. Further, the bottomed holes 19r to 19t in the wiring board 1 may be formed at an arbitrary position on the surface 3 of the substrate body 2. For example, between the external connection terminals 14 and 14 on the peripheral side of the surface 3 It is good also as the arrangement
  • FIG. 7 is a partial vertical sectional view showing the vicinity of the bottomed hole 19 in the wiring board 1a of a different form.
  • the wiring board 1 a includes the same substrate body 2, cavity 6, frame-shaped metallized layer 15, and a plurality of external connection terminals 14 (not shown).
  • a bottomed hole 19 similar to the above is formed in the vicinity of one corner of the surface 3 of the substrate body 2 or an arbitrary peripheral side, and the same wall surface as described above is formed on the inner wall surface of the bottomed hole 19.
  • the conductor layer 21 is formed, and the plating electrode surface 18 of the electroplating conductor layer 16 is exposed on the bottom surfaces of the wall surface conductor layer 21 and the bottomed hole 19.
  • connection wiring 22 formed along the surface 3 of the substrate body 2 is electrically connected between the frame-shaped metallized layer 15 formed along the opening of the cavity 6 and the upper surface of the wall surface conductor layer 21. It is connected.
  • the connection wiring 22 is disposed with a relatively narrow width so as to pass between the external connection terminals 14 and 14.
  • connection wiring 22 can be placed at an arbitrary position such as between the external connection conductors 14, 14 which are other conductor portions on the surface 3 of the board body 2.
  • the volume (area) occupied inside the substrate body 2 is minimized, and the surface of the frame-shaped metallized layer 15 that is the surface conductor portion is reliably coated with the required metal plating film. It has become.
  • the bottomed holes 19r to 19s in which the wall surface conductor layer 21 is formed on the inner wall surface may be applied.
  • FIG. 8 is a partial plan view showing the vicinity of the bottomed hole 19 in the wiring board 1b of still another form
  • FIG. 9 is a partial vertical sectional view visually in the direction of arrow Z in FIG.
  • the wiring board 1 b includes the same substrate body 2, cavity 6, frame-shaped metallized layer 15, a plurality of external connection conductors 14, and the like.
  • at least one of the plurality of element connection terminals 11 formed on the surface of the step portion 8 in the cavity 6 is a terminal formed on a mother board (not shown) or another conductor portion 11 in use.
  • 14 are not electrically connected, that is, they are formed as electrically independent dummy element connection terminals (surface conductor portions) 11a.
  • a bottomed hole 19 similar to the above is formed in the vicinity of the upper right corner of the surface 3 of the substrate body 2, and the bottom surface thereof is formed between the ceramic layers C3 and C4.
  • the plating electrode surface 18 of the electroplating conductor layer 16 thus exposed is exposed.
  • the electroplating conductor layer 16 is also electrically independent from the other conductor portions 11 and 14 and is separated from the side surface 5 of the substrate body 2.
  • the base end side of the element connection terminal 11a is connected to one end side of the connection wiring 24 formed between the ceramic layers C2 and C3, and the other end side of the connection wiring 24 is a via penetrating the ceramic layer C3. It is electrically connected to the electroplating conductor layer 16 through a conductor 25. Therefore, as shown in FIG. 9, the tip of the same electrode pin Pi is brought into contact with the plating electrode surface (part) 18 in the bottomed hole 19, and the same electrolytic Ni plating and electrolytic Au plating as described above are performed. By applying, the Ni plating film and the Au plating film can be reliably coated on the surface (exposed surface) of the element connection terminal 11a which is electrically independent. Therefore, the wiring substrate 1b coated with a predetermined metal plating film can be formed on the surface of the element connection terminal 11a having a relatively small area.
  • FIG. 10 is a similar partial vertical cross-sectional view showing a different form of the wiring board 1b.
  • the wiring board 1 b also includes the same substrate body 2, cavity 6, frame-shaped metallized layer 15, a plurality of external connection conductors 14 (not shown), and the like.
  • an element connection terminal 11a which is at least one surface conductor portion is formed.
  • a bottomed hole 19 that opens to the back surface 4 is formed at an arbitrary position on the peripheral side of the back surface 4 of the substrate body 2 so as to penetrate the relatively thick ceramic layer C1, and on the bottom surface thereof,
  • the plating electrode surface 18 of the electroplating conductor layer 16 formed between the ceramic layers C1 and C2 is exposed.
  • the electroplating conductor layer 16 is also electrically independent from the other conductor portions 11 and 14 and is separated from the side surface 5 of the substrate body 2.
  • the base end side of the element connection terminal 11a that is electrically independent when in use is connected to one end side of the connection wiring 24 formed between the ceramic layers C2 and C3.
  • the end side is electrically connected to the electroplating conductor layer 16 via a via conductor 25 penetrating the ceramic layer C2. Therefore, as shown in FIG. 10, the tip of the same electrode pin Pi is brought into contact with the electrode surface 18 for plating in the bottomed hole 19 from the back surface 4 side of the substrate body 2, and the same electrolytic Ni plating and By applying electrolytic Au plating, the Ni plating film and the Au plating film can be reliably covered on the surface (exposed surface) of the element connection terminal 11a which is electrically independent.
  • FIG. 11 is a similar partial vertical sectional view showing a wiring board 1b which is an application form of the form shown in FIG.
  • the lowermost relatively thick ceramic layer C1 constituting the substrate body 2 is divided into upper and lower ceramic layers C11 and C12, and a bottomed hole 19 opened on the back surface 4 of the substrate body 2 is formed.
  • a plating electrode surface 18 of the same electroplating conductor layer 16 formed between the ceramic layers C11 and C12 is exposed on the bottom surface.
  • the base end side of the element connection terminal 11a which is a surface conductor portion is connected to one end side of the connection wiring 24 formed between the ceramic layers C2 and C3, and the other end side of the connection wiring 24 is connected to the ceramic layer C2.
  • connection wiring 26 Is connected to one end side of a connection wiring 26 formed between the ceramic layers C12 and C2 via a via conductor 25 penetrating the ceramic layer C2, and the other end side of the connection wiring 26 is connected via a via conductor 25 penetrating the ceramic layer C11.
  • connection wiring 26 Is connected to one end side of a connection wiring 26 formed between the ceramic layers C12 and C2 via a via conductor 25 penetrating the ceramic layer C2, and the other end side of the connection wiring 26 is connected via a via conductor 25 penetrating the ceramic layer C11.
  • the element connection terminal 11a which is the surface conductor portion, and the electroplating conductor layer 16 are electrically connected via the upper and lower two-layer connection wirings 24 and 26 and the upper and lower two via conductors 25. Accordingly, it becomes easy to open the bottomed hole 19 having a relatively small inner diameter in the back surface 4 of the substrate body 2.
  • the wiring substrate 1b having the above-described configuration also becomes the wiring substrate 1b in which the surface of the element connection terminal 11a having a relatively small area is coated with a predetermined metal plating film. In the form of the wiring board 1b shown in FIGS.
  • the bottomed holes 19r to 19s are formed in place of the bottomed holes 19, or the inner wall surfaces of the bottomed holes 19, 19r to 19s are formed.
  • the wall conductor layer 21 may be further formed.
  • a plurality of element mounting pads are formed on the bottom surface 7 of the cavity 6 instead of the single element mounting pad 10, and the element A part of the mounting pad is used as an electrically independent surface conductor when in use, and the surface of the element mounting pad, which is the surface conductor, is formed according to any of the forms shown in FIGS. You may make it coat
  • the surface of the substrate body may be a flat surface, and the same cavity may be opened in the reverse direction on the back surface of the substrate body.
  • the surface conductor portion in the present invention includes a part of the external connection conductor formed at an arbitrary position on the front surface or the back surface of the substrate body made of ceramic.
  • the external connection terminal is, for example, a part of a certain pattern that is an object of image recognition in a plan view of the front surface or the back surface, together with a plurality of external connection conductors that are different conductor portions, Alignment marks for positioning in plan view of the front or back surface of the substrate body are included.
  • the bottomed hole which is the opening of the present invention is formed at a plurality of locations on the front or back surface of the same wiring board, and a part of the electroplating conductor layer is individually exposed on the bottom surface of each bottomed hole. It is good also as the form which is doing.
  • the bottomed hole may have a wide-shaped cross section in which the opening diameter of the front surface or the back surface of the substrate body is small and the bottom surface side is larger than the opening diameter.
  • the present invention even if there is an electrically independent surface conductor portion on the surface of the substrate body made of ceramic, or an electrically independent surface conductor portion on the bottom surface side of the cavity opened on the surface of the substrate body.

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Abstract

セラミックからなる基板本体の表面などに電気的に独立した表面導体部があっても、表面に電解メッキ法による金属メッキ膜が確実に被覆される配線基板を提供する。セラミックｃ１～ｃ４からなり、表面３および裏面４と、該表面３と裏面４との周辺間に位置する側面５とを有する基板本体２と、該基板本体２の表面３に形成され、且つ表面に金属メッキ膜が被覆された枠形メタライズ層（表面導体部）１５と、基板本体２の内部に形成され、一端が枠形メタライズ層１５と電気的に接続し、他端が基板本体２の表面３に形成され且つ枠形メタライズ層１５とは別の導体部１１，１４には電気的に独立していると共に、基板本体２の側面５から離間している電解メッキ用導体層１６と、を含み、基板本体２の表面３には、電解メッキ用導体層１６の一部１８を底面に露出させる開口部１９が形成されている、配線基板１。

Description

配線基板
　本発明は、セラミックからなる基板本体の表面などに外部接続用導体とは電気的に接続されていない非導通の表面導体部などを有していても、該表面導体部などの表面に電解金属メッキ膜が確実に被覆されている配線基板に関する。
　例えば、絶縁基体の側面に複数のパッドおよび全てを短絡させた単一で長尺なパッドの少なくとも一方を形成し、これらのパッドに同一の枠体から立設した複数の外部リード端子を接触させることにより、前記パッドと電気的に個別に接続しており且つ上記絶縁基体の表面に開口するキャビティの底面側に設けた複数の配線用メタライズ層の表面ごとに、金属メッキ膜を電解メッキによって被覆可能とした半導体素子収納用パッケージの製造方法の発明が提案されている（例えば、特許文献１参照）。
　しかし、前記のような構造である半導体素子収納用パッケージの場合、前記メッキ後には、不要となる絶縁基体の側面に形成された複数のパッドを研磨して除去する工程が必要になる。しかも、上記パッドを除去した後の絶縁基体の側面には内部配線ごとの端面が露出するため、電気的に不用意な短絡などを招くなどのおそれもあった。
　一方、セラミックからなる基板本体の表面に形成した平面視が矩形枠状で且つ比較的幅の狭いキャビティ封止用のメタライズ層や、上記基体本体の表面または該表面に開口するキャビティの底面側に設けた比較的小さな複数のパッドのうち、電流が流れない非導通パッドがある場合、上記メタライズ層の表面や前記非導通パッドの表面に先尖状の電極ピンを点接触させた状態で、Ｎｉメッキ膜およびＡｕメッキ膜を電解メッキにより順次被覆することも行われている。
　しかし、上記電極ピンを点接触させたり、該電極ピンの周面を線接触させた場合、不用意に接触部分がズレて上記メタライズ層やパッドの表面にキズが付いたりする。しかも、前記メタライズ層の幅が狭かたり、非導通パッドが小さい場合、上記電極ピンが外れて電解メッキができなくなる場合があった。更に、前記メタライズ層の外側における基板本体の表面に、上記電極ピンと接触させるための電極用導体部を別に張り出すと、基板本体のサイズが大型化してしまう、という問題点もあった。
特開２００３－１６８７５４号公報(第１～７頁、図１～５)
　本発明は、背景技術において説明した問題点を解決し、セラミックからなる基板本体の表面などに外部接続用導体とは電気的に接続されていない表面導体部や、前記基板本体の表面に開口するキャビティの底面側に外部接続用導体とは電気的に接続されていない表面導体部があっても、これらの表面に電解メッキ法による金属メッキ膜が確実に被覆されており、電極ピンとの接触によるキズが目立ちにくく且つ基板本体の小型化も可能な配線基板を提供する、ことを課題とする。
課題を解決するための手段および発明の効果
　本発明は、前記課題を解決するため、セラミックからなる基板本体の表面および裏面の少なくとも一方に電極ピンが挿入できる開口部を形成し、該開口部の底面に一部が露出する電解メッキ用導体層と、金属メッキ膜の被覆が必要な表面導体部とを電気的に導通可能とする、ことに着想して成されたものである。
　即ち、本発明による第１の配線基板（請求項１）は、セラミックからなり、表面および裏面と、該表面と裏面との間に位置する側面とを有する基板本体と、該基板本体の表面および裏面の少なくとも一方に形成され、且つ表面に金属メッキ膜が被覆された表面導体部と、上記基板本体の内部に形成され、一端が上記表面導体部と電気的に接続し、他端が基板本体の表面または裏面に形成され且つ上記表面導体部とは別の導体部には電気的に独立していると共に、基板本体の側面から離間している電解メッキ用導体層と、を含む配線基板であって、上記基板本体の表面または裏面の少なくとも一方には、上記電解メッキ用導体層の少なくとも一部を露出させる開口部が形成されている、ことを特徴とする。
　尚、上記のうち、「上記基板本体の内部に形成され、一端が上記表面導体部と電気的に接続し、他端が基板本体の表面または裏面に形成され且つ上記表面導体部とは別の導体部には電気的に独立していると共に、基板本体の側面から離間している電解メッキ用導体層」は、「上記基板本体の内部に形成され、一端が上記表面導体部と電気的に接続し、他端が基板本体の表面または裏面に形成され且つ上記表面導体部とは別の導体部には電気的に接続しないと共に、基板本体の側面には露出しない電解メッキ用導体層」と表現することもできる。
　これによれば、前記表面導体部は、前記基板本体の表面または裏面の少なくとも一方に形成された開口部に一部が露出する前記電解メッキ用導体層の一端部と電気的に接続されている。そのため、例えば、基板本体の表面が別の導体部によって広く占有されていても、上記表面導体部は、上記電解メッキ用導体層とビア導体などを介して導通可能とされているので、前記開口部から電解メッキ用の電極ピンの先端部を挿入し且つ該開口部に露出する電解メッキ用導体層の一部に接触させることにより、該表面導体部の表面に対して確実にＮｉやＡｕなどの金属メッキ膜が被覆されている。従って、使用時には外部接続用導体などの別の導体層とは電気的に独立したものとなる表面導体部の表面に金属メッキ膜が確実に被覆された配線基板となっている。
　しかも、前記電解メッキ用導体層は、その一部が前記開口部に露出するため、該開口部内に挿入される電解メッキ用の電極ピンの先端部がズレたり、当該開口部から外れにくくなると共に、仮に、上記ピンによる圧痕などのキズが生じても、上記開口部の底面側に位置しているので、該キズを目立ちにくくすることもできる。更に、前記電解メッキ用導体層は、基板本体の内部に形成され且つ前記開口部にその一部が露出するため、従来における不用意な短絡を予防できると共に、該基板本体の小型化も容易となる。
　尚、前記セラミックは、アルミナ、ムライト、窒化アルミニウムなどの高温焼成セラミック、あるいはガラス－セラミックなどの低温焼成セラミックである。
　また、前記基板本体は、平坦な表面を有する板形状の形態のほか、後述するように、上記表面の中央側に該表面に開口するキャビティを有していても良い。
　更に、前記表面導体部は、使用時には、マザーボードに形成された端子と電気的に接続される外部接続端子などの別の導体層とは電気的に独立した非導通の導体部であり、例えば、キャビティを封止するための金属枠体や金属蓋板を取り付けるための枠形メタライズ層（キャビティ封止用のメタライズ層）や、別の導体層とは電気的に独立した非導通の外部接続端子などが例示される。一方、前記別の導体部は、使用時にはマザーボードの端子と電気的に接続される導体部である。
　また、前記表面導体部や電解メッキ用導体層、ビア導体、別の導体部である配線層、接続配線などには、前記基板本体のセラミックが高温焼成セラミックの場合には、ＷまたはＭｏおよびこれらの何れか一方をベースとする合金などが適用され、基板本体のセラミックが低温焼成セラミックの場合には、ＡｇまたはＣｕなどが適用される。
　更に、前記電解メッキ用導体層のうち、前記開口部の底面に露出する一部（露出面）には、前記表面導体部の表面に電解メッキ用の電流を給電するための給電用のピンにおける先尖り形状の先端部が点状にして当接される。
　更に、前記開口部は、前記基板本体の表面または裏面を形成する最外層のセラミック層、あるいは該セラミック層およびこれに隣接するセラミックを厚み方向に沿って貫通して形成されている。
　加えて、前記金属メッキ膜は、例えば、ＮｉおよびＡｕメッキ膜が例示される。
　また、本発明には、前記表面導体部は、前記基板本体の表面に開口するキャビティの開口部に沿って形成された該キャビティ封止用の枠形メタライズ層、あるいは、上記基板本体の表面または裏面に形成された一部の外部接続用導体である、配線基板（請求項２）も含まれる。
　これによれば、上記枠形メタライズ層の幅が比較的狭かったり、使用時に非導通となる外部接続用導体のサイズの面積が比較的小さい場合であっても、これらの表面に対し、前記電解メッキ用導体層およびこれに導通する導体部を介して、所要の金属メッキ膜を確実に被覆した配線基板とすることができる。
　尚、前記外部接続用導体は、使用時には電流が流れないもので、例えば、画像処理に活用されるパターンの一部を構成するダミーパッド、実装すべき素子の姿勢を安定させるためのダミーの素子実装用パッド、あるいは、配線基板の位置決め用のアライメントマークとして用いるものである。
　更に、本発明には、前記基板本体は、その表面に開口するキャビティを有し、該キャビティの底面側に前記表面導体部である非導通パッドが形成されている、配線基板（請求項３）も含まれる。
　これによれば、上記非導通（ダミー）パッドの面積が比較的小さい場合、例えば、実装すべき電子部品などの素子実装用パッドよりも面積が比較的小さい場合であっても、その表面に対し、前記電解メッキ用導体およびこれに導通する導体を介して、所要の金属メッキ膜を確実に被覆した配線基板とすることができる。
　尚、前記キャビティの底面側には、該キャビティの底面のほか、該底面の周辺に比較的近接する段部の水平面も含まれる。
　また、前記キャビティの底面における中央部には、当該キャビティに実装すべき電子部品などの単一の素子実装用パッドが形成されているが、該実装用パッドが比較的広い表面積を有している場合には、本発明における前記表面導体部には含まれない。但し、複数の素子実装用パッドから構成され、その一部に非導通の（ダミー）素子実装用パッドが含まれる場合、該非導通の素子実装用パッドは、前記表面導体部に含まれる。
　また、本発明には、前記表面導体部と電解メッキ用導体層との間は、ビア導体および接続配線の少なくとも何れか一方を介して導通可能とされている、配線基板（請求項４）も含まれる。
　これによれば、前記基板本体の表面と裏面との厚み方向、あるいは該表面および裏面に沿った方向において、前記表面導体部と電解メッキ用導体層との配置位置ごとの乖離を確実に解消し、両者間における電気的な接続を確保できるので、上記表面導体部の表面に前記金属メッキ膜を確実に被覆することができる。
　尚、上記表面導体部と電解メッキ用導体層との間は、単数または複数の上記ビア導体と、前記基板本体の内部、表面、あるいは裏面に形成された単数または複数の接続配線（配線層）とを介して導通可能とされていても良い。
　更に、本発明には、前記開口部は、有底孔であり、該有底孔の底面に前記電解メッキ用導体層の一部が露出している、配線基板（請求項５）も含まれる。
　これによれば、電解メッキ用の電極ピンの先端部を上記開口部から挿入し且つ該有底孔の底面に露出する電解メッキ用導体層の一部（メッキ用面電極）に容易に接触させることができる。しかも、仮に電極ピンが有底孔の径方向にズレても、その先端部と電解メッキ用導体層の露出面との接触状態を容易に保てる。従って、前記表面導体部の表面に所要の金属メッキ膜を確実に被覆した配線基板となる。
　尚、前記開口部となる有底孔は、平面視が円形で且つ全体が円柱形、平面視が楕円形で且つ全体が楕円柱形、平面視が長円形で且つ全体が長円柱形、該有底孔の底面側が狭い逆円錐形状、逆楕円錐形状、逆長円錐形状、あるいは、平面視が三角形以上の多角形で且つ全体が三角柱以上の多角柱形状などを呈する形態を含んでおり、これらの底面に電解メッキ用導体部の平坦な一部が露出している。
　また、本発明には、前記有底孔の内壁面には、前記電解メッキ用導体層と電気的に接続される壁面導体層が形成されている、配線基板（請求項６）も含まれる。
　これによれば、例えば、不用意な外力によって電極ピンが有底孔の径方向にズレた場合でも、その先端部が壁面導体層に確実に接触するので、前記表面導体部の表面に所要の金属メッキ膜を確実に被覆した配線基板とすることができる。
　加えて、本発明には、前記表面導体部と電解メッキ用導体層とは、前記基板本体の表面または裏面に形成された接続配線および前記壁面導体層を介して、電気的に接続されている、配線基板（請求項７）も含まれる。
　これによれば、例えば、前記基板本体の表面または裏面において、比較的幅の狭い接続配線と、前記有底孔の内壁面に形成された壁面導体層とを介して、前記表面導体部と電解メッキ用導体層との間を導通できる。従って、基板本体の表面または裏面における他の導体同士の間や裏面における任意の位置に上記接続配線を形成することで、基板本体の内部への占有体積（領域）を最少にして、前記表面導体部の表面に所要の金属メッキ膜を確実に被覆した配線基板とすることができる。
本発明による一形態の配線基板を示す平面図。 図１中のＸ－Ｘ線の矢視に沿った部分垂直断面図。 図１中のＹ－Ｙ線の矢視に沿った部分垂直断面図。 （Ａ）は上記配線基板における異なる形態の有底孔の付近を示す部分平面図、（Ｂ）は更に異なる形態の有底孔の付近を示す部分平面図。 別異な形態の有底孔の付近を示す部分垂直断面図。 応用形態の有底孔の付近を示す部分垂直断面図。 異なる形態の配線基板における有底孔の付近を示す部分垂直断面図。 更に異なる形態の配線基板における有底孔の付近を示す部分平面図。 図８中の矢印Ｚ方向の視覚による部分垂直断面図。 上記配線基板の異なる形態を示す図９と同様の部分垂直断面図。 上記配線基板の更に異なる形態を示す図９と同様の部分垂直断面図。
　以下において、本発明を実施するための形態について説明する。
　図１は、本発明による一形態の配線基板１を示す平面図、図２は、図１中のＸ－Ｘ線の矢視に沿った部分断面図、図３は、図１中のＹ－Ｙ線の矢視に沿った部分断面図である。
　上記配線基板１は、図１～図３に示すように、全体が板形状の基板本体２と、該基板本体２の表面３に形成された枠形メタライズ層（表面導体部）１５と、基板本体２の内部に形成された電解メッキ用導体層１６と、上記基板本体２の表面３における右上のコーナ付近に形成された有底孔（開口部）１９とを備えている。
　上記基板本体２は、平面視が正方形（矩形）状の表面３および裏面４と、該表面３と裏面４との周辺間に位置する四辺の側面５とを有し、セラミック層Ｃ１～Ｃ４を一体に積層したものである。
　尚、上記セラミック層Ｃ１～Ｃ４を構成するセラミックは、アルミナなどの高温焼成セラミック、またはガラス－セラミックなどの低温焼成セラミックである。
　図１～図３に示すように、前記基板本体２の表面の中央側には、平面視が正方形状のキャビティ６が開口している。該キャビティ６は、平面視が正方形状の底面７と、その周辺から立設し且つ全体が四角柱形状の側面９と、該側面９のうち底面７側に近接し且つ平面視が矩形枠状の段部８とを有している。上記底面７には、その周辺部を除いたほぼ全面に、平面視が矩形状で単一の素子実装用パッド１０が形成されている。該素子実装用パッド１０の上面には、追って半導体素子２０などが接着により実装される。
　上記段部８の表面（水平面）には、複数の素子接続端子（別の導体部）１１が形成されている。該素子接続端子１１と上記半導体素子２０との間は、追って複数のボンディングワイヤｗｉを介して導通可能とされる。尚、前記枠形メタライズ層１５は、上記キャビティ６の開口部付近に沿って形成されている。
　また、前記基板本体２の表面３の周辺側には、一辺が各側面５に露出する平面視が矩形状である複数の外部接続用導体（別の導体部）１４が形成されている。かかる外部接続用導体１４ごとの上には、図１に示すように、複数のリードＬｉの先端部が追ってロウ付けなどによって個別に接合されている。
　更に、図２に示すように、セラミック層Ｃ２～Ｃ４間には、前記素子接続端子１１の一部と配線層１２とが形成され、これらおよび前記外部接続用導体１４との間は、セラミック層Ｃ３，Ｃ４を個別に貫通するビア導体１３を介して、互いに電気的に接続されている。上記素子接続端子１１の残部と外部接続用導体１４の一部とは、電気的に独立したものであっても良い。
　加えて、図１，図３に示すように、記基板本体２の表面３における右上のコーナ付近には、平面視が円形の前記有底孔１９が開口し、該有底孔１９の底面には、セラミック層Ｃ３，Ｃ４間に形成された前記電解メッキ用導体層１６の他端側における一部（メッキ用電極面）１８が露出している。該電解メッキ用導体層１６の一端側は、前記枠形メタライズ層１５の右上コーナ付近の下面に接続するビア導体１７と接続されている。
　しかも、図１，図３で示すように、上記電解メッキ用導体層１６は、基板本体２における上辺および右辺を含む全ての側面５には露出しないように、該側面５から離間している。更に、該電解メッキ用導体層１６は、前記素子接続端子（別の導体部）１１や外部接続用導体（別の導体部）１４とは電気的に独立している。
　尚、前記素子実装用パッド１０、素子接続端子１１、配線層１２、ビア導体１３，１７、外部接続用端子１４、枠形メタライズ層１５、電解メッキ用導体層１６は、前記セラミック層Ｃ１～Ｃ４を構成するセラミックが、アルミナなどの高温焼成セラミックからなる場合には、主にＷまたはＭｏやこれらの何れか一方をベースとする合金などからなり、ガラス－セラミックなどの低温焼成セラミックからなる場合には、主にＣｕまたはＡｇやこれらの何れか一方をベースとする合金などからなる。また、素子実装用パッド１０、素子接続端子１１の先端側（素子実装用パッド１０側）、外部接続用導体１４、枠形メタライズ層１５、および電解メッキ用導体層１６の一部１８の外部に露出する表面には、それぞれ所要厚さのＮｉメッキ膜およびＡｕメッキ膜（金属メッキ膜：図示せず）が２層にして順次被覆されている。
　前記のような配線基板１は、概略以下のようにして制作されものである。
　予め、例えば、アルミナ粉末などを含む４枚のグリーンシートを用意し、かかるグリーンシートの所要の位置ごとに対し、打ち抜き加工や、Ｗ粉末などを含む導電性ペーストのパターン印刷や貫通孔への充填などを行った後、これら４枚のグリーンシートを積層および圧着してから、所定の温度帯で焼成して、前記図１～図３に示したとほぼ同様である焼成済みの配線基板１を得た。
　次いで、図３中の二点鎖線で示すように、側面視が全体でＬ字形状を呈する電極ピンＰｉの先尖形の先端部を、基板本体２の表面３側から有底孔１９の内部に挿入し、該有底孔１９の底面に露出する電解メッキ用導体層１６の一部１８の表面に若干の圧力を伴って点接触させた。この際、該導体層１６の一部１８は、メッキ用電極面となる。
　かかる状態で、上記配線基板１を電極ピンＰｉと共に、図示しない電解Ｎｉメッキ槽および電解Ａｕメッキ槽に順次浸漬し、電解Ｎｉメッキおよび電解Ａｕメッキを順次施した。その結果、別の導体層１１，１４とは電気的に接続していない表面導体部である枠形メタライズ層１５の表面に対し、Ｎｉメッキ膜およびＡｕメッキ膜を順次被覆することができた。
　尚、比較的広い面積の素子実装用パッド１０の表面には、別の電極ピンＰｉを接触させ、更に別の導体部である素子接続端子１１の先端側、外部接続用導体１４の表面には、これらの何れかに別の電極ピンＰｉを接触することなどにより、前記と同時に前記同様の電解金属メッキを施した。
　以上の各工程を経た結果、前記のような配線基板１を得ることができた。
　前記配線基板１によれば、表面導体部である前記枠形メタライズ層１５は、前記基板本体２の表面３に形成された有底孔（開口部）１９に一部１８が露出する前記電解メッキ用導体層１６の一端部とビア導体１７を介して電気的に接続されている。そのため、基板本体２の表面３における周辺側が外部接続端子（別の導体部）１４によって広く占有され、上記枠形メタライズ層１５の幅が狭く且つ面積が小さいため、電解メッキ用の電極ピンＰｉを直に接触し難い場合でも、該枠形メタライズ層１５の表面は、電解メッキ用導体層１６とビア導体１７とを介して導通可能とされている。そのため、有底孔１９の開口部から電解メッキ用の電極ピンＰｉの先端部を挿入し且つ該有底孔１９に露出する電解メッキ用導体層１６の一部（メッキ用電極面）１８に接触させることで、上記枠形メタライズ層１５の表面に対し確実にＮｉおよびＡｕの金属メッキ膜が被覆されている。従って、使用時には別の導体部１１，１４とは非導通になる枠形メタライズ層１５の表面にも金属メッキ膜が確実に被覆された配線基板１となっている。
　しかも、前記電解メッキ用導体層１６は、その一部１８が有底孔１９に露出するため、該有底孔１９に挿入される前記電極ピンＰｉの先端部がズレたり、該有底孔１９から外れにくいと共に、仮に、該ピンＰｉによる圧痕などのキズを招いても、上記有底孔１９の底部に位置しているので、該キズが目立ちにくくなる。
　更に、前記電解メッキ用導体層１６は、基板本体２の内部に形成され且つ前記有底孔１９の底面にその一部１８が露出するので、不用意な短絡を予防できると共に、該基板本体２を含めた配線基板１全体の小型化も容易となる。
　図４（Ａ）は、前記配線基板１における異なる形態の有底孔１９ｒの付近を示す部分平面図である。図示のように、上記有底孔１９ｒは、平面視で基板本体２の表面３における１コーナ付近で、該表面３の中心部を通る対角線に沿った長軸を有する楕円形を呈し、その底面に前記電解メッキ用導体層１６のメッキ用電極面（一部）１８が楕円形状にして露出している。尚、上記有底孔１９ｒは、平面視で長円形を呈する形態としても良い。また、上記表面３における有底孔１９ｒの長軸は、任意の方向に沿ったものとしても良い。
　また、図４（Ｂ）は、前記配線基板１における更に異なる形態の有底孔１９ｓの付近を示す部分平面図である。図示のように、上記有底孔１９ｓは、平面視で基板本体２の表面３における１コーナ付近で、該表面３の中心部を通る対角線に沿った一対の長辺を有する長方形状を呈し、その底面に前記電解メッキ用導体層１６のメッキ用電極面（一部）１８が長方形状にして露出している。尚、上記有底孔１９ｓは、平面視で正方形状を呈する形態としても良い。また、上記表面３における有底孔１９ｓの各長辺や各辺は、任意の方向に沿ったものとしても良い。
　更に、図５は、前記配線基板１における別異な形態の有底孔１９ｔの付近を示す部分垂直断面図である。図５に示すように、上記有底孔１９ｔは、基板本体２の表面３側からセラミック層Ｃ３，Ｃ４間に位置する電解メッキ用導体層１６のメッキ用電極面（一部）１８に向かって順次狭くなる傾斜した内壁面（テーパ面）を有している。そのため、該有底孔１９ｔは、平面視が円形の場合には円錐形状を、平面視が楕円形または長円形の場合には楕円錐形状または長円錐形状を、平面視が長方形状または正方形状の場合には四角錐形状を呈するものとなる。
　以上のような有底孔１９ｒ～１９ｔによっても、前記有底孔１９と同様な効果を奏することができ、特に傾斜した内壁面を有する上記有底孔１９ｔの場合には、図５に示すように、前記電極ピンＰｉの先端部の挿入操作が容易となる。
　図６は、前記配線基板１における応用形態の有底孔１９の付近を示す部分垂直断面図である。図６に示すように、平面視が円形である有底孔１９の内壁面には、電解メッキ用導体層１６のメッキ用電極面１８に底面が接続した円柱形の壁面導体層２１が更に形成されている。かかる壁面導体層２１を有する有底孔１９によれば、前記電極ピンＰｉの先端部がメッキ用電極面１８から不用意に外れても、壁面導体層２１の内周面に点接触で当接するので、上記電極ピンＰｉと電解メッキ用導体層１６との電気的な接続を確保することができる。
　尚、上記壁面導体層２１は、前記有底孔１９ｒ～１９ｔの内壁面に対しても、これを更に追加して形成しても良い。
　また、配線基板１における前記有底孔１９ｒ～１９ｔは、基板本体２の表面３における任意の位置に形成しても良く、例えば、該表面３の周辺側における前記外部接続端子１４，１４間に配置した形態としても良い。
　図７は、異なる形態の配線基板１ａにおける有底孔１９の付近を示す部分垂直断面図である。
　上記配線基板１ａは、図７に示すように、前記同様の基板本体２、キャビティ６、枠形メタライズ層１５、および複数の外部接続端子１４（図示せず）などを備えている。該配線基板１ａにおいて、基板本体２の表面３における１コーナ付近あるいは任意の周辺側には、前記同様の有底孔１９が形成され、該有底孔１９の内壁面には、前記同様の壁面導体層２１が形成されていると共に、該壁面導体層２１および有底孔１９の底面には、電解メッキ用導体層１６のメッキ用電極面１８が露出している。一方、キャビティ６の開口部に沿って形成された枠形メタライズ層１５と壁面導体層２１の上面との間には、基板本体２の表面３に沿って形成された接続配線２２により電気的に接続されている。該接続配線２２は、前記外部接続端子１４，１４間を通過するように比較的狭い幅で配設されている。
　以上のような配線基板１ａによれば、前記配線基板１による効果に加え、基板本体２の表面３における別の導体部である外部接続用導体１４，１４間などの任意の位置に接続配線２２を形成することで、基板本体２の内部への占有体積（領域）を最少にして、表面導体部である枠形メタライズ層１５の表面に所要の金属メッキ膜を確実に被覆した配線基板１ａとなっている。
　尚、上記有底孔１９に替えて、内壁面に壁面導体層２１を形成した前記有底孔１９ｒ～１９ｓを適用しても良い。
　また、前記基板本体２の裏面４に形成された表面導体部（図示せず）についても、該裏面４に開口する有底孔１９、その内壁面に形成された壁面導体層２１、およびこれらの間の裏面４に沿って形成した接続配線２２を介して、電解メッキ用導体層１６のメッキ用電極面１８と導通可能としても良い。
　図８は、更に異なる形態の配線基板１ｂにおける前記有底孔１９の付近を示す部分平面図、図９は、図８中の矢印Ｚ方向の視覚による部分垂直断面図である。
　上記配線基板１ｂは、図８，図９に示すように、前記同様の基板本体２、キャビティ６、枠形メタライズ層１５、および複数の外部接続用導体１４などを備えている。該配線基板１ｂでは、キャビティ６内の段部８の表面に形成された複数の素子接続端子１１のうち、少なくとも１個は、使用時には、図示しないマザーボードに形成された端子や別の導体部１１，１４とは電気的接続されない、即ち、電気的に独立したダミーの素子接続端子（表面導体部）１１ａとして形成されている。
　図８，図９に示すように、基板本体２の表面３における右上のコーナ付近には、前記同様の有底孔１９が形成され、その底面には、セラミック層Ｃ３，Ｃ４間に沿って形成された電解メッキ用導体層１６のメッキ用電極面１８が露出している。かかる電解メッキ用導体層１６も、別の導体部１１，１４とは電気的に独立しており、且つ基板本体２の側面５からは離間している。
　更に、前記素子接続端子１１ａの基端側は、セラミック層Ｃ２，Ｃ３間に形成された接続配線２４の一端側に接続し、該接続配線２４の他端側は、セラミック層Ｃ３を貫通するビア導体２５を介して上記電解メッキ用導体層１６と電気的に接続されている。
　そのため、図９に示すように、前記同様の電極ピンＰｉの先端部を有底孔１９内のメッキ用電極面（一部）１８に接触させ、且つ前記同様の電解Ｎｉメッキおよび電解Ａｕメッキを施すことにより、電気的に独立している前記素子接続端子１１ａの表面（露出面）に対し、Ｎｉメッキ膜およびＡｕメッキ膜を確実に被覆することができる。従って、比較的小面積である素子接続端子１１ａの表面に対しても、所定の金属メッキ膜を被覆した配線基板１ｂとすることができる。
　図１０は、前記配線基板１ｂにおける異なる形態を示す前記同様の部分垂直断面図である。
　上記配線基板１ｂも、図１０に示すように、前記同様の基板本体２、キャビティ６、枠形メタライズ層１５、および複数の外部接続用導体１４（図示せず）などを備え、上記キャビティ６内の段部８の表面には、少なくとも１個の表面導体部である素子接続端子１１ａが形成されている。図示のように、基板本体２の裏面４における周辺側の任意の位置には、該裏面４に開口する有底孔１９が比較的厚いセラミック層Ｃ１を貫通して形成され、その底面には、セラミック層Ｃ１，Ｃ２間に形成された電解メッキ用導体層１６のメッキ用電極面１８が露出している。かかる電解メッキ用導体層１６も、別の導体部１１，１４とは電気的に独立しており、且つ基板本体２の側面５からは離間している。
　更に、使用時には、電気的に独立したものとなる前記素子接続端子１１ａの基端側は、セラミック層Ｃ２，Ｃ３間に形成された接続配線２４の一端側に接続し、該接続配線２４の他端側は、セラミック層Ｃ２を貫通するビア導体２５を介して上記電解メッキ用導体層１６と電気的に接続されている。
　そのため、図１０に示すように、前記同様の電極ピンＰｉの先端部を基板本体２の裏面４側から有底孔１９内のメッキ用電極面１８に接触させ、且つ前記同様の電解Ｎｉメッキおよび電解Ａｕメッキを施すことで、電気的に独立している前記素子接続端子１１ａの表面（露出面）にＮｉメッキ膜およびＡｕメッキ膜を確実に被覆することができる。
　図１１は、図１０で示した形態の応用形態である配線基板１ｂを示す前記同様の部分垂直断面図である。
　上記配線基板１ｂでは、基板本体２を構成する最下層の比較的厚いセラミック層Ｃ１を上下のセラミック層Ｃ１１，Ｃ１２に分割し、基板本体２の裏面４に開口する有底孔１９を形成し、その底面には、上記セラミック層Ｃ１１，Ｃ１２間に形成した前記同様の電解メッキ用導体層１６のメッキ用電極面１８を露出させている。
　更に、表面導体部である前記素子接続端子１１ａの基端側は、セラミック層Ｃ２，Ｃ３間に形成した接続配線２４の一端側に接続し、該接続配線２４の他端側は、セラミック層Ｃ２を貫通するビア導体２５を介してセラミック層Ｃ１２，Ｃ２間に形成した接続配線２６の一端側に接続すると共に、該接続配線２６の他端側をセラミック層Ｃ１１を貫通するビア導体２５を介して、上記電解メッキ用導体層１６と電気的に接続している。
　以上のように、表面導体部である前記素子接続端子１１ａと電解メッキ用導体層１６との間を、上下２層の接続配線２４，２６および上下２個のビア導体２５を介して導通することにより、内径が比較的小さな有底孔１９を、基板本体２の裏面４に開口することが容易となる。
　前記のような形態の配線基板１ｂによっても、比較的面積が小さい素子接続端子１１ａの表面に対し所定の金属メッキ膜を被覆した配線基板１ｂにとなる。
　尚、前記図９～図１１に示す配線基板１ｂの形態において、前記有底孔１９に替えて、前記有底孔１９ｒ～１９ｓを形成したり、かかる有底孔１９，１９ｒ～１９ｓの内壁面に対して前記壁面導体層２１を更に形成した形態としても良い。
　また、前記図８～図１１に示す配線基板１ｂの各形態において、キャビティ６の底面７に、単一の前記素子実装用パッド１０に替えて、複数の素子実装用パッドを形成し、該素子実装用パッドの一部を使用時には電気的に独立する表面導体部とし、該表面導体部である素子実装用パッドの表面に対し、図８～図１１に示した何れかの形態によって、所定の金属メッキ膜を被覆するようにしても良い。
　本発明は、以上において説明した各形態に限定されるものではない。
　例えば、前記基板本体の表面は、平坦面であっても良く、しかも、該基板本体の裏面には、前記同様のキャビティが逆向きに開口する形態としても良い。
　また、本発明における前記表面導体部には、セラミックからなる基板本体の表面または裏面における任意の位置に形成された外部接続用導体の一部も含まれる。該外部接続端子は、例えば、複数の別の導体部である外部接続用導体と共に、上記表面または裏面の平面視において、画像認識の対象となる一定のパターンの一部を構成するものや、上記基板本体の表面または裏面の平面視における位置決め用のアライメントマークが含まれる。
　更に、本発明の開口部である前記有底孔は、同じ配線基板の表面または裏面における複数の箇所に形成され、かかる有底孔ごとの底面に電解メッキ用導体層の一部が個別に露出している形態としても良い。
　加えて、前記有底孔は、基板本体の表面または裏面の開口径が小さく且つその底面側が前記開口径よりも大きい底広形状の断面を有する形態としても良い。
　本発明によれば、セラミックからなる基板本体の表面などに電気的に独立した表面導体部や、前記基板本体の表面に開口するキャビティの底面側に電気的に独立した表面導体部があっても、これらの表面に金属メッキ膜が確実に被覆されており、且つ電極ピンとの接触によるキズが目立ちにくく且つ基板本体の小型化も可能な配線基板を確実に提供可能となる。
　１，１ａ，１ｂ…………配線基板
　２…………………………基板本体
　３…………………………表面
　４…………………………裏面
　５…………………………側面
　１１………………………素子接続端子（別の導体部）
　１１ａ……………………素子接続端子（表面導体部）
　１３，２５………………ビア導体
　１４………………………外部接続用導体（別の導体部）
　１５………………………枠形メタライズ層（表面導体部）
　１６………………………電解メッキ用導体層
　１８………………………メッキ用電極面（一部）
　１９，１９ｒ～１９ｔ…有底孔（開口部）
　２１………………………壁面導体層
　２２………………………接続配線
　ｃ１～ｃ４………………セラミック層（セラミック）

Claims (7)

  1. 　セラミックからなり、表面および裏面と、該表面と裏面との間に位置する側面とを有する基板本体と、
    　上記基板本体の表面および裏面の少なくとも一方に形成され、且つ表面に金属メッキ膜が被覆された表面導体部と、
    　上記基板本体の内部に形成され、一端が上記表面導体部と電気的に接続し、他端が基板本体の表面または裏面に形成され且つ上記表面導体部とは別の導体部には電気的に独立していると共に、基板本体の側面から離間している電解メッキ用導体層と、を含む配線基板であって、
    　上記基板本体の表面または裏面の少なくとも一方には、上記電解メッキ用導体層の少なくとも一部を露出させる開口部が形成されている、
    　ことを特徴とする配線基板。
  2. 　前記表面導体部は、前記基板本体の表面に開口するキャビティの開口部に沿って形成された該キャビティ封止用の枠形メタライズ層、あるいは、上記基板本体の表面または裏面に形成された一部の外部接続用導体である、
    　ことを特徴とする請求項１に記載の配線基板。
  3. 　前記基板本体は、その表面に開口するキャビティを有し、
    　上記キャビティの底面側に前記表面導体部である非導通パッドが形成されている、
    　ことを特徴とする請求項１に記載の配線基板。
  4. 　前記表面導体部と電解メッキ用導体層との間は、ビア導体および接続配線の少なくとも何れか一方を介して導通可能とされている、
    　ことを特徴とする請求項１乃至３の何れか一項に記載の配線基板。
  5. 　前記開口部は、有底孔であり、該有底孔の底面に前記電解メッキ用導体層の一部が露出している、
    　ことを特徴とする請求項１乃至４の何れか一項に記載の配線基板。
  6. 　前記有底孔の内壁面には、前記電解メッキ用導体層と電気的に接続される壁面導体層が形成されている、
    　ことを特徴とする請求項５に記載の配線基板。
  7. 　前記表面導体部と電解メッキ用導体層とは、前記基板本体の表面または裏面に形成された接続配線および前記壁面導体層を介して、電気的に接続されている、
    　ことを特徴とする請求項６に記載の配線基板。
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