WO2015110003A1 - 一种阶梯阻焊的封装产品制作方法 - Google Patents

一种阶梯阻焊的封装产品制作方法 Download PDF

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Publication number
WO2015110003A1
WO2015110003A1 PCT/CN2015/071189 CN2015071189W WO2015110003A1 WO 2015110003 A1 WO2015110003 A1 WO 2015110003A1 CN 2015071189 W CN2015071189 W CN 2015071189W WO 2015110003 A1 WO2015110003 A1 WO 2015110003A1
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WIPO (PCT)
Prior art keywords
package substrate
solder resist
layer
printing
manufacturing
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PCT/CN2015/071189
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English (en)
French (fr)
Inventor
崔永涛
李志东
谢添华
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广州兴森快捷电路科技有限公司
深圳市兴森快捷电路科技股份有限公司
宜兴硅谷电子科技有限公司
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Publication of WO2015110003A1 publication Critical patent/WO2015110003A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/8391—Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/83911—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning

Definitions

  • FC-CSP Flexible Chip-Chip Scale Package
  • FC-CSP Flexible Chip-Chip Scale Package
  • FC-CSP Flexible Chip-Chip Scale Package
  • the process of re-exposure, development, curing, etc. produces a stepped relief structure.
  • the step solder resist package product produced by the method has the first layer of the first layer of the solder resist and the second layer of the second layer of the solder resist layer, and the first layer of the solder joint may be broken.
  • the alignment accuracy between the solder resist layers is low, and the quality of the package substrate is low.
  • the present invention overcomes the defects of the prior art, and provides a method for manufacturing a packaged product of step solder resist which can improve production efficiency and improve product quality.
  • a method for manufacturing a step soldering package product comprising the steps of: firstly printing a solder resist on a package substrate, and performing the first alignment on the first layer of solder resist printed on the package substrate Exposing; performing a second printing solder mask on the package substrate exposed for the first time, performing a second alignment exposure on the second layer of solder resist printed on the package substrate; and performing a second alignment exposure
  • the package substrate is subjected to development processing; and the package substrate subjected to development processing is subjected to a curing process.
  • the semi-curing treatment is performed after the first printing solder mask and/or after the second printing solder mask.
  • the first printing is screen printing and the second printing is roll printing.
  • the screen printing uses a mesh number of 100 to 200, a screen printing speed of 50 to 200 mm/s, the roll printing uses a mesh number of 400 to 700, and a roller speed of 1 to 3 m. /min.
  • the number of meshes used in the screen printing is 120-180, and the screen printing speed is 60- 180mm/s, the number of meshes used for the roll coating is 430-650, and the roller speed is 1.4-2 m/min.
  • the alignment exposure is performed by UVDI exposure, and the exposure energy is 200 to 500 mj/cm 2 .
  • the exposure energy is 220 to 400 mj/cm 2 .
  • the exposure energy is 280 to 320 mj/cm 2 .
  • the first solder resist layer and the second solder resist layer need to be fenestrated at the same position, 50 to 70 ⁇ m in the same position edge of the second solder resist layer is also exposed.
  • the package substrate of the curing process is subjected to a UV curing treatment.
  • the invention firstly exposes the solder resists printed twice on the packaged product, then rinses off the blocked solder resist with the developer solution, and cures the two layers of solder resist together, and uses two developments relative to the prior art.
  • the method of rinsing off the blocked solder resist and curing separately, the present invention reduces the number of development steps while reducing the curing step after the development step.
  • Uniform development after layer can avoid the undercut of the window edge at the same position of the first solder resist layer and the second solder resist layer caused by the split development, and avoid the influence of the excessive development amount on the package substrate product in the chip. Quality reliability in the package. Therefore, the present invention can greatly save time, improve production efficiency, and improve the quality of the package substrate product.
  • 1 is a flow chart of a method for fabricating a ladder solder resist package according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a first alignment exposure of a packaged product according to an embodiment of the present invention.
  • FIG. 6 is a schematic view showing a second alignment exposure of a packaged product according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural view of a packaged product after development processing according to an embodiment of the present invention.
  • Figure 8 is a schematic enlarged view of the structure of Figure 7 at A;
  • Fig. 9 is a view showing the comparison between the time taken to manufacture the step solder resist and the time used in the conventional method in the embodiment of the present invention.
  • FIG. 1 it is a flow chart of a method for manufacturing a step solder resist package product according to an embodiment of the present invention.
  • the method for manufacturing a step solder resist package product according to the present invention comprises the following steps:
  • Providing a package substrate to be printed with solder resist first performing surface roughening treatment on the package substrate, ensuring uniformity of copper surface of the package substrate by super-roughening treatment, and improving bonding force between the copper surface of the package substrate and the solder resist layer .
  • FIG. 3 is a schematic structural view of one of the package substrates after the first print solder resist, as shown in FIG. 3, after the first print solder resist, on the package substrate.
  • a first layer of solder resist 20 is formed thereon.
  • the package substrate is semi-cured after the first print solder mask, that is, the solder resist layer on the surface of the package substrate is pre-baked according to a conventional method.
  • the first print resist welding of the present invention is screen printed, and the solder resist can be printed on the surface of the package substrate.
  • the through holes 21 on the package substrate are filled with solder resist.
  • the first alignment soldering of the first layer of solder resist printed on the package substrate is performed.
  • FIG. 4 is a schematic diagram of the first alignment exposure of one of the embodiments.
  • FIG. 5 is a schematic structural view of one of the package substrates after the second print solder resist, and the second is formed on FIG.
  • the layer solder resist 30, the second layer of solder resist 30 is laid on the first layer of solder resist 20.
  • the package substrate is semi-cured.
  • a second alignment exposure is performed on the second layer of solder resist printed on the package substrate
  • FIG. 6 is a schematic view of the second alignment exposure of one of the embodiments.
  • the second printing is performed by roll coating, and the roll printing method can improve the surface flatness of the second layer of solder resist and improve the product quality of the package substrate.
  • FIG. 7 is a structural view of the package substrate after development of one of the embodiments.
  • the package substrate subjected to development processing is subjected to a curing treatment.
  • the curing process of the package substrate is subjected to UV curing treatment, wherein the UV curing treatment is prior art, and the present invention will not be described herein.
  • the invention firstly forms a first solder resist layer formed by the first printing on the packaged product and forms a second printing
  • the second set of solder layers are separately exposed, and then the first layer of solder resist and the second layer of solder resist are simultaneously rinsed off by the developer, and the first layer of solder resist and the second layer are resisted.
  • the present invention reduces the number of development steps while reducing the curing step after the development step, in combination with the prior art method of rinsing the light-blocking solder resist layer with two developing solutions and curing the film separately.
  • FIG. 9 it is a comparison chart between the time used for manufacturing the step solder resist and the time used in the conventional method according to the embodiment of the present invention.
  • the conventional method requires 7.8 hours for the stepped solder resist package substrate, and the present invention requires only 4.6 hours.
  • the present invention greatly saves time compared to the prior art and greatly improves production efficiency.
  • the 50-70 ⁇ m in the same position edge of the second solder resist layer is also Exposure processing.
  • the first alignment exposure diagram and the second alignment exposure diagram of the package substrate are respectively indicated by an arrow pointing in the exposed area map, and no arrow in the unexposed area diagram, wherein The area of the first alignment exposure 21 and the area of the second alignment exposure 31 are exposed at the same position of the package substrate. Therefore, in this embodiment, the second exposure 31 area is larger than the first exposure 21 area.
  • FIG. 8 is an enlarged schematic view of FIG. 9 at A.
  • the first layer of the solder resist and the second layer of the solder resist are often reacted by the developer.
  • a slanted overdeveloping region, the width d of the overdeveloped region is also referred to as an overdeveloped value d.
  • the wider the overdeveloped value d the more severe the solder resist offset, indicating the poorer quality of the package substrate product.
  • the exposure energy control 280 ⁇ 320mj / cm 2 i.e., an exposure apparatus provided on energy 300mj / cm 2
  • the package substrate overdevelopment d value is small, this The quality of the package substrate is good.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

一种阶梯阻焊的封装产品制作方法，包括如下步骤，在封装基板上第一次印刷阻焊，对该封装基板上印刷的第一层阻焊进行第一次对位曝光；在第一次对位曝光的该封装基板上第二次印刷阻焊，对该封装基板上印刷的第二层阻焊进行第二次对位曝光；对第二次对位曝光的该封装基板进行显影处理；对显影处理的该封装基板进行固化处理。该制作方法先将封装产品上两次印刷的阻焊分别曝光，然后再用显影液冲洗掉被挡光的阻焊，并将两层阻焊固化处理，相对于用两次显影液冲洗掉被挡光的阻焊并分别固化的方法，减少了一次显影步骤，同时减少了显影步骤后的固化步骤，能节省时间，提高生产效率。

Description

一种阶梯阻焊的封装产品制作方法 技术领域
本发明涉及一种封装产品制作方法,尤其是涉及一种阶梯阻焊的封装产品制作方法。
背景技术
对于部分FC-CSP(Flip Chip-Chip Scale Package，倒装芯片规模封装)产品在封装过程中，需要在用于焊接芯片的基板周围通过贴阻焊、首次曝光、显影、固化、再次贴阻焊、再次曝光、显影、固化等工艺制作出阶梯状的凹凸结构。该方法制作的阶梯阻焊封装产品，第一次贴的第一层阻焊与第二次贴的第二层阻焊层之间存有杂物和气泡，第一层阻焊会出现断裂现象，阻焊层之间对位精度低，封装基板产品质量低。
发明内容
基于此，本发明在于克服现有技术的缺陷，提供一种能提高生产效率、提高产品质量的阶梯阻焊的封装产品制作方法。
其技术方案如下：一种阶梯阻焊的封装产品制作方法，包括如下步骤，在封装基板上第一次印刷阻焊，对所述封装基板上印刷的第一层阻焊进行第一次对位曝光；在第一次对位曝光的所述封装基板上第二次印刷阻焊，对所述封装基板上印刷的第二层阻焊进行第二次对位曝光；对第二次对位曝光的所述封装基板进行显影处理；对显影处理的所述封装基板进行固化处理。
下面对进一步技术方案进行说明：
优选的，在第一次印刷阻焊和/或在第二次印刷阻焊后均进行半固化处理。
优选的，所述第一次印刷为丝网印刷,所述第二次印刷为滚涂印刷。
优选的，所述丝网印刷所采用的网纱目数为100～200,丝网印刷速度为50～200mm/s，所述滚涂印刷所采用的目数为400～700，滚轮速度为1～3m/min。
优选的，所述丝网印刷所采用的网纱目数为120～180,丝网印刷速度为60～ 180mm/s，所述滚涂印刷所采用的目数为430～650，滚轮速度为1.4～2m/min。
优选的，所述对位曝光采用UVDI曝光，曝光能量为200～500mj/cm2。
优选的，所述曝光能量为220～400mj/cm2。
优选的，所述曝光能量为280～320mj/cm2。
优选的，所述第一阻焊层与所述第二阻焊层上同一位置需要开窗处理时，将所述第二阻焊层的该同一位置边缘内的50～70μm也曝光处理。
优选的，对固化处理的所述封装基板进行UV固化处理。
下面对前述技术方案的原理、效果等进行说明：
本发明是先将封装产品上两次印刷的阻焊分别曝光，然后再用显影液冲洗掉被挡光的阻焊，并将两层阻焊一起固化处理，相对于现有技术用两次显影液冲洗掉被挡光的阻焊并分别固化的方法，本发明减少了一次显影步骤，同时减少了显影步骤后的固化步骤。其次，可以避免第一次印刷固化引入的微尘杂质出现在两层阻焊层中，防止产生第一阻焊层与第二组焊层分层的品质现象，再次，贴完两层阻焊层后统一显影，可以避免分次显影后造成的第一阻焊层与第二阻焊层同一位置开窗边缘的过度显影量(undercut)不同，避免因过度显影量不同影响封装基板产品在芯片封装中的品质可靠性。因此，本发明能大大节省时间，提高生产效率，提高了封装基板产品的质量。
附图说明
图1是本发明实施例所述阶梯阻焊的封装产品制作方法流程图；
图2是本发明实施例准备印刷阻焊的封装产品；
图3是本发明实施例第一次印刷阻焊后的封装产品；
图4是本发明实施例对封装产品进行第一次对位曝光示意图；
图5是本发明实施例第二次印刷阻焊后的封装产品；
图6是本发明实施例对封装产品进行第二次对位曝光示意图；
图7是本发明实施例对封装产品进行显影处理后的结构示意图；
图8是图7在A处的放大结构示意图；
图9是本发明实施例制作阶梯阻焊所用的时间与传统方法所用时间对比图。
具体实施方式
下面对本发明的实施例进行详细说明：
如图1所示，它是本发明实施例所述阶梯阻焊的封装产品制作方法流程图，本发明所述一种阶梯阻焊的封装产品制作方法，包括如下步骤：
提供待印刷阻焊的封装基板，先对封装基板进行表面超粗化处理，通过超粗化处理能保证封装基板的铜面均匀性，提高封装基板的铜面与阻焊层之间的结合力。
然后在封装基板上第一次印刷阻焊，图3是第一次印刷阻焊后的其中一个实施例封装基板的结构示意图,如图3所示,第一次印刷阻焊后,在封装基板上形成了第一层阻焊20。在其中一个实施例中，第一次印刷阻焊后对封装基板进行半固化处理，即对封装基板表面上的阻焊层按照常规方法预烘处理。在其中一个实施例中，如图2所示，在封装基板上存在通孔21的情况下，本发明第一次印刷阻焊采用丝网印刷，在封装基板表面上印刷阻焊的同时能将封装基板上的通孔21装满阻焊。对所述封装基板上印刷的第一层阻焊进行第一次对位曝光，图4是其中一个实施例第一次对位曝光示意图。
接着，在第一次对位曝光的所述封装基板上第二次印刷阻焊，图5是第二次印刷阻焊后的其中一个实施例封装基板的结构示意图,图5上形成有第二层阻焊30,第二层阻焊30铺在第一层阻焊20上。在其中一个实施例中，第二次印刷阻焊后，对封装基板半固化处理。对所述封装基板上印刷的第二层阻焊进行第二次对位曝光，图6是其中一个实施例第二次对位曝光示意图。在其中一个实施例中，第二次印刷采用滚涂印刷，滚涂印刷方式能提高第二层阻焊的表面平整度，提高封装基板的产品质量。
接着，对第二次对位曝光的所述封装基板进行显影处理，图7是其中一个实施例显影后的封装基板结构意图。对显影处理的所述封装基板进行固化处理。对固化处理的所述封装基板进行UV固化处理,其中,UV固化处理为现有技术,本发明在此不再赘述。
本发明是先将封装产品上第一次印刷形成的第一阻焊层与第二次印刷形成 的第二组焊层分别进行曝光处理，然后再用显影液将第一层阻焊与第二层阻焊同时冲洗掉被挡光的阻焊，并将第一层阻焊与第二层阻焊一起固化处理，相对于现有技术用两次显影液冲洗掉被挡光的阻焊层并分别固化处理的方法，本发明减少了一次显影步骤，同时减少了显影步骤后的固化步骤。如图9所示，它是本发明实施例制作阶梯阻焊所用的时间与传统方法所用时间对比图，由图可知,从封装基板前处理到第一次印刷阻焊到最后的固化处理,制作出阶梯阻焊的封装基板，传统方法需要7.8小时,本发明只需要4.6小时。本发明相对于现有技术大大节省了时间，并大大提高了生产效率。
在其中一个实施例中，所述第一阻焊层与所述第二阻焊层上同一位置需要开窗处理时，将所述第二阻焊层的该同一位置边缘内的50～70μm也曝光处理。如图4和图6所示，分别是封装基板的第一次对位曝光示意图和第二次对位曝光示意图，曝光的区域图中用箭头指向表示，未曝光的区域图中无箭头，其中第一次对位曝光21的区域与第二次对位曝光31的区域是对该封装基板的同一个位置曝光，因此，本实施例中，第二次曝光31区域比第一次曝光21区域朝向挡光区域多50～70μm，这样第二层阻焊上未被曝光的区域在被显影液反应后形成的开窗，该开窗能够掩盖第一层阻焊未被曝光的区域被显影液显影时所产生的侧蚀量。
如图8所示，图8是图9在A处的放大示意图，本发明所述封装基板在显影处理后，第一层阻焊与第二层阻焊共同被显影液反应的地方往往会出现一个倾斜的过度显影区域,该过度显影区域的宽度d又称作为过度显影值d，该过度显影值d越宽，阻焊层偏移越严重，说明封装基板产品质量越差。
下表格为本发明编号1到编号20封装产品的工艺参数：
Figure PCTCN2015071189-appb-000001
Figure PCTCN2015071189-appb-000002
由上述20种封装基板产品的工艺参数可知，当将曝光能量控制在280～320mj/cm2(即在曝光设备上设置能量300mj/cm2)时，封装基板的过度显影值d较小，此时封装基板产品质量较好。
以上所述实施例仅表达了本发明的具体实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。

Claims (10)

  1. 一种阶梯阻焊的封装产品制作方法，其特征在于，包括如下步骤，
    在封装基板上第一次印刷阻焊，对所述封装基板上印刷的第一层阻焊进行第一次对位曝光；
    在第一次对位曝光的所述封装基板上第二次印刷阻焊，对所述封装基板上印刷的第二层阻焊进行第二次对位曝光；
    对第二次对位曝光的所述封装基板进行显影处理；
    对显影处理的所述封装基板进行固化处理。
  2. 根据权利要求1所述的封装产品制作方法，其特征在于，在第一次印刷阻焊和/或在第二次印刷阻焊后均进行半固化处理。
  3. 根据权利要求1所述的封装产品制作方法，其特征在于，所述第一次印刷为丝网印刷,所述第二次印刷为滚涂印刷。
  4. 根据权利要求3所述的封装产品制作方法，其特征在于，所述丝网印刷所采用的网纱目数为100～200,丝网印刷速度为50～200mm/s，所述滚涂印刷所采用的目数为400～700，滚轮速度为1～3m/min。
  5. 根据权利要求4所述的封装产品制作方法，其特征在于，所述丝网印刷所采用的网纱目数为120～180,丝网印刷速度为60～180mm/s，所述滚涂印刷所采用的目数为430～650，滚轮速度为1.4～2m/min。
  6. 根据权利要求1所述的封装产品制作方法，其特征在于，所述对位曝光采用UVDI曝光，曝光能量为200～500mj/cm2。
  7. 根据权利要求5所述的封装产品制作方法，其特征在于，所述曝光能量为220～400mj/cm2。
  8. 根据权利要求6所述的封装产品制作方法，其特征在于，所述曝光能量为280～320mj/cm2。
  9. 根据权利要求1所述的封装产品制作方法，其特征在于，所述第一阻焊层与所述第二阻焊层上同一位置需要开窗处理时，将所述第二阻焊层的该同一位置边缘内的50～70μm也曝光处理。
  10. 根据权利要求1所述的封装产品制作方法，其特征在于，对固化处理 的所述封装基板还包括进行UV固化处理。
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