TW503545B - An integrated circuit package substrate - Google Patents

An integrated circuit package substrate Download PDF

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Publication number
TW503545B
TW503545B TW90104966A TW90104966A TW503545B TW 503545 B TW503545 B TW 503545B TW 90104966 A TW90104966 A TW 90104966A TW 90104966 A TW90104966 A TW 90104966A TW 503545 B TW503545 B TW 503545B
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TW
Taiwan
Prior art keywords
integrated circuit
substrate
solder mask
package
thickness
Prior art date
Application number
TW90104966A
Other languages
Chinese (zh)
Inventor
Fang-Jeng Tsai
Juo-Liang Jung
Camille Lin
Teng-Yueh Tsai
Original Assignee
Chipmos Technologies Inc
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Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW90104966A priority Critical patent/TW503545B/en
Application granted granted Critical
Publication of TW503545B publication Critical patent/TW503545B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

An integrated circuit package substrate is disclosed. The substrate has an upper surface and a bottom surface. Two solder masks are formed on the attach-IC area of the upper surface for improving the water-resistance of the integrated circuit package.

Description

本發明係有關於一種 Μ 於—種在用以黏貼積體=粗毛路封裝基板，特別係有關 〔solder mask〕之藉辦路之區域具有雙層防焊膜 【先前技術】 电路封裝基板。 積體電路在結合至£卩私丨_ 結構，以保護該積體電 】：板之J係先組裝成-封裝 體電路封裝係為球格陣列封裝^ 一種 < 見以基板構裝之積 電路封裝截圖，」種果國專利第5,889, 655號之積體 電性傳輸與承載一積體電路$積體電路一封裝係以-基板50 體電路6。’該基板50之 ：二：:\裝f 63密封該積 53，以供導綠费从*表面51具有複數個弟一連接墊 塾53，並在基板5!:= '體電路6°之焊墊61與第-連接 導通之第二連接整54下=，有複數個與第-連接墊53 以作為該積體電 f弟一連接墊54上結合有焊球64， 5。與印刷電路板社C接點，為了能更有效防止基板 5。之下表導致短路：如第2圖所示，在基板 然而，僅管有一封梦一下防焊臈55及第二下防焊膜56， 用下，水氣仍可心Ϊ6/保護積體電路6〇，但在長時間使 表面ί板5°之Γ〔基板5〇上表面51與下 使積體電路6。：法:V=:eV導致黏著力失效， 壞。特別：目;ί 基板產生移動或裂縫而損 、 則積體電路封裝愈做愈小，如晶片尺寸封芽 503545 發明說明 〔Chip Scale Package〕，同樣地基板也愈來愈薄，其防 水性也變得較差，如何在不過度增加封裝成本下製造良好 防水性之小型積體電路封裝係極需解決之課題。 【發明目的及概要】 本發明之主要目的在於提供一種積體電路封裝基板， 利用基板本體上表面在用以黏貼積體電路之區域形 層防焊膜，以防止水氣侵入，增加積體電路封裝之防水 j本發明之積體電路封裝基板，其主要包含有： 有複ίΐΐ丄”一上表面與一下表面中上表面形成 . 接墊及至少一用以黏貼積體電路之區域， ί形成ΐ複數個與第一連接墊導通之第二連接墊； 口，μ ^ I:焊膜，形成於本體之下表面並具有複數個開 出至少部份第二連接墊之外表面； 口，以裸於t體之上表面並具有複數個開 第一爲至^#伤第一連接墊之外表面；及 用以黏位於本體之上表面並至少覆蓋上述 領蒞冤路之區域。 【舍明详細說明】 w月多*閱所紛 依太菸ΒΒ 、圖式’本發明將列舉以下之實施例說明： 實施例之積體^粗路封裝基板，第5圖係為第一具體 例之積體電路封封裝基板’第3至5圖係為第一具體實施 具體實施例之浐f基板之製造過程，第6至8圖係為由第一 只肢電路封裝基板形成一積體電路封裝之過The present invention relates to a substrate having a double-layer solder mask in an area for borrowing a circuit of a [solder mask], particularly a circuit packaging substrate. The integrated circuit is being integrated into the structure of the private circuit to protect the integrated circuit.]: The J series of the board is first assembled-the package circuit package is a ball grid array package. ^ A < A screenshot of the circuit package, "the integrated electrical transmission of the No. 5,889, 655 seeds and a integrated circuit $ Integrated circuit-a package is-substrate 50 body circuit6. 'The substrate 50: 2 :: \ install f 63 seals the product 53 for the green guide fee from the * surface 51 has a plurality of younger one connection pads 塾 53, and on the substrate 5!: =' Body circuit 6 ° The second connection between the bonding pad 61 and the first connection is 54. There are a plurality of connection pads 53 connected to the first connection pad 53 as the integrated circuit. The connection pads 54 have solder balls 64, 5. The contact with the printed circuit board company C is to prevent the substrate 5 more effectively. The following table causes a short circuit: As shown in Figure 2, on the substrate, however, there is only one dream solder mask 55 and the second lower solder mask 56. With use, water and gas can still be used. 6 / Protective integrated circuit 6〇, but for a long time to make the surface of the plate 5 ° Γ [the upper surface 51 of the substrate 50 and the lower surface of the integrated circuit 6. : Method: V =: eV causes the adhesive force to fail, bad. Special: mesh; ί The substrate is moved or cracked and damaged, the integrated circuit package becomes smaller and smaller, such as chip size package 503545 Description of the invention [Chip Scale Package], the substrate is also getting thinner and thinner, and its water resistance is also It becomes worse. How to make a small integrated circuit package with good water resistance without excessively increasing the packaging cost is a problem that needs to be solved. [Objective and Summary of the Invention] The main object of the present invention is to provide a package circuit package substrate, which uses a top surface of the substrate body to form a layer of solder mask on the area for bonding the package circuit to prevent water vapor from invading and increase the package circuit. Package waterproofing The integrated circuit packaging substrate of the present invention mainly includes: a complex upper surface and a lower surface formed on the upper surface. The pads and at least one area for adhering the integrated circuit are formed. ΐ a plurality of second connection pads which are in communication with the first connection pad; mouth, μ ^ I: solder film formed on the lower surface of the body and having a plurality of outer surfaces which open at least part of the second connection pad; It is naked on the upper surface of the body and has a plurality of outer surfaces of the first connection pads that are open to the first wound; and is used to adhere to the upper surface of the body and at least cover the above-mentioned areas of injustice. Detailed description] 月 月 多 * 读 所 依 太 烟 ΒΒ, scheme 'The present invention will enumerate the following examples: The integration of the embodiment ^ rough road package substrate, Figure 5 is the first specific example Integrated circuit package base 'On line 3-5 of FIG Chan manufacturing process f of the substrate of the first embodiment DETAILED DESCRIPTION DETAILED embodiment, based on FIGS. 6 to 8 only by a first leg of an integrated circuit package substrate is formed through the circuit package

503545 五、發明說明（3) 程。 =一具體實施例之積體電路封裝基板之製造過程 中，如弟3圖所示，首先一基板本體1〇具有一上表面 一下表面12，該基板本體10係為一種由雙層或多層玻璃纖 維強化裱乳樹脂〔glass fabric reinf〇rced ep〇xy resin〕屢合形成之印刷電路板，如βτ樹脂 二 Bismaleiniide Triazine resin〕、FR_“1FR_5 樹脂等 等，在本體10之上表面11形成有複數個第一金屬墊13 〔contact pad〕以及至少一用以黏貼積體電路之區域 18，亚在本體1〇之下表面12形成有複數個第二金屬墊η， 其中第一金屬墊1 3係與對應之第二金屬墊14相互電性導 通，而該用以黏貼積體電路之區域18係預留作為黏貼固定 積體電路20。 之後，如第4圖所示，第一次形成防焊膜〔f〇rming solder mask〕，其係將一種液態可照相顯影之墨水 〔1 iquid phtoimageable ink〕，如具有Si〇2 及BaS04 等 填充劑之環氧丙烯酸樹脂〔ep〇Xy-acry 1丨c res i η〕，網 版印刷於本體10之上表面“與下表面12，通常每次網版印 刷之厚度約在2 〇〜5 0 // m，在烘烤固化後，針對第一金屬墊 1 3與第二金屬墊1 4部位敍刻形成開口，而形成如第4圖所 示之第一上防焊膜16於本體1〇之上表面11，以及_層下防 焊膜15於本體1〇之下表面15。 接著，如第5圖所示，第二次形成防悍膜〔f〇rming s〇lder mask〕，其係在本體10之上表面丨丨上形成有一第503545 V. Description of Invention (3) Process. = In the manufacturing process of the integrated circuit package substrate of a specific embodiment, as shown in Figure 3, a substrate body 10 has an upper surface and a lower surface 12, and the substrate body 10 is a kind of double-layer or multi-layer glass. Fiber-reinforced epoxy resin (glass fabric reinf rced ep〇xy resin) printed circuit boards formed repeatedly, such as βτ resin bis Bisaleiniide Triazine resin], FR_ "1FR_5 resin, etc., a plurality is formed on the top surface 11 of the body 10 First metal pads 13 (contact pads) and at least one region 18 for attaching integrated circuit, a plurality of second metal pads η are formed on the surface 12 below the body 10, wherein the first metal pads 13 are It is electrically connected with the corresponding second metal pad 14, and the area 18 for pasting the integrated circuit is reserved as the pasting and fixing integrated circuit 20. Then, as shown in FIG. 4, a solder mask is formed for the first time. Film [f〇rming solder mask], which is a liquid photographic developable ink [1 iquid phtoimageable ink], such as epoxy acrylic resin with fillers such as Si〇2 and BaS04 [ep〇Xy-acry 1 丨 c res i η], screen printing on the upper surface of the body 10 and the lower surface 12, usually the thickness of each screen printing is about 2 0 ~ 5 0 // m, after the baking and curing, the first metal pad 1 3 and the second metal pad 14 form openings, and a first upper solder mask 16 as shown in FIG. 4 is formed on the upper surface 11 of the body 10, and a lower solder mask 15 is formed on the body 1 〇 下 表面 15。 15 below the surface. Next, as shown in FIG. 5, a fouling mask [f0rming solder mask] is formed for the second time, which is formed on the upper surface 丨 丨 of the body 10

第6頁 五、發明說明（4) 焊膜17於本體10之上表面11，第二上防焊膜17係至 盍上述用以黏貼積體電路之區域18，而成為如第5圖 所=之積體電路封裝基板，因此，本體10之上表面〗丨在用 =^貼積體電路之區域丨8之防焊膜厚度〔即第一防焊膜1 6 加第,防焊膜17之總合厚度〕係大於在本體1〇下表面12之 下=焊膜1 5厚度，較佳地，第一防焊膜丨6與第二防焊膜】7 合厚度係在3〇]〇〇"m之間，更佳為在4〇，"之 間，=提供一高品質之積體電路封裝。 …當上述之積體電路封裝基板運用於BGA封裝時，可先 經過-黏晶過程，以得到一如第6圖所示之組合構造，直 隨ί !dc 係將一積體電路20係以如銀膠之黏著劑22黏固於上述用以 ίΐ積體電路之區域18，其中該積體電路2〇係具有複數個 之後，在經過打線〔wire-bonding〕盥封膠 〔㈣l—ding〕之過程後，得到一如第7圖之組合構造f其包 含有複數個導線23及-封裝體24，其中該導線23係内部電 性連接積體電路2G之焊墊21與對應之第—連接墊13，而該 封裝體24係密封導線23及積體電路2()，最後，在經過植球 〔Planting〕與切割〔dicing〕後，得到一呈bga型態 二Ball Grid Array，球格陣列〕之積體電路封裝，其本 體下表面12之第二連接墊14係結合有焊球託〔s〇ider ball〕。 -士在第9一圖中’係為習知之積體電路封裝在未封裝前隨 =時間進打PCT試驗而得到—測試曲線3G，以檢測晶片與 土板剪向結合強度〔dle shear strength〕之變化，發現Page 6 V. Description of the invention (4) The solder film 17 is on the upper surface 11 of the body 10, and the second upper solder mask 17 is connected to the above-mentioned area 18 for attaching the integrated circuit, and becomes as shown in FIG. 5 = The integrated circuit package substrate, therefore, the upper surface of the body 10 丨 丨 the area where the integrated circuit is used 丨 8 thickness of the solder mask [that is, the first solder mask 16 plus the first, the solder mask 17 The total thickness] is greater than the thickness of the lower surface 12 of the body 10 = the thickness of the solder film 15, preferably, the first solder mask 6 and the second solder mask] 7 The thickness is 30 mm. " m, more preferably between 40, ", to provide a high-quality integrated circuit package. … When the above-mentioned integrated circuit package substrate is applied to a BGA package, it may first go through a -sticking process to obtain a combined structure as shown in FIG. 6, and directly follow a! Dc system to connect an integrated circuit 20 to For example, the adhesive 22 of silver glue is fixed on the area 18 for the integrated circuit described above. The integrated circuit 20 has a plurality of integrated circuits, and then passes through wire-bonding and potting glue [胶 l-ding]. After the process, a combined structure f as shown in FIG. 7 is obtained, which includes a plurality of wires 23 and -package 24, wherein the wires 23 are internally electrically connected to the pad 21 of the integrated circuit 2G and the corresponding first connection Pad 13, and the package 24 is the sealed wire 23 and the integrated circuit 2 (). Finally, after the ball planting and dicing, a ball grid array of bga type is obtained. In the integrated circuit package, the second connection pad 14 of the lower surface 12 of the body is combined with a solder ball holder [soeder ball]. -The figure in Figure 9 'is for the conventional integrated circuit package. It is obtained by entering the PCT test with = time before unpacking. The test curve is 3G to detect the shear strength of the chip and the soil plate. Changes, found

第7頁 五、發明說明（5)Page 7 V. Description of Invention (5)

Ik著忒驗¥間之增加約在7 2小時後在積體電路與基板之間 著劑，如銀膠，產生水解而失去黏性，顯然黏著劑係 易梃水，分解失效，所謂的「pcT」係為pressure c〇〇ked est之間稱，即壓力蒸煮試驗，其條件為攝氏12丨。〇、兩 =氣壓、相對濕度100%及168小時，同樣地，將本發明上 =之積體電路封裝與習知之積體電路封裝進行pcT試驗比 日ί二i it，明，積體電路封裝在嚴格之高壓高溫高水氣長 ^ M g時〕试驗後，利用超音波掃瞄發現積體電路 盥第二^ Γ 口於基板1 〇，是以了解係因為第一上防焊膜16 方焊膜17之存在，㈣不易侵入至黏著劑22 , I:體= = =試驗後以超 基板侵人至黏H ^㉟，其係因水氣已由 法固定在其p社導黏劑水解〔hydrolysis〕，無 縫形成不^。之貝體電路，導致積體電路滑動並產生裂 外，^ t ^ 電路封裝基板除了適用於BGA封裝之 格陣列封裝〕，如第1〇m^ GridArray packMe，面 實施例之積體電路封裝：：第係：依本發明之第二具體 係以相同圖號表示，該#㈣具體實施例相同之構件 第二連接塾14雷获^ μ積體包路封裝係在本體下表面12之 焊接之導電金屬Ί:!二層4〇，如鎳、銦、金等易於 電路封裝在第-防焊m I封裝結構，此外，該積體 述用以黏貼積體電路之 5第;'上防焊膜17除了覆蓋上 ^域18 ’更與第一防焊膜16覆蓋相 第8頁 同之區域並裸露出在上 樣使得基板10在黏貼有表面1 1之複數個第一連接墊13 防焊膜厚度，以提昇颉^體電路20之上表面丨〗具有 : 結t於高品質之電子袭：體電路封裝之防水性，特別適Ϊ 話或如工程用防水性之迷你 故本發明之保瓊 电 =準，任何熟c後附之申請專利範圍所界定 乾圍内所作之任何變化與在不脫離本發明之精神和 圍。 ’改’均屬於本發明之保護範 圖式簡單說明 【圖式說明 第1 圖： 第2 圖： 第3 _ · 第4 Γ5Ε1 · 圃· 第5 圖： 第6 圖： 第7 圖： 第8 圖： 第9 圖· 第1 0圖： 在基板上表面黏 在基板上表面進 一BGA封裝之截 美國專利第5, 889, 655號之積體電路封裝截面 圖； 在美國專利第5,889,655號之積體電路封裝中， 其結合有一焊球之基板局部放大截面示意圖； 依本發明之積體電路封裝基板，一基板本體之截 面示意圖； 依本發明之積體電路封裝基板，一基板本體之上 下表面分別形成有第一層上防焊膜及一層下防焊 膜之截面示意圖； 依本發明之積體電路封裝基板，一基板本體之上 表面形成有第二層上防焊膜，而構成本發明之封 裝基板之截面示意圖； I#發明之積體電路封裝基板 貝占有一積體電路之截面示意圖 &本發明之積體電路封裝基板 #打、線與封膠後之截面示意圖 I本發明之積體電路封裝基板 面示意圖； 在pct試驗下，習知之積體電路封裝在未封壯i 隨著時間進行對其晶片剪向結合強度之 '衣前 表；及 I化圖 I本發明之積體電路封裝基板 面示意圖。 讓 LGA封装之截Ik said that the increase between ¥ and about 7 2 hours later, the agent between the integrated circuit and the substrate, such as silver glue, hydrolyzes and loses its viscosity. Obviously, the adhesive is easily water-soluble and decomposes. The so-called " "pcT" is a pressure cooker, which is a pressure cooking test, and its condition is 12 ° C. 〇, two = air pressure, relative humidity 100%, and 168 hours. Similarly, the integrated circuit package of the present invention and the conventional integrated circuit package are subjected to a pcT test. It is clear that integrated circuit packaging After rigorous high pressure, high temperature, high water vapor length ^ Mg] test, ultrasonic scanning was used to find the integrated circuit's second ^ Γ port on the substrate 1 〇, to understand the reason because the first solder mask 16 The existence of the square solder film 17 makes it difficult to penetrate into the adhesive 22, I: body = = = after the test, the invasion of the substrate with the super substrate to the adhesive H ^ ㉟, because it has been fixed to its p-guide adhesive by water and gas. Hydrolysis [hydrolysis], seamless formation is not ^. In addition to the fact that the integrated circuit slides and cracks, the ^ t ^ circuit package substrate is applicable to the grid array package of the BGA package], such as 10m ^ GridArray packMe, the integrated circuit package of the embodiment: : Series: According to the second embodiment of the present invention, the same drawing number is used. The second component of the same embodiment is the same. The second connection is obtained by 14 ^ μ integrated package package. It is welded on the lower surface 12 of the body. Conductive metal Ί :! Two layers of 40, such as nickel, indium, gold, etc., are easy to package in the first solder-proof ML package structure. In addition, the integrated circuit is used to attach the fifth circuit of the integrated circuit; In addition to covering the upper region 18, the film 17 covers the same area as the first solder mask 16 on the eighth page and is exposed on the sample so that the substrate 10 is adhered to the plurality of first connection pads 13 on the surface 11. The thickness of the film to improve the upper surface of the body circuit 20 has the following characteristics: high-quality electronic attack: the waterproofness of the body circuit package is particularly suitable, or a mini such as engineering waterproofing Qiongdian = Just, made within the scope of the patent application as defined in the appended patent application Any change without departing from the spirit of the invention and around. 'Modification' is a brief description of the protection paradigm of the present invention. [Schematic illustration 1st figure: 2nd figure: 3rd _ · 4th Γ5E1 · garden · 5th figure: 6th figure: 7th figure: 8th Figure: Figure 9 · Figure 10: A cross-sectional view of the integrated circuit package of US Patent No. 5,889, 655 with a BGA package adhered to the upper surface of the substrate; the product of US Patent No. 5,889,655 In a bulk circuit package, a partially enlarged cross-sectional view of a substrate incorporating a solder ball is shown; a cross-sectional schematic view of a integrated circuit package substrate according to the present invention, a substrate body; and a top and bottom surface of a integrated circuit package substrate according to the present invention A cross-sectional schematic diagram of a first upper solder mask and a lower solder mask is formed respectively; according to the integrated circuit packaging substrate of the present invention, a second layer of upper solder mask is formed on the upper surface of a substrate body to constitute the present invention. Schematic cross-section of the package substrate; I # invention of the integrated circuit package substrate occupies a cross-section of the integrated circuit & the integrated circuit package substrate of the present invention # after cutting, wiring and sealing Schematic diagram I Schematic diagram of the integrated circuit package substrate of the present invention; Under the pct test, the conventional integrated circuit package is unsealed i. The "clothing table" of the shear bond strength of its wafers over time; and FIG. 1 is a schematic diagram of the integrated circuit package substrate of the present invention. Let the LGA package cut

第10頁 503545Page 10 503545

_ 圖式簡單說明 [ 圖號 說 明 ] 10 基 板 本 體 11 上 表 面 12 下 表 面 13 第一 連 接 塾 14 第 二 連 接墊 15 下 防 焊膜 16 第一 上 防 焊 膜 17 第 二 上 防焊 m is 用 以 黏貼積體 電路 之區域 20 積 體 電 路 21 焊 墊 22 黏 著 劑 23 導線 24 封 裝 體 25 焊 球 30 習 知 之 積體 電路封 裝之試驗曲線 40 電 鍍 層 50 基 板 本 體 51 上 表 面 52 下 表 面 53 第一 連 接 墊 54 第 二 連 接墊 55 第 一 下防焊膜 56 第二 下 防 焊 膜 60 積 體 電 路 61 焊 墊 62 導 線 63 封裝 體 64 焊 球_ Brief description of drawings [Illustration of drawing number] 10 Base body 11 Upper surface 12 Lower surface 13 First connection 塾 14 Second connection pad 15 Lower solder mask 16 First upper solder mask 17 Second upper solder mask Areas of integrated circuit 20 Integrated circuit 21 Welding pad 22 Adhesive 23 Lead 24 Package 25 Solder ball 30 Test curve of conventional integrated circuit package 40 Plating layer 50 Substrate body 51 Upper surface 52 Lower surface 53 First Connection pad 54 Second connection pad 55 First lower solder mask 56 Second lower solder mask 60 Integrated circuit 61 Solder pad 62 Wire 63 Package 64 Solder ball

第11頁Page 11

Claims (1)

月 曰 六、申請專利範圍 膜； 一積體電路，社人於兮1 一封驶μ …口於该基板之上表面；及 ，密封該積體電路； 域 ,、特徵在於，該基板之上 ，其形成有至少一第-上 ^、，'°s有積體電路之區 广上防焊膜厚度下板上 度。 _ <下防焊膜厚 6、如申請專利範圍第5項所述之積 該些上防焊膜之厚度係在3〇〜i〇〇#ra之間封4，其中該 士申明專利範圍第5項戶斤述 些上防焊膜之厚度係在4"M二路封装，其中該June 6th, the patent application scope film; an integrated circuit, the company Yu Xi 1 driving μ… mouth on the upper surface of the substrate; and, sealing the integrated circuit; domain, is characterized in that on the substrate It is formed with at least a first upper surface, and a lower surface area of the solder mask thickness in the area with integrated circuits. _ < Thick solder mask thickness 6, as described in item 5 of the scope of patent application, the thickness of these upper solder masks is sealed between 30 ～ i〇〇 # ra, where the patent claims the patent scope Item 5 describes the thickness of the solder mask on the 4 " M two-way package, where the 8人3申°月專利範圍第5項所述之積體電路封f，其另勹 含有複數個導線，連接基板之第 1 =包 甲明專利範圍第5項所述之積體電路封 含有複數個焊球，結合於基板之第二連接塾 U其另包 10、 一種積體電路封裝基板之製造方法，包含·· 提供一基板本體，其中該基板本體具有一上表面與 一下表面，該上表面形成有複數個第_連接墊及至少 一用以黏貼積體電路之區域，而下表面形成有複數個 與第一連接墊導通之第二連接墊； 第一次形成一防焊膜於基板本體之上表面及下表 面；及 第二次形成一防焊膜於基板本體之上表面。 11、 如申請專利範圍第丨〇項所述之積體電路封裝基板之8 people apply for the integrated circuit package f described in item 5 of the patent scope of the month, which additionally contains a plurality of wires, and the connection substrate 1 = Bao Jiaming includes the integrated circuit package described in item 5 of the patent scope. A plurality of solder balls, which are combined with the second connection of the substrate, and include an additional package 10. A method for manufacturing an integrated circuit package substrate, including providing a substrate body, wherein the substrate body has an upper surface and a lower surface, the A plurality of _ connection pads and at least one area for attaching the integrated circuit are formed on the upper surface, and a plurality of second connection pads which are in communication with the first connection pad are formed on the lower surface; a solder resist film is formed for the first time An upper surface and a lower surface of the substrate body; and a second time forming a solder mask on the upper surface of the substrate body. 11, as described in the scope of the patent application of the integrated circuit package substrate 2002. 04. 08.013 第13頁2002. 04. 08.013 p. 13 製造方法，其中第一 A 成之防焊臈均至少^ =所形成之防焊膜與第一次所形 體電路之區域，=覆蓋基板本體上表面之用以黏貼積 部位之防焊骐厚户在上述區域之防焊膜厚度大於其它Manufacturing method, in which the solder mask of the first A is at least ^ = the area of the solder mask formed and the circuit of the first shaped body, = the solder mask that covers the upper surface of the substrate body and is used to adhere the deposition part. Thickness of solder mask in the above area is greater than other 12、一種積體電路 一太辨 a 3 了展基板，其包含有： 本體，具有_ u * ^ ^ ^ - ^ 上表面與一下表面，其中上表面形 成有複數個第一 i*. u T· ^ ^ 思幾塾及至少一用以黏貼積體電路之 區域，而下砉而游1 衣曲形成有後數個與第一連接墊導通之第 二連接墊； 一下防焊膜’形成於本體之下表面並裸露出至少部 份第二連接墊之外表面；及 一上防焊膜，形成於本體之上表面並裸露出至少部 份第一連接墊之外表面，其中該上防焊膜之厚度係在 3 0〜1 0 0 /z m之間，以使其大於該下防焊膜之厚度，以增 進防水性。 912. An integrated circuit, a polarimeter a3, has a display substrate, which includes: a body with _ u * ^ ^ ^-^ upper surface and lower surface, wherein the upper surface is formed with a plurality of first i *. U T · ^ ^ 塾 塾 至少 and at least one area for attaching the integrated circuit, and the lower part of the body 1 is formed with a plurality of second connection pads which are in communication with the first connection pads; the lower solder mask is formed on A lower surface of the main body and exposing at least part of the outer surface of the second connection pad; and an upper solder mask formed on the upper surface of the main body and exposing at least part of the outer surface of the first connection pad, wherein the upper solder resist The thickness of the film is between 30 and 100 / zm, so that it is larger than the thickness of the lower solder mask to improve the water resistance. 9 第14頁 2002. 04. 08. 014Page 14 2002. 04. 08. 014
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015110003A1 (en) * 2014-01-24 2015-07-30 广州兴森快捷电路科技有限公司 Manufacturing method for ladder solder mask package product

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015110003A1 (en) * 2014-01-24 2015-07-30 广州兴森快捷电路科技有限公司 Manufacturing method for ladder solder mask package product

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