KR19990069439A - Stack chip package - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a stack chip package configured by stacking two chips using a tab tape and solder balls. The present invention includes at least two semiconductor chips stacked to face each other; A tab tape having a metal line connected to a bond pad of a first chip of the two semiconductor chips and attached to an upper surface of the first chip, the other end of which is protruded out of the chip and connected to a substrate; A conductive member for electrically connecting the tab tape attached to the first chip and the bond pads of the second chip positioned thereon; An insulating spacer having a rectangular frame shape interposed between edges of the adhesive part of the first chip and the second chip to isolate the inside and the outside of the chip; And an adhesive member interposed between the insulating spacer and the second chip to attach and support the second chip. The stack chip package according to the present invention can increase the memory capacity while improving the appearance (small size and light weight) and can improve the electrical characteristics and reliability. It can also be manufactured in a simple process and can implement high pin contact packages.

Description

Stack chip package

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a stack chip package configured by stacking two chips using tab tape and solder balls.

In the related art, a stacked semiconductor package having a structure in which two semiconductor chips are stacked and packaged, or two packages are stacked, and a mounting area of a printed circuit board is reduced while its capacity is doubled is known. If described with reference to:

As shown, the conventional stacked semiconductor package has a structure in which two packages 1 and 2 are stacked up and down, and the two stacked semiconductor packages 1 and 2 are each tab tape ( 3) 3 'is electrically connected, so that the signal generated from the upper and lower chips 4 and 4' is transmitted through one line, i.e., the tap tape 3 'of the lower package 2 It is supposed to be delivered.

However, the general stacked semiconductor package as described above is manufactured by bonding two side surfaces of the package as shown in FIG. 1, and the number of steps is increased because the guide 5 is connected to the side surface of the package. In addition, the use of TSOP or other packages not only has a large package itself, but also has a large mounting area on the substrate, which hinders miniaturization and thinning of the product.

In addition, the conventional stacked semiconductor package has problems in reliability, such as solder joint cracks occurring at connection sites between packages, and also has a disadvantage in that signal transmission is delayed due to a long electrical signal transmission path by using the existing package.

In addition, the conventional stacked semiconductor package has a problem in the process of heat dissipation by having a separate heat sink for heat dissipation by showing a problem in heat dissipation.

The present invention has been made in order to solve the above problems, by stacking the two bare chips through the solder ball as a medium and electrically connected to the stack chip in a simpler, thinner and excellent electrical characteristics in a simpler process An object is to provide a package and a method of manufacturing the same.

1 is a cross-sectional view showing an example of a conventional stack chip package.

2 to 5 are cross-sectional views showing the structure and manufacturing process of the stack chip package according to the present invention.

6a and 6b are a cross-sectional view and a plan view showing the structure of an insulating circuit film used in the package of the present invention.

7a and 7b are a perspective view and a cross-sectional view showing the structure of the spacer used in the package of the present invention.

Fig. 7C is a detailed view of the main portion showing the bonding state of the spacer and the chip.

8A and 8B are diagrams illustrating a first embodiment of interconnection of upper and lower chips.

9A and 9B are diagrams illustrating a second embodiment of interconnection of upper and lower chips.

10 is a third embodiment of the interconnection of the upper and lower chips.

11A and 11B illustrate a fourth embodiment of the interconnection of upper and lower chips.

12 is a detailed view showing a structure for preventing oxidation of solder balls during chip interconnection in a package according to the present invention.

13 is a cross-sectional view showing the structure of a chip stack package according to another embodiment of the present invention.

14 is a cross-sectional view showing the structure of a chip stack package according to another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10,10 '; Semiconductor chip 20,60; Tap tape

21; metal lines 22,22 '; adhesive layer

Solder ball 31; hot solder bumps

32; low temperature solder ball 33; high temperature solder ball

34; anisotropic conductor 35; micro spring

36; powder bump 40, 70, 100; insulation spacer

50; adhesive glass 80,130; encapsulant

101; power line pattern 101a; empty hole

102; ground plan 110; external connection lead

The stack chip package for achieving the object of the present invention as described above comprises at least two semiconductor chips are arranged so that the upper surface facing each other; A tab tape having a metal line connected to a bond pad of a first chip of the two semiconductor chips and attached to an upper surface of the first chip, the other end of which is protruded out of the chip and connected to a substrate; A conductive member for electrically connecting the tab tape attached to the first chip and the bond pads of the second chip positioned thereon; An insulating spacer having a rectangular frame shape interposed between edges of the adhesive part of the first chip and the second chip to isolate the inside and the outside of the chip; And an adhesive member interposed between the insulating spacer and the second chip to attach and support the second chip.

In the stack chip package according to the present invention, the tab tape is adhered to one of two semiconductor chips, that is, the upper surface of the first chip, which is disposed so that the top surfaces thereof face each other, and the metal line of the tab tape is chip pads. Connecting to; Bonding an insulating spacer having a rectangular frame shape to an outermost surface of the chip on an upper surface of the tab tape; Forming solder balls on electrically conductive portions of the tab tape, respectively; And placing the second chip on the structure of the step to electrically connect with the solder ball.

Such a stack chip package according to the present invention can be obtained by stacking bare chips to obtain a package having a large capacity while reducing the appearance.

Furthermore, the present invention can reduce solder joint crack defects and the like during interconnection, eliminate warpage defects, and expose the back side of the chip to improve heat dissipation characteristics.

In addition, the present invention can realize a high reliability stack chip package with high reliability in a simpler process using existing equipment and materials without reinvestment of new materials or equipment, and high pin contact by using tap tape and solder balls. The package is easy to implement.

Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

2 to 5 are views showing the structure and manufacturing process of the stack chip package according to the present invention, wherein 10 and 10 'are the first chip and the second chip, 20 is the tab tape, and 30 is the drawing. Solder ball, 40 is an insulating spacer, 50 is adhesive glass.

As illustrated, the first chip 10 and the second chip 10 ′ are stacked to face each other so as to face an upper surface thereof, that is, a surface on which a bond pad is formed. Tab tape 20 is attached to an upper surface of the first chip 10. One end of the tab tape 20 is electrically connected to the pad of the first chip 10, and the other end thereof is protruded to the outside of the chip so as to be connected to the substrate. Such a tap tape 20 may be replaced by a conventional lead frame.

In addition, the first pad 10 and the second chip 10 ′ are electrically connected to the same pad by a plurality of solder balls 30 interposed therebetween. The rectangular spacer spacer 40 is positioned to isolate the inside and outside of the chip. The insulating spacer 40 is again attached to and supported by the second chip 10 ′ by the adhesive glass 50.

Hereinafter, the structure of the present invention will be described in more detail.

The chip pad is formed in a rectangular shape having a size of at least 15 × 15 μm and at most 500 × 500 μm to enable double bonding, but is not shown in the drawings.

As shown in FIGS. 6A and 6B, the tab tape 20 has an adhesive layer 22 for attaching and supporting the chip 10 and the insulating spacer 40 on both sides thereof with an intermediate metal line 21 therebetween. 22 'is formed, and one end of the metal line portion is opened to be connected to the chip pad by thermocompression bonding or super sonic compression.

Here, the metal line 21 may be composed of Cu, Ni, Au, and may also be composed of Cu, Ni, Cr, Au, or Cu, Ni, Co, Au. Cu, Ni, Au, Tin; It may be composed of Cu, Ni, Cr, Au, Tin and Cu, Ni, Co, Au, Tin, and the like, but may not be limited to materials such as may be composed of other similar metal lines.

In addition, the adhesive layers 22 and 22 ′ may be made of an epoxy-related thermoplastic resin, adhesive glass, and a polymer-based insulating adhesive tape. In the case of an adhesive tape, the thickness is preferably at least 10 µm and at most 100 µm. And the thickness of the metal line located inside the adhesive layer is preferably formed within at least 1MIL to 4MIL.

Meanwhile, a rectangular metal electrode may be formed on one surface of the tab tape 20 to facilitate electrical connection, and in addition, a metal bump may be formed on the metal electrode. In addition, a via hole may be formed by electrically connecting the metal electrode of the tab tape 20 with the pads of the first chip 10 and the second chip 10 ′. Herein, the metal electrode is formed to have a size of at least 15 × 15 μm and at most 500 × 500 μm, and the size of the via hole is preferably about 2 MIL to 6 MIL. Although the drawings of these metal electrodes, metal bumps, and via holes are omitted in the drawings, those skilled in the art will be able to implement them.

In addition, as described above, the insulating spacer 40 is positioned at an edge between the stacked first chip 10 and the second chip 10 'to isolate the inside and the outside of the chip, and thus, FIGS. 7A and 7B. And 7c, which has a rectangular frame shape, and is formed to be inclined downward from the outside of the upper surface so that the adhesive glass 50 applied to attach the upper second chip 10 'slips into the chip. It does not leak out outside. In addition, the insulating spacer 40 may be formed of an oxide series such as aluminum oxide, silicon oxide, BeO, or the like, and may be formed of a nitride series such as aluminum nitride, titanium nitride, silicon nitride, or BN. It may also be formed of carbide-based aluminum carbide, titanium carbide, silicon carbide, diamond or glass ceramic.

The solder ball 30 is a conductive member for electrically connecting the tab tape 20 connected to the pad of the first chip 10 and the pad of the second chip 10 'positioned at the upper portion thereof. There are many other than solder balls. Some examples are shown in FIGS. 8 to 11.

8A and 8B show the interconnection using the solder balls 30, and it can be seen that the pads of the first chip 10 and the second chip 10 ′ are connected by the solder balls 30. In such a structure, when the first chip and the second chip are mechanically bonded through the solder balls and then reflowed, the chip pads are connected while forming a wide solder bridge up and down.

9A and 9B show another example of interconnection, which forms gold bumps or silver bumps or aluminum bumps or high temperature solder bumps 31 on the second chip 10 'and the first chip 10 and tabs. Low temperature solder balls 32 or solder paste are formed on the electrodes of the tape 20 and connected to each other. After mechanically bonding the high temperature solder bumps 31 and the low temperature solder balls 32 as described above, after the reflow process, the low temperature solder balls are melted and connected to the high temperature solder bumps.

FIG. 10 shows another example of interconnection, which forms a gold or hot solder ball 33 on a pad of a second chip 10 'and attaches an anisotropic conductor 34 to a connection including the same. The filling is such that the electrical conduction between chips is achieved. Here, the anisotropic conductor 34 is a resin containing particles for electrical conduction, epoxy, modified epoxy resin, polyester, modified polymer, acrylic ester, modified ester, silicone resin, phenoxy resin, polyurethane , Polysulfide, cyanocryretz, polylexin or other polymers cured by thermocompression. The particles may be formed in almost any shape such as spherical, square, triangular, hexahedral, square pyramid or triangular pyramid having a size of 3 μm to 20 μm. In addition, the particles have a polymer inside and a metal is coated on the outside. The metal consists of silver, gold, nickel, indium, tin or indium tin oxide.

11A and 11B show yet another embodiment of interconnection, which incorporates a micro spring 35 into the solder balls 30 and solder paste to better maintain inter-chip interconnections. Although not shown, the same effect can be obtained by using a C-ring instead of a micro spring.

On the other hand, one of the most problematic in the interconnection of the chip as described above is that the electrical characteristics of the conductivity decrease due to the oxidation of the solder ball is reduced. This is caused by rapidly forming an oxide film on the surface by exposing the solder ball to external oxygen in the reflow process of the solder ball. To solve this, a technique as shown in FIG. 12 may be used.

That is, during the reflow of the solder balls, the metal line 21a of a predetermined portion of the tab tape 20 entering the inside of the chip, which does not affect the interconnection, is exposed to the powder bumps of oxygen and moisture reactive materials on the portions. 36), the second chip is mounted, and then heated to the metal line 21 where the bumps 36 are formed externally before the reflow or reflow process so as to react with oxygen and moisture therein. This can prevent oxidation of the solder ball during reflow. In other words, when the metal line is heated and reacted, since the inside of the package is disconnected from the outside air by the adhesive glass, oxygen in the air inside the package is converted to the oxide. Therefore, when reflowing later, the solder is wetted without forming oxides and interconnected. In addition, this oxygen reaction creates a vacuum inside the package, which not only improves the adhesion of the reflow glass, but also compensates for the overpressure caused by fine outgassing from the reflow tap tape or solder. It can work as well. In addition, the addition of a material that can react with water vapor can improve the reliability of the package. Here, the powder bumps of the oxygen and water reactive materials are formed of Li, Na, K, Ca, Ti, W, Ta or a mixture thereof.

The adhesive glass 50 used to attach the second chip 10 'to the insulating spacer 40 is an example of an adhesive member, and in addition to this, an epoxy-related thermoplastic resin, a polymer-based insulating adhesive tape, or the like may be used. Can be.

Hereinafter, a method of manufacturing a stack chip package according to the present invention configured as described above will be described.

The basic manufacturing process comprises the steps of: adhering a tab tape to one of two semiconductor chips, the top surfaces of which are disposed so as to face each other, that is, the first chip, and simultaneously connecting the metal line of the tab tape to the chip pad; Bonding an insulating spacer having a rectangular frame shape to an outermost surface of the chip on an upper surface of the tab tape; Forming solder balls on electrically conductive portions of the tab tape, respectively; And placing a second chip on the structure of the step to electrically connect with the solder ball. Other detailed manufacturing processes are omitted since they have already been mentioned in describing the structure.

That is, the present invention can be configured a stack chip package having a smaller and excellent electrical characteristics and a high reliability through a simpler process.

Meanwhile, FIG. 13 shows another embodiment of the stack chip package according to the present invention. The basic principle is the same as that of the above-described embodiment, but there are other parts in the structure.

As shown, another embodiment of the present invention includes at least two semiconductor chips (10, 10 ') arranged and stacked so that their bottom surfaces face each other; A tab tape (60) having a metal line electrically connected to pads of the first chip and the second chip (10) (10 '); An insulating spacer 70 installed to support the tab tape 60 and surround the outer edge of the chip; And an encapsulant 80 which is filled and molded into the inner space of the insulating spacer 70. The tab tape 60 is connected to the pads of the first chip 10 and the second chip 10 ′ by separating the metal lines 62 up and down around the center insulating layer 61. Here, the encapsulant 80 is formed by filling an epoxy molding compound in the inner space of the spacer 70, but a ceramic cap is formed on the upper and lower portions of the insulating spacer 70 without using the encapsulant as described above. It can be configured to act as an encapsulant. In forming the encapsulant, it is preferable that the surfaces of the first chip 10 and the second chip 10 'are exposed to facilitate heat dissipation of the chip.

14 is a view illustrating another embodiment of a stack chip package according to the present invention, which is configured as follows.

At least two semiconductor chips 10 and 10 'disposed to face each other such that their top surfaces face each other; H-shaped insulating spacers 100 having a space portion for accommodating the first chip and the second chip 10, 10 ′ are formed in upper and lower portions, respectively, and a power line pattern 101 is formed in a central passage. ); And an external connection lead 110 connected to the power line pattern 101 of the insulating spacer 100. Several via holes 101a are formed through the power line pattern 101 of the insulating spacer 100, and the via holes 101a and corresponding pads of the first chip 10 and the second chip 10 ′ are formed. The connection member, that is, the solder ball 120 is installed between the first chip 10 and the second chip 10 'is configured to transmit the signal of the same pad to the outside.

In addition, ground plans 102 are provided on upper and lower portions of the power line pattern 101 of the insulating spacer 100 to reduce noise of an electric circuit, and a chip accommodating space part of the insulating space 100 is provided. An encapsulant 130 is formed therein.

The encapsulant 130 is formed by filling an epoxy molding compound in the upper and lower spaces of the insulating spacer, and the encapsulant 130 is exposed to expose the surfaces of the first chip 10 and the second chip 10 '. Formation is very effective in heat dissipation.

In addition, instead of the encapsulant, a ceramic cap (not shown) may be installed in the upper and lower spaces of the insulating spacer 100 to seal the chip.

The insulating spacer 100 may be formed of ceramic, BT resin, or BN resin, and the power line pattern 101 and the ground plan 102 may be formed of a single layer or a multilayer structure having a flat plate or a mesh shape.

In addition, the via hole 101a formed in the power line pattern 101 may include a multilayer structure having a Cu, Ni, and Au coating layers; Or a multilayer structure having a Cu, Ni, Cr, Au coating layer; Or a multilayer structure having a Cu, Ni, Co, Au coating layer; Or a multilayer structure having a Cu, Ni, Au, Tin coating layer; Or a multilayer structure having a Cu, Ni, Cr, Au, Tin coating layer; Or it may be made of a multilayer structure having a Cu, Ni, Co, Au, Tin coating layer.

In addition, the external connection lead 110 may be composed of a tab tape or a lead frame.

In addition, the solder ball 120 may be replaced with a conductive pump or an anisotropic conductive layer, wherein the anisotropic conductive layer uses the same as described in the embodiment of the present invention.

Another embodiment of the stack chip package according to the present invention can improve the electrical characteristics that are problematic in the stack chip by forming a ground plan on both sides of the power line pattern connected to an external signal at the spacer. Since there is no warpage defect in the up and down symmetry, it is possible to solve the problem that the reliability caused by thermal fatigue due to temperature change is deteriorated.

As described above, in the stack chip package according to the present invention, by stacking bare chips, a package with a small capacity can be obtained with a small appearance and a short signal transmission path can be used to improve electrical characteristics. have.

Furthermore, the present invention can reduce crack defects during interconnection, eliminate warpage defects, and improve the heat dissipation characteristics by exposing the back side of the chip, thereby obtaining a highly reliable package.

In addition, the present invention can realize a high reliability stack chip package with high reliability in a simpler process using existing equipment and materials without reinvestment of new materials or equipment, and high pin contact by using tap tape and solder balls. The effect is that packages can be easily implemented.

In the above, the stack chip package according to the present invention and a preferred embodiment for carrying out the manufacturing method thereof have been shown and described, but the present invention is not limited to the above-described embodiment, and the gist of the present invention as claimed in the following claims. Various changes can be made by those skilled in the art without departing from the scope of the present invention.

Claims (25)

At least two semiconductor chips stacked on top of each other; A tab tape having a metal line connected to a bond pad of a first chip of the two semiconductor chips and attached to an upper surface of the first chip, the other end of which is protruded out of the chip and connected to a substrate; A conductive member for electrically connecting the tab tape attached to the first chip and the bond pads of the second chip positioned thereon; An insulating spacer having a rectangular frame shape interposed between edges of the adhesive part of the first chip and the second chip to isolate the inside and the outside of the chip; And And a bonding member interposed between the insulating spacer and the second chip to attach and support the second chip. The stack chip package of claim 1, wherein the tab tape has an adhesive layer for attaching and supporting chips and insulating spacers on both sides with an intermediate metal line therebetween. The method of claim 2, wherein the metal line is Cu, Ni, Au; Cu, Ni, Cr, Au; Cu, Ni, Co, Au; Cu, Ni, Au, Tin; A stack chip package comprising Cu, Ni, Cr, Au, Tin or Cu, Ni, Co, Au, Tin. The stack chip package of claim 2, wherein the metal line has a thickness of at least 1 MIL to 4 MIL. The stack chip package of claim 2, wherein the adhesive layer is formed of a thermoplastic resin, adhesive glass, or polymer-based insulating adhesive tape. The stack chip package of claim 5, wherein the adhesive tape has a thickness of at least 10 μm and at most 100 μm. The stack chip package of claim 1, wherein a rectangular metal electrode for electrical connection is formed on one surface of the tab tape, and bumps are formed on the metal electrode. 8. The stack chip package of claim 7, wherein a via hole for electrically conducting the metal electrode of the tab tape and the first and second chip pads is formed in a size of at least 2 MIL to 6 MIL. The stack chip package of claim 1, wherein the conductive member is a simple solder ball or solder paste. 2. The conductive member of claim 1, wherein the conductive member comprises gold, silver, aluminum bumps or high temperature solder balls formed on the pad of the second chip, and low temperature solder balls or solder paste formed on the metal electrode of the tab tape. Stack chip package. The stack chip package according to claim 9 or 10, wherein a C-ring or a micro-ring is embedded in the solder balls and the solder paste. The stack chip package of claim 1, wherein the conductive member comprises a gold or hot solder ball formed on a pad of a second chip, and an anisotropic conductor filled between the solder ball and the tab tape. The method of claim 12, wherein the anisotropic conductor is a resin containing particles for electrical conduction, epoxy, modified epoxy resin, polyester, modified polymer, acrylic ester, modified ester, silicone resin, phenoxy resin, A stack chip package comprising a polymer that is cured by polyurethane, polysulfide, cyanocryretz, polylexin or other thermocompression bonding. The method of claim 1, wherein the insulating spacer is an oxide-based aluminum oxide, silicon oxide, BeO or nitride-based aluminum nitride, titanium nitride, silicon nitride, BN or carbide-based aluminum carbide, titanium carbide, silicon carbide Stack chip package, characterized in that formed of diamond or glass ceramic. The stack chip package of claim 14, wherein an upper surface of the insulating spacer is inclined downward from the outside to the inside so that the adhesive member used for the upper chip stack does not slip out of the chip and leak out. At least two semiconductor chips facing each other such that their top surfaces face each other; H-shaped insulating spacers each having upper and lower spaces formed therein for accommodating the first chip and the second chip, and having a power line pattern formed therein; And an external connection lead connected to the power line pattern of the insulating spacer, wherein several via holes are formed through the power line pattern of the insulating spacer, and the corresponding via holes and the first chip and the second chip are formed. A stack chip package, characterized in that a connection member is installed between the pads and configured to transmit a signal of the same pad of the first chip and the second chip to the outside. The method of claim 16, wherein the ground plan to reduce the noise of the electrical circuit is provided on the upper and lower portions of the power line pattern of the insulating spacer, respectively, characterized in that the sealing member for sealing the chip receiving space of the insulating space is provided. Stack chip package. The stack chip package of claim 16, wherein the sealing member is an encapsulant formed by filling an epoxy molding compound in upper and lower spaces of the insulating spacer. The stack chip package of claim 18, wherein the encapsulant is formed to expose surfaces of the first chip and the second chip. The stack chip package of claim 16, wherein the sealing member is a ceramic cap which is fixed to the upper and lower spaces of the insulating spacer. The stack chip package of claim 16, wherein the insulating spacer is formed of ceramic, BT resin, or BN resin. The stack chip package of claim 16, wherein the power line pattern and the ground plan are formed of a single layer or a multilayer structure having a flat plate or a net shape. The semiconductor device of claim 16, wherein the via hole formed in the power line pattern comprises: a multilayer structure having a Cu, Ni, Au coating layer; Or a multilayer structure having a Cu, Ni, Cr, Au coating layer; Or a multilayer structure having a Cu, Ni, Co, Au coating layer; Or a multilayer structure having a Cu, Ni, Au, Tin coating layer; Or a multilayer structure having a Cu, Ni, Cr, Au, Tin coating layer; Or Cu, Ni, Co, Au, Stack chip package, characterized in that consisting of a multi-layer structure having a coating layer. 17. The stack chip package of claim 16, wherein the externally connected leads are tab tapes or lead frames. The stack chip package of claim 16, wherein the connection member is a solder ball, a conductive bump, or an anisotropic conductive layer.