589724 玖、發明說明 相關申請案之對照 本申請案係依據及主張20〇2年3月28日所申請之先前 曰本專利申請案第2002- 0903 93號之優先權的權益；其整 個內容將引用於本文中供參考。 【發明所屬之技術領域】 本發明有關一種半導體裝置，尤其有關一種其中半導 體晶片係使用封膠樹脂予以封膠之半導體裝置。 【先前技術】 近年來，在保持技術發展於相對於半導體積體電路之 積體性以及可靠性增強之半導體積體電路的領域中，致力 於進一步之小型化及使半導體裝置更薄，現正密集地完成 。爲符合此一趨勢，目前正存在漸增之需求於發展性質上 優異之封膠樹脂。 在習知覆晶型之QON(四邊輪廓無引線封裝）中，半導 體晶片4係經由導電性連接器構件2而安裝於基板1之表面 上，如第1圖中所示。在此例中之基板1係由樹脂或陶質物 所製成，且在其表面上配置有配線電路（未圖示），該基板 1亦在其下方面之上配置有端子6用於外部連接。該導電性 連接器構件2係由用於基板1之配線電路端子的凸塊2a及用 於半導體晶片的凸塊2 6所建構，該等凸塊係藉例如金或焊 料所形成。 -6 - (2) (2)589724 封膠樹脂層5係配置於半導體晶片4之頂部表面及側面 上以及在基板1與半導體晶片4之晶的空間或縫隙中，此封 膠樹脂層5可藉造模樹脂合成物整體地密封有半導體晶片4 安裝於該處上之基板1而形成。 因爲基板1與半導體晶片4之間的空間或縫隙在高度上 相較模具與半導體晶片4間之距離係相當地小，當使用造 模樹脂合成物整體地密封基板1之時，空隙會更可能地產 生於上述空間或縫隙中。同時，使半導體裝置之本體更薄 之技術在近年中已更爲進步，以致該封膠樹脂層5的厚度 不可避免地作得專薄。因此，已產生有一問題，即，難以 在使用造模樹脂合成物執行半導體裝置之封膠過程中完美 地配置一造模樹脂合成物於半導體裝置4之頂部表面上， 以及難於以造模樹脂合成物充塡上述空間或縫隙，因而增 加了產生空隙於該處中之可能性。 特別地，若空隙存在於基板1與半導體晶片4間之空間 中之時，該半導體晶片4遭受到以造模樹脂合成物充塡該 空間時所採之壓力。結果，將向下地按壓該半導體晶片4 之中央部分，因而導致半導體晶片4之裂痕產生。該樹脂 層會從空隙剝離以及裂痕會產生，因而使該半導體裝置之 長期可靠性劣化。 可在以造模樹脂合成物充塡該空間時增加壓力及溫度 而抑制空隙的產生。然而，該半導體晶片會由於使用於此 充塡之壓力而移開，或者會由於高溫而熔化。 該等問題呈大大地劣化半導體裝置之可靠性的原因。 -7- (3) (3)589724 【發明內容】 根據本發明一實施例之半導體裝置包含： 一基板； 一第一半導體晶片，透過覆晶連接而安裝於該基板之 上，該第一半導體晶片與該基板間隔開0.055毫米或更小的 距離，該第一半導體晶片具有0.25毫米或更小的厚度； 一導電性連接器構件，電性地連接該第一半導體晶片 於該基板；以及 一造模樹脂層，配置於該基板上而覆蓋該第一半導體 晶片，且由含有75至92重量百分比之無機充塡物及〇·5至1.5 重量百分比之碳黑的硬化樹脂合成物所形成，一部分相對於 該基板之造模樹脂層具有0.1 5毫米或更小的厚度，99重量百 分比之無機充塡物具有35微米或更小之最長直徑，該無機充 塡物之平均最長直徑係15微米或更小，且具有10微米或更小 之最長直徑的細微充塡物之含量依據該無機充塡物之整體重 量而限制於30至50重量百分比的範圍內。 根據本發明另一實施例之半導體裝置包含： 一基板； 一第一半導體晶片，安裝於該基板之上； 一第一配線，具有28微米或更小的直徑及電性連接該 第一半導體晶片於該基板；以及 一造模樹脂層，配置於該基板上而覆蓋該第一半導體 晶片，且由含有75至92重量百分比之無機充塡物及〇.5至1.5 -8- (4) (4)589724 重量百分比之碳黑的硬化樹脂合成物所形成’ 一部分相對於 該基板之造模樹脂層具有〇·2毫米或更小的厚度，99重量百 分比之無機充塡物具有35微米或更小之最長直徑’該無機充 塡物之平均最長直徑係15微米或更小，且具有1 〇微米或更小 之最長直徑的細微充塡物之含量依據該無機充塡物之整體重 量而限制於3 0至5 0重量百分比的範圍內。 【實施方式】 根據本發明之實施例將參照附圖詳細解說如下： 第2圖係橫截面視圖，描繪本發明一實施例之半導體 裝置。 在此處所示之半導體裝置中，一半導體晶片4係經由 一導電性連接器構件2而安裝於基板1之表面上，該基板1 可由聚亞醯胺卷帶或陶質物所形成，且具有端子6配置於 其下方面以用於外部連接。 雖未顯示於圖式中，該導電性連接器構件2係由用於 半導體晶片4之凸塊及用於基板1之配線電路端子之凸塊所 建構，該等凸塊例如可藉錫/銀焊料，金，錫/鉛焊料，錫 ’錫/銀/銅焊料，錫/鋅焊料，錫/鉍焊料或鎳所形成，用 於外部連接之端子例如可藉錫/銀焊料，錫/鉛焊料或錫所 形成。 封膠樹脂層5係配置於半導體晶片4之頂部表面及側面 之上，基板1的頂部表面之上以及基板1與半導體晶片4間 之空間中。 -9- (5) 在第2圖所示之實施例中，基板1與半導體晶片4間之 空間的高度爲0.0 5 5毫米或更小’而半導體晶片4之厚度則 爲〇 2 5毫米或更小。進一步地，相對於基板之部分d膠樹 脂層5的厚度爲〇.15毫米或更小。在此例中，配置於半導 體晶片4之上的部分封膠樹脂層5的厚度爲0 · 1 5毫米或更小 。該等尺寸係限制如上述以爲了使整個半導體裝置最小化 〇 較佳地，半導體裝置之整個高度（測量自用於外部連 接之端子6至造模樹脂層5之距離）應爲0.500毫米或更小。 進一步較佳地，配置於半導體晶片4上之部分封膠樹脂層5 應較佳地限制厚度不大於該空間高度的3倍。 爲了形成造模樹脂層5而防止空隙產生於小至〇 . 〇 5 5毫 米或更小的狹窄空間中，需採用在流體性造模性之上優異 的造模樹脂合成物。因此，針對取得最適化之造模樹脂合 成物，種種硏討已由本發明人完成。 該造模樹脂合成物包含無機充塡物，環氧樹脂，酌樹 脂，硬化助催化劑以及碳黑。 至於環氧樹脂，並沒有任何特定的限制且因此可選自 該等每分子具有兩個或更多個環氧族，此環氧樹脂之特定 實例包含例如鄰甲酚-酚醛淸漆型環氧樹脂，經二環戊二 嫌改質的環氧樹脂’三酣甲院型環氧樹脂，聯苯基型環氧樹 脂，表雙（bls兩環氧樹脂。該等環氧樹脂可單獨地或 組合地使用。 至於苯酚樹脂，並沒有任何特定的限制，只要提供有 -10- (6) (6)589724 兩種或多種能與環氧樹脂之環氧族反應的苯酚羥基族即可。 此苯酚樹脂之特定實例包含例如苯酚-酚醛淸漆樹脂，苯 酚苯芳烷基樹脂，萘酚芳烷基樹脂以及經二環戊二烯改質的 苯酚樹脂。該等環氧樹脂可單獨地或組合地使用。 至於硬化助催化劑，可使用不同種類之硬化助催化劑 ’諸如磷硬化助催化劑，咪唑硬化助催化劑，DBU型硬化助 催化劑，等。該等硬化助催化劑可單獨地或組合地使用。該 等硬化助化劑的混合比例較佳地應依據樹脂合成物之整個重 量在0.01至5重量百分比之範圍內，若此混合比例小於〇.〇1重 量百分比，則此樹脂合成物之膠結時間會延長，且同時，該 樹脂合成物之硬化性質會劣化。相反地，若此混合比例超過 5重量百分比，則該樹脂合成物之流體性將極度地劣化，所 以可能招致電氣性質以及造模樹脂層之濕度阻力上的劣化。 碳黑結合於此處係用於防止半導體晶片會由於光之透 射所造成的不良，使得碳黑可爲任何一般使用爲密封或封膠 材料的種類。 該造模樹脂合成物的流體性係高度依賴將結合之無機 充塡物的種類。爲比較之目的，如下文第1表中所示之8種造 模樹脂合成物係利用不同種類之熔化矽石爲無機充塡物予以 製備。 接著，如第2圖中所示之半導體裝置係利用各該等造模 樹脂合成物所製造。在此例子中，係檢視該等造模樹脂合成 物進入基板1與半導體晶片4間之空間內的充塡性質。在此評 估之中，其中沒有空隙產生於空間中之造模樹脂合成物係表 -11 - (7)589724 示爲、、〇〃，而其中空隙產生於空間中之造模樹脂合成物則 表示爲'' X 〃 。 附帶地，至少檢視3 0個樣品而空隙係界定爲在較長直 徑中具有0.020毫米或更大者。 第1表 樹脂 組態 最長直徑 平均直徑 含量 充塡物 編號 (微米） (微米） (重量百分比） 性質 1 壓碎的 105 30 86 X 2 球狀的 75 16 86 X 3 球狀的 75 9 86 X 4 球狀的 75 6 86 X 5 球狀的 75 6 82 X 6 球狀的 3 5 9 86 〇 7 球狀的 3 5 6 86 〇 8 球狀的 3 5 6 82 〇 最長直徑意指表示無機充塡物顆粒之最長部分的長度 ，而平均直徑則意指表示該等充塡物顆粒之最長直徑的平 均値。 如第1表中所示，由樹脂編號第6，7及8號中所表示之 造模樹脂合成物在充塡性質上係優異的。因此，有用於本 發明實施例中之無機充塡物係界定爲具有3 5微米或更小的 最長直徑，及1 5微米或更小的平均直徑。附帶地，在本發 -12- (8) (8)589724 明實施例中’需要99重量百分比或更大重量百分比之無機 充塡物顆粒滿足上述有關最長直徑之條件。更企望的是，滿 足上述條件之無機充塡物顆粒的含量爲99.9重量百分比或更 大重量百分比，最佳地爲99.99重量百分比或更大的重量百 分比。 在使用於該等樹脂編號第6，7及8號中所使用之熔化矽 石中’具有1 〇微米或更小之最長直徑的充塡物比例係依據該 熔化之矽石而限制於30至50重量百分比的範圍內。 進一步所發現的是，當該無機充塡物之含量小於75重 量百分比時，半導體裝置之回流阻力及封裝可靠性會劣化。 另一方面所發現的是，無機充塡物含量之上限限制於92重量 百分比將便利於製造該造模樹脂。 依據上述條件，將結合於本發明實施例中所使用之造 模樹脂合成物之內的無機充塡物係限制於下列特性： (1) 其最長的直徑爲35微米或更小； (2) 其平均的直徑爲1 5微米或更小； (3) 具有10微米或更小之最長直徑細微充塡物含量係限 制於30至50重量百分比的範圍內；以及 (4) 無機充塡物之含量係限制於75至92重量百分比之範 圍。 在上述解說中，熔化的矽石係描述爲無機充塡物之實 例。然而，只要符合上述條件，亦可使用壓碎的矽石等。 其中如上述所界定之無機充塡物特性將包含於其中之 造模樹脂合成物在流體性以及造模性之中係優異的。因此， -13- (9) (9)589724 上文所界定之造模樹脂合成物可易於在執行上述整個樹脂封 膠時導入於狹窄的空間之內，藉此可抑制空隙的產生。此外 ，因爲空隙的產生可以以此方式抑制，故可防止晶片中由於 在以造模樹脂合成物充塡狹窄空間時所施加之壓力而產生之 裂痕，所以可增強將製造之半導體裝置的可靠性，而且，可 製造在厚度上小型化之半導體裝置，樹脂層之剝離不會產生 ，所以可改善半導體裝置之長時間可靠性。 此外，因爲上文所界定之造模樹脂合成物在流體性之 中係優異的，故無需在半導體之封膠時增加樹脂合成物的充 塡壓力，因此，該半導體裝置並不會因樹脂充塡中所使用之 壓力而流出。 進一步地，在本發明之實施例中，將結合於造模樹脂 合成物之內的碳黑之含量係界定於0.5至1.5重量百分比的範 圍之內。 在碳黑中之此範圍係界定如下。若干種之造模樹脂合 成物係藉變化碳黑之含量而予以製備，然後藉使用各該等造 模樹脂合成物製造半導體裝置，及測量所生成之半導體裝置 之光透射比。在此例子中，該半導體之總高度係設定於 0.450毫米且光之波長限制於1000至2000奈米之範圍內。 結果，藉使用含有〇 . 5 0或更大重量百分比之造模樹脂 所封膠之半導體裝置的光透射比係取得爲0.20%或更小。附 帶地，可確認的是，只要半導體裝置之光透射比限制於 0.20%或更小，則可實質地防止半導體裝置之不良產生。此 外’亦可保持該造模樹脂合成物之體積電阻係數於室溫時爲 -14- (10) (10)589724 1 0y歐姆·公分。 相反地，若碳黑之含量超過1.5重量百分比，則該造丰吴 樹脂合成物之體積電阻係數會劣化，因而造成將製造之半導 體裝置之不良產生。因此，碳黑含量中之上限應限制於1.5 重量百分比。 碳黑之含量係限制於0.50至1.5重量百分比的範圍內， 以爲了抑制光透射比以及防止半導體裝置之不良產生，即使 是在其中樹脂封膠係執行相當薄的例子中。 因爲無機充塡物及碳黑係以此一如上述之方式包含於 造模樹脂合成物之中，故根據本發明實施例之半導體裝置在 可靠性上係優異的，且同時，由於光透射比之不良可以預防 〇 也就是說，在根據本發明實施例之半導體裝置中之造 模樹脂層係藉硬化一含有75至92重量百分比之無機充塡物及 0.5至1.5重量百分比之碳黑的造模樹脂合成物所形成。特別 地，99重量百分比之無機充塡具有35微米或更小的最長直徑 ，該無機充塡物之平均最長直徑係1 5微米或更小，以及具有 1 0微米或更小的最長直徑之細微充塡物含量係依據該無機充 塡物的整個重量而限制於30至50重量百分比之範圍內。 第2圖中所示之半導體裝置可變化地修正。 例如，如第3圖中所不，黏著層7可插置於基板1與半導 體晶片4之間，插置於基板1與半導體晶片4之間的此黏著層7 作用爲減緩內部應力。因此，該黏著層之配置係特別有效於 其中半導體裝置之大小特別地大，例如7毫米平方或更大， -15- (11) (11)589724 或半導體晶片4之大小特別地大，例如6耄米平方或更大的例 子中。 進一步地，如第4圖中所示地，一第二半導體晶片灿可 疊層於第一半導體晶片4a之上，此第二半導體晶片4b係經由 一貫穿第一半導體晶片4a及導電性連接器構件2所形成之貫 穿導電性部分9而連接於基板1 ° 如第5圖中所示地，此第二半導體晶片4 b可經由一線連 接於基板1。在第5圖中所不之半導體裝置中’此弟一半導體 晶片4b係以插置於該處之間的黏著層7b配置於第一半導體晶 片4 a之上，且係藉一第二線8 b連接於基板1 ’此弟一線8 b可 由有直徑約28微米之金線予以形成。 第6圖係橫截面視圖，描繪根據本發明另一實施例之半 導體裝置。 在第6圖所示之半導體裝置中，半導體晶片4係透過一 黏著層7安裝於基板1之上，此半導體晶片4係使用一具有直 徑28微米或更小的金線8而電性地連接於基板之配線電路（未 圖示）的端子。至於基板1之材料，可採用相同於上述之材料 〇 封膠樹脂層5係配置於半導體晶片4之頂部表面及側面 上以及在基板1之頂部表面之上。此封膠樹脂層5可藉硬化一 相於無機材料及碳黑所形成之造模樹脂合成物以滿足已於上 文所述之條件。 在第6圖所示之半導體裝置中，爲使半導體裝置之總厚 度最小化，相對於基板1之封膠樹脂層5部分之厚度限制於 -16- (12) (12)589724 0.2毫米或更小。在此例子中，配置於半導體晶片4上之封膠 樹脂層5部分之厚度限制於0.2毫米或更小。 在其中半導體晶片係透過一線連接於基板之習知半導 體裝置之例子中，該線會在封膠過程之期間遭受造模樹脂合 成物所造成之剪力效應所變形。在該例中，線會相互接觸， 因而造成半導體裝置電性不良的產生。 然而，在第6圖所示之半導體裝置的例子中，該半導體 裝置係利用流體性及造模性優異之造模樹脂合成物予以封膠 ，故可預防線變形。 第6圖中所示之半導體裝置可建構爲如第4及5圖中所 示之兩層疊層結構。第7及8圖描繪此修正之實例。 第7圖中所示之半導體裝置係以如第4圖中所示半導體 裝置之相同方式予以建構，除了第一半導體晶片4a係經由 線8 a連接於基板1。第8圖中所示之半導體裝置亦可構如第 5圖中所示半導體裝置之相同方式，除了第一半導體晶片 4 a係經由線8a連接於基板1。如第5及8圖中所示，配置以 便接第二半導體晶片4b於基板1之第二線8b比第一線8a更 長。因爲在流體性上優異之造模樹脂合成物係使用於本發 明實施例中，甚至此長的線可防止免於遭受變形。 附帶地，亦可疊層一第三半導體晶片於該第二半導體 晶片4b之上而使其成爲一 3層疊層結構。 本發明可在其精神內予以變化地修正。 額外的優點及修正將立即產生於該等熟習於本項技術 之人士，因此，在其較廣義觀點中之本發明並未受限於本 -17- (13) ，724 文所示及所述之特定細節以及代表性之實施例。所以’ 種修正例可予以完成而不會背離如附錄之申請專利範圍及 其等效例所界定之一般發明觀念之精神及範疇。 【圖式簡單說明】 第1圖係橫截面視圖，描繪根據習知技術之半導體裝 置；589724 (2) Contrast of related applications of invention description This application is based on and claims the right of priority of this patent application No. 2002- 0903 93, filed on March 28, 2002; the entire content will be It is incorporated herein by reference. [Technical field to which the invention belongs] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a semiconductor wafer is sealed with a sealing resin. [Prior technology] In recent years, in the field of maintaining semiconductor technology with respect to semiconductor integrated circuits that are more integrated and more reliable than semiconductor integrated circuits, efforts have been made to further miniaturize and make semiconductor devices thinner. Densely completed. To meet this trend, there is an increasing demand for sealant resins with excellent development properties. In a conventional flip chip type QON (quad-lead outline leadless package), a semiconductor wafer 4 is mounted on the surface of a substrate 1 via a conductive connector member 2 as shown in Fig. 1. The substrate 1 in this example is made of resin or ceramics, and a wiring circuit (not shown) is arranged on the surface. The substrate 1 is also provided with a terminal 6 on the lower side for external connection. . The conductive connector member 2 is constituted by a bump 2a for a wiring circuit terminal of the substrate 1 and a bump 26 for a semiconductor wafer, and these bumps are formed by, for example, gold or solder. -6-(2) (2) 589724 The sealant resin layer 5 is arranged on the top surface and side surfaces of the semiconductor wafer 4 and in the space or gap between the crystals of the substrate 1 and the semiconductor wafer 4. The sealant resin layer 5 may The substrate 1 on which the semiconductor wafer 4 is mounted is integrally sealed by the molding resin composition. Since the space or gap between the substrate 1 and the semiconductor wafer 4 is considerably smaller than the distance between the mold and the semiconductor wafer 4, the gap is more likely when the substrate 1 is completely sealed using the molding resin composition. Ground is created in the above-mentioned space or gap. At the same time, the technology for making the body of a semiconductor device thinner has progressed in recent years, so that the thickness of the sealant resin layer 5 is inevitably made thinner. Therefore, there have been problems that it is difficult to perfectly arrange a molding resin composition on the top surface of the semiconductor device 4 during the sealing process of the semiconductor device using the molding resin composition, and it is difficult to synthesize with the molding resin. Objects fill the above-mentioned spaces or gaps, thereby increasing the possibility of creating voids there. In particular, if a void exists in the space between the substrate 1 and the semiconductor wafer 4, the semiconductor wafer 4 is subjected to a pressure applied when the space is filled with a molding resin composition. As a result, the central portion of the semiconductor wafer 4 will be pressed downward, thereby causing cracks in the semiconductor wafer 4. The resin layer is peeled from the void and cracks are generated, thereby deteriorating the long-term reliability of the semiconductor device. It is possible to suppress the generation of voids by increasing pressure and temperature when filling the space with a molding resin composition. However, the semiconductor wafer may be removed due to the pressure used for the filling, or may be melted due to the high temperature. These problems are the cause of greatly deteriorating the reliability of the semiconductor device. -7- (3) (3) 589724 [Summary] A semiconductor device according to an embodiment of the present invention includes: a substrate; a first semiconductor wafer mounted on the substrate through a flip-chip connection, the first semiconductor The wafer is separated from the substrate by a distance of 0.055 mm or less, and the first semiconductor wafer has a thickness of 0.25 mm or less; a conductive connector member electrically connecting the first semiconductor wafer to the substrate; and A molding resin layer is disposed on the substrate to cover the first semiconductor wafer, and is formed of a hardened resin composition containing 75 to 92 weight percent of an inorganic filler and 0.5 to 1.5 weight percent of carbon black. A part of the molding resin layer with respect to the substrate has a thickness of 0.1 5 mm or less, and 99% by weight of the inorganic filler has a longest diameter of 35 microns or less. The average longest diameter of the inorganic filler is 15 microns. The content of the fine filling material having a longest diameter of 10 microns or less or less is limited to a range of 30 to 50 weight percent based on the total weight of the inorganic filling materialA semiconductor device according to another embodiment of the present invention includes: a substrate; a first semiconductor wafer mounted on the substrate; a first wiring having a diameter of 28 microns or less and electrically connected to the first semiconductor wafer On the substrate; and a molding resin layer disposed on the substrate to cover the first semiconductor wafer, and comprising 75 to 92 weight percent of an inorganic filler and 0.5 to 1.5 -8- (4) ( 4) 589724 weight percent of the carbon black hardened resin composition is formed with a portion having a thickness of 0.2 mm or less relative to the molding resin layer of the substrate, and 99 weight percent of the inorganic filler has 35 microns or less Smallest longest diameter 'The average longest diameter of the inorganic filler is 15 microns or less, and the content of the fine filler having a longest diameter of 10 microns or less is limited based on the overall weight of the inorganic filler In the range of 30 to 50 weight percent. [Embodiment] An embodiment according to the present invention will be explained in detail with reference to the drawings as follows: FIG. 2 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. In the semiconductor device shown here, a semiconductor wafer 4 is mounted on the surface of a substrate 1 via a conductive connector member 2, and the substrate 1 may be formed of a polyimide tape or a ceramic material, and has The terminal 6 is arranged on the lower side thereof for external connection. Although not shown in the drawing, the conductive connector member 2 is constructed of bumps for the semiconductor wafer 4 and bumps for the wiring circuit terminals of the substrate 1. The bumps can be made of tin / silver, for example. Solder, gold, tin / lead solder, tin'tin / silver / copper solder, tin / zinc solder, tin / bismuth solder, or nickel. Terminals used for external connection can be tin / silver solder, tin / lead solder, for example. Or formed by tin. The sealant resin layer 5 is disposed on the top surface and the side surfaces of the semiconductor wafer 4, on the top surface of the substrate 1, and in the space between the substrate 1 and the semiconductor wafer 4. -9- (5) In the embodiment shown in FIG. 2, the height of the space between the substrate 1 and the semiconductor wafer 4 is 0.0 5 5 mm or less, and the thickness of the semiconductor wafer 4 is 0 2 5 mm or smaller. Further, the thickness of the gum resin layer 5 with respect to the portion d of the substrate is 0.15 mm or less. In this example, the thickness of the part of the sealant resin layer 5 disposed on the semiconductor wafer 4 is 0. 15 mm or less. These dimensions are limited as described above in order to minimize the entire semiconductor device. Preferably, the entire height of the semiconductor device (measured from the distance from the terminal 6 for external connection to the molding resin layer 5) should be 0.500 mm or less . Further preferably, a part of the sealing resin layer 5 disposed on the semiconductor wafer 4 should preferably limit the thickness to not more than three times the height of the space. In order to form the molding resin layer 5 and prevent voids from being generated in a narrow space as small as 0.05 mm or less, it is necessary to use a molding resin composition excellent in fluid moldability. Therefore, various investigations have been made by the present inventors in order to obtain an optimized molding resin composition. The molding resin composition contains an inorganic filler, an epoxy resin, a resin, a hardening promoter, and carbon black. As for the epoxy resin, there is no particular limitation and therefore it may be selected from those having two or more epoxy groups per molecule, and specific examples of this epoxy resin include, for example, o-cresol-phenolic epoxy resin Resin, epoxy resin modified by dicyclopentadiene, 'Sanjiajiayuan type epoxy resin, biphenyl type epoxy resin, table double (bls two epoxy resins. These epoxy resins can be individually or It is used in combination. As for the phenol resin, there is no particular limitation, as long as two or more phenolic hydroxyl groups capable of reacting with the epoxy group of the epoxy resin are provided as -10- (6) (6) 589724. Specific examples of the phenol resin include, for example, a phenol-phenol novolak resin, a phenol benzoaralkyl resin, a naphthol aralkyl resin, and a dicyclopentadiene-modified phenol resin. These epoxy resins may be used alone or in combination As for the hardening co-catalyst, different kinds of hardening co-catalysts such as a phosphorus hardening co-catalyst, an imidazole hardening co-catalyst, a DBU type hardening co-catalyst, etc. may be used. These hard-co-catalysts may be used alone or in combination. The mixing ratio of the isohardening accelerator should preferably be in the range of 0.01 to 5 weight percent based on the entire weight of the resin composition. If the mixing ratio is less than 0.01 weight percent, the cementing time of the resin composition will be Prolonged, and at the same time, the hardening properties of the resin composition will be deteriorated. On the contrary, if the mixing ratio exceeds 5 weight percent, the fluidity of the resin composition will be extremely deteriorated, so electrical properties and mold resin layers may be caused The carbon black is used to prevent the semiconductor wafer from being defective due to the transmission of light, so that the carbon black can be any type generally used as a sealing or sealing material. The molding resin The fluidity of the composition is highly dependent on the type of inorganic filler to be combined. For comparison purposes, the eight molding resin composites shown in Table 1 below use different types of fused silica as the inorganic filler. An object is prepared. Next, a semiconductor device as shown in FIG. 2 is manufactured using each of these molding resin compositions. In this example, the Depending on the filling properties of the molding resin composition entering the space between the substrate 1 and the semiconductor wafer 4. In this evaluation, the molding resin composition in which no void is generated in the space is shown in Table-11-(7 ) 589724 is shown as,, 〇〃, and the molding resin composition in which voids are generated in the space is indicated as `` X 。. Incidentally, at least 30 samples are inspected and the voids are defined as having in the longer diameter 0.020 mm or greater. Table 1 Resin Configuration Longest Diameter Average Diameter Content Filling Number (micron) (micron) (weight percentage) Properties 1 Crushed 105 30 86 X 2 Spherical 75 16 86 X 3 Spherical 75 9 86 X 4 Spherical 75 6 86 X 5 Spherical 75 6 82 X 6 Spherical 3 5 9 86 〇7 Spherical 3 5 6 86 〇8 Spherical 3 5 6 82 〇 The longest diameter means the length of the longest portion of the inorganic filler particles, and the average diameter means the average diameter of the longest diameter of the filler particles. As shown in Table 1, the molding resin compositions shown in Resin Nos. 6, 7 and 8 are excellent in filling properties. Therefore, inorganic fillers useful in the examples of the present invention are defined as having a longest diameter of 35 microns or less and an average diameter of 15 microns or less. Incidentally, in the embodiment of the present invention -12- (8) (8) 589724 ', 99% by weight or more of inorganic filler particles are required to satisfy the above-mentioned condition regarding the longest diameter. It is more desirable that the content of the inorganic filler particles satisfying the above-mentioned conditions is 99.9% by weight or more, and most preferably 99.99% by weight or more. The proportion of the filler having the longest diameter of 10 micrometers or less in the fused silica used in these resin Nos. 6, 7 and 8 is limited to 30 to 30 depending on the fused silica Within 50 weight percent. It has further been found that when the content of the inorganic filler is less than 75% by weight, the reflow resistance and packaging reliability of the semiconductor device may be deteriorated. On the other hand, it was found that limiting the upper limit of the inorganic filler content to 92% by weight would facilitate the manufacture of the molding resin. According to the above conditions, the inorganic fillers incorporated in the molding resin composition used in the examples of the present invention are limited to the following characteristics: (1) its longest diameter is 35 microns or less; (2) Its average diameter is 15 micrometers or less; (3) the content of the fine charge with a longest diameter of 10 microns or less is limited to the range of 30 to 50 weight percent; and (4) the inorganic charge The content is limited to a range of 75 to 92 weight percent. In the above explanation, the fused silica series is described as an example of an inorganic filler. However, as long as the above conditions are met, crushed silica or the like may be used. Among them, the mold filling resin composition in which the characteristics of the inorganic filler as defined above are included is excellent in fluidity and moldability. Therefore, -13- (9) (9) 589724 The molding resin composition defined above can be easily introduced into a narrow space when the entire resin sealing is performed, thereby suppressing the generation of voids. In addition, since the generation of voids can be suppressed in this way, cracks in the wafer due to pressure applied when the narrow space is filled with the molding resin composition can be prevented, and the reliability of the semiconductor device to be manufactured can be enhanced. Moreover, a semiconductor device that is miniaturized in thickness can be manufactured, and peeling of the resin layer does not occur, so the long-term reliability of the semiconductor device can be improved. In addition, because the molding resin composition defined above is excellent in fluidity, there is no need to increase the filling pressure of the resin composition during the sealing of the semiconductor, so the semiconductor device is not affected by the resin filling. The pressure used in the 塡 is discharged. Further, in the embodiment of the present invention, the content of carbon black incorporated in the molding resin composition is defined within the range of 0.5 to 1.5 weight percent. This range in carbon black is defined as follows. Several kinds of molding resin composites are prepared by varying the content of carbon black, and then semiconductor devices are manufactured by using each of these molding resin compositions, and the light transmittance of the generated semiconductor devices is measured. In this example, the total height of the semiconductor is set to 0.450 mm and the wavelength of light is limited to the range of 1000 to 2000 nm. As a result, the light transmittance of the semiconductor device encapsulated by using a molding resin containing 0.5% by weight or more was obtained as 0.20% or less. Incidentally, it can be confirmed that, as long as the light transmittance of the semiconductor device is limited to 0.20% or less, the occurrence of defects in the semiconductor device can be substantially prevented. In addition, it is also possible to keep the volume resistivity of the molding resin composition at room temperature to be -14- (10) (10) 589724 1 0 ohm · cm. On the contrary, if the content of carbon black exceeds 1.5% by weight, the volume resistivity of the made-up resin composition will be deteriorated, thereby causing defects in the semiconductor device to be manufactured. Therefore, the upper limit in the carbon black content should be limited to 1.5 weight percent. The content of carbon black is limited to the range of 0.50 to 1.5 weight percent in order to suppress the light transmittance and prevent the occurrence of defects in the semiconductor device, even in the case where the resin sealant is performed relatively thinly. Since the inorganic filler and carbon black are included in the molding resin composition in this manner as described above, the semiconductor device according to the embodiment of the present invention is excellent in reliability, and at the same time, due to the light transmittance The defects can be prevented. That is, the molding resin layer in the semiconductor device according to the embodiment of the present invention is formed by hardening an inorganic filler containing 75 to 92% by weight and 0.5 to 1.5% by weight of carbon black. Formed from a resin composition. Specifically, 99% by weight of the inorganic filler has a longest diameter of 35 micrometers or less, the average longest diameter of the inorganic filler is 15 micrometers or less, and fines having a longest diameter of 10 micrometers or less The charge content is limited to a range of 30 to 50 weight percent based on the entire weight of the inorganic charge. The semiconductor device shown in FIG. 2 can be modified variably. For example, as shown in FIG. 3, the adhesive layer 7 may be interposed between the substrate 1 and the semiconductor wafer 4, and the adhesive layer 7 interposed between the substrate 1 and the semiconductor wafer 4 functions to reduce internal stress. Therefore, the configuration of the adhesive layer is particularly effective in that the size of the semiconductor device is particularly large, such as 7 mm square or larger, and the size of -15- (11) (11) 589724 or the semiconductor wafer 4 is particularly large, such as 6 In the case of square meters or larger. Further, as shown in FIG. 4, a second semiconductor wafer can be stacked on the first semiconductor wafer 4a, and the second semiconductor wafer 4b is passed through the first semiconductor wafer 4a and the conductive connector. The second semiconductor wafer 4 b is connected to the substrate 1 through the conductive portion 9 formed by the component 2 and connected to the substrate 1 as shown in FIG. 5. In the semiconductor device shown in FIG. 5, 'this younger semiconductor wafer 4b is arranged on the first semiconductor wafer 4a with an adhesive layer 7b interposed therebetween, and is borrowed from a second wire 8 b is connected to the substrate 1 ′, and the first line 8 b may be formed by a gold wire having a diameter of about 28 μm. Fig. 6 is a cross-sectional view depicting a semiconductor device according to another embodiment of the present invention. In the semiconductor device shown in FIG. 6, a semiconductor wafer 4 is mounted on the substrate 1 through an adhesive layer 7, and the semiconductor wafer 4 is electrically connected using a gold wire 8 having a diameter of 28 microns or less. Terminals for wiring circuits (not shown) on the substrate. As for the material of the substrate 1, the same materials as those described above can be used. The sealant resin layer 5 is disposed on the top surface and side surfaces of the semiconductor wafer 4 and on the top surface of the substrate 1. The sealant resin layer 5 can be used to harden a molding resin composition formed of inorganic materials and carbon black to satisfy the conditions already described above. In the semiconductor device shown in FIG. 6, in order to minimize the total thickness of the semiconductor device, the thickness of the portion of the sealing resin layer 5 relative to the substrate 1 is limited to -16- (12) (12) 589724 0.2 mm or more. small. In this example, the thickness of the sealant resin layer 5 portion disposed on the semiconductor wafer 4 is limited to 0.2 mm or less. In the example of a conventional semiconductor device in which a semiconductor wafer is connected to a substrate through a wire, the wire is deformed by a shearing effect caused by a molding resin composition during a sealing process. In this example, the wires are in contact with each other, thereby causing electrical failure of the semiconductor device. However, in the example of the semiconductor device shown in FIG. 6, the semiconductor device is sealed with a molding resin composition having excellent fluidity and moldability, so that the wire can be prevented from being deformed. The semiconductor device shown in FIG. 6 can be constructed as a two-layer structure as shown in FIGS. 4 and 5. Figures 7 and 8 depict examples of this modification. The semiconductor device shown in Fig. 7 is constructed in the same manner as the semiconductor device shown in Fig. 4, except that the first semiconductor wafer 4a is connected to the substrate 1 via a line 8a. The semiconductor device shown in Fig. 8 can also be constructed in the same manner as the semiconductor device shown in Fig. 5, except that the first semiconductor wafer 4a is connected to the substrate 1 via a line 8a. As shown in Figs. 5 and 8, the second line 8b arranged to connect the second semiconductor wafer 4b to the substrate 1 is longer than the first line 8a. Since the molding resin composition excellent in fluidity is used in the embodiment of the present invention, even this long wire can be prevented from being deformed. Incidentally, a third semiconductor wafer may be laminated on the second semiconductor wafer 4b to make it a three-layer structure. The present invention can be modified in various ways within its spirit. Additional advantages and amendments will immediately arise from those familiar with this technology, so the invention in its broader perspective is not limited to those shown and described in this -17- (13), 724 Specific details and representative embodiments. Therefore, a variety of amendments can be completed without departing from the spirit and scope of the general concept of invention as defined by the scope of patent applications in the appendix and its equivalents. [Schematic description] Figure 1 is a cross-sectional view depicting a semiconductor device according to conventional technology;
第2圖係橫截面視圖，描繪根據本發明一實施例之半 導體裝置； 第3圖係橫截面視圖，描繪根據本發明另一實施例之 半導體裝置； 第4圖係橫截面視圖，描繪根據本發明另一實施例之 半導體裝置； 第5圖係橫截面視圖，描繪根據本發明另一實施例之 半導體裝置；FIG. 2 is a cross-sectional view depicting a semiconductor device according to an embodiment of the present invention; FIG. 3 is a cross-sectional view depicting a semiconductor device according to another embodiment of the present invention; FIG. 4 is a cross-sectional view depicting a semiconductor device according to the present invention; FIG. 5 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention;
第6圖係橫截面視圖，描繪根據本發明一實施例之半 導體裝置； 第7圖係橫截面視圖，描繪根據本發明另一實施例之 半導體裝置； % 8圖係橫截面視圖’描繪根據本發明另一實施例之 半導體裝置。 主要元件對照表 基板 -18- 1 (14)589724 2 導 電 性 連 接 器 構件 2a，2b 凸 塊 4 半 導 骨扭 晶 片 4 a 第 一 半 導 體 晶 片 5 造 模 樹 脂 層 6 端 子 7 黏 著 層 7a，7b 黏 著 層 8 金 線 8 a 第 一 線 9 貫 穿 導 電 性 部 分 4b 第 二 半 導 體 晶 片 8b 第 一 線 -19-FIG. 6 is a cross-sectional view depicting a semiconductor device according to an embodiment of the present invention; FIG. 7 is a cross-sectional view depicting a semiconductor device according to another embodiment of the present invention; Invented a semiconductor device according to another embodiment. Main components comparison table substrate-18-1 (14) 589724 2 Conductive connector members 2a, 2b Bumps 4 Semi-conductive bone twisted wafers 4 a First semiconductor wafer 5 Molding resin layer 6 Terminals 7 Adhesive layers 7a, 7b Adhesive Layer 8 Gold wire 8 a First wire 9 penetrates the conductive portion 4b Second semiconductor wafer 8b First wire -19-