TW200306654A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW200306654A
TW200306654A TW092107022A TW92107022A TW200306654A TW 200306654 A TW200306654 A TW 200306654A TW 092107022 A TW092107022 A TW 092107022A TW 92107022 A TW92107022 A TW 92107022A TW 200306654 A TW200306654 A TW 200306654A
Authority
TW
Taiwan
Prior art keywords
semiconductor
substrate
semiconductor wafer
less
inorganic filler
Prior art date
Application number
TW092107022A
Other languages
Chinese (zh)
Other versions
TW589724B (en
Inventor
Kaoru Kawai
Masatoshi Fukuda
Original Assignee
Toshiba Corp
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Filing date
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Priority to JP2002090393 priority Critical
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of TW200306654A publication Critical patent/TW200306654A/en
Application granted granted Critical
Publication of TW589724B publication Critical patent/TW589724B/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

Disclosed is a semiconductor device comprising: a substrate; a first semiconductor chip having a thickness of 0.25 mm or less and mounted on the substrate through flip chip connection with a gap of 0.055 mm or less; a conductive connector member electrically connecting the chip to the substrate; and a molding resin layer covering the chip and formed of a cured resin composition comprising 75-92% by weight of an inorganic filler and 0.5-1.5% by weight of carbon black, a portion of the molding resin layer opposite to the substrate having a thickness of 0.15 mm or less, 99 wt% of the filler having longest diameter of 35 μ m or less, the average longest diameter of the filler being 15 μ m or less, and the content of fine filler having a longest diameter of 10 μ m or less is within the range of 30-50% by weight based on the entire weight of the filler.

Description

200306654 (1) (ii) Contrast of related applications of invention description This application is based on and claims the right of priority of the previous Japanese Patent Application No. 2002- 09〇3 93 filed on March 28, 2002. ; The entire contents of which are incorporated herein by reference. [Technical field to which the invention belongs] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor wafer is sealed with a sealing resin. [Previous Technology] In recent years, in the field of maintaining semiconductor technology with respect to semiconductor integrated circuits with integrated properties and enhanced reliability, efforts have been made to further miniaturize and make semiconductor devices thinner. Densely completed. To meet this trend, there is currently a growing demand for sealant resins that are superior in development properties. In the conventional flip-chip type QON (quadrilateral outline leadless package), a semiconductor wafer 4 is mounted on the surface of a substrate 1 via a conductive connector member 2 as shown in Fig. 1. The substrate 1 in this example is made of resin or ceramics, and a wiring circuit (not shown) is arranged on the surface. The substrate 1 is also provided with a terminal 6 on the lower side for external connection. . The conductive connector member 2 is constructed by a bump 2a for a wiring circuit terminal of the substrate 1 and a bump 26 for a semiconductor wafer, and these bumps are formed of, for example, gold or solder. -6-(2) (2) 200306654 The sealing resin layer 5 is arranged on the top surface and side surfaces of the semiconductor wafer 4 and in the space or gap between the crystals of the substrate 1 and the semiconductor wafer 4. The sealing resin layer 5 may be The substrate 1 having the semiconductor wafer 4 mounted thereon is integrally sealed by molding the resin composition. Because the space or gap between the substrate 1 and the semiconductor wafer 4 is considerably smaller than the distance between the mold and the semiconductor wafer 4, the gap is more likely when the substrate 1 is completely sealed using the molding resin composition. Ground is created in the above-mentioned space or gap. At the same time, the technology for making the body of a semiconductor device thinner has progressed in recent years, so that the thickness of the sealant resin layer 5 is inevitably made thinner. Therefore, there have been problems that it is difficult to perfectly arrange a molding resin composition on the top surface of the semiconductor device 4 during the sealing process of the semiconductor device using the molding resin composition, and it is difficult to synthesize the molding resin with the molding resin. Objects fill the above-mentioned spaces or gaps, thereby increasing the possibility of creating voids there. In particular, if a void exists in the space between the substrate 1 and the semiconductor wafer 4, the semiconductor wafer 4 is subjected to a pressure applied when the space is filled with a molding resin composition. As a result, the central portion of the semiconductor wafer 4 will be pressed downward, thereby causing cracks in the semiconductor wafer 4. The resin layer is peeled from the void and cracks are generated, thereby deteriorating the long-term reliability of the semiconductor device. It is possible to suppress the generation of voids by increasing pressure and temperature when filling the space with a molding resin composition. However, the semiconductor wafer may be removed due to the pressure used for the filling, or may be melted due to the high temperature. These problems are the cause of greatly deteriorating the reliability of the semiconductor device. -7- (3) (3) 200306654 [Summary] A semiconductor device according to an embodiment of the present invention includes a substrate; a first semiconductor wafer is mounted on the g-board through a flip-chip connection ^: on the 'the first The semiconductor wafer is spaced apart from the substrate by 0.055 mm or more, and the distance is' the first semiconductor wafer has a thickness of 0.25 mm or less; a conductive connector member electrically connected to the first semiconductor wafer; On the substrate; and a molding resin layer disposed on the substrate to cover the first semiconductor wafer, and synthesized from a hardening resin containing 75 to 92 weight percent of inorganic filler and 0.5 to 1.5 weight percent of carbon black Some of the inorganic fillers have a thickness of 0.1 5 mm or less relative to the molding resin layer of the substrate, and 99% by weight of the inorganic filler has a longest diameter of 35 microns or less. The content of fine fillers with a diameter of 15 microns or less and a longest diameter of 10 microns or less is limited to the range of 30 to 50 weight percent based on the total weight of the inorganic filler . A semiconductor device according to another embodiment of the present invention includes a substrate; a first semiconductor wafer mounted on the substrate; a first wiring having a diameter of 28 microns or less and electrically connecting the first semiconductor wafer to The substrate; and a molding resin layer disposed on the substrate to cover the first semiconductor wafer, and comprising 75 to 92 weight percent of an inorganic filler and 0.5 to 1.5 -8- (4) (4 ) 200306654 weight percent of carbon black hardened resin composition, a portion of which has a thickness of 0.2 mm or less relative to the substrate's molding resin layer, and 9 9 weight percent of the inorganic filler has 35 microns or less The smallest longest diameter, the average longest diameter of the inorganic filler is 15 microns or less, and the content of the fine filler having a longest diameter of 10 microns or less is limited depending on the overall weight of the inorganic filler Within the range of 30 to 50 weight percent. [Embodiment] An embodiment according to the present invention will be explained in detail with reference to the drawings as follows. FIG. 2 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. In the semiconductor device shown here, a semiconductor wafer 4 is mounted on a surface of a substrate 1 via a conductive connector member 2, and the substrate 1 may be formed of a polyurethane tape or ceramic and has The terminal 6 is arranged on the lower side thereof for external connection. Although not shown in the drawing, the conductive connector member 2 is constructed of bumps for the semiconductor wafer 4 and bumps for the wiring circuit terminals of the substrate 1. The bumps can be made of tin / silver, for example. Solder, gold, tin / lead solder, tin, tin / silver / copper solder, tin / zinc solder, tin / bismuth solder or nickel. Terminals for external connection can be borrowed from tin / silver solder, tin / lead solder. Or formed by tin. The sealant resin layer 5 is disposed on the top surface and side surfaces of the semiconductor wafer 4, on the top surface of the substrate 1, and in the space between the substrate 1 and the semiconductor wafer 4. -9- (5) (5) 200306654 In the embodiment shown in FIG. 2, the height of the space between the substrate 1 and the semiconductor wafer 4 is 0.05 mm or less, and the thickness of the semiconductor wafer 4 is 0 2 5 mm or less. Further, the thickness of the sealant resin layer 5 with respect to the substrate is 0.15 mm or less. In this example, the thickness of the part of the sealant resin layer 5 disposed on the semiconductor wafer 4 is 0.15 mm or less. These dimensions are limited as described above in order to minimize the entire semiconductor device. Preferably, the entire height of the semiconductor device (measured from the distance from the terminal 6 for external connection to the molding resin layer 5) should be 0 500 mm or more small. Further preferably, a part of the sealing resin layer 5 disposed on the semiconductor wafer 4 should preferably limit the thickness to not more than 3 times the height of the space. In order to form the molding resin layer 5 and prevent voids from being generated in a narrow space as small as 0.05 mm or less, it is necessary to use a molding resin composition excellent in fluid moldability. Therefore, various discussions have been made by the present inventors in order to obtain an optimized molding resin composition. The molding resin composition contains an inorganic filler, an epoxy resin, a phenol resin, a hardening promoter, and carbon black. As for the epoxy resin, there is no specific limitation and therefore it may be selected from those having two or more epoxy groups per molecule, and a specific embodiment of this epoxy resin includes, for example, an o-cresol-phenolic lacquer type ring Oxygen resin, epoxy resin modified by dicyclopentadiene, triphenol methane epoxy resin, biphenyl epoxy resin, Epoxy-bis (bis) epoxy resin, etc. The epoxy resin can be used singly or in combination. As for the present phenol resin, there is no specific limitation, as long as there are -10- (6) (6) 200306654 two or more kinds of epoxy groups that can react with the epoxy resin The phenolic hydroxyl group is sufficient. Specific examples of this phenol resin include, for example, a phenol-phenolic lacquer resin, a phenol benzoaralkyl resin, a naphthol aralkyl resin, and a phenol resin modified with dicyclopentadiene. The epoxy resin may be used singly or in combination. As for the hardening co-catalyst, different kinds of hardening co-catalysts such as phosphorus hardening co-catalyst, imidazole hardening co-catalyst, DBU type hard-co-catalyst, etc. Individually or in groups The mixing ratio of these hardening accelerators should preferably be in the range of 0.01 to 5 weight percent based on the entire weight of the resin composition. If the mixing ratio is less than 0.01 weight percent, the cementing time of the resin composition It will be prolonged, and at the same time, the hardening properties of the resin composition will be deteriorated. On the contrary, if the mixing ratio exceeds 5 weight percent, the fluidity of the resin composition will be extremely deteriorated, so electrical properties and molding resin may be caused The degradation of the layer's humidity resistance. Carbon black is incorporated here to prevent semiconductor wafers from being defective due to light transmission, so that carbon black can be any type commonly used as a sealing or sealing material. The fluidity of the resin composition is highly dependent on the type of inorganic filler to be combined. For comparison purposes, the eight molding resin compositions shown in Table 1 below use different types of fused silica as inorganic The filling material is prepared. Next, the semiconductor device shown in FIG. 2 is manufactured using each of these molding resin compositions. In this example In the review, the filling properties of these molding resin compositions entering the space between the substrate 1 and the semiconductor wafer 4. In this evaluation, the molding resin compositions in which no voids were generated in the space are shown in Table-11. -(7) 200306654 is shown as 、, 〇〃, and the molding resin composition in which voids are generated in the space is expressed as > X 。. Incidentally, at least 30 samples are inspected and the voids are defined as longer The diameter is 0020 mm or greater. Table 1 Resin Configuration Longest Diameter Average Diameter Content Filling Number (Micron) (Micron) (Weight Percent) Properties 1 Crushed 105 30 86 X 2 Spherical 75 16 86 X 3 spherical 75 9 86 X 4 spherical 75 6 86 X 5 spherical 75 6 82 X 6 spherical 3 5 9 86 〇7 spherical 3 5 6 86 〇 8 spherical 3 5 6 82 〇 The longest diameter means the length of the longest portion of the inorganic filler particles, and the average diameter means the average diameter of the longest diameter of the filler particles. As shown in Table 1, the molding resin compositions shown in Resin Nos. 6, 7 and 8 are excellent in filling properties. Therefore, inorganic fillers useful in the examples of the present invention are defined as having a longest diameter of 35 microns or less and an average diameter of 15 microns or less. Incidentally, in the embodiment of the present invention (12) (8) (8) 200306654, 99% by weight or more of the inorganic filler particles are required to satisfy the above-mentioned conditions regarding the longest diameter. More desirably, the content of the inorganic filler particles satisfying the above conditions is 99.9% by weight or more, and most preferably 99.99% by weight or more. Among the fused silicas used in these resins Nos. 6, 7 and 8, the proportion of fillers having the longest diameter of 10 microns or less is limited to 30 based on the molten sand and gravel. Within the range of 50 weight percent. It has further been found that when the content of the inorganic filler is less than 75% by weight, the reflow resistance and packaging reliability of the semiconductor device may be deteriorated. On the other hand, it was found that limiting the upper limit of the inorganic filler content to 92% by weight would facilitate the manufacture of the molding resin. According to the above conditions, the inorganic fillers incorporated in the molding resin composition used in the examples of the present invention are limited to the following characteristics (1) its longest diameter is 35 microns or less; (2) its The average diameter is 15 microns or less; (3) the content of fine fillers with the longest diameter of 10 microns or less is limited to the range of 30 to 50 weight percent; and (4) the content of inorganic fillers It is limited to the range of 75 to 92 weight percent. In the above explanation, the fused silica series is described as an example of an inorganic filler. However, as long as the above conditions are met, crushed silica or the like may be used. Among them, the mold filling resin composition in which the properties of the inorganic filler as defined above are included is excellent in fluidity and moldability. Therefore, -13- (9) (9) 200306654 The molding resin composition defined above can be easily introduced into a narrow space when the entire resin sealing is performed, thereby suppressing the generation of voids. In addition, since the generation of voids can be suppressed in this way, cracks in the wafer due to the pressure applied when the narrow space is filled with the molding resin composition can be prevented, and the reliability of the semiconductor device to be manufactured can be enhanced. In addition, a semiconductor device that is miniaturized in thickness can be manufactured, and peeling of the resin layer does not occur, so the long-term reliability of the semiconductor device can be improved. In addition, because the molding resin composition defined above is excellent in fluidity, there is no need to increase the pressure of the resin composition during the sealing of the semiconductor. Therefore, the semiconductor device is not affected by the resin filling. The pressure used in the 塡 is discharged. Further, in the embodiment of the present invention, the content of carbon black incorporated in the molding resin composition is defined within the range of 0.5 to 1.5 weight percent. This range in carbon black is defined as follows. Several kinds of molding resin composites are prepared by varying the content of carbon black, and then semiconductor devices are manufactured by using each of these molding resin compositions, and the light transmittance of the generated semiconductor devices is measured. In this example, the total height of the semiconductor is set to 0.450 mm and the wavelength of light is limited to the range of 1000 to 2000 nm. As a result, the light transmittance of the semiconductor device encapsulated by using a molding resin containing 0. 50% by weight or more was obtained as 0.20% or less. Incidentally, it can be confirmed that as long as the light transmittance of the semiconductor device is limited to 0.20% or less, the occurrence of defects in the semiconductor device can be substantially prevented. In addition, the volume resistivity of the molding resin composition can also be kept at -14-(10) (10) 200306654 1 ohm · cm at room temperature. On the contrary, if the content of carbon black exceeds 1.5% by weight, the volume resistivity of the molding resin composition may be deteriorated, thereby causing a defect in the semiconductor device to be manufactured. Therefore, the upper limit in the carbon black content should be limited to 1.5 weight percent. The content of carbon black is limited to the range of 0.50 to 1.5 weight percent in order to suppress the light transmittance and prevent the occurrence of defects in the semiconductor device, even in the case where the resin sealant system is performed relatively thinly. Since the inorganic filler and carbon black are included in the molding resin composition in the same manner as described above, the semiconductor device according to the embodiment of the present invention is excellent in reliability, and at the same time, due to the light transmittance The defects can be prevented. That is, the molding resin layer in the semiconductor device according to the embodiment of the present invention is formed by hardening an inorganic filler containing 75 to 92 weight percent of inorganic filler and 0.5 to 1.5 weight percent of carbon black. Formed from a molding resin composition. In particular, 99% by weight of the inorganic filler has a longest diameter of 35 micrometers or less, and the average longest diameter of the inorganic filler is 15 micrometers or less, and has a longest diameter of 0 micrometers or less. The fine charge content is limited to a range of 30 to 50 weight percent based on the entire weight of the inorganic charge. The semiconductor device shown in FIG. 2 can be modified variably. For example, as shown in FIG. 3, the adhesive layer 7 may be interposed between the substrate 1 and the semiconductor wafer 4, and the adhesive layer 7 interposed between the substrate 1 and the semiconductor wafer 4 functions to reduce internal stress. Therefore, the configuration of the adhesive layer is particularly effective in that the size of the semiconductor device is particularly large, such as 7 mm square or larger, and the size of -15- (11) (11) 200306654 or the semiconductor wafer 4 is particularly large, such as 6 Mm square or larger example. Further, as shown in FIG. 4, a second semiconductor wafer 4 b may be laminated on the first semiconductor wafer 4 a. The second semiconductor wafer 4 b is passed through the first semiconductor wafer 4 a and the conductive connector. The member 2 is connected to the substrate 1 through the conductive portion 9. As shown in Fig. 5, this second semiconductor wafer 4b can be connected to the substrate 1 via a line. In the semiconductor device shown in FIG. 5 'the second semiconductor wafer 4b is disposed on the first semiconductor wafer 4a with an adhesive layer 7b interposed therebetween, and is connected by a second wire 8b On the substrate 1, the second line 8b can be formed by a gold line having a diameter of about 28 microns. Fig. 6 is a cross-sectional view depicting a semiconductor device according to another embodiment of the present invention. In the semiconductor device shown in FIG. 6, a semiconductor wafer 4 is mounted on the substrate 1 through an adhesive layer 7, and the semiconductor wafer 4 is electrically connected using a gold wire 8 having a diameter of 28 microns or less. Terminals for wiring circuits (not shown) on the substrate. As for the material of the substrate 1, the same materials as those described above can be used. The sealant resin layer 5 is disposed on the top surface and side surfaces of the semiconductor wafer 4 and on the top surface of the substrate 1. This sealant resin layer 5 can be used to harden a molding resin composition formed of inorganic materials and carbon black to meet the conditions already described above. In the semiconductor device shown in FIG. 6, in order to minimize the total thickness of the semiconductor device, the thickness of the portion of the sealing resin layer 5 with respect to the substrate 1 is limited to -16- (12) (12) 200306654 0.2 mm or more small. In this example, the thickness of the sealant resin layer 5 portion disposed on the semiconductor wafer 4 is limited to 0.2 mm or less. In the example of a conventional semiconductor device in which a semiconductor wafer is connected to a substrate through a wire, the wire is deformed by a shearing effect caused by a molding resin composition during a sealing process. In this example, the wires are in contact with each other, thereby causing electrical failure of the semiconductor device. However, in the example of the semiconductor device shown in FIG. 6, the semiconductor device is sealed with a molding resin composition having excellent fluidity and moldability, so that the wire can be prevented from being deformed. The semiconductor device shown in Fig. 6 can be constructed as a two-layer structure as shown in Figs. 4 and 5. Figures 7 and 8 depict examples of this modification. The semiconductor device shown in Fig. 7 is constructed in the same manner as the semiconductor device shown in Fig. 4, except that the first semiconductor wafer 4a is connected to the substrate 1 via a line 8a. The semiconductor device shown in FIG. 8 can also be constructed in the same manner as the semiconductor device shown in FIG. 5, except that the first semiconductor wafer 4a is connected to the substrate 1 via a line Sa. As shown in Figs. 5 and 8, the first line 8b of the semiconductor wafer 4b on the substrate 1 is arranged to be longer than the first * line 8a. Since the molding resin composition excellent in fluidity is used in the embodiment of the present invention, even this long wire can be prevented from being deformed. Incidentally, a third semiconductor wafer may be laminated on the second semiconductor wafer 4b to make it a three-layer structure. The present invention can be modified in various ways within its spirit. Additional advantages and amendments will immediately arise from those familiar with this technology, so the invention in its broader perspective is not limited to those shown in this -17- (13) (13) 200306654 text and Specific details as well as representative examples. Therefore, various amendments can be completed without departing from the spirit and scope of the general concept of invention as defined by the scope of patent applications in the appendix and its equivalents. [Brief description of the drawings] FIG. 1 is a cross-sectional view depicting a semiconductor device according to a conventional technology; FIG. 2 is a cross-sectional view 'illustrating a semiconductor device according to an embodiment of the present invention; FIG. 3 is a cross-sectional view' FIG. 4 illustrates a semiconductor device according to another embodiment of the present invention; FIG. 4 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention; FIG. 5 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention; Device; FIG. 6 is a cross-sectional view depicting a semiconductor device according to an embodiment of the present invention; FIG. 7 is a cross-sectional view depicting a semiconductor device according to another embodiment of the present invention; A semiconductor device according to another embodiment of the present invention. Main component comparison table 1 Base plate-18- (14) 200306654 (14)

2 Conductive connector member 2a, 2b Bump 4 Semiconductor wafer 4 a First semiconductor wafer 5 Molding resin layer 6 Terminal 7 Adhesive layer 7a, 7b Adhesive layer 8 Gold wire 8 a First line 9 Passes through the conductive portion 4b Two semiconductor wafers 8b Second line

-19-

Claims (1)

  1. (1) (1) 200306654 Patent application scope 1 A semiconductor device including a substrate; a first semiconductor wafer is mounted on the substrate through a flip-chip connection, the first semiconductor wafer is spaced from the substrate 0 05 at a distance of 5 mm or less, the first semiconductor wafer has a thickness of 205 mm or less; a conductive connector member electrically connecting the first semiconductor wafer to the substrate; and a molding resin A layer disposed on the substrate to cover the first semiconductor wafer, and a portion formed of a hardened resin composition containing 75 to 92 weight percent of inorganic filler and 0.5 to 1.5 weight percent of carbon black relative to The molding resin layer of the substrate has a thickness of 0.15 mm or less, and the 99% by weight inorganic filler has a longest diameter of 35 microns or less, and the average longest diameter of the inorganic filler is 15 microns or less. The content of the fine filler, which is small and has a longest diameter of 10 micrometers or less, is limited to the range of 30 to 50 weight percent depending on the overall weight of the inorganic filler. 2. The semiconductor device according to item 1 of the patent application scope, further comprising a molding resin layer interposed between the substrate and the first semiconductor wafer, and comprising 75 to 92% by weight of an inorganic filler and 0.5 To 1.5% by weight of a carbon black hardened resin composition, 99% by weight of an inorganic filler having a longest diameter of 35 microns or less. The average longest diameter of the inorganic filler is 15 microns or less, And, the content of the fine filler having a longest diameter of 10 micrometers or less is limited to the range of 30 to 50 weight percent according to the overall weight of the inorganic filler. -20- (2) (2) 200306654 3 The semiconductor device according to item 1 of the patent application scope further includes an adhesive layer interposed between the substrate and the first semiconductor wafer. 4. The semiconductor device according to item 1 of the scope of patent application, wherein a portion of the molding resin layer disposed on the first semiconductor wafer has a thickness that is not greater than a distance between the substrate and the first semiconductor wafer. three times. 5. The semiconductor device as claimed in claim 1, wherein the conductive connector member is formed of a material containing tin / silver solder. 6. The semiconductor device as claimed in claim 1, wherein the conductive connector member is formed of a material containing gold. 7. The semiconductor device as claimed in claim 1, wherein the conductive connector member is formed of a material including tin / lead solder. 8. The semiconductor device as claimed in claim 1, wherein the conductive connector member is formed of a material including tin, tin / silver / copper solder, tin / zinc solder, tin / bismuth solder, or nickel. 9. The semiconductor device according to item 1 of the scope of patent application, further comprising a second semiconductor wafer disposed on the first semiconductor wafer, the second semiconductor wafer is electrically connected to the substrate and is connected to the first semiconductor wafer. The semiconductor wafers are covered by the resin. 10. The semiconductor device according to item 1 of the patent application scope, wherein the second semiconductor wafer is electrically connected to the substrate through a bump. 1 1 · The semiconductor device according to item 9 of the patent application scope, wherein the second semiconductor wafer is electrically connected to the substrate through a wiring. 1 2 · The semiconductor device according to item 丨 丨 of the application, wherein the wiring is formed of a material containing gold. -21-(3) (3) 200306654 13. The semiconductor device according to item 12 of the patent application scope, wherein the wiring has a diameter of 28 microns. 14. A semiconductor device comprising a substrate; a first semiconductor wafer mounted on the substrate; a first wiring having a diameter of 28 microns or less and electrically connecting the first semiconductor wafer to the substrate; and A molding resin layer is disposed on the substrate to cover the first semiconductor wafer, and is formed of a hardened resin composition containing 75 to 92 weight percent of inorganic filler and 0.5 to 1.5 weight percent of carbon black. Relative to the substrate, the molding resin layer has a thickness of 0.2 mm or less, 99 weight percent of the inorganic filler has a longest diameter of 35 microns or less, and the average longest diameter of the inorganic filler is 15 microns or less The content of the fine filler, which is small and has the longest diameter of 10 micrometers or less, is limited to the range of 30 to 50 weight percent depending on the overall weight of the inorganic filler. 15. The semiconductor device according to item 14 of the application, further comprising an adhesive layer interposed between the substrate and the first semiconductor wafer. 16. The semiconductor device according to item 14 of the scope of patent application, further comprising a second semiconductor wafer disposed on the first semiconductor wafer. The second semiconductor wafer is electrically connected to the substrate and is connected to the first semiconductor wafer. A semiconductor wafer is collectively covered with the molding resin. 17. The semiconductor device as claimed in claim 16 in which the second semiconductor wafer is electrically connected to the substrate through a bump. 1 8. The semiconductor device according to item 16 of the scope of patent application, wherein the second -22- (4) 200306654 semiconductor wafer is electrically connected to the substrate through two wires. 19. The semiconductor device as claimed in claim 18, wherein the second-type wiring is formed of a material containing gold. 20. The semiconductor device according to claim 19, wherein the second wiring has a diameter of 28 micrometers. -twenty three-
TW092107022A 2002-03-28 2003-03-26 Semiconductor device TW589724B (en)

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Application Number Priority Date Filing Date Title
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TW589724B TW589724B (en) 2004-06-01

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