JP3846890B2 - Semiconductor device - Google Patents

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JP3846890B2
JP3846890B2 JP2004031161A JP2004031161A JP3846890B2 JP 3846890 B2 JP3846890 B2 JP 3846890B2 JP 2004031161 A JP2004031161 A JP 2004031161A JP 2004031161 A JP2004031161 A JP 2004031161A JP 3846890 B2 JP3846890 B2 JP 3846890B2
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resin
semiconductor chip
semiconductor device
bump
wiring board
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JP2004134821A (en
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浩 山田
隆 栂嵜
雅之 斉藤
荘一 本間
三樹 森
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Toshiba Corp
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    • HELECTRICITY
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
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    • H01L2224/731Location prior to the connecting process
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    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/73203Bump and layer connectors
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    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/83102Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
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    • H01L2224/83104Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
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    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/8319Arrangement of the layer connectors prior to mounting
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    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
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    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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    • H01L2924/151Die mounting substrate
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus having an improvement in reliability by preventing the occurrence of bubbles from resin disposed in a gap between a semiconductor device and a circuit board. <P>SOLUTION: The semiconductor apparatus has a circuit board and a semiconductor device mounted on the board through bump electrodes, wherein resin is disposed in a gap between the circuit board and the semiconductor device, and around the semiconductor device. The bump electrodes are formed along the circumference of the semiconductor device, and a concave portion is formed in an area surrounded by the bump electrodes on the surface of the circuit board. <P>COPYRIGHT: (C)2004,JPO

Description

本発明は半導体装置に係り、特にバンプ電極部分の接続信頼性を高くするために、半導体チップと回路配線基板の隙間部分に樹脂を封入したフリップチップ構造の半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a flip chip structure semiconductor device in which a resin is sealed in a gap portion between a semiconductor chip and a circuit wiring board in order to increase connection reliability of a bump electrode portion.

近年、半導体装置は高集積化に伴って、実装技術も高密度化が求められており、ワイヤボンディング技術、TAB技術などに加えて、図18に示すようなフリップチップ実装技術(米国特許第3,401,126号公報、および米国特許第3,429,040号公報等)が、コンピュータ機器などの分野で広く用いられている。   2. Description of the Related Art In recent years, semiconductor devices have been required to have higher mounting density with higher integration. In addition to wire bonding technology, TAB technology, and the like, a flip chip mounting technology (US Pat. No. 3) as shown in FIG. , 401, 126 and U.S. Pat. No. 3,429,040) are widely used in the field of computer equipment and the like.

一般的に、半導体チップの熱膨張係数と回路配線基板の熱膨張係数とは異なるので、半導体チップの動作中に発生した熱が、バンプ電極を通して回路配線基板に伝達して熱膨張係数の違いに起因する変位が半導体チップと回路配線基板に発生する。発生した変位は、半導体チップと回路配線基板を接続するバンプ電極に応力歪みを発生させ、この応力歪みは、バンプ電極を破壊させることになり、結果として装置の信頼性寿命を低下させてしまう(Microelectronic Packaging Handbook(Van Nostrand Reinhold,1989”)。   Generally, since the thermal expansion coefficient of a semiconductor chip and the thermal expansion coefficient of a circuit wiring board are different, the heat generated during the operation of the semiconductor chip is transferred to the circuit wiring board through bump electrodes, resulting in a difference in thermal expansion coefficient. The resulting displacement occurs in the semiconductor chip and the circuit wiring board. The generated displacement generates a stress strain in the bump electrode connecting the semiconductor chip and the circuit wiring board, and this stress strain destroys the bump electrode, resulting in a decrease in the reliability life of the device ( Microelectronic Packaging Handbook (Van Nostrand Reinhold, 1989 ").

なお、信頼性寿命は、Nf=Cf1/3 γmax ・exp(1428/Tmax)
(Cは定数、fは周波数、Tmaxは最大温度である。)で表されるサイクル寿命の式から、バンプ部分に発生する最大剪断歪みγmax を減少させることにより信頼性寿命が向上することが知られている(IBM J.Res.Develop.,13;251(1969))。
The reliability life is Nf = Cf 1/3 γ max · exp (1428 / Tmax)
(C is a constant, f is a frequency, and Tmax is a maximum temperature.) From the formula of the cycle life expressed by the formula, the reliability life can be improved by reducing the maximum shear strain γ max generated in the bump portion. (IBM J. Res. Develop., 13; 251 (1969)).

ここで、バンプ電極に発生する最大剪断歪みは以下の式で表される。   Here, the maximum shear strain generated in the bump electrode is expressed by the following equation.

γmax ={1/(Dmin /2)2/β }(V/πh1+β1/β ・d・ΔT・Δα
(Dmin;最小バンプ径,β;材料定数,V;はんだ体積,h;はんだ高さ,Δα;熱膨張係数の差,ΔT;温度差,d;チップ中心からバンプ中心までの距離)
したがって、従来のフリップチップ実装技術においては、以下に挙げるような手段を用いてバンプ電極に発生する応力を低減させてきた。すなわち、(1)半導体チップの中心からバンプ電極の中心までの距離を小さくする、(2)半導体チップの熱膨張係数と回路配線基板の熱膨張係数との差を小さくする、(3)接続部の温度差が大きくならないように装置の放熱性を向上させる、(4)発生する応力歪みを充分に吸収できるように、バンプ電極の構造を改良する等の手段である。
γ max = {1 / (Dmin / 2) 2 / β } (V / πh 1 + β ) 1 / β · d · ΔT · Δα
(Dmin: minimum bump diameter, β: material constant, V: solder volume, h: solder height, Δα: thermal expansion coefficient difference, ΔT: temperature difference, d: distance from chip center to bump center)
Therefore, in the conventional flip chip mounting technology, the stress generated in the bump electrode has been reduced by using the following means. (1) The distance from the center of the semiconductor chip to the center of the bump electrode is reduced. (2) The difference between the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the circuit wiring board is reduced. And (4) improving the structure of the bump electrode so that the generated stress strain can be sufficiently absorbed.

さらに、図19に示すように半導体チップ72と回路配線基板71との間隙およびチップの周囲に樹脂78を注入する方法、および、半導体チップをシリコンゲルなどで封止することによって、耐湿性の向上を図るとともに、バンプ電極部分に加わる応力を軽減してサイクル寿命を低下させない構造を得ることが提案されている。   Further, as shown in FIG. 19, the method of injecting resin 78 into the gap between the semiconductor chip 72 and the circuit wiring board 71 and the periphery of the chip, and sealing the semiconductor chip with silicon gel or the like improves the moisture resistance. In addition, it has been proposed to obtain a structure that reduces the stress applied to the bump electrode portion and does not reduce the cycle life.

しかしながら、半導体チップと回路配線基板の隙間を充填する実装方法(特開昭57−208149号公報、実開昭58−18348号公報)では、樹脂の物性が特定されていないため、接続バンプ部分の破壊が加速されることがあった。また、樹脂の充填をスムーズに行うためにガラス基板に孔を開け、この孔部分から樹脂を充填する方法(実開昭58−18348号公報、特開昭58−103143号公報等)では、熱サイクルストレスに起因して基板に設けられた孔周辺にクラックが発生することは明らかであり、実用上問題があるとともに、バンプ接続部分の信頼性を保証できるものではなかった。   However, the mounting method for filling the gap between the semiconductor chip and the circuit wiring board (Japanese Patent Laid-Open No. 57-208149, Japanese Utility Model Laid-Open No. 58-18348) does not specify the physical properties of the resin. Destruction was sometimes accelerated. In addition, in order to smoothly fill the resin, a method of filling a hole in the glass substrate and filling the resin from the hole (Japanese Utility Model Laid-Open No. 58-18348, Japanese Patent Laid-Open No. 58-103143, etc.) It is clear that cracks are generated around the hole provided in the substrate due to the cycle stress, and there are practical problems and the reliability of the bump connection portion cannot be guaranteed.

このため、図20に示すように、半導体チップ72、回路配線基板71およびバンプ電極73で囲まれた領域81に樹脂を充填しないことによって、バンプ接続部の信頼性向上を図ることが提案された(特開昭58−204546号公報、特開昭57−208149号公報、特開昭58−134449号公報等)が、この場合には、間隙部分81に水分が堆積保持されて、バンプ電極73の腐食が発生するという問題があった。   For this reason, as shown in FIG. 20, it has been proposed to improve the reliability of the bump connection part by not filling the region 81 surrounded by the semiconductor chip 72, the circuit wiring board 71 and the bump electrode 73. (Japanese Patent Laid-Open Nos. 58-204546, 57-208149, 58-134449, etc.). There was a problem that corrosion occurred.

さらに、アレイバンプが形成されたはんだ接続点の少なくとも外側の1部分を封止して、中央部分のはんだ接続部分と隣接の上下面を誘電材料で埋め込まずに残すことにより凹凸形状になるアッセンブリ構造体の信頼性を向上させる方法(特開昭61−177738号公報)が提案されたが、熱膨張係数差が極めて大きい有機高分子基板の場合には、応力を十分に緩和することができなかった。   Further, an assembly structure is formed which has a concave-convex shape by sealing at least one portion outside the solder connection point where the array bump is formed and leaving the upper and lower surfaces adjacent to the solder connection portion in the center portion without being embedded with a dielectric material. A method for improving the reliability of the body (Japanese Patent Laid-Open No. 61-1777738) has been proposed. However, in the case of an organic polymer substrate having a very large difference in thermal expansion coefficient, the stress cannot be sufficiently relaxed. It was.

また、半導体チップと回路配線基板との間隙に軟質樹脂を充填する方法も開示されている(特開昭58−10841号公報)が、軟質樹脂の熱膨張係数が非常に大きいため、バンプ接続部分の熱サイクル寿命の向上は十分ではない。   Also, a method of filling a soft resin in the gap between the semiconductor chip and the circuit wiring board is disclosed (Japanese Patent Laid-Open No. 58-10841). However, since the thermal expansion coefficient of the soft resin is very large, the bump connection portion is also disclosed. The improvement of the thermal cycle life is not sufficient.

これらの問題を解決するために、樹脂の物性、組成等を選択してバンプ接続部分の熱サイクル寿命を向上させることが提案されており(特公平4−51057号公報、特開昭63−316447号公報、特開平4−219944号公報等)、比較的寸法の小さい半導体チップを実装する場合には、効果を発揮していた。   In order to solve these problems, it has been proposed to improve the thermal cycle life of the bump connection portion by selecting the physical properties and composition of the resin (Japanese Patent Publication No. 4-51057, Japanese Patent Laid-Open No. Sho 63-316447). In the case of mounting a semiconductor chip having a relatively small size, the effect was exhibited.

なお、半導体チップと回路配線基板との隙間に樹脂を配置する際には、半導体チップの表面または回路配線基板の半導体チップ搭載場所に予め樹脂を塗布し、半導体チップを回路配線基板に接続ボンディングする方法(特開平4−7447号公報、特開平2−234447号公報等)が代表的であり、封止樹脂をバンプ電極を除いた基板上の一部に適量を塗布後、半導体チップをアッセンブリ加圧して隙間全体に樹脂を配置して接続不良を避ける方法(特開昭62−132331号公報等)も提案されている。   When resin is placed in the gap between the semiconductor chip and the circuit wiring board, the resin is applied in advance to the surface of the semiconductor chip or the semiconductor chip mounting position of the circuit wiring board, and the semiconductor chip is connected and bonded to the circuit wiring board. Methods (Japanese Patent Laid-Open No. 4-7447, Japanese Patent Laid-Open No. 2-234447, etc.) are typical. After an appropriate amount of sealing resin is applied to a part of the substrate excluding the bump electrodes, the semiconductor chip is assembled. There has also been proposed a method (such as Japanese Patent Application Laid-Open No. Sho 62-132331) in which a resin is arranged in the entire gap to avoid poor connection.

さらに、半導体チップを回路配線基板にフリップチップ実装後、毛細管現象を利用して半導体チップと回路配線基板との隙間部分に樹脂を封止する方法(特開昭60−147140号公報、特開平3−18435号公報等)も行われており、この場合には、樹脂を硬化温度以下で加熱して樹脂粘度を下げることによって、20μm〜50μm程度の間隙への樹脂封止を可能にしている。   Further, after flip-chip mounting of the semiconductor chip on the circuit wiring board, a resin is sealed in a gap portion between the semiconductor chip and the circuit wiring board using a capillary phenomenon (Japanese Patent Laid-Open Nos. 60-147140 and 3). In this case, the resin is sealed in a gap of about 20 μm to 50 μm by lowering the resin viscosity by heating the resin below the curing temperature.

しかしながら、前述のように毛細管減少を利用して半導体チップと回路基板との間隙に樹脂を注入する場合には、半導体チップの寸法が大きくなるにつれて、樹脂の封入が困難となる。   However, when the resin is injected into the gap between the semiconductor chip and the circuit board by using capillary reduction as described above, it becomes difficult to encapsulate the resin as the size of the semiconductor chip increases.

なお、樹脂の注入速度は、V=1200h/(μL)で表わされる(hは間隙寸法(mm)、μは粘度(ポイズ)、Lは流入距離(mm)である)。すなわち、注入速度は、半導体チップと回路基板との距離(間隙寸法)に比例し、粘度と半導体チップの寸法に反比例するので、半導体チップの寸法が大きくなるにしたがって、樹脂の粘度を低下させる、または間隙寸法を大きくする等の対策をとる必要がある。 The injection rate of the resin is expressed by V = 1200 h / (μL) (h is the gap size (mm), μ is the viscosity (poise), and L is the inflow distance (mm)). That is, the injection speed is proportional to the distance (gap size) between the semiconductor chip and the circuit board, and inversely proportional to the viscosity and the size of the semiconductor chip, so that the resin viscosity decreases as the size of the semiconductor chip increases. It is also necessary to take measures such as increasing the gap size.

半導体チップと回路基板との熱膨張係数の差を小さくするためには、樹脂にフィラを混入する必要があるものの、フィラの混入によって樹脂の粘度は増加してしまう。一方、間隙寸法は接続後におけるバンプの高さに等しくなるが、接続時にはバンプが溶融して球状となるので、バンプ高さをバンプ直径以上に高くすることは不可能である。したがって、バンプの高さには限界があり、半導体チップと回路配線基板との距離を大きくして樹脂の封入を容易にすることも困難である。   In order to reduce the difference in coefficient of thermal expansion between the semiconductor chip and the circuit board, it is necessary to mix filler into the resin, but the viscosity of the resin increases due to the filler being mixed. On the other hand, the gap size is equal to the height of the bump after connection. However, since the bump melts into a spherical shape at the time of connection, it is impossible to make the bump height higher than the bump diameter. Therefore, there is a limit to the height of the bump, and it is difficult to increase the distance between the semiconductor chip and the circuit wiring board to facilitate resin encapsulation.

さらに、樹脂の注入速度は、図21に示すように、流入距離が大きくなると急激に低下する。なお、図21に示す曲線は、半導体チップと回路基板との距離(間隙寸法)を0.5mmとし、10〜100ポイズの5種類の粘度の樹脂について得た結果である。 Further, as shown in FIG. 21, the injection rate of the resin rapidly decreases as the inflow distance increases. The curves shown in FIG. 21 are the results obtained with respect to resins having five types of viscosity of 10 to 100 poise with the distance (gap size) between the semiconductor chip and the circuit board being 0.5 mm.

また、半導体チップと回路基板との間隙に樹脂を注入する際には、図22(a)〜(c)に示すように、樹脂86は、チップ84と基板83との間隙のみならず、チップ84の周囲をも進行する。樹脂の流れる速度は、チップの中央部と比較してチップの周辺で大きくなるので、最終的に図22(d)に示すように気泡87が発生するおそれがある。   Further, when the resin is injected into the gap between the semiconductor chip and the circuit board, the resin 86 is not limited to the gap between the chip 84 and the substrate 83, as shown in FIGS. Proceed around 84. Since the flow rate of the resin is larger in the periphery of the chip as compared with the center portion of the chip, there is a possibility that bubbles 87 are finally generated as shown in FIG.

さらに、特開昭63−245942では半導体チップ周囲にバンプを露出させたコーティング層を設け、半導体能動素子部分が凹部となる構造が提案されているが、この構造においては、バンプ接続部分での半導体チップと回路配線基板との間隙がバンプ高さ以下と狭くなり、樹脂の封入が困難になるという問題があった。   Further, Japanese Patent Laid-Open No. 63-245942 proposes a structure in which a bump is exposed around a semiconductor chip and a semiconductor active element portion is a recess. In this structure, the semiconductor at the bump connection portion is proposed. There was a problem that the gap between the chip and the circuit wiring board became narrower than the bump height, making it difficult to encapsulate the resin.

半導体チップと回路配線基板とを接続するバンプ電極に発生する応力を緩和するためには、熱膨張係数の小さい樹脂を、半導体チップと回路基板との間隙に配置することが好ましい。したがって、従来は、フィラの含有量を多くすることによって、熱膨張係数を小さくし弾性係数を大きくした樹脂を、半導体チップと回路配線基板との間隙に配置していた。水分遮蔽の目的からも、フィラの含有量は高い方が好ましく、さらに、フィラの粒径は大きい方がより水分遮蔽効果を発揮できる。   In order to relieve the stress generated in the bump electrode connecting the semiconductor chip and the circuit wiring board, it is preferable to dispose a resin having a small thermal expansion coefficient in the gap between the semiconductor chip and the circuit board. Therefore, conventionally, by increasing the filler content, a resin having a reduced thermal expansion coefficient and an increased elastic coefficient has been disposed in the gap between the semiconductor chip and the circuit wiring board. From the viewpoint of moisture shielding, it is preferable that the filler content is high, and that the larger the particle size of the filler, the better the moisture shielding effect.

しかしながら、近年、半導体チップの寸法が大きくなるにつれて、従来の樹脂では対処しきれない問題が発生し、半導体装置の信頼性を十分に確保することが困難になりつつある。すなわち、フィラ含有量が多い樹脂は粘度が高くなるので、半導体チップと回路基板との間隙に注入することが不可能となる。   However, in recent years, as the dimensions of semiconductor chips increase, problems that cannot be dealt with by conventional resins have occurred, and it has become difficult to ensure sufficient reliability of semiconductor devices. That is, since the resin having a high filler content has a high viscosity, it cannot be injected into the gap between the semiconductor chip and the circuit board.

また、粒径の大きなフィラが含有された樹脂では、バンプ電極ピッチの微細化に対応できず、バンプ電極の内側領域に注入することが不可能となる。仮に注入が可能な程度のフィラが含有されている樹脂の場合でも、フィラが半導体チップのパッシベーション膜を通過して、半導体チップを破壊するおそれがある。   In addition, a resin containing a filler with a large particle size cannot cope with the finer pitch of the bump electrodes and cannot be injected into the inner region of the bump electrodes. Even in the case of a resin containing filler that can be injected, the filler may pass through the passivation film of the semiconductor chip and destroy the semiconductor chip.

上述の問題に加えて、半導体チップの寸法が大きくなるにしたがって、半導体チップと回路基板との間隙に樹脂を注入する際に樹脂中に気泡を巻き込みやすくなり、機械的強度の低下、気泡中への結露による配線の腐食等が生じ、信頼性が低下するという問題があった。   In addition to the above-described problems, as the size of the semiconductor chip increases, it becomes easier for air bubbles to be entrained in the resin when the resin is injected into the gap between the semiconductor chip and the circuit board, resulting in a decrease in mechanical strength and into the air bubbles. There is a problem that reliability of the wiring is lowered due to corrosion of the wiring due to the dew condensation.

そこで本発明は、半導体チップと回路基板との間隙に配置される樹脂中での気泡の発生を防止し、信頼性を向上させた半導体装置を提供することを目的とする。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device in which generation of bubbles in a resin disposed in a gap between a semiconductor chip and a circuit board is prevented and reliability is improved.

上記課題を解決するために、本発明は、回路配線基板と、この基板上にバンプ電極を介して実装された半導体チップとを具備し、前記回路配線基板と半導体チップとの間隙および半導体チップの周囲に樹脂が配置された半導体装置において、前記バンプ電極は前記半導体チップの外周に沿って接続電極を介して形成され、前記回路配線基板表面のバンプ電極で囲まれている領域内で前記接続電極の内端から0.3mm乃至2.0mm内側の領域に凹部が形成されていることを特徴とする半導体装置を提供する。   In order to solve the above problems, the present invention comprises a circuit wiring board and a semiconductor chip mounted on the board via bump electrodes, and the gap between the circuit wiring board and the semiconductor chip and the semiconductor chip. In the semiconductor device in which resin is arranged around, the bump electrode is formed through the connection electrode along the outer periphery of the semiconductor chip, and the connection electrode is within a region surrounded by the bump electrode on the surface of the circuit wiring board. A semiconductor device is provided in which a recess is formed in a region 0.3 mm to 2.0 mm inside from the inner end of the semiconductor device.

本発明によれば、半導体チップと回路基板との間隙に配置される樹脂中での気泡の発生を防止し、信頼性を向上させた半導体装置が提供される。 ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which prevented generation | occurrence | production of the bubble in resin arrange | positioned in the clearance gap between a semiconductor chip and a circuit board, and improved reliability is provided.

本発明の半導体装置においては、回路基板表面の半導体チップの中央に相当する部分に凹部を形成している。このため、半導体チップ中央部での樹脂の速度が増加して間隙部分への注入が容易になり、一方、半導体チップ周辺部分での樹脂の封入速度が増加しない。すなわち、半導体チップの周辺部分と中央部とにおける樹脂の注入速度の差を小さくしているので、樹脂中への気泡の巻き込みを防ぐことができる。 In the semiconductor device of the present invention, a recess is formed in a portion corresponding to the center of the semiconductor chip on the surface of the circuit board. For this reason, the speed of the resin at the central portion of the semiconductor chip is increased and the injection into the gap portion is facilitated, while the sealing speed of the resin at the peripheral portion of the semiconductor chip is not increased. That is, since the difference in the resin injection speed between the peripheral portion and the central portion of the semiconductor chip is reduced, it is possible to prevent bubbles from being involved in the resin.

さらに、本発明者らは、封止樹脂が流れる速度は、バンプ電極より外側の領域(半導体チップの外周辺部)では樹脂の塗布量の増加につれて大きくなるのに対し、バンプ電極より内側の領域では、樹脂の塗布量に依存しないことを見出だした。本発明はこのような知見のもとになされたものである。   Furthermore, the present inventors have found that the flow rate of the sealing resin increases as the amount of resin applied increases in the region outside the bump electrode (outer peripheral portion of the semiconductor chip), whereas the region inside the bump electrode. Then, it discovered that it did not depend on the application quantity of resin. The present invention has been made based on such knowledge.

すなわち、本発明では、半導体チップと回路基板との間隙および半導体チップの周囲に配置される樹脂の塗布量を、前記間隙の体積の1倍以上3倍以下と限定しているので、気泡の巻き込みを防止することができる。 That is, in the present invention, the amount of resin applied to the gap between the semiconductor chip and the circuit board and the periphery of the semiconductor chip is limited to 1 to 3 times the volume of the gap. Can be prevented.

以下、図面を参照して、本発明をより詳細に説明する。   Hereinafter, the present invention will be described in more detail with reference to the drawings.

(参考例I)
図1に、参考例Iの半導体装置の断面図を示し、図2にこの装置の平面図を示す。
(Reference Example I)
FIG. 1 shows a cross-sectional view of the semiconductor device of Reference Example I, and FIG. 2 shows a plan view of this device.

図1に示すように、半導体装置9においては、接続用端子4が形成された回路配線基板2上に、バンプ電極3およびAlボンディングパッド8を介して半導体チップ1が実装されている。さらに、図2に示すように、半導体チップ1と回路配線基板2との間隙、すなわち、最外周バンプ電極で囲まれている領域の内側には、第1の樹脂5が配置されている。一方、この最外周バンプ電極で囲まれていない外側の領域には第2の樹脂6が配置されている。なお、最外周バンプ電極で囲まれている領域とは、具体的には、最外周バンプ電極の中心線7をつないだ領域内をさす。   As shown in FIG. 1, in a semiconductor device 9, a semiconductor chip 1 is mounted on a circuit wiring board 2 on which connection terminals 4 are formed via bump electrodes 3 and Al bonding pads 8. Further, as shown in FIG. 2, the first resin 5 is disposed in the gap between the semiconductor chip 1 and the circuit wiring board 2, that is, inside the region surrounded by the outermost peripheral bump electrode. On the other hand, the second resin 6 is disposed in an outer region not surrounded by the outermost peripheral bump electrode. Note that the area surrounded by the outermost bump electrode specifically refers to the area where the center line 7 of the outermost bump electrode is connected.

樹脂としては、無機充填材を含有し、無溶剤型の熱硬化性樹脂を使用することができ、例えば、フェノール系エポキシ樹脂のうち、ビスフェノール型エポキシ樹脂と、酸無水物硬化剤とイミダゾール硬化触媒との混合物、または、シリコンゴムとしてのジメチルポリシロキサン、有機過酸化物の混合物、またはポリイミド樹脂、マレイミド樹脂、ポリウレタン樹脂、アクリル樹脂、フェノール系エポキシ樹脂等が挙げられる。また、無機充填材としては、シリカ、石英、および溶融シリカ等を使用することができる。   As the resin, an inorganic filler can be used, and a solvent-free thermosetting resin can be used. For example, among phenolic epoxy resins, bisphenol type epoxy resins, acid anhydride curing agents, and imidazole curing catalysts. Or dimethylpolysiloxane as a silicone rubber, a mixture of organic peroxides, or a polyimide resin, a maleimide resin, a polyurethane resin, an acrylic resin, a phenolic epoxy resin, or the like. As the inorganic filler, silica, quartz, fused silica and the like can be used.

なお、前記第1の樹脂および第2の樹脂に含有されるフィラの含有量および粒径は、それぞれの相対的な関係で決定することができる。すなわち、第1の樹脂においては、第2の樹脂に含有されるフィラの最大粒径および平均粒径より小さい粒径のフィラを、第2の樹脂より少ない割合で混合して使用する。例えば、第1の樹脂におけるフィラ含有量は、45重量%以下とすることが好ましく、40重量%以下がより好ましい。また、フィラの最大粒径および平均粒径は、好ましくは、それぞれ45μm以下および25μm以下であり、より好ましくは、それぞれ40μm以下および20μm以下である。   The filler content and particle size contained in the first resin and the second resin can be determined by their relative relationships. That is, in the first resin, fillers having a particle size smaller than the maximum particle size and average particle size of the filler contained in the second resin are mixed and used in a smaller proportion than the second resin. For example, the filler content in the first resin is preferably 45% by weight or less, and more preferably 40% by weight or less. Further, the maximum particle size and the average particle size of the filler are preferably 45 μm or less and 25 μm or less, respectively, more preferably 40 μm or less and 20 μm or less, respectively.

一方、第2の樹脂におけるフィラ含有量は、50重量%以下とすることが好ましく、45重量%以下がより好ましい。また、フィラの最大粒径および平均粒径は、好ましくは、それぞれ60μm以下および40μm以下であり、より好ましくは、それぞれ50μm以下および45μm以下である。   On the other hand, the filler content in the second resin is preferably 50% by weight or less, and more preferably 45% by weight or less. The maximum particle size and the average particle size of the filler are preferably 60 μm or less and 40 μm or less, respectively, and more preferably 50 μm or less and 45 μm or less, respectively.

さらに、第1の樹脂に含有されるナトリウムイオン量および塩素イオン量の少なくとも一方を、第2の樹脂よりも少なくすることによって、腐食による不良の発生を防止することができる。   Furthermore, the occurrence of defects due to corrosion can be prevented by reducing at least one of the amount of sodium ions and the amount of chlorine ions contained in the first resin as compared to the second resin.

この場合には、第1の樹脂中のナトリウムイオン量およびは塩素イオン量は、例えば、それぞれ1ppm以下、および5ppm以下であることが好ましく、第2の樹脂のナトリウムイオン量およびは塩素イオン量は、例えば、それぞれ10ppm以下、および10ppm以下であることが好ましい。   In this case, the amount of sodium ions and the amount of chlorine ions in the first resin are preferably, for example, 1 ppm or less and 5 ppm or less, respectively, and the amount of sodium ions and the amount of chlorine ions in the second resin are For example, it is preferably 10 ppm or less and 10 ppm or less, respectively.

図1に示した半導体装置は、例えば、以下のような工程で製造することができる。図3および4に、製造方法の第1の例を表わす工程図を示す。   The semiconductor device shown in FIG. 1 can be manufactured by the following processes, for example. 3 and 4 are process diagrams showing a first example of the manufacturing method.

まず、図3(a)に示すような半導体チップ1と、図3(b)に示すような回路配線基板2とを準備する。半導体チップ1の裏面のバンプ電極3は、例えば、蒸着法または電気メッキ法を用いて形成することができる。このバンプ電極の材質としては、一般的には、はんだが用いられるが、これに限定されるものではなく、例えば、はんだと比較して剛性を有するAu,Cu等の金属を使用しても良い。   First, a semiconductor chip 1 as shown in FIG. 3A and a circuit wiring board 2 as shown in FIG. 3B are prepared. The bump electrode 3 on the back surface of the semiconductor chip 1 can be formed by using, for example, a vapor deposition method or an electroplating method. Generally, solder is used as the material of the bump electrode, but is not limited thereto. For example, a metal such as Au or Cu having rigidity compared to solder may be used. .

なお、半導体チップのサイズ、バンプ電極数、およびバンプピッチは、任意とすることができ、レイアウトもエリア化されたものであってもよく、何等限定されるものではない。   The size of the semiconductor chip, the number of bump electrodes, and the bump pitch can be set arbitrarily, and the layout may be an area, and is not limited at all.

ここでは、10mm×10mmの半導体チップを使用し、Cu/Tiバリアメタル10を形成した後、Pb/Sn=40/60合金で、直径100μm、高さ75μm±5μmのバンプ3を形成した。なお、バンプは、半導体チップの周囲に添って256個配置した。   Here, a 10 mm × 10 mm semiconductor chip was used to form the Cu / Ti barrier metal 10, and then a bump 3 having a diameter of 100 μm and a height of 75 μm ± 5 μm was formed from a Pb / Sn = 40/60 alloy. In addition, 256 bumps were arranged along the periphery of the semiconductor chip.

すなわち、図3(a)に示すように、半導体チップ1表面には、Alボンディングパッド8およびパッシベーション膜11が形成されており、さらに、Alボンディングパッド8表面には、バリアメタル10を介してバンプ電極3が形成されている。   That is, as shown in FIG. 3A, an Al bonding pad 8 and a passivation film 11 are formed on the surface of the semiconductor chip 1, and bumps are formed on the surface of the Al bonding pad 8 via the barrier metal 10. An electrode 3 is formed.

また、回路配線基板2の材質および構造は、特に限定されるものではなく、例えば、積層ガラスエポキシ基板等を使用することができる。以下、基板として、ガラスエポキシ基板上に、絶縁層と導体層とをビルドアップさせた方式のプリント基板SLC(Surface Laminar Circuit)基板を用いて説明する。   Moreover, the material and structure of the circuit wiring board 2 are not particularly limited, and for example, a laminated glass epoxy board or the like can be used. Hereinafter, a printed circuit board SLC (Surface Laminar Circuit) substrate in which an insulating layer and a conductor layer are built up on a glass epoxy substrate will be described as a substrate.

すなわち、図3(b)に示すように、回路配線基板2には、半導体チップのバンプ電極に対する接続用端子部分4に110μmφの開孔が設けられ、端子材料としてのCuが露出しており、基板の端子部分以外にはソルダレジスト12が被覆されている。   That is, as shown in FIG. 3B, the circuit wiring board 2 is provided with a 110 μmφ opening in the connection terminal portion 4 for the bump electrode of the semiconductor chip, and Cu as a terminal material is exposed, A solder resist 12 is coated on portions other than the terminal portion of the substrate.

このような構成の回路配線基板2の上に、図3(c)に示すように、フリップチップボンダーを用いて半導体チップ1を位置合わせし、バンプ電極3と回路配線基板2の接続用端子4とを電気的、機械的に接触させる。このとき、回路配線基板2は、加熱機構を有するステージ13上に保持され、窒素雰囲気中で、Pb/Sn=40/60の融点よりも高い200℃に予備加熱されている。   On the circuit wiring board 2 having such a configuration, as shown in FIG. 3C, the semiconductor chip 1 is aligned using a flip chip bonder, and the bump electrodes 3 and the connection terminals 4 of the circuit wiring board 2 are aligned. Are brought into electrical and mechanical contact. At this time, the circuit wiring board 2 is held on a stage 13 having a heating mechanism and preheated to 200 ° C. higher than the melting point of Pb / Sn = 40/60 in a nitrogen atmosphere.

さらに、半導体チップ1と回路配線基板2とが接触された状態に保ち、半導体チップを保持するコレット14を、窒素雰囲気中で、前述のステージ13と同じ温度200℃に加熱する。これによって、はんだを溶融させ、半導体チップ1と回路配線基板2の電極とを電気的および機械的に仮接続させる。最後に、窒素雰囲気で250℃に加熱されたリフロー炉中に、半導体チップ1を搭載した回路配線基板2を通過させ、半導体チップと回路配線基板とを電気的、機械的に接続する。   Further, the semiconductor chip 1 and the circuit wiring board 2 are kept in contact with each other, and the collet 14 holding the semiconductor chip is heated to the same temperature as the stage 13 described above at 200 ° C. in a nitrogen atmosphere. Thereby, the solder is melted, and the semiconductor chip 1 and the electrodes of the circuit wiring board 2 are temporarily connected electrically and mechanically. Finally, the circuit wiring board 2 on which the semiconductor chip 1 is mounted is passed through a reflow furnace heated to 250 ° C. in a nitrogen atmosphere, and the semiconductor chip and the circuit wiring board are electrically and mechanically connected.

このとき、はんだの表面張力によりセルフアライン効果が発生し、マウント時に発生した多少の位置ずれは修正されるので、正確な位置にボンディングが可能になる。   At this time, a self-alignment effect is generated by the surface tension of the solder, and a slight positional deviation generated during mounting is corrected, so that bonding can be performed at an accurate position.

以上の工程により、図3(d)に示すように、半導体チップ1を回路配線基板2にバンプにより実装した構造が得られる。次いで、図4(a)に示すように、半導体チップ1と回路配線基板2とにより形成される隙間部分に、ディスペンサー15により第1の樹脂をポッティングする。樹脂5は、毛細管現象によりバンプ電極3で囲まれている領域内に注入され、図4(b)に示すように配置される。   Through the above steps, a structure in which the semiconductor chip 1 is mounted on the circuit wiring board 2 with bumps as shown in FIG. Next, as shown in FIG. 4A, the first resin is potted by a dispenser 15 in a gap formed by the semiconductor chip 1 and the circuit wiring board 2. The resin 5 is injected into a region surrounded by the bump electrode 3 by a capillary phenomenon, and is arranged as shown in FIG.

樹脂としては、ビスフェノール系エポキシ、イミダゾール硬化触媒、酸無水物硬化剤、および球状石英フィラ(最大粒径20μm、平均粒径5μm)を含有するものを用いた。フィラの含有量は30重量%とし、このような組成の樹脂を約4ml配置した。   As the resin, a resin containing a bisphenol-based epoxy, an imidazole curing catalyst, an acid anhydride curing agent, and a spherical quartz filler (maximum particle size 20 μm, average particle size 5 μm) was used. The filler content was 30% by weight, and about 4 ml of resin having such a composition was disposed.

第1の樹脂は、後に配置する第2の樹脂とは組成が異なるので、バンプ電極3で囲まれている領域のゲル化時間が短くなる。したがって、第1の樹脂を注入することにより半導体チップ1が仮固定されるので、信頼性良く半導体チップ1を回路配線基板2にフリップチップ実装することができる。   Since the first resin has a composition different from that of the second resin to be disposed later, the gelation time of the region surrounded by the bump electrode 3 is shortened. Therefore, since the semiconductor chip 1 is temporarily fixed by injecting the first resin, the semiconductor chip 1 can be flip-chip mounted on the circuit wiring board 2 with high reliability.

続いて、図4(c)に示すように、半導体チップ1周囲に、第2の樹脂6をポッティングして毛細管現象を利用してバンプ電極で囲まれていない領域に樹脂封止する。   Subsequently, as shown in FIG. 4C, the second resin 6 is potted around the semiconductor chip 1 to seal the resin in a region not surrounded by the bump electrodes by using a capillary phenomenon.

第2の樹脂は、最大粒径35μm、平均粒径10μmの球状の石英フィラを、45重量%の割合で混合した以外は、第1の樹脂と同様の組成であり、この第2の樹脂を、約2ml配置した。   The second resin has the same composition as the first resin except that a spherical quartz filler having a maximum particle size of 35 μm and an average particle size of 10 μm is mixed at a ratio of 45% by weight. About 2 ml.

なお、配置される樹脂の量は、第1および第2の樹脂とも、半導体チップの寸法およびバンプ電極の高さ等によって適宜選択することできる。さらに、80℃で4時間クリーンオーブン中に保存して、配置された樹脂を硬化させることにより、図1に示した半導体装置が得られる。   The amount of the resin to be arranged can be appropriately selected for the first and second resins depending on the dimensions of the semiconductor chip, the height of the bump electrodes, and the like. Furthermore, the semiconductor device shown in FIG. 1 is obtained by storing in a clean oven at 80 ° C. for 4 hours and curing the arranged resin.

なお、第1および第2の樹脂の配置方法は、上述の例に限定されるものではなく、以下のようにして配置してもよい。図5に、図1に示した半導体装置の製造方法の第2の例を表わす工程図を示す。なお、ここで用いる半導体チップおよび回路配線基板は、それぞれ前述の図3(a)および図3(b)に示したものと同様の構造であり、第1の例で用いたものと同様の組成の樹脂を同量配置する。   In addition, the arrangement | positioning method of 1st and 2nd resin is not limited to the above-mentioned example, You may arrange | position as follows. FIG. 5 is a process chart showing a second example of the method for manufacturing the semiconductor device shown in FIG. The semiconductor chip and the circuit wiring board used here have the same structure as that shown in FIG. 3A and FIG. 3B, respectively, and the same composition as that used in the first example. The same amount of resin is placed.

まず、図5(a)に示すように、第1の樹脂5を、回路配線基板2上のバンプ電極3で囲まれる領域内に予めポッティングしておく。次に、図5(b)に示すように、回路配線基板2の上に、フリップチップボンダーを用いて、半導体チップ1を位置合わせし、バンプ電極3と回路配線基板2の接続用端子4とを電気的、機械的に接続する。このとき、回路配線基板2は、加熱機構を有するステージ13上に保持され、窒素雰囲気中200℃で加熱される。   First, as shown in FIG. 5A, the first resin 5 is potted in advance in a region surrounded by the bump electrodes 3 on the circuit wiring board 2. Next, as shown in FIG. 5B, the semiconductor chip 1 is aligned on the circuit wiring board 2 by using a flip chip bonder, and the bump electrodes 3 and the connection terminals 4 of the circuit wiring board 2 are arranged. Are electrically and mechanically connected. At this time, the circuit wiring board 2 is held on a stage 13 having a heating mechanism and heated at 200 ° C. in a nitrogen atmosphere.

予めポッティングされている第1の樹脂5は、図5(c)に示すように半導体チップ1と回路配線基板2との間隙内に完全に封入され、封止された樹脂も200℃の熱により仮硬化の状態にある。   The first resin 5 that has been potted in advance is completely enclosed in the gap between the semiconductor chip 1 and the circuit wiring board 2 as shown in FIG. 5C, and the sealed resin is also heated by 200 ° C. It is in the state of temporary hardening.

さらに、図4(c)と同様にして、第2の樹脂6を半導体チップ周囲にポッティングし、最後に80℃のクリーンオーブン中で4時間完全に硬化させる。なお、第1の樹脂5は、図6(a)に示すように、半導体チップ1上のバンプ電極3で囲まれる領域に部分に予めポッティングしてもよい。   Further, in the same manner as in FIG. 4C, the second resin 6 is potted around the semiconductor chip and finally completely cured in a clean oven at 80 ° C. for 4 hours. The first resin 5 may be potted in advance in a region surrounded by the bump electrode 3 on the semiconductor chip 1 as shown in FIG.

このように第1の樹脂が配置された半導体チップ1を、図6(b)に示すように、フリップチップボンダーを用いて回路配線基板2の上に位置合わせし、バンプ電極3と回路配線基板2の接続用端子4とを電気的、機械的に接触させる。このとき、回路配線基板2は、加熱機構を有するステージ13上に保持され、窒素雰囲気中200℃で加熱される。   As shown in FIG. 6B, the semiconductor chip 1 on which the first resin is arranged as described above is aligned on the circuit wiring board 2 using a flip chip bonder, and the bump electrode 3 and the circuit wiring board are aligned. Two connection terminals 4 are brought into electrical and mechanical contact. At this time, the circuit wiring board 2 is held on a stage 13 having a heating mechanism and heated at 200 ° C. in a nitrogen atmosphere.

第1の樹脂5は、図6(c)に示すように半導体チップ1と回路配線基板2との間隙内に完全に封入されており、封止された樹脂も200℃の熱により仮硬化の状態にある。   The first resin 5 is completely enclosed in the gap between the semiconductor chip 1 and the circuit wiring board 2 as shown in FIG. 6C, and the sealed resin is temporarily cured by heat at 200 ° C. Is in a state.

さらに、図4(c)と同様にして、第2の樹脂6を半導体チップ周囲にポッティングし、最後に80℃のクリーンオーブン中で4時間完全に硬化させる。図7に、図1に示した半導体装置の製造方法の第3の例を表わす工程図を示す。なお、ここで用いる半導体チップおよび回路配線基板は、それぞれ前述の図3(a)および図3(b)に示したものと同様の構造であり、第1の例で用いたものと同様の組成の樹脂を同量配置する。   Further, in the same manner as in FIG. 4C, the second resin 6 is potted around the semiconductor chip and finally completely cured in a clean oven at 80 ° C. for 4 hours. FIG. 7 is a process chart showing a third example of the method for manufacturing the semiconductor device shown in FIG. The semiconductor chip and the circuit wiring board used here have the same structure as that shown in FIG. 3A and FIG. 3B, respectively, and the same composition as that used in the first example. The same amount of resin is placed.

まず、図7(a)に示すように、第1の樹脂5、および第2の樹脂6を、回路配線基板2上のバンプ電極3で囲まれる領域内、および囲まれない領域にそれぞれポッティングしておく。   First, as shown in FIG. 7A, the first resin 5 and the second resin 6 are respectively potted in a region surrounded by the bump electrode 3 on the circuit wiring board 2 and a region not surrounded. Keep it.

次に、図7(b)に示すように、回路配線基板2の上に、フリップチップボンダーを用いて、半導体チップ1を位置合わせし、バンプ電極3と回路配線基板2の接続用端子4とを電気的、機械的に接続する。   Next, as shown in FIG. 7B, the semiconductor chip 1 is aligned on the circuit wiring board 2 by using a flip chip bonder, and the bump electrodes 3 and the connection terminals 4 of the circuit wiring board 2 are arranged. Are electrically and mechanically connected.

予めポッティングされている樹脂5および6は、図7(c)に示すように、半導体チップ1と回路配線基板2とで作られる間隙、および半導体チップの周囲にそれぞれ配置される。なお、第1および第2の樹脂は、いずれも仮硬化の状態にある。   As shown in FIG. 7C, the pre-potted resins 5 and 6 are respectively disposed in the gap formed by the semiconductor chip 1 and the circuit wiring board 2 and around the semiconductor chip. Note that both the first and second resins are in a temporarily cured state.

最後に、80℃のクリーンオーブン中で4時間完全に硬化させる。なお、第1の樹脂5および第2の樹脂6は、図8(a)に示すように、半導体チップ1上のバンプ電極3で囲まれている領域、および囲まれていない領域にそれぞれポッティングしてもよい。   Finally, it is completely cured in a clean oven at 80 ° C. for 4 hours. As shown in FIG. 8A, the first resin 5 and the second resin 6 are potted in a region surrounded by the bump electrode 3 and a region not surrounded by the semiconductor chip 1, respectively. May be.

このように第1の樹脂5および第2の樹脂6が配置された半導体チップ1を、図7(b)に示すように、フリップチップボンダーを用いて回路配線基板2の上に位置合わせし、バンプ電極3と回路配線基板2の接続用端子4とを電気的、機械的に接触させる。このとき、回路配線基板2は、加熱機構を有するステージ13上に保持され、窒素雰囲気中200℃で加熱される。   The semiconductor chip 1 in which the first resin 5 and the second resin 6 are arranged in this way is aligned on the circuit wiring board 2 using a flip chip bonder, as shown in FIG. The bump electrodes 3 and the connection terminals 4 of the circuit wiring board 2 are brought into electrical and mechanical contact. At this time, the circuit wiring board 2 is held on a stage 13 having a heating mechanism and heated at 200 ° C. in a nitrogen atmosphere.

以上説明したような種々の方法によって、図1に示した半導体装置を製造することができる。次に、具体例を示して参考例Iをより詳細に説明する。   The semiconductor device shown in FIG. 1 can be manufactured by various methods as described above. Next, Reference Example I will be described in more detail with a specific example.

上述の第1の製造方法を用いて、10mm×10mmの半導体チップ上にPb/Sn=40/60のバンプ電極を256個、径100μmφで形成し、SLC基板上にフリップチップ実装して、参考例(I−1)の半導体装置を得た。   Using the first manufacturing method described above, 256 bump electrodes of Pb / Sn = 40/60 with a diameter of 100 μmφ are formed on a 10 mm × 10 mm semiconductor chip and flip-chip mounted on an SLC substrate. The semiconductor device of Example (I-1) was obtained.

この参考例(I−1)においては、バンプで囲まれている領域に配置される樹脂(樹脂1)の弾性係数E1を900×107Paとし、バンプで囲まれていない領域に配置される樹脂(樹脂2)の弾性係数E2を1200×107Paとした。また、熱膨張係数αは、いずれの樹脂も39×10-6/℃とし、これらの物性は、樹脂に混入するフィラの含有率を主にして、最大粒径および平均粒径、必要に応じて樹脂分子量を変えることにより決定した。なお、第1の樹脂におけるフィラの含有率は25重量%、最大粒径は30μm、平均粒径は7μmとし、第2の樹脂におけるフィラの含有率は40重量%、最大粒径は40μm、平均粒径は15μmとした。 In this reference example (I-1), the elastic coefficient E 1 of the resin (resin 1) disposed in the region surrounded by the bumps is set to 900 × 10 7 Pa, and the resin is disposed in the region not surrounded by the bumps. The elastic modulus E 2 of the resin (resin 2) is 1200 × 10 7 Pa. In addition, the thermal expansion coefficient α is 39 × 10 −6 / ° C. for any resin, and these physical properties are the maximum particle size and the average particle size, mainly depending on the filler content mixed in the resin, as required. It was determined by changing the resin molecular weight. The filler content in the first resin is 25% by weight, the maximum particle size is 30 μm, the average particle size is 7 μm, the filler content in the second resin is 40% by weight, the maximum particle size is 40 μm, the average The particle size was 15 μm.

得られた半導体装置を熱サイクル試験に供し、256ピンの1箇所でも接続がオープンになった場合を不良として、温度サイクルと累積不良率との関係を調べ、得られた結果を図9に曲線aで示した。なお、サンプル数は1000個とし、温度サイクルの条件は(−55℃(30分)〜25℃(5分)〜125℃(30分)〜25℃(5分))で行った。   The obtained semiconductor device was subjected to a thermal cycle test, and the relationship between the temperature cycle and the cumulative failure rate was investigated by assuming that the connection was open even at one of the 256 pins, and the obtained result is shown in the curve of FIG. Indicated by a. The number of samples was 1000, and the temperature cycle conditions were (-55 ° C. (30 minutes) to 25 ° C. (5 minutes) to 125 ° C. (30 minutes) to 25 ° C. (5 minutes)).

曲線aに示すように、バンプ電極で囲まれていない領域に配置される樹脂(樹脂2)の弾性係数E2 を、バンプ電極で囲まれている領域に配置される樹脂(樹脂1)の弾性係数E1 よりも大きくすることによって、2500サイクルまで不良は発生しないことがわかる。 As shown by the curve a, the elastic coefficient E 2 of the resin (resin 2) disposed in the region not surrounded by the bump electrode is represented by the elasticity of the resin (resin 1) disposed in the region surrounded by the bump electrode. By making it larger than the coefficient E 1, it can be seen that no defect occurs until 2500 cycles.

また、熱膨張係数の異なる樹脂を用いる以外は、同様にして参考例(I−2)の半導体装置を製造した。この参考例(I−2)においては、バンプで囲まれている領域に配置される樹脂(樹脂1)の熱膨張係数α1 を39×10-6/℃とし、バンプで囲まれていない領域に配置される樹脂(樹脂2)の熱膨張係数α2 を20×10-6/℃とした。また、弾性係数は、いずれの樹脂も900×107 Paとし、これらの物性は、樹脂に混入するフィラの含有率と必要に応じて樹脂の分子量とを変えることにより決定した。なお、第1の樹脂におけるフィラの含有率は30重量%、最大粒径は20μm、平均粒径は5μmとし、第2の樹脂におけるフィラの含有率は45重量%、最大粒径は35μm、平均粒径は10μmとした。 Further, a semiconductor device of Reference Example (I-2) was manufactured in the same manner except that resins having different thermal expansion coefficients were used. In this reference example (I-2), the thermal expansion coefficient α 1 of the resin (resin 1) disposed in the region surrounded by the bumps is 39 × 10 −6 / ° C., and the region is not surrounded by the bumps The thermal expansion coefficient α 2 of the resin (resin 2) disposed on the substrate was set to 20 × 10 −6 / ° C. The elastic modulus was 900 × 10 7 Pa for all the resins, and these physical properties were determined by changing the filler content mixed in the resin and the molecular weight of the resin as required. The filler content in the first resin is 30% by weight, the maximum particle size is 20 μm, the average particle size is 5 μm, the filler content in the second resin is 45% by weight, the maximum particle size is 35 μm, the average The particle size was 10 μm.

得られた半導体装置を、前述と同様の熱サイクル試験に供し、サイクル数と累積不良率との関係を図9中に曲線bで示す。曲線bに示すように、バンプ電極で囲まれていない半導体チップ周辺領域の樹脂(樹脂2)の熱膨張係数α2を、バンプ電極で囲まれている領域に配置される樹脂(樹脂1)の熱膨張係数α1よりも小さくすることによって、3500サイクルまで不良は発生せず、信頼性は極めて向上することがわかる。 The obtained semiconductor device is subjected to the same thermal cycle test as described above, and the relationship between the number of cycles and the cumulative defect rate is shown by a curve b in FIG. As shown by the curve b, the thermal expansion coefficient α 2 of the resin (resin 2) in the peripheral region of the semiconductor chip that is not surrounded by the bump electrode is expressed by the resin (resin 1) disposed in the region surrounded by the bump electrode. It can be seen that by making it smaller than the thermal expansion coefficient α 1 , no defect occurs up to 3500 cycles, and the reliability is greatly improved.

さらに、弾性係数900×107Pa、熱膨張係数39×10-6/℃の樹脂をバンプ電極の内外の領域を配置する以外は、同様にして製造した半導体装置を比較例(I−1)とし、樹脂を配置せず製造した半導体装置を比較例(I−2)とした。これらの比較例(I−1)および(I−2)の半導体装置を同様の熱サイクル試験に供し、得られた結果を、それぞれ、曲線cおよびdで示す。 Further, a semiconductor device manufactured in the same manner as above except that a resin having an elastic coefficient of 900 × 10 7 Pa and a thermal expansion coefficient of 39 × 10 −6 / ° C. is disposed in the inner and outer regions of the bump electrode is a comparative example (I-1). A semiconductor device manufactured without placing resin was set as Comparative Example (I-2). The semiconductor devices of Comparative Examples (I-1) and (I-2) were subjected to the same thermal cycle test, and the obtained results are shown by curves c and d, respectively.

曲線cに示すように、均一な物性の樹脂をバンプ電極の内外の領域に配置した場合には、2000サイクルまで不良が発生しないものの、2500サイクルでほぼ100%が不良となり、樹脂を配置しない場合(曲線d)では2サイクルで不良が発生し、10サイクル以上で100%が不良となった。   As shown in curve c, when resin with uniform physical properties is arranged in the inner and outer regions of the bump electrode, no defect occurs until 2000 cycles, but almost 100% becomes defective in 2500 cycles, and no resin is arranged In (curve d), a defect occurred in 2 cycles, and 100% became defective in 10 cycles or more.

以上の結果から、バンプ電極で囲まれている領域と囲まれていない領域とで、配置される樹脂の物性に差異を持たせることによって、信頼性が著しく向上することがわかる。   From the above results, it can be seen that the reliability is remarkably improved by providing a difference in the physical properties of the resin disposed between the region surrounded by the bump electrode and the region not surrounded by the bump electrode.

次に、以下のようにフィラの含有量、平均粒径、および最大粒径を変化させた2種類の樹脂を用いて、前述の第1の製造方法により半導体装置を製造し、参考例(I−3)とした。 なお、バンプ電極で囲まれている領域に配置した樹脂(第1の樹脂)、およびバンプ電極で囲まれていない領域に配置した樹脂(第2の樹脂)に混入したフィラの含有量、平均粒径、および最大粒径は以下の通りである。   Next, a semiconductor device is manufactured by the first manufacturing method described above using two kinds of resins in which the filler content, the average particle diameter, and the maximum particle diameter are changed as described below. -3). In addition, the content of filler mixed in the resin (first resin) arranged in the region surrounded by the bump electrode and the resin (second resin) arranged in the region not surrounded by the bump electrode, the average particle The diameter and the maximum particle diameter are as follows.

第1の樹脂 第2の樹脂
フィラ含有量(重量%) 30 45
平均粒径(μm) 5 10
最大粒径(μm) 20 35
得られた半導体装置100個について、85℃,85%,VDD=5Vの高温高湿バイアス保存試験を行い、バンプ電極が1箇所でもオープンあるいはショートを発生した場合を不良として、保存時間と累積不良率との関係を調べ、図10中に曲線eで示した。
1st resin 2nd resin
Filler content (% by weight) 30 45
Average particle size (μm) 5 10
Maximum particle size (μm) 20 35
A high temperature and high humidity bias storage test at 85 ° C., 85%, VDD = 5V was performed on 100 obtained semiconductor devices, and the case where the bump electrode was open or shorted even at one location was regarded as defective, and the storage time and cumulative failure The relationship with the rate was examined, and is shown by a curve e in FIG.

曲線eに示すように、バンプ電極で囲まれた領域と囲まれていない領域とでフィラの含有量、平均粒径、および最大粒径に差異を設けることによって、3000サイクルを超えるまで不良を発生しない。これは、チップ周囲の樹脂のフィラ含有量、最大粒径、平均粒径が大きいために、樹脂の水分遮蔽効果が充分に発揮されたことに起因すると考えられる。   As shown by curve e, defects are generated up to 3000 cycles by providing differences in filler content, average particle size, and maximum particle size between the region surrounded by the bump electrode and the region not surrounded by the bump electrode. do not do. This is considered to be due to the fact that the resin has a sufficient moisture shielding effect because the filler content, maximum particle size, and average particle size of the resin around the chip are large.

さらに、平均粒径7μm、最大粒径20μmのフィラを、40重量%の割合で混入した樹脂を、バンプ電極の内外領域に配置して製造した半導体装置を比較例(I−3)とし、樹脂を配置せずに製造した半導体装置を比較例(I−4)とした。これらの比較例(I−3)および比較例(I−4)の半導体装置について、前述の参考例(I−3)と同様の試験を行ない、得られた結果を図10中に、それぞれ曲線fおよび曲線gで示す。   Furthermore, a semiconductor device manufactured by placing a resin mixed with filler having an average particle size of 7 μm and a maximum particle size of 20 μm at a ratio of 40% by weight in the inner and outer regions of the bump electrode is referred to as Comparative Example (I-3). A semiconductor device manufactured without arranging was used as Comparative Example (I-4). About the semiconductor device of these comparative examples (I-3) and comparative examples (I-4), the same test as the above-mentioned reference example (I-3) was conducted, and the obtained results are shown in FIG. Indicated by f and curve g.

曲線fに示すように、均一な樹脂をバンプ電極の内外領域に配置した場合には、2000Hを超えるまで不良の発生を抑えることができたものの、2300Hで不良が発生し、樹脂を配置しない場合(曲線g)には、500Hで不良が発生し、保存時間が1000Hを超えると、100%が不良となった。   When a uniform resin is disposed in the inner and outer regions of the bump electrode as shown by the curve f, the occurrence of a defect can be suppressed until exceeding 2000H, but a defect occurs at 2300H and the resin is not disposed. In (curve g), a defect occurred at 500H, and when the storage time exceeded 1000H, 100% became defective.

以上の結果から、本参考例の半導体装置は、高温高湿下でも優れた信頼性を有することがわかる。   From the above results, it can be seen that the semiconductor device of this reference example has excellent reliability even under high temperature and high humidity.

(実施例I)
以下、図面を参照して、本発明の半導体装置を詳細に説明する。
Example I
Hereinafter, a semiconductor device of the present invention will be described in detail with reference to the drawings.

図11に、本発明の半導体装置の一例を表わす断面図を示す。図11に示すように、本発明に係る半導体装置20は、回路基板21の接続電極22に、シリコン製半導体チップ23の外周に沿って形成された接続電極24が、ハンダバンプ25により接続されている。また、半導体チップ23と回路基板21との間隙および半導体チップ23の周辺部分には樹脂26が配置されている。   FIG. 11 is a cross-sectional view illustrating an example of the semiconductor device of the present invention. As shown in FIG. 11, in the semiconductor device 20 according to the present invention, a connection electrode 24 formed along the outer periphery of a silicon semiconductor chip 23 is connected to a connection electrode 22 of a circuit board 21 by a solder bump 25. . A resin 26 is disposed in the gap between the semiconductor chip 23 and the circuit board 21 and in the peripheral portion of the semiconductor chip 23.

本実施例に用いられる回路基板21の材質は、特に限定されるものではなく、例えば、ガラスエポキシ製、アラミド−エポキシ製、BTレジン製、PPE、Al23 製等の絶縁性の基板を使用することができる。この回路基板21表面の半導体チップ23の中央部に対応する領域には、凹部27が形成されている。なお、半導体チップ23の中央部とは、チップの外周に沿って形成された接続電極24で囲まれた領域の内側であり、好ましくは、接続電極24の内端から、0.3mmないし2.0mm程度内側の領域である。 The material of the circuit board 21 used in the present embodiment is not particularly limited. For example, an insulating board such as glass epoxy, aramid-epoxy, BT resin, PPE, Al 2 O 3 or the like is used. Can be used. A concave portion 27 is formed in a region corresponding to the central portion of the semiconductor chip 23 on the surface of the circuit board 21. The central portion of the semiconductor chip 23 is the inner side of a region surrounded by the connection electrode 24 formed along the outer periphery of the chip, and preferably 0.3 mm to 2 mm from the inner end of the connection electrode 24. It is an area inside about 0 mm.

基板21表面に形成された凹部27の深さ、すなわち段差は、チップ23の寸法、ハンダバンプ25の高さ等によって適宜選択することができるが、10μm以上100μm以下とすることが好ましい。   The depth of the recess 27 formed on the surface of the substrate 21, that is, the level difference can be appropriately selected depending on the dimensions of the chip 23, the height of the solder bump 25, etc., but is preferably 10 μm or more and 100 μm or less.

回路基板表面の凹部27は、例えば、回路基板21の表面を研削加工することによって形成することができるが、複数のガラスエポキシシートを積層してガラスエポキシ基板を形成する場合には、基板最上層のシートの所定領域をプレスで打ち抜き加工した後に積層することによって凹部を形成してもよい。さらに、半導体チップの周辺部のみに所定の膜厚でハンダレジストを塗布することによって、中央部に凹部を形成することもできる。   The concave portion 27 on the surface of the circuit board can be formed by, for example, grinding the surface of the circuit board 21. When a glass epoxy board is formed by laminating a plurality of glass epoxy sheets, the top layer of the board is formed. The predetermined area of the sheet may be punched with a press and then laminated to form a recess. Furthermore, the concave portion can be formed in the central portion by applying a solder resist with a predetermined film thickness only to the peripheral portion of the semiconductor chip.

なお、接続電極24は、例えば、チタンと銅とを順次積層することによって形成することができ、チタンと銅と金またはパラジウムとを順次積層してもよい。接続電極22は銅、または銅、ニッケル、金を順次積層することにより形成することができる。また、ハンダバンプ25は、SnとPbとの比率が6対4からなり、その高さは40から80μmとすることができる。   The connection electrode 24 can be formed by sequentially laminating titanium and copper, for example, and may be sequentially laminated with titanium, copper and gold or palladium. The connection electrode 22 can be formed by sequentially stacking copper, or copper, nickel, and gold. Further, the solder bump 25 has a ratio of Sn to Pb of 6: 4, and its height can be 40 to 80 μm.

間隙に配置される樹脂26としては、充填材を混入した任意の熱硬化性樹脂を使用することができるが、室温での粘度が50ポイズ以下のものが好ましい。なお、充填材としては、例えば、球状の石英フィラ、シリカ、粉砕シリカ、および熔融シリカ等を使用することができ、その最大粒径は、凹部27における半導体チップ23と基板21との距離の1/2以下が好ましく、樹脂中におけるフィラの含有量は、20重量%以上70重量%以下とすることが好ましい。   As the resin 26 disposed in the gap, any thermosetting resin mixed with a filler can be used, but those having a viscosity at room temperature of 50 poise or less are preferable. As the filler, for example, spherical quartz filler, silica, pulverized silica, fused silica and the like can be used, and the maximum particle size thereof is 1 of the distance between the semiconductor chip 23 and the substrate 21 in the recess 27. / 2 or less is preferable, and the filler content in the resin is preferably 20 wt% or more and 70 wt% or less.

この樹脂は、半導体チップ23および回路基板21の表面および、バンプ電極の内側面で囲まれる間隙の体積の1倍以上2倍以下の体積で用いることが好ましい。   This resin is preferably used in a volume of 1 to 2 times the volume of the gap surrounded by the surfaces of the semiconductor chip 23 and the circuit board 21 and the inner surface of the bump electrode.

本実施例の半導体装置は、例えば、以下に示す工程で製造することができる。図12に、製造工程を表わす断面図を示す。まず、図12(a)に示すように、回路基板21にハンダバンプ25を介して半導体チップ23を接続する。   The semiconductor device of this embodiment can be manufactured, for example, by the steps shown below. FIG. 12 is a sectional view showing the manufacturing process. First, as shown in FIG. 12A, the semiconductor chip 23 is connected to the circuit board 21 via the solder bumps 25.

次に、図12(b)は吐出量を制御する機能を有する液体吐出装置30を用いて、半導体チップ23の4辺のうちの1辺の端部に封止樹脂26を塗布する。続いて、回路基板を40℃から60℃に加熱して樹脂の粘度を低下させることにより、樹脂26は、図12(c)に示すように、毛細管現象によって半導体チップ23と回路基板21との間隙に流入する。   Next, in FIG. 12B, the sealing resin 26 is applied to the end of one of the four sides of the semiconductor chip 23 using the liquid ejection device 30 having a function of controlling the ejection amount. Subsequently, by reducing the viscosity of the resin by heating the circuit board from 40 ° C. to 60 ° C., the resin 26 is formed between the semiconductor chip 23 and the circuit board 21 by capillary action as shown in FIG. Flows into the gap.

最後に、オーブン中で加熱して、図12(d)に示すように樹脂を硬化させる。なお、加熱は、100℃で1時間、続いて120℃で3時間行ない、その雰囲気は、例えば、大気雰囲気、酸素濃度2%以下の窒素雰囲気、または1Pa以下の減圧雰囲気中とすることができる。   Finally, it is heated in an oven to cure the resin as shown in FIG. The heating is performed at 100 ° C. for 1 hour, and then at 120 ° C. for 3 hours. The atmosphere can be, for example, an air atmosphere, a nitrogen atmosphere having an oxygen concentration of 2% or less, or a reduced pressure atmosphere having a pressure of 1 Pa or less. .

以上の工程により、本発明の半導体装置が得られる。次に、具体例を示して、本発明をより詳細に説明する。8×8mm、深さ50±10μmの凹部が表面に形成されたガラスエポキシ製回路基板(50×35mm)の接続電極に、ハンダバンプにより半導体チップ(10.2×10.4mm)を接続した。なお、接続後のバンプの高さは70μmであった。   Through the above steps, the semiconductor device of the present invention is obtained. Next, the present invention will be described in more detail with reference to specific examples. A semiconductor chip (10.2 × 10.4 mm) was connected by solder bumps to connection electrodes of a glass epoxy circuit board (50 × 35 mm) having a recess of 8 × 8 mm and a depth of 50 ± 10 μm formed on the surface. The height of the bump after connection was 70 μm.

半導体チップと回路基板との間隙内に、上述の方法を用いて樹脂を配置した。なお、本実施例においては、ビスフェノール系エポキシ、イミダゾール硬化触媒、酸無水物硬化剤、および球状の石英フィラー(平均粒径7μm、最大粒径20μm)を約40重量%の割合で含有し、室温での粘度が40ポイズのものを使用し、その量は、間隙の体積の3倍とした。   Resin was placed in the gap between the semiconductor chip and the circuit board using the method described above. In this example, bisphenol-based epoxy, imidazole curing catalyst, acid anhydride curing agent, and spherical quartz filler (average particle size 7 μm, maximum particle size 20 μm) are contained at a ratio of about 40% by weight, The viscosity was 40 poise, and the amount was 3 times the volume of the gap.

この際、樹脂の流入距離と注入速度との関係を測定し、図13(a)中に曲線hで示した。なお、流入距離は、図13(b)に示すようにして測定した。さらに、比較例として、図14(a)および(b)に示すような従来の構造の半導体装置に、前述と同様の樹脂を注入し、その際の流入距離と注入速度との関係を調べた。なお、図14(a)に示す構造は、基板31の表面が平坦であり、図14(b)に示す構造では、基板表面が平坦であることに加えて、バンプ25の周囲にエポキシコーティング38が施されている。 At this time, the relationship between the inflow distance of the resin and the injection speed was measured and indicated by a curve h in FIG. The inflow distance was measured as shown in FIG. Further, as a comparative example, a resin similar to that described above was injected into a semiconductor device having a conventional structure as shown in FIGS. 14A and 14B, and the relationship between the inflow distance and the injection speed at that time was examined. . In the structure shown in FIG. 14A, the surface of the substrate 31 is flat. In the structure shown in FIG. 14B, in addition to the substrate surface being flat, the epoxy coating 38 is provided around the bumps 25. Is given.

図14(a)および(b)に示す構造体に樹脂を注入する際に得られた結果を、図13中にそれぞれ曲線iおよび曲線jで示した。図13に示すように、流入が進むにつれて、樹脂の注入速度は低下する傾向にあるが、本発明(曲線h)の場合には、注入速度の低下が小さく十分な速度を維持できる。したがって、容易に含浸を行なえることがわかる。 The results obtained when injecting the resin into the structures shown in FIGS. 14A and 14B are shown by curve i and curve j in FIG. 13, respectively. As shown in FIG. 13, as the inflow proceeds, the resin injection rate tends to decrease. However, in the case of the present invention (curve h), the decrease in the injection rate is small and a sufficient rate can be maintained. Therefore, it turns out that impregnation can be performed easily.

これに対して、曲線iに示されるように、図14(a)に示すような構造において樹脂含浸を行った場合には、間隙での注入速度が小さくなって含浸が不可能となる。なお、このような構造において、含浸を容易にするために低粘度樹脂を用いた場合には、半導体チップの周囲での樹脂の注入速度が大きくなるために、樹脂中に気泡を巻き込み易くなるおそれがある。 On the other hand, as shown by the curve i, when resin impregnation is performed in the structure shown in FIG. 14A, the injection rate in the gap becomes small and impregnation becomes impossible. In such a structure, when a low-viscosity resin is used to facilitate the impregnation, the resin injection speed around the semiconductor chip increases, which may cause air bubbles to be easily involved in the resin. There is.

また、曲線jに示すように、図14(b)に示すような構造においては、ハンダバンプが形成されているチップの周辺部での間隙寸法が小さいために、樹脂の流入速度は、この領域で著しく減少する。したがって、含浸が不可能となることがわかる。   Further, as shown by the curve j, in the structure as shown in FIG. 14B, since the gap size at the periphery of the chip on which the solder bump is formed is small, the inflow speed of the resin is in this region. Remarkably reduced. Therefore, it turns out that impregnation becomes impossible.

次に、チップの寸法を変えて、前述の樹脂を注入し、その際の樹脂含浸の可否、および含浸工程での気泡の巻き込みの有無を調べた。なお、樹脂の含浸状態の観察を容易にするために、ガラスチップを用い、チップ寸法は5.14×4.8mm、10.2×10.4mm、および12.52×11.96mmの3種類とした。これらのチップを実装するための基板表面の凹部の寸法は、それぞれ3.2×3.0mm、8.0×8.0mm、11.6×11.0mmとし、凹部の深さはいずれも50±10μmとした。   Next, the above-mentioned resin was injected by changing the dimensions of the chip, and whether or not the resin was impregnated at that time and whether or not bubbles were involved in the impregnation step were examined. In order to facilitate the observation of the impregnation state of the resin, a glass chip is used, and the chip dimensions are 5.14 × 4.8 mm, 10.2 × 10.4 mm, and 12.52 × 11.96 mm. It was. The dimensions of the recesses on the substrate surface for mounting these chips are 3.2 × 3.0 mm, 8.0 × 8.0 mm, and 11.6 × 11.0 mm, respectively, and the depths of the recesses are all 50 ± 10 μm.

さらに、比較例として、前述の図14(a)に示す構造体に同様の樹脂を注入して、その際の樹脂含浸の可否、および含浸工程での気泡の巻き込みの有無を調べた。得られた結果をそれぞれ下記表1および表2にまとめる。

Figure 0003846890
Figure 0003846890
Furthermore, as a comparative example, the same resin was injected into the structure shown in FIG. 14A, and the possibility of resin impregnation at that time and the presence or absence of bubbles in the impregnation step were examined. The obtained results are summarized in Tables 1 and 2 below.
Figure 0003846890
Figure 0003846890

表1に示すように、本発明の半導体装置は、基板温度を40℃に設定することで、チップの寸法が大きくなっても含浸は可能であり、気泡の巻き込みも発生しなかった。   As shown in Table 1, by setting the substrate temperature to 40 ° C., the semiconductor device of the present invention was able to be impregnated even when the chip size was increased, and bubble entrainment did not occur.

一方、従来の構造の比較例では、40℃の加熱温度では、樹脂の含浸が困難であったため、基板温度を80℃にして樹脂の粘度を下げた状態での含浸も行った。その結果、基板温度を40℃とした場合には、10.2mm×10.4mmのチップを用いた場合に含浸不可能となる試料が発生し、12.52mm×11.96mmのチップでは、全て不良となった。また、基板温度を80℃とした場合には、5.14mm×4.8mmの最小のチップでも気泡の巻き込みが発生した。   On the other hand, in the comparative example of the conventional structure, since it was difficult to impregnate the resin at a heating temperature of 40 ° C., the impregnation was also performed in a state where the substrate temperature was set to 80 ° C. and the viscosity of the resin was lowered. As a result, when the substrate temperature is 40 ° C., a sample that cannot be impregnated is generated when a chip of 10.2 mm × 10.4 mm is used, and all of the chips of 12.52 mm × 11.96 mm It became defective. In addition, when the substrate temperature was 80 ° C., bubbles were caught even with the smallest chip of 5.14 mm × 4.8 mm.

以上のことから、本実施例のように基板表面に凹部を形成することによって、樹脂含浸時の流入性が向上するので、大型の半導体チップの樹脂封止が可能であること、さらに樹脂含浸時の気泡の巻き込み防止にも効果があることがわかる。   From the above, by forming a recess on the surface of the substrate as in this embodiment, the inflow property during resin impregnation is improved, so that resin sealing of a large semiconductor chip is possible, and further during resin impregnation It can be seen that it is also effective in preventing entrainment of bubbles.

(実施例II)
図15に、実施例IIの半導体装置の一例を表わす断面図を示す。
Example II
FIG. 15 is a sectional view showing an example of the semiconductor device of Example II.

図15に示すように、半導体装置40は、回路基板41の接続電極42に、シリコン製半導体チップ43の接続電極44が、ハンダバンプ45により接続されている。また、半導体チップ43と回路基板41との間隙および半導体チップ43の周辺部分には樹脂46が配置されている。   As shown in FIG. 15, in the semiconductor device 40, the connection electrodes 44 of the silicon semiconductor chip 43 are connected to the connection electrodes 42 of the circuit board 41 by solder bumps 45. A resin 46 is disposed in the gap between the semiconductor chip 43 and the circuit board 41 and in the peripheral portion of the semiconductor chip 43.

回路基板41の材質は、特に限定されるものではなく、例えば、ガラスエポキシ製、アラミドエポキシ製、BTレジン製、アルミナセラミックス、窒化アルミニウム、ガラス製等の基板を使用することができる。   The material of the circuit board 41 is not particularly limited. For example, a board made of glass epoxy, aramid epoxy, BT resin, alumina ceramics, aluminum nitride, glass or the like can be used.

なお、接続電極42は銅、または銅、ニッケル、金を順次積層することにより形成することができる。接続電極44は、チタンとニッケルとを順次積層することにより形成することができ、チタンとニッケルと金またはパラジウムを順次積層することによって形成してもよい。また、ハンダバンプ45は、SnとPbとの比率が6対4の組成物からなり、その高さは50ないし80μmとすることができる。   The connection electrode 42 can be formed by sequentially stacking copper, or copper, nickel, and gold. The connection electrode 44 can be formed by sequentially stacking titanium and nickel, or may be formed by sequentially stacking titanium, nickel, gold, or palladium. The solder bump 45 is made of a composition having a ratio of Sn to Pb of 6: 4, and the height thereof can be 50 to 80 μm.

間隙に配置される樹脂46としては、実施例Iで説明したものと同様の任意の熱硬化性樹脂を使用することができるが、室温での粘度が50ポイズ以下のものである。なお、充填材としては、その最大粒径は、半導体チップ表面と基板表面との距離の1/2以下とする以外は、前述と同様の球状の石英フィラ等を使用することができる。なお、樹脂中におけるフィラの含有量は、20重量%以上70重量%以下とする。   As the resin 46 disposed in the gap, any thermosetting resin similar to that described in Example I can be used, but the viscosity at room temperature is 50 poise or less. As the filler, the same spherical quartz filler as described above can be used except that the maximum particle size is ½ or less of the distance between the semiconductor chip surface and the substrate surface. In addition, content of the filler in resin shall be 20 to 70 weight%.

この樹脂は、半導体チップ23および回路基板21の表面および、バンプ電極の内側面で囲まれる間隙の体積の1倍以上3倍以下の体積で用いる。図15に示した半導体装置は、例えば、以下に示すような工程で製造することができる。図16に、製造工程を表わす断面図を示す。   This resin is used in a volume of 1 to 3 times the volume of the gap surrounded by the surfaces of the semiconductor chip 23 and the circuit board 21 and the inner surface of the bump electrode. The semiconductor device shown in FIG. 15 can be manufactured by the following processes, for example. FIG. 16 is a sectional view showing the manufacturing process.

まず、図16(a)に示すように、回路基板41にハンダバンプ45を介して半導体チップ43を接続する。次に、図16(b)は吐出量を制御する機能を有する液体吐出装置50を用いて、半導体チップ43の4辺のうちの1辺の端部に封止樹脂46を塗布する。   First, as shown in FIG. 16A, the semiconductor chip 43 is connected to the circuit board 41 via the solder bumps 45. Next, in FIG. 16B, the sealing resin 46 is applied to the end of one of the four sides of the semiconductor chip 43 using the liquid ejection device 50 having a function of controlling the ejection amount.

続いて、回路基板を40℃から60℃に加熱して樹脂の粘度を低下させることにより、樹脂46は、図16(c)に示すように、毛細管現象によって半導体チップ43と回路基板41との間隙に流入する。   Subsequently, by reducing the viscosity of the resin by heating the circuit board from 40 ° C. to 60 ° C., the resin 46 is formed between the semiconductor chip 43 and the circuit board 41 by capillary action as shown in FIG. Flows into the gap.

最後に、オーブン中で加熱して、図16(d)に示すように樹脂を硬化させる。なお、加熱は、100℃で1時間、続いて120℃で3時間行ない、その雰囲気は、例えば、大気雰囲気、酸素濃度2%以下の窒素雰囲気、または1Pa以下の減圧雰囲気中とすることができる。   Finally, it is heated in an oven to cure the resin as shown in FIG. The heating is performed at 100 ° C. for 1 hour, and then at 120 ° C. for 3 hours. The atmosphere can be, for example, an air atmosphere, a nitrogen atmosphere having an oxygen concentration of 2% or less, or a reduced pressure atmosphere having a pressure of 1 Pa or less. .

以上の工程により、図15に示した半導体装置が得られる。次に、具体例を示して、本実施例をより詳細に説明する。ガラスエポキシ製回路基板(50×35mm)の接続電極に、ハンダバンプにより半導体チップ(10.2×10.4mm)を接続した。なお、接続後のバンプの高さは70μmであり、基板、チップおよびバンプ電極で囲まれた間隙の体積は7.4mm3 であった。 Through the above steps, the semiconductor device shown in FIG. 15 is obtained. Next, this example will be described in more detail with reference to specific examples. A semiconductor chip (10.2 × 10.4 mm) was connected to a connection electrode of a glass epoxy circuit board (50 × 35 mm) by solder bumps. The height of the bump after connection was 70 μm, and the volume of the gap surrounded by the substrate, chip and bump electrode was 7.4 mm 3 .

さらに、半導体チップと回路基板との間隙内に、上述の方法を用いて樹脂を配置した。ここでは、ビスフェノール系エポキシ、イミダゾール硬化触媒、酸無水物硬化剤および球状の石英フィラー(平均粒径5μm、最大粒径12μm)を約40重量%の割合で含有し、室温での粘度が30ポイズのものを使用し、樹脂の体積は、半導体チップ、回路基板およびバンプ電極で囲まれた領域の体積の1.5倍とした。   Further, a resin was disposed in the gap between the semiconductor chip and the circuit board using the method described above. Here, it contains bisphenol-based epoxy, imidazole curing catalyst, acid anhydride curing agent and spherical quartz filler (average particle size 5 μm, maximum particle size 12 μm) in a proportion of about 40% by weight, and the viscosity at room temperature is 30 poise. The volume of the resin was 1.5 times the volume of the region surrounded by the semiconductor chip, the circuit board, and the bump electrodes.

まず、配置する樹脂の体積を変化させ、チップ中央とチップ周辺とにおける樹脂量と注入速度との関係を調べた。得られた結果を図17に示す。なお、注入速度は、半導体チップの封止樹脂を塗布した辺から5mmの距離までの樹脂の注入速度の平均値を用いた。 First, the volume of the resin to be arranged was changed, and the relationship between the resin amount and the injection rate at the chip center and the chip periphery was examined. The obtained result is shown in FIG. Incidentally, infusion rate, using the average value of the injection rate of the resin of the sealing resin of the semiconductor chips from the sides coated to a distance of 5 mm.

図17に示すように、半導体チップの周辺を流れる樹脂の速度は、樹脂の塗布量が大きくなるにしたがって急激に増大する。一方、チップ中央での注入速度は、塗布量によらずほぼ一定である。したがって、樹脂の塗布量が少ないほどチップの周辺と中央とでの注入速度との差が小さくなる。 As shown in FIG. 17, the speed of the resin flowing around the semiconductor chip increases rapidly as the amount of resin applied increases. On the other hand, the injection speed at the center of the chip is substantially constant regardless of the coating amount. Therefore, the smaller the amount of resin applied, the smaller the difference between the injection rate at the periphery and center of the chip.

次に、樹脂の塗布量を変えて、前述の図16に示す工程で種類の試料を作製してボイドの発生数を調べた。なお、回路基板、半導体チップおよび樹脂は、前述と同様のものを使用した。得られた結果を下記表3に示す。

Figure 0003846890
Next, by changing the amount of resin applied, various types of samples were prepared in the process shown in FIG. 16 and the number of voids was examined. The circuit board, semiconductor chip, and resin were the same as described above. The obtained results are shown in Table 3 below.
Figure 0003846890

表3に示すように、封止樹脂の体積が、半導体チップと回路基板との間隙の体積の5倍以上となると、気泡の巻き込みが発生する。したがって、樹脂の体積は、間隙体積の3倍以下と限定することによって、ボイドの発生を防げることができる。   As shown in Table 3, when the volume of the sealing resin is 5 times or more the volume of the gap between the semiconductor chip and the circuit board, entrainment of bubbles occurs. Therefore, the generation of voids can be prevented by limiting the volume of the resin to 3 times or less of the gap volume.

参考例の半導体装置を示す断面図。Sectional drawing which shows the semiconductor device of a reference example. 参考例の半導体装置を示す平面図。The top view which shows the semiconductor device of a reference example. 参考例の半導体装置の製造工程の一例を示す断面図。Sectional drawing which shows an example of the manufacturing process of the semiconductor device of a reference example. 参考例の半導体装置の製造工程の一例を示す断面図。Sectional drawing which shows an example of the manufacturing process of the semiconductor device of a reference example. 参考例の半導体装置の製造工程の他の例を示す断面図。Sectional drawing which shows the other example of the manufacturing process of the semiconductor device of a reference example. 参考例の半導体装置の製造工程の他の例を示す断面図。Sectional drawing which shows the other example of the manufacturing process of the semiconductor device of a reference example. 参考例の半導体装置の製造工程の他の例を示す断面図。Sectional drawing which shows the other example of the manufacturing process of the semiconductor device of a reference example. 参考例の半導体装置の製造工程の他の例を示す断面図。Sectional drawing which shows the other example of the manufacturing process of the semiconductor device of a reference example. サイクル数と累積不良率との関係を示すグラフ図。The graph which shows the relationship between a cycle number and a cumulative defect rate. 保持時間と累積不良率との関係を示すグラフ図。The graph which shows the relationship between holding time and a cumulative defect rate. 本発明の半導体装置の一例を示す断面図。FIG. 10 is a cross-sectional view illustrating an example of a semiconductor device of the invention. 本発明に係る半導体装置の製造工程を示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this invention. 樹脂の流入距離と注入速度との関係を示す図。The figure which shows the relationship between the inflow distance of resin, and injection | pouring speed . 従来の構造の半導体装置を示す断面図。Sectional drawing which shows the semiconductor device of the conventional structure. 本発明にかかる半導体装置の他の例を示す断面図。Sectional drawing which shows the other example of the semiconductor device concerning this invention. 本発明にかかる半導体装置の製造工程の他の例を示す断面図。Sectional drawing which shows the other example of the manufacturing process of the semiconductor device concerning this invention. 樹脂塗布量と注入速度との関係を示すグラフ図。The graph which shows the relationship between resin application amount and injection | pouring speed | rate . 従来の半導体装置を示す断面図。Sectional drawing which shows the conventional semiconductor device. 従来の半導体装置を示す断面図。Sectional drawing which shows the conventional semiconductor device. 従来の半導体装置を示す断面図。Sectional drawing which shows the conventional semiconductor device. 樹脂の流入距離と注入速度との関係を示すグラフ図。The graph which shows the relationship between the inflow distance of resin, and injection | pouring speed . 半導体チップと回路基板との間に注入された樹脂の流入状態を示す図。The figure which shows the inflow state of the resin inject | poured between the semiconductor chip and the circuit board.

符号の説明Explanation of symbols

1…半導体チップ,2…回路配線基板,3…バンプ電極,4…接続用端子
5…第1の樹脂,6…第2の樹脂,7…最外周バンプ電極の中心
8…Alボンディングパッド,9…半導体装置,10…バリアメタル
11…パッシベーション膜,12…ソルダーレジスト,13…ステージ
14…コレット,15…ディスペンサー,20…半導体装置,21…回路基板
22…接続電極,23…半導体チップ,24…接続電極,25…ハンダバンプ
26…樹脂,27…凹部,28…液体吐出装置,30…半導体装置,31…回路基板
32…接続電極,33…半導体チップ,34…接続電極,35…ハンダバンプ
36…樹脂,37…半導体装置,38…エポキシコーティング層,40…半導体装置
41…回路基板,42…接続電極,43…半導体チップ,44…接続電極
45…ハンダバンプ,46…樹脂,48…液体吐出装置,70…半導体装置
71…回路配線基板,72…半導体チップ,73…バンプ電極,74…接続用端子
75…接続用端子,77…半導体装置,78…従来の樹脂,80…半導体装置
81…間隙部分,83…回路基板,84…半導体チップ,85…バンプ電極
86…樹脂,87…気泡。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Circuit wiring board, 3 ... Bump electrode, 4 ... Connection terminal 5 ... 1st resin, 6 ... 2nd resin, 7 ... Center of outermost periphery bump electrode 8 ... Al bonding pad, 9 ... Semiconductor device, 10 ... Barrier metal 11 ... Passivation film, 12 ... Solder resist, 13 ... Stage 14 ... Collet, 15 ... Dispenser, 20 ... Semiconductor device, 21 ... Circuit board 22 ... Connection electrode, 23 ... Semiconductor chip, 24 ... Connection electrode, 25 ... Solder bump 26 ... Resin, 27 ... Recess, 28 ... Liquid discharge device, 30 ... Semiconductor device, 31 ... Circuit board 32 ... Connection electrode, 33 ... Semiconductor chip, 34 ... Connection electrode, 35 ... Solder bump 36 ... Resin 37 ... Semiconductor device, 38 ... Epoxy coating layer, 40 ... Semiconductor device 41 ... Circuit board, 42 ... Connection electrode, 43 ... Semiconductor chip , 44 ... Connection electrodes 45 ... Solder bumps, 46 ... Resin, 48 ... Liquid ejection devices, 70 ... Semiconductor devices 71 ... Circuit wiring boards, 72 ... Semiconductor chips, 73 ... Bump electrodes, 74 ... Connection terminals 75 ... Connection terminals, DESCRIPTION OF SYMBOLS 77 ... Semiconductor device, 78 ... Conventional resin, 80 ... Semiconductor device 81 ... Gap part, 83 ... Circuit board, 84 ... Semiconductor chip, 85 ... Bump electrode 86 ... Resin, 87 ... Bubble.

Claims (1)

回路配線基板と、この基板上にバンプ電極を介して実装された半導体チップとを具備し、前記回路配線基板と半導体チップとの間隙および半導体チップの周囲に樹脂が配置された半導体装置において、
前記バンプ電極は前記半導体チップの外周に沿って接続電極を介して形成され、前記回路配線基板表面のバンプ電極で囲まれている領域内で前記接続電極の内端から0.3mm乃至2.0mm内側の領域に凹部が形成されていることを特徴とする半導体装置。
In a semiconductor device comprising a circuit wiring board and a semiconductor chip mounted on the board via bump electrodes, and a resin disposed in the gap between the circuit wiring board and the semiconductor chip and around the semiconductor chip,
The bump electrode is formed through a connection electrode along the outer periphery of the semiconductor chip, and is 0.3 mm to 2.0 mm from the inner end of the connection electrode in a region surrounded by the bump electrode on the surface of the circuit wiring board. A semiconductor device, wherein a recess is formed in an inner region .
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