JP2004179292A - Semiconductor device, semiconductor-device mounting body and manufacturing method - Google Patents

Semiconductor device, semiconductor-device mounting body and manufacturing method Download PDF

Info

Publication number
JP2004179292A
JP2004179292A JP2002342083A JP2002342083A JP2004179292A JP 2004179292 A JP2004179292 A JP 2004179292A JP 2002342083 A JP2002342083 A JP 2002342083A JP 2002342083 A JP2002342083 A JP 2002342083A JP 2004179292 A JP2004179292 A JP 2004179292A
Authority
JP
Japan
Prior art keywords
semiconductor device
conductive resin
resin
support substrate
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002342083A
Other languages
Japanese (ja)
Other versions
JP3951903B2 (en
Inventor
Toshiaki Tanaka
俊明 田中
Masaaki Takekoshi
正明 竹越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP2002342083A priority Critical patent/JP3951903B2/en
Publication of JP2004179292A publication Critical patent/JP2004179292A/en
Application granted granted Critical
Publication of JP3951903B2 publication Critical patent/JP3951903B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, in which the number of manufacturing processes and the cost can be reduced and which has an excellent reliability about electrical connection, a semiconductor device mounting body and methods for manufacturing these. <P>SOLUTION: In the semiconductor device or the semiconductor device mounting body, a bump electrically connecting an electrode pad for a semiconductor element or the semiconductor device and the electrode pad for a supporting substrate is composed of a conductive resin, and an air gap between the semiconductor element or the semiconductor device and the supporting substrate is supported by an insulating resin. The semiconductor device or the semiconductor device mounting body in which the coefficient of thermal expansion of the insulating resin is larger than that of the conductive resin is provided. Methods for manufacturing these are also provided. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子又は半導体装置と支持基板が導電性樹脂を介して電気的に接続された半導体装置、半導体装置実装体、及びこれらの製造方法に関する。
【０００２】
【従来の技術】
近年、電子機器の小型化、処理速度の高速化に伴い、樹脂封止型半導体パッケージの多ピン化、狭ピッチ化、薄型化の動きが急速に進展しており、半導体素子を支持基板に直接実装したフリップ実装方式が多く採用されるようになってきた。フリップ実装方式は、パッケージを小型化、薄型化できるばかりでなく、半導体素子の電極と支持基板の電極を接続する距離を最小にできることから高周波特性に優れる特徴がある。
【０００３】
図６はフリップチップ実装方式の一例を示す図である。従来技術では、バンプ材料としてＳｎ−Ｐｂ系はんだを用いており、半導体素子１の回路面に形成されたＡｌ電極３上には、はんだの拡散防止のためにＣｒやＡｕなどのバリアメタル層が形成されている。また、はんだバンプは、球形のはんだボールを電極３上に搭載した後、リフロー工程で溶融させることで形成されるが、このとき、はんだの濡れ性を向上するためにフラックスを用いる。さらに、支持基板への実装は、支持基板にはんだバンプ付き半導体素子を搭載し、再度リフロー工程を経ることで行われ、さらに、接続信頼性を向上させるために半導体素子１と支持基板８の間隙に補強樹脂であるアンダーフィルを注入し、これを硬化させて半導体装置を得ることができる。
【０００４】
しかしながら、上記のようなはんだを用いた半導体素子または半導体装置の実装方法では、（１）バリアメタル層形成による半導体装置の製造工程およびコストの増加、（２）Ｐｂ系はんだの環境負荷及び法規制、（３）フラックスによる半導体装置の汚染、（４）アンダーフィル注入による半導体装置の製造工程及びコストの増加、などの問題があった。
【０００５】
このような問題を解決するため、導電性樹脂を使用したフリップチップ技術が提案されている（例えば、特許文献１参照）。この方法によれば、フリップチップのボンドパッドにおける導電性の重合可能な前駆物質の形成により、フリップチップのボンドパッドと基板のボンドパッドとの間の電気接続が得られ、はんだのリフローよりも低温条件下でバンプを重合でき、チップや基板の熱膨張係数の大きな不一致により生じる信頼性の問題を相当に減少させることができ、低温でバンプ重合ができるので広範囲の基板を用いることが可能であり、はんだバンプ形成のための複雑かつ長時間を要する蒸着及び電気めっきが不要になり、さらにフラックスが不要になる特徴がある。
【０００６】
【特許文献１】
特許第２７１７９９３号公報
【特許文献２】
特開２０００−２３６００２号公報（第１図）
【０００７】
【発明が解決しようとする課題】
しかしながら、上記技術は、チップと基板の間隙を絶縁性樹脂で補強してないため、落下衝撃や高温と低温に繰り返し曝される冷熱サイクルに弱く、電気的接続信頼性が低いという問題がある。一方、チップと基板の間隙に補強樹脂を注入して周囲環境の変化による接続部位への影響を小さくする方法（例えば、特許文献２参照）が提案されているが、この方法では、チップと基板を接着する接着用封止樹脂と接続部位を保護する保護用封止樹脂の２種類の樹脂が必要であり、工程が煩雑になるという問題がある。
【０００８】
上記を鑑みて、本発明は、製造工程数およびコストの低減が可能であり、かつ電気的接続信頼性に優れる半導体装置、半導体装置実装体、およびこれらの製造方法を提供することを目的とする。
【０００９】
【課題を解決するための手段】
本発明は、半導体素子の電極パッドと支持基板の電極パッドを電気的に接続するバンプが導電性樹脂からなり、半導体素子と支持基板の間の空隙が絶縁性樹脂により支持されている半導体装置であって、絶縁性樹脂の熱膨張係数が導電性樹脂の熱膨張係数よりも大きいことを特徴とする半導体装置を提供する。
【００１０】
また、本発明は、半導体装置の電極パッドと支持基板の電極パッドを電気的に接続するバンプが導電性樹脂からなり、半導体装置と支持基板の間の空隙が絶縁性樹脂により支持されている半導体装置実装体であって、絶縁性樹脂の熱膨張係数が導電性樹脂の熱膨張係数よりも大きいことを特徴とする半導体装置実装体を提供する。
【００１１】
また、本発明は、半導体素子の電極パッドに導電性樹脂からなるバンプを形成する工程と、導電性樹脂を硬化させる工程と、支持基板の電極パッドに導電性樹脂からなるバンプを形成する工程と、熱膨張係数が導電性樹脂の熱膨張係数よりも大きい絶縁性樹脂を支持基板上の半導体素子実装領域に半導体素子の電極パッドに形成したバンプよりも高くなるように塗布する工程と、半導体素子と支持基板の両バンプが互いに重なるように半導体素子と支持基板を接合する工程と、導電性樹脂と絶縁性樹脂を硬化させる工程と、を含むことを特徴とする半導体装置の製造方法を提供する。
【００１２】
また、本発明は、半導体素子の電極パッドに導電性樹脂からなるバンプを形成する工程と、導電性樹脂をＢステージまで硬化させる工程と、熱膨張係数が導電性樹脂の熱膨張係数よりも大きい絶縁性樹脂を支持基板上の半導体素子実装領域に半導体素子の電極パッドに形成したバンプよりも高くなるように塗布する工程と、半導体素子のバンプと支持基板の電極パッドが互いに重なるように半導体素子と支持基板を接合する工程と、導電性樹脂と絶縁性樹脂を硬化させる工程と、を含むことを特徴とする半導体装置の製造方法を提供する。
【００１３】
また、本発明は、半導体装置の電極パッドに導電性樹脂からなるバンプを形成する工程と、導電性樹脂を硬化させる工程と、支持基板の電極パッドに導電性樹脂からなるバンプを形成する工程と、熱膨張係数が導電性樹脂の熱膨張係数よりも大きい絶縁性樹脂を支持基板上の半導体装置実装領域に半導体装置の電極パッドに形成したバンプよりも高くなるように塗布する工程と、半導体装置と支持基板の両バンプが互いに重なるように半導体装置と支持基板を接合する工程と、導電性樹脂と絶縁性樹脂を硬化させる工程と、を含むことを特徴とする半導体装置実装体の製造方法を提供する。
【００１４】
また、本発明は、半導体装置の電極パッドに導電性樹脂からなるバンプを形成する工程と、導電性樹脂をＢステージまで硬化させる工程と、熱膨張係数が導電性樹脂の熱膨張係数よりも大きい絶縁性樹脂を支持基板上の半導体装置実装領域に半導体装置の電極パッドに形成したバンプよりも高くなるように塗布する工程と、半導体装置のバンプと支持基板の電極パッドが互いに重なるように半導体装置と支持基板を接合する工程と、導電性樹脂と絶縁性樹脂を硬化させる工程と、を含むことを特徴とする半導体装置実装体の製造方法を提供する。
【００１５】
上記本発明によれば、絶縁性樹脂の熱膨張係数が導電性樹脂の熱膨張係数よりも大きいため、両樹脂硬化後、硬化温度以下になると、絶縁性樹脂が導電性樹脂より大きく収縮し、導電性樹脂からなるバンプに圧縮応力が作用することとなり、その結果、電極パッドとバンプの密着力が向上し、信頼性の高い電気的接続状態を得ることができる。
【００１６】
また、本発明に用いる絶縁性樹脂のゲル化時間が導電性樹脂のそれよりも長いことが好ましい。これによれば、導電性樹脂が硬化してから絶縁性樹脂が硬化するため、バンプに対する導電性樹脂と絶縁性樹脂との膨張・収縮量の相違による負担が小さくなり、バンプに適切な圧縮応力が作用することとなり、電気的接続信頼性がより確実なものとなる。
【００１７】
以下、本発明の実施形態について図面を参照して説明する。
【００１８】
【発明の実施の形態】
本発明の特徴は、導電性樹脂からなるバンプを用いた半導体素子または半導体装置の基板への実装方法において、導電性樹脂よりも熱膨張係数が大きい絶縁性樹脂を導電性樹脂と同時に実装硬化する点にある。
【００１９】
図１は本発明の半導体装置の製造過程の一例を示す断面図である。
【００２０】
図１（ａ）は、半導体素子の一般的な構造を示す図である。本発明の半導体素子１は電子回路が形成されたものであれば、特に限定されず、どのような種類又は大きさの半導体素子でも使用可能である。例えば、メモリ回路が形成された半導体素子、ロジック回路が形成された半導体素子等が挙げられる。半導体素子１の上面には、電極３があり、アルミで構成されていても金めっきされた電極でもよく、特に限定されない。さらに、半導体素子１の上面には、半導体素子保護膜２が形成されている。本半導体素子保護膜２は、窒化膜やポリイミド膜等、従来公知のものでよく、特に限定されない。
【００２１】
図１（ｂ）は、半導体素子の電極３上に導電性樹脂からなるバンプ４を形成した図である。バンプを形成する導電性樹脂としては、特に限定されないが、導電性微粉体と樹脂を少なくとも含んでなる樹脂であり、その熱膨張係数が３５×１０−６〜５０×１０−６／℃の範囲であるものが好ましい。熱膨張係数が３５×１０−６／℃未満であると導電性微粉体に対して樹脂の割合が低くなるため接着性が悪化する傾向にあり、５０×１０−６／℃を超えると導電性微粉体が少なくなり、導電性が悪化する傾向にある。導電性微粉体としては、導電性樹脂の硬化後に導電性を有するのもであればとくに材質は限定されず、Ａｇ、Ｃｕ、Ｎｉ、Ｐｄ、Ａｌ、Ａｕなどの金属微粉体や、金属微粉体の表面を異種金属でメッキした粉体や、樹脂粉体の表面をＡｕなどの金属で被覆した粉体や、炭素粉末、あるいは前述の導電微粉体を混合したものが挙げられる。樹脂としては、熱によって硬化するものであれば、とくに材質は限定されず、エポキシ樹脂、フェノール樹脂などの熱硬化型樹脂や、ポリアミドイミドなどの溶剤乾燥型の樹脂が挙げられる。また、バンプの形成方法は、特に限定されず、スクリーン印刷や、転写、ポッティング、フォトプロセスなど、従来公知の方法で形成することができる。
【００２２】
図１（ｃ）は、支持基板８の電極９上に導電性樹脂からなるバンプ６を形成した図である。ここでのバンプは上記同様の導電性樹脂を用い、上記と同様の形成方法により形成される。また、半導体素子１の電極３上に形成したバンプ４がＢステージ状態にあり、これを支持基板８の電極９上に直接付着、硬化させる場合には、支持基板８のバンプ６は特になくてもよい。
【００２３】
図１（ｄ）は、支持基板に絶縁性樹脂５の層を形成した図である。ここで用いられる絶縁性樹脂としては、熱によって硬化し、その熱膨張係数がバンプのそれよりも大きければよいが、好ましくは熱膨張係数が４０×１０−６〜６０×１０−６／℃のものである。また、材質は限定されず、例えば、エポキシ樹脂、フェノール樹脂などの熱硬化型樹脂や、ポリアミドイミドなどの溶剤乾燥型の樹脂が挙げられる。また、バンプを形成する導電性樹脂よりも硬化速度が遅い、すなわち、ゲル化時間が長い絶縁性樹脂であることが好ましく、さらに、（絶縁性樹脂のゲル化時間／導電性樹脂ゲル化時間）の比が１．５より大きいことがより好ましく、２．０より大きいことが特に好ましい。例えば、１５０℃における導電性樹脂のゲル化時間は１０〜６０秒の範囲であることが好ましく、絶縁性樹脂のゲル化時間は６０〜１８０秒の範囲であることが好ましい。これら両樹脂に共通して、１５０℃におけるゲル化時間が１０秒未満となると保存安定性が低下する傾向にあり、１８０秒を超えると硬化時間が長くなり、生産性が低下する。これによれば、導電性樹脂が硬化してから絶縁性樹脂が硬化するため、バンプに対する導電性樹脂と絶縁性樹脂との膨張・収縮量の相違による負担が小さくなる。すなわち、導電性樹脂の硬化収縮量の方が絶縁性樹脂よりも大きい場合、導電性樹脂と絶縁性樹脂を同時に硬化させると、絶縁性樹脂によって導電性樹脂の硬化収縮が阻害されて半導体装置と支持基板に引張られた応力がバンプに生じるが、導電性樹脂が硬化してから絶縁性樹脂を硬化させることで、導電性樹脂と絶縁性樹脂の硬化収縮量の相違による影響をバンプが受けることなく、より確実に圧縮応力が作用し、優れた信頼性の電気的接続状態を得ることができる。なお、本発明においてゲル化時間とは、ＪＩＳ Ｃ２１０５（電機絶縁用無溶剤液状レジン試験方法）に準じて測定した値である。また、絶縁性樹脂の形成方法としては、その高さが半導体素子と支持基板の間隙よりも高く、未硬化の状態であれば、特に限定するものでなく、スクリーン印刷や、転写、ポッティングなど、従来公知の方法で形成することができる。
【００２４】
図１（ｅ）は、図１（ｂ）で作製した半導体素子１を支持基板８に実装する工程を示した図である。導電性樹脂からなるバンプ及び絶縁性樹脂の硬化は、一定温度でも、あるいは導電性樹脂のゲル化時間を経過した後に硬化温度を高めて硬化時間の短縮を図る温度プロファイルでもよい。また、硬化時間は、特に制限されないが、絶縁性樹脂のゲル化時間の１０倍以上であることが好ましい。
【００２５】
図１（ｆ）及び図２は、半導体素子１を支持基板８に実装して得られた半導体装置の一例を示す図である。このとき、絶縁性樹脂５がバンプ４に接触することなく、半導体素子と支持基板の一部のみを接続した構造（図１（ｆ））であっても、バンプ４全てを包含した構造（図２）であってもよい。図１（ｆ）の場合には、図３に示すように、半導体素子１と支持基板８の間隙に第２の絶縁性樹脂１０を充填してもよい。このとき、第２の絶縁性樹脂１０の熱膨張係数は、第１の絶縁性樹脂５の熱膨張係数と等しいことが好ましい。
【００２６】
図４および図５は、半導体装置を支持基板８に実装した半導体装置実装体の一例を示すの断面図である。本発明の半導体装置実装体は、上記半導体素子の実装時と同様に、半導体装置の電極と支持基板の電極を導電性樹脂からなるバンプで接合して得ることができ、半導体装置と支持基板の空隙には硬化後の熱膨張係数がバンプの硬化後の熱膨張係数よりも大きい絶縁性樹脂層が形成されている。その他の構造は特に限定されるものではなく、（１）ベアチップ（図１）、（２）ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）（図４）、（３）ＣＳＰ（ＣｈｉｐＳｉｚｅ Ｐａｃｋａｇｅ）、（４）ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）（図５）、（５）ＴＳＯＰ（Ｔｈｉｎ Ｓｏｌｉｄ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）などに適用可能である。
【００２７】
【実施例】
外形１０ｍｍ×８．５ｍｍの半導体素子の電極（直径０．４０ｍｍ）にビスフェノールＦ型エポキシ樹脂（東都化成（株）、ＹＤＦ−１７０）１０重量部、ビスフェノールＡ型エポキシ樹脂（油化シェルエポキシ（株）ＹＬ−９８０）１０重量部、硬化剤（四国化成（株）、キュアダクトＰ−０５０５）４重量部、硬化剤（四国化成（株）、キュアダクトＬ−０１Ｂ）２重量部、導電性フィラ（徳力化学研究所（株）、ＴＣＧ−１）１２０重量部、および希釈剤（東都化成（株）、Ｐ−１０１）４重量部からなる導電性樹脂（熱膨張係数４０×１０−６／℃、ゲル化時間５０秒／１５０℃）をスクリーン印刷法で印刷した後、１５０℃で１時間硬化してバンプを形成した。次いで、大きさ３０ｍｍ×３０ｍｍ、厚さ１．６ｍｍの支持基板（日立化成工業（株）製、商品名：Ｅ−６７）の電極に上記と同様の導電性樹脂をスクリーン印刷法で印刷し、さらに、支持基板の中央近傍の電極に接触しない領域にビスフェノールＦ型エポキシ樹脂（東都化成（株）、ＹＤＦ−１７０）７９重量部、脂環式エポキシ樹脂２１重量部、メチルテトラヒドロ無水フタル酸１２０重量部、球形溶融シリカ（平均粒径１５．２μｍ）４５０重量部、角形溶融シリカ（平均粒径１５．５μｍ）１５０重量部からなる第１の絶縁性樹脂（熱膨張係数５０×１０−６／℃、ゲル化時間１５０秒／１５０℃）をポッティングした。次いで、半導体素子の電極と支持基板の電極が互いに一致するように、半導体素子を支持基板上に搭載して、１５０℃で１時間硬化して半導体装置を得た。これを熱衝撃試験機（楠本化成（株）、ウインテクＮＴ５００）に投入して、−５５℃１５分間、１２５℃１５分間を１サイクルとする温度サイクル試験を行った。その結果、１０００サイクルまで、導電性樹脂接続部の不良、半導体装置内部のはく離及びクラックは観察されなかった。
【００２８】
【発明の効果】
本発明によれば、製造工程数およびコストの低減が可能であり、かつ電気的接続信頼性に優れる半導体装置、半導体装置実装体、およびこれらの製造方法を提供することができる。
【図面の簡単な説明】
【図１】本発明の半導体装置の製造過程の一実施例を示す断面図。
【図２】本発明の半導体装置の一例を示す断面図。
【図３】本発明の半導体装置の一例を示す断面図。
【図４】本発明の半導体装置実装体の一例を示す断面図。
【図５】本発明の半導体装置実装体の一例を示す断面図。
【図６】従来のフリップチップ実装方式の一例を示す断面図。
【符号の説明】
１ 半導体素子
２ 半導体素子保護膜
３ 電極
４ 導電性バンプ
５ 絶縁性樹脂
６ 導電性バンプ
７ 配線保護膜
８ 支持基板
９ 電極
１０ 絶縁性樹脂
１１ Ａｕ線
１２ 封止樹脂
１３ 半導体素子接着剤
１４ 第２回路基板
１５ 配線保護膜
１６ リード
１７ はんだバンプ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which a semiconductor element or a semiconductor device and a support substrate are electrically connected via a conductive resin, a semiconductor device package, and a method of manufacturing these.
[0002]
[Prior art]
In recent years, with the miniaturization of electronic devices and the increase in processing speed, the trend of increasing the number of pins, narrowing the pitch, and reducing the thickness of resin-encapsulated semiconductor packages has been progressing rapidly, and semiconductor devices have been directly mounted on supporting substrates. Many flip-chip mounting methods have been adopted. The flip mounting method is characterized in that not only the package can be reduced in size and thickness, but also that the distance between the electrode of the semiconductor element and the electrode of the supporting substrate can be minimized, so that high-frequency characteristics are excellent.
[0003]
FIG. 6 is a diagram showing an example of a flip chip mounting method. In the prior art, Sn—Pb-based solder is used as a bump material, and a barrier metal layer such as Cr or Au is formed on the Al electrode 3 formed on the circuit surface of the semiconductor element 1 to prevent the diffusion of the solder. Is formed. The solder bump is formed by mounting a spherical solder ball on the electrode 3 and then melting it in a reflow process. At this time, a flux is used to improve the wettability of the solder. Further, the mounting on the support substrate is performed by mounting the semiconductor element with the solder bump on the support substrate and performing the reflow process again. Further, in order to improve the connection reliability, the gap between the semiconductor element 1 and the support substrate 8 is improved. A semiconductor device can be obtained by injecting an underfill, which is a reinforcing resin, and curing it.
[0004]
However, in the method of mounting a semiconductor element or a semiconductor device using the solder as described above, (1) an increase in the manufacturing process and cost of the semiconductor device due to the formation of a barrier metal layer, and (2) an environmental load of Pb-based solder and legal regulations. And (3) contamination of the semiconductor device by the flux, and (4) an increase in the manufacturing process and cost of the semiconductor device due to underfill injection.
[0005]
In order to solve such a problem, a flip chip technology using a conductive resin has been proposed (for example, see Patent Document 1). According to this method, the formation of a conductive polymerizable precursor at the flip-chip bond pad provides an electrical connection between the flip-chip bond pad and the substrate bond pad, which is lower than the solder reflow. It is possible to polymerize bumps under conditions, significantly reduce the reliability problems caused by large mismatches in the coefficients of thermal expansion of chips and substrates, and use a wide range of substrates because bump polymerization can be performed at low temperatures. In addition, there is no need for complicated and long-time deposition and electroplating for forming solder bumps, and further, no flux is required.
[0006]
[Patent Document 1]
Japanese Patent No. 2717993 [Patent Document 2]
JP-A-2000-236002 (FIG. 1)
[0007]
[Problems to be solved by the invention]
However, since the above-mentioned technology does not reinforce the gap between the chip and the substrate with an insulating resin, it is susceptible to a drop impact or a thermal cycle repeatedly exposed to high and low temperatures, and has a problem that electrical connection reliability is low. On the other hand, a method has been proposed in which a reinforcing resin is injected into the gap between the chip and the substrate to reduce the influence on the connection site due to a change in the surrounding environment (for example, see Patent Document 2). In this case, two types of resin are required, ie, an adhesive sealing resin for adhering the resin and a protective sealing resin for protecting the connection site.
[0008]
In view of the above, an object of the present invention is to provide a semiconductor device, a semiconductor device package, and a method for manufacturing the same, which can reduce the number of manufacturing steps and cost and are excellent in electrical connection reliability. .
[0009]
[Means for Solving the Problems]
The present invention relates to a semiconductor device in which a bump electrically connecting an electrode pad of a semiconductor element and an electrode pad of a support substrate is made of a conductive resin, and a gap between the semiconductor element and the support substrate is supported by an insulating resin. In addition, a semiconductor device is provided in which the thermal expansion coefficient of the insulating resin is larger than the thermal expansion coefficient of the conductive resin.
[0010]
Further, according to the present invention, there is provided a semiconductor device wherein a bump electrically connecting an electrode pad of a semiconductor device and an electrode pad of a support substrate is made of a conductive resin, and a gap between the semiconductor device and the support substrate is supported by an insulating resin. Provided is a device mounted body, wherein the thermal expansion coefficient of the insulating resin is larger than the thermal expansion coefficient of the conductive resin.
[0011]
The present invention also provides a step of forming a bump made of a conductive resin on an electrode pad of a semiconductor element, a step of curing the conductive resin, and a step of forming a bump made of a conductive resin on an electrode pad of a support substrate. Applying an insulating resin having a thermal expansion coefficient larger than that of the conductive resin to a semiconductor element mounting area on the support substrate so as to be higher than bumps formed on electrode pads of the semiconductor element; and Providing a method of manufacturing a semiconductor device, comprising: a step of bonding a semiconductor element and a support substrate such that both bumps of the substrate and the support substrate overlap each other; and a step of curing a conductive resin and an insulating resin. .
[0012]
Further, the present invention provides a step of forming a bump made of a conductive resin on an electrode pad of a semiconductor element, a step of curing the conductive resin to a B stage, and a coefficient of thermal expansion larger than that of the conductive resin. A step of applying an insulating resin to a semiconductor element mounting area on the support substrate so as to be higher than a bump formed on an electrode pad of the semiconductor element; and a step of applying a semiconductor element such that the bump of the semiconductor element and the electrode pad of the support substrate overlap with each other. And a supporting substrate, and a step of curing the conductive resin and the insulating resin.
[0013]
Further, the present invention provides a step of forming a bump made of a conductive resin on an electrode pad of a semiconductor device, a step of curing the conductive resin, and a step of forming a bump made of a conductive resin on an electrode pad of a support substrate. Applying an insulating resin having a thermal expansion coefficient larger than that of the conductive resin to a semiconductor device mounting area on the support substrate so as to be higher than bumps formed on electrode pads of the semiconductor device; and Bonding the semiconductor device and the support substrate such that both bumps of the semiconductor substrate and the support substrate overlap with each other, and curing the conductive resin and the insulating resin. provide.
[0014]
Further, the present invention provides a step of forming a bump made of a conductive resin on an electrode pad of a semiconductor device, a step of curing the conductive resin to a B stage, and a coefficient of thermal expansion larger than that of the conductive resin. A step of applying an insulating resin to the semiconductor device mounting area on the support substrate so as to be higher than the bumps formed on the electrode pads of the semiconductor device; and a step of applying the semiconductor device such that the bumps of the semiconductor device and the electrode pads of the support substrate overlap with each other. And a step of curing the conductive resin and the insulating resin.
[0015]
According to the present invention, since the coefficient of thermal expansion of the insulating resin is larger than the coefficient of thermal expansion of the conductive resin, after the curing of both resins, when the temperature is below the curing temperature, the insulating resin shrinks more than the conductive resin, Compressive stress acts on the bump made of the conductive resin, and as a result, the adhesion between the electrode pad and the bump is improved, and a highly reliable electrical connection state can be obtained.
[0016]
Further, it is preferable that the gelation time of the insulating resin used in the present invention is longer than that of the conductive resin. According to this, since the insulating resin is hardened after the conductive resin is hardened, the load on the bumps due to the difference in the amount of expansion and contraction between the conductive resin and the insulating resin is reduced, and an appropriate compressive stress is applied to the bumps. And the electrical connection reliability is further ensured.
[0017]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
A feature of the present invention is that, in a method for mounting a semiconductor element or a semiconductor device on a substrate using bumps made of a conductive resin, an insulating resin having a larger thermal expansion coefficient than the conductive resin is mounted and cured at the same time as the conductive resin. On the point.
[0019]
FIG. 1 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of the present invention.
[0020]
FIG. 1A is a diagram showing a general structure of a semiconductor device. The semiconductor element 1 of the present invention is not particularly limited as long as an electronic circuit is formed, and any type or size of semiconductor element can be used. For example, a semiconductor element in which a memory circuit is formed, a semiconductor element in which a logic circuit is formed, and the like are given. An electrode 3 is provided on the upper surface of the semiconductor element 1, and may be made of aluminum or a gold-plated electrode, and is not particularly limited. Further, a semiconductor element protection film 2 is formed on the upper surface of the semiconductor element 1. The semiconductor element protection film 2 may be a conventionally known film such as a nitride film or a polyimide film, and is not particularly limited.
[0021]
FIG. 1B is a diagram in which bumps 4 made of a conductive resin are formed on the electrodes 3 of the semiconductor element. The conductive resin forming the bump is not particularly limited, but is a resin containing at least a conductive fine powder and a resin, and has a coefficient of thermal expansion in a range of 35 × 10 −6 to 50 × 10 −6 / ° C. Is preferred. Thermal expansion coefficient tends to adhesion deteriorates the proportion of the resin is lower than the conductive fine powder is less than 35 × 10 -6 / ℃, conductivity exceeds 50 × 10 -6 / ℃ The amount of fine powder decreases, and the conductivity tends to deteriorate. The material of the conductive fine powder is not particularly limited as long as it has conductivity after the conductive resin is cured. Metal fine powders such as Ag, Cu, Ni, Pd, Al, and Au, and metal fine powders Powder obtained by plating the surface with a dissimilar metal, powder obtained by coating the surface of a resin powder with a metal such as Au, carbon powder, or a mixture of the aforementioned conductive fine powder. The resin is not particularly limited as long as it can be cured by heat, and examples thereof include a thermosetting resin such as an epoxy resin and a phenol resin, and a solvent-drying resin such as polyamideimide. The method for forming the bump is not particularly limited, and the bump can be formed by a conventionally known method such as screen printing, transfer, potting, and a photo process.
[0022]
FIG. 1C is a diagram in which bumps 6 made of a conductive resin are formed on electrodes 9 of a support substrate 8. The bumps here are formed using the same conductive resin as described above and by the same forming method as described above. When the bumps 4 formed on the electrodes 3 of the semiconductor element 1 are in the B-stage state and are directly adhered and cured on the electrodes 9 of the support substrate 8, the bumps 6 of the support substrate 8 are not particularly provided. Is also good.
[0023]
FIG. 1D is a diagram in which a layer of an insulating resin 5 is formed on a support substrate. The insulating resin used here may be cured by heat and have a coefficient of thermal expansion larger than that of the bump, but preferably has a coefficient of thermal expansion of 40 × 10 −6 to 60 × 10 −6 / ° C. Things. The material is not limited, and examples thereof include a thermosetting resin such as an epoxy resin and a phenol resin, and a solvent-drying resin such as polyamideimide. Further, it is preferable that the curing speed is lower than that of the conductive resin forming the bumps, that is, it is an insulating resin having a long gelation time. Further, (gelation time of insulating resin / gelling time of conductive resin) Is more preferably greater than 1.5, particularly preferably greater than 2.0. For example, the gel time of the conductive resin at 150 ° C. is preferably in the range of 10 to 60 seconds, and the gel time of the insulating resin is preferably in the range of 60 to 180 seconds. When the gelation time at 150 ° C. is shorter than 10 seconds, the storage stability tends to decrease. When the gelation time exceeds 180 seconds, the curing time increases, and the productivity decreases. According to this, since the insulating resin is hardened after the conductive resin is hardened, the burden due to the difference in the amount of expansion and contraction between the conductive resin and the insulating resin on the bumps is reduced. That is, when the amount of curing shrinkage of the conductive resin is larger than that of the insulating resin, if the conductive resin and the insulating resin are simultaneously cured, the curing shrinkage of the conductive resin is hindered by the insulating resin and the semiconductor device is hardened. The tensile stress applied to the supporting substrate is applied to the bumps, but the conductive resin is cured before the insulating resin is cured, so that the bumps are affected by the difference in the amount of curing shrinkage between the conductive resin and the insulating resin. Therefore, a compressive stress acts more reliably, and an electrical connection state with excellent reliability can be obtained. In the present invention, the gelation time is a value measured according to JIS C2105 (Testing method for solvent-free liquid resin for electrical insulation). In addition, as a method for forming the insulating resin, the height is higher than the gap between the semiconductor element and the support substrate, and is not particularly limited as long as it is in an uncured state.Screen printing, transfer, potting, It can be formed by a conventionally known method.
[0024]
FIG. 1E shows a step of mounting the semiconductor element 1 manufactured in FIG. 1B on a support substrate 8. The curing of the conductive resin bumps and the insulating resin may be performed at a fixed temperature or a temperature profile in which the curing time is increased after the gelling time of the conductive resin is increased to shorten the curing time. The curing time is not particularly limited, but is preferably at least 10 times the gelation time of the insulating resin.
[0025]
FIGS. 1F and 2 are diagrams illustrating an example of a semiconductor device obtained by mounting the semiconductor element 1 on a support substrate 8. At this time, even if the insulating resin 5 does not come into contact with the bumps 4 and only the semiconductor element and a part of the support substrate are connected (FIG. 1F), the structure including all the bumps 4 (FIG. 2). In the case of FIG. 1F, the gap between the semiconductor element 1 and the support substrate 8 may be filled with the second insulating resin 10 as shown in FIG. At this time, the coefficient of thermal expansion of the second insulating resin 10 is preferably equal to the coefficient of thermal expansion of the first insulating resin 5.
[0026]
FIGS. 4 and 5 are cross-sectional views illustrating an example of a semiconductor device mounted body in which the semiconductor device is mounted on a support substrate 8. The semiconductor device mounted body of the present invention can be obtained by bonding the electrodes of the semiconductor device and the electrodes of the support substrate with bumps made of a conductive resin, as in the case of mounting the semiconductor element, and forming the semiconductor device and the support substrate. An insulating resin layer whose thermal expansion coefficient after curing is larger than the thermal expansion coefficient after curing of the bump is formed in the gap. Other structures are not particularly limited. (1) Bare chip (FIG. 1), (2) BGA (Ball Grid Array) (FIG. 4), (3) CSP (ChipSize Package), (4) QFP (Quad) Flat Package (FIG. 5), (5) TSOP (Thin Solid Outline Package) and the like.
[0027]
【Example】
10 parts by weight of a bisphenol F type epoxy resin (Toto Kasei Co., Ltd., YDF-170) and a bisphenol A type epoxy resin (Yuika Shell Epoxy Co., Ltd.) are applied to the electrodes (diameter 0.40 mm) of a semiconductor element having an outer shape of 10 mm × 8.5 mm. ) YL-980) 10 parts by weight, curing agent (Shikoku Chemicals Co., Ltd., Cureduct P-0505) 4 parts by weight, curing agent (Shikoku Chemicals Co., Ltd., Cureduct L-01B) 2 parts by weight, conductive filler (Tokuriki Chemical Laboratory Co., Ltd., TCG-1) 120 parts by weight and a diluent (Toto Kasei Co., Ltd., P-101) 4 parts by weight of a conductive resin (coefficient of thermal expansion 40 × 10 −6 / ° C.) , A gel time of 50 seconds / 150 ° C.), and then cured at 150 ° C. for 1 hour to form a bump. Next, the same conductive resin as described above was printed on an electrode of a support substrate (manufactured by Hitachi Chemical Co., Ltd., trade name: E-67) having a size of 30 mm × 30 mm and a thickness of 1.6 mm by screen printing, Further, 79 parts by weight of a bisphenol F-type epoxy resin (Toto Kasei Co., Ltd., YDF-170), 21 parts by weight of an alicyclic epoxy resin, and 120 parts by weight of methyltetrahydrophthalic anhydride are provided in a region near the center of the support substrate which is not in contact with the electrode. Parts, 450 parts by weight of spherical fused silica (average particle size: 15.2 μm) and 150 parts by weight of square fused silica (average particle size: 15.5 μm) (coefficient of thermal expansion: 50 × 10 −6 / ° C.) , Gel time 150 seconds / 150 ° C.). Next, the semiconductor element was mounted on the support substrate so that the electrode of the semiconductor element and the electrode of the support substrate coincided with each other, and cured at 150 ° C. for 1 hour to obtain a semiconductor device. This was put into a thermal shock tester (Kusumoto Kasei Co., Ltd., Wintech NT500), and a temperature cycle test was performed in which one cycle was performed at -55 ° C for 15 minutes and 125 ° C for 15 minutes. As a result, up to 1000 cycles, no defect in the conductive resin connection portion, peeling and cracks inside the semiconductor device were not observed.
[0028]
【The invention's effect】
According to the present invention, it is possible to provide a semiconductor device, a semiconductor device package, and a method for manufacturing the same, which can reduce the number of manufacturing steps and cost and have excellent electrical connection reliability.
[Brief description of the drawings]
FIG. 1 is a sectional view showing one embodiment of a process of manufacturing a semiconductor device of the present invention.
FIG. 2 is a cross-sectional view illustrating an example of a semiconductor device of the present invention.
FIG. 3 is a cross-sectional view illustrating an example of a semiconductor device of the present invention.
FIG. 4 is a cross-sectional view illustrating an example of a semiconductor device package according to the present invention.
FIG. 5 is a cross-sectional view illustrating an example of a semiconductor device package according to the present invention.
FIG. 6 is a cross-sectional view showing an example of a conventional flip chip mounting method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Semiconductor element protective film 3 Electrode 4 Conductive bump 5 Insulating resin 6 Conductive bump 7 Wiring protective film 8 Support substrate 9 Electrode 10 Insulating resin 11 Au wire 12 Sealing resin 13 Semiconductor element adhesive 14 Second Circuit board 15 Wiring protective film 16 Lead 17 Solder bump

Claims (10)

半導体素子の電極パッドと支持基板の電極パッドを電気的に接続するバンプが導電性樹脂から成り、前記半導体素子と前記支持基板の間の空隙が絶縁性樹脂により支持されている半導体装置であって、前記絶縁性樹脂の熱膨張係数が前記導電性樹脂の熱膨張係数よりも大きいことを特徴とする半導体装置。A semiconductor device in which a bump electrically connecting an electrode pad of a semiconductor element and an electrode pad of a support substrate is made of a conductive resin, and a gap between the semiconductor element and the support substrate is supported by an insulating resin. A semiconductor device, wherein the thermal expansion coefficient of the insulating resin is larger than the thermal expansion coefficient of the conductive resin. 前記絶縁性樹脂のゲル化時間が、前記導電性樹脂よりも長いことを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the gelling time of the insulating resin is longer than that of the conductive resin. 半導体装置の電極パッドと支持基板の電極パッドを電気的に接続するバンプが導電性樹脂から成り、前記半導体装置と前記支持基板の間の空隙が絶縁性樹脂により支持されている半導体装置実装体であって、前記絶縁性樹脂の熱膨張係数が前記導電性樹脂の熱膨張係数よりも大きいことを特徴とする半導体装置実装体。A bump that electrically connects an electrode pad of a semiconductor device and an electrode pad of a support substrate is made of a conductive resin, and a gap between the semiconductor device and the support substrate is a semiconductor device mounted body supported by an insulating resin. Wherein the thermal expansion coefficient of the insulating resin is larger than the thermal expansion coefficient of the conductive resin. 前記絶縁性樹脂のゲル化時間が、前記導電性樹脂よりも長いことを特徴とする請求項３記載の半導体装置実装体。4. The semiconductor device package according to claim 3, wherein the gelling time of the insulating resin is longer than that of the conductive resin. 半導体素子の電極パッドに導電性樹脂からなるバンプを形成する工程と、前記導電性樹脂を硬化させる工程と、支持基板の電極パッドに導電性樹脂からなるバンプを形成する工程と、熱膨張係数が前記導電性樹脂の熱膨張係数よりも大きい絶縁性樹脂を前記支持基板上の半導体素子実装領域に、前記半導体素子の電極パッドに形成したバンプよりも高くなるように、塗布する工程と、前記半導体素子と前記支持基板の両バンプが互いに重なるように前記半導体素子と前記支持基板を接合する工程と、前記導電性樹脂と前記絶縁性樹脂を硬化させる工程と、を含むことを特徴とする半導体装置の製造方法。Forming a bump made of a conductive resin on the electrode pad of the semiconductor element, curing the conductive resin, forming a bump made of the conductive resin on the electrode pad of the support substrate, Applying an insulating resin having a coefficient of thermal expansion greater than that of the conductive resin to a semiconductor element mounting region on the support substrate so as to be higher than a bump formed on an electrode pad of the semiconductor element; A semiconductor device comprising: a step of joining the semiconductor element and the support substrate so that both bumps of the element and the support substrate overlap with each other; and a step of curing the conductive resin and the insulating resin. Manufacturing method. 半導体素子の電極パッドに導電性樹脂からなるバンプを形成する工程と、前記導電性樹脂をＢステージまで硬化させる工程と、熱膨張係数が前記導電性樹脂の熱膨張係数よりも大きい絶縁性樹脂を前記支持基板上の半導体素子実装領域に、前記半導体素子の電極パッドに形成したバンプよりも高くなるように、塗布する工程と、前記半導体素子のバンプと前記支持基板の電極パッドが互いに重なるように前記半導体素子と前記支持基板を接合する工程と、前記導電性樹脂と前記絶縁性樹脂を硬化させる工程と、を含むことを特徴とする半導体装置の製造方法。A step of forming a bump made of a conductive resin on an electrode pad of a semiconductor element, a step of curing the conductive resin to a B stage, and a step of forming an insulating resin having a coefficient of thermal expansion larger than that of the conductive resin. In the semiconductor element mounting area on the support substrate, a coating step is performed so that the height is higher than the bumps formed on the electrode pads of the semiconductor element, and the bumps of the semiconductor element and the electrode pads of the support substrate overlap with each other. A method of manufacturing a semiconductor device, comprising: a step of joining the semiconductor element and the support substrate; and a step of curing the conductive resin and the insulating resin. 前記絶縁性樹脂のゲル化時間が、前記導電性樹脂よりも長いことを特徴とする請求項５または６記載の半導体装置の製造方法。7. The method according to claim 5, wherein the gelling time of the insulating resin is longer than that of the conductive resin. 半導体装置の電極パッドに導電性樹脂からなるバンプを形成する工程と、前記導電性樹脂を硬化させる工程と、支持基板の電極パッドに導電性樹脂からなるバンプを形成する工程と、熱膨張係数が前記導電性樹脂の熱膨張係数よりも大きい絶縁性樹脂を前記支持基板上の半導体装置実装領域に、前記半導体装置の電極パッドに形成したバンプよりも高くなるように、塗布する工程と、前記半導体装置と前記支持基板の両バンプが互いに重なるように前記半導体装置と前記支持基板を接合する工程と、前記導電性樹脂と前記絶縁性樹脂を硬化させる工程と、を含むことを特徴とする半導体装置実装体の製造方法。A step of forming a bump made of a conductive resin on an electrode pad of the semiconductor device, a step of curing the conductive resin, a step of forming a bump made of a conductive resin on the electrode pad of the support substrate, Applying an insulating resin having a coefficient of thermal expansion greater than that of the conductive resin to a semiconductor device mounting region on the support substrate so as to be higher than bumps formed on electrode pads of the semiconductor device; and A semiconductor device comprising: a step of bonding the semiconductor device and the support substrate such that both bumps of the device and the support substrate overlap with each other; and a step of curing the conductive resin and the insulating resin. Manufacturing method of the mounted body. 半導体装置の電極パッドに導電性樹脂からなるバンプを形成する工程と、前記導電性樹脂をＢステージまで硬化させる工程と、熱膨張係数が前記導電性樹脂の熱膨張係数よりも大きい絶縁性樹脂を前記支持基板上の半導体装置実装領域に、前記半導体装置の電極パッドに形成したバンプよりも高くなるように、塗布する工程と、前記半導体装置のバンプと前記支持基板の電極パッドが互いに重なるように前記半導体装置と前記支持基板を接合する工程と、前記導電性樹脂と前記絶縁性樹脂を硬化させる工程と、を含むことを特徴とする半導体装置実装体の製造方法。A step of forming a bump made of a conductive resin on an electrode pad of a semiconductor device, a step of curing the conductive resin to a B stage, and a step of forming an insulating resin having a coefficient of thermal expansion larger than that of the conductive resin. In the semiconductor device mounting area on the support substrate, a coating step is performed so that the height is higher than the bumps formed on the electrode pads of the semiconductor device, and the bumps of the semiconductor device and the electrode pads of the support substrate overlap with each other. A method for manufacturing a semiconductor device package, comprising: a step of joining the semiconductor device and the support substrate; and a step of curing the conductive resin and the insulating resin. 前記絶縁性樹脂のゲル化時間が、前記導電性樹脂よりも長いことを特徴とする請求項８または９記載の半導体装置実装体の製造方法。The method according to claim 8, wherein a gelation time of the insulating resin is longer than that of the conductive resin.
JP2002342083A 2002-11-26 2002-11-26 Semiconductor device and method for manufacturing semiconductor device package Expired - Fee Related JP3951903B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002342083A JP3951903B2 (en) 2002-11-26 2002-11-26 Semiconductor device and method for manufacturing semiconductor device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002342083A JP3951903B2 (en) 2002-11-26 2002-11-26 Semiconductor device and method for manufacturing semiconductor device package

Publications (2)

Publication Number Publication Date
JP2004179292A true JP2004179292A (en) 2004-06-24
JP3951903B2 JP3951903B2 (en) 2007-08-01

Family

ID=32704236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002342083A Expired - Fee Related JP3951903B2 (en) 2002-11-26 2002-11-26 Semiconductor device and method for manufacturing semiconductor device package

Country Status (1)

Country Link
JP (1) JP3951903B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8183690B2 (en) 2007-08-13 2012-05-22 Seiko Epson Corporation Electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8183690B2 (en) 2007-08-13 2012-05-22 Seiko Epson Corporation Electronic device

Also Published As

Publication number Publication date
JP3951903B2 (en) 2007-08-01

Similar Documents

Publication Publication Date Title
US6696644B1 (en) Polymer-embedded solder bumps for reliable plastic package attachment
US7214561B2 (en) Packaging assembly and method of assembling the same
US6693349B2 (en) Semiconductor chip package having a leadframe with a footprint of about the same size as the chip
KR100511728B1 (en) Compact semiconductor device capable of mounting a plurality of semiconductor chips with high density and method of manufacturing the same
TWI453840B (en) Protected solder ball joints in wafer level chip-scale packaging
JP3450236B2 (en) Semiconductor device and manufacturing method thereof
US20020030261A1 (en) Multi-flip-chip semiconductor assembly
US6448108B1 (en) Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
US6933221B1 (en) Method for underfilling semiconductor components using no flow underfill
WO1999036957A1 (en) Semiconductor package
JP3277997B2 (en) Ball grid array package and manufacturing method thereof
US20040222522A1 (en) Semiconductor device and manufacturing method of the same
US6841884B2 (en) Semiconductor device
US6544813B1 (en) Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
KR100809698B1 (en) Mounting structure of semiconductor device having soldering flux and under fill resin layer and method of mounting method of semiconductor device
JP3116926B2 (en) Package structure and semiconductor device, package manufacturing method, and semiconductor device manufacturing method
JP2003086626A (en) Electronic component and manufacturing method thereof, and packaged body and packaging method for electronic component
JP3951903B2 (en) Semiconductor device and method for manufacturing semiconductor device package
KR100192758B1 (en) Method of manufacturing semiconductor package and structure of the same
JPH10321750A (en) Semiconductor device and manufacture of wiring board having semiconductor chip mounted thereon
JP2914569B1 (en) Semiconductor device mounting method and its mounting body
JP2003297977A (en) Method for producing electronic component
KR0127034B1 (en) Semiconductor package and the manufacture method
JP2001185642A (en) Package substrate for mounting semiconductor
JPH0680701B2 (en) Chip carrier with pin

Legal Events

Date Code Title Description
A621 Written request for application examination

Effective date: 20050909

Free format text: JAPANESE INTERMEDIATE CODE: A621

A977 Report on retrieval

Effective date: 20061222

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070109

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070309

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070403

A61 First payment of annual fees (during grant procedure)

Effective date: 20070416

Free format text: JAPANESE INTERMEDIATE CODE: A61

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100511

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110511

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 4

Free format text: PAYMENT UNTIL: 20110511

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120511

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130511

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees