KR20030078706A - Semiconductor device - Google Patents

Abstract

Board; A first semiconductor chip mounted on the substrate with a gap of 0.055 mm or less from the substrate and having a thickness of 0.25 mm or less through flip chip connection; A conductive connection member for electrically connecting the chip to the substrate; And a molding resin layer disposed on the substrate so as to cover the chip, the molding resin layer being formed of a cured resin compound including 75-92 wt% of an inorganic filler and 0.5-1.5 wt% of carbon black, and opposing the substrate of the molding resin layer. The content of the fine filler having a thickness of 0.15 mm or less, 99% by weight of the inorganic filler having a longest diameter of 35 µm or less, an average longest diameter of 15 µm or less, and a longest diameter of 10 µm or less is determined by the amount of the inorganic filler. A semiconductor device is disclosed that is limited to within the range of 30 to 50 weight percent based on total weight.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a semiconductor chip is encapsulated using an encapsulating resin.

As recent technological advances in the field of semiconductor integrated circuits enhance integration and the reliability of semiconductor integrated circuits, efforts to further miniaturize and thin semiconductor devices have been concentrated. In order to satisfy this trend, there is an increasing demand for the development of encapsulating resins having excellent properties.

In a conventional flip chip type quad outline nonlead package (QON), the semiconductor chip 4 is mounted through the conductive connection member 2 on the surface of the substrate 1 as shown in FIG. In this case, the substrate 1 is made of resin or ceramic, and a wiring circuit (not shown) is provided on the surface thereof. The substrate 1 is also provided at its lower side with a terminal 6 for external connection. The conductive connection member 2 is composed of a bump 2a for a wiring circuit terminal of the substrate 1 and a bump 2b for a semiconductor chip. These bumps are formed, for example, of gold or solder.

The encapsulation resin layer 5 is disposed on the upper surface and side surfaces of the semiconductor chip 4 and in the space or gap between the substrate 1 and the semiconductor chip 4. This encapsulation resin layer 5 can be formed by tying and sealing a substrate with a semiconductor chip 4 mounted by a molding resin compound.

Since the space or gap between the substrate 1 and the semiconductor chip 4 has a small height compared to the distance between the mold and the semiconductor chip 4, the voids are formed by using a molding resin compound. It is more likely to occur in the above-mentioned space or gap when sealing together.

By the way, the technique for thinning the body of a semiconductor device has advanced more recently, and the thickness of the encapsulation resin layer 5 is inevitably thinned. Therefore, the molding resin compound is perfectly disposed on the upper surface of the semiconductor chip 4, and it is difficult to fill the above-mentioned space or gap in the molding resin compound in the process of encapsulating the semiconductor device by using the molding resin compound. This raises the problem of increasing the possibility of generating voids therein.

In particular, if voids exist in the space between the substrate 1 and the semiconductor chip 4, the semiconductor chip 4 is subjected to pressure generated when the space is filled with the molding resin compound. As a result, the center portion of the semiconductor chip 4 is pushed downward, causing cracks in the semiconductor chip 4. The resin layer is peeled off from the voids and cracks are generated, thereby deteriorating the reliability of the semiconductor device for a long time.

In the case of filling the space with the molding resin compound, it is possible to suppress the generation of voids by increasing the pressure and the temperature. However, the semiconductor chip will either flow away by the pressure used in this filling or will melt by high temperatures.

These problems cause significant deterioration in the reliability of the semiconductor device.

Therefore, an object of the present invention is to provide a semiconductor device capable of improving the reliability of the semiconductor device.

1 is a cross-sectional view illustrating a semiconductor device according to the prior art.

2 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

3 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

4 is a sectional view illustrating a semiconductor device according to another embodiment of the present invention.

5 is a sectional view illustrating a semiconductor device according to another embodiment of the present invention.

6 is a sectional view illustrating a semiconductor device according to another embodiment of the present invention.

7 is a sectional view illustrating a semiconductor device according to another embodiment of the present invention.

8 is a sectional view illustrating a semiconductor device according to another embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

1: substrate

2: conductive connection member

4: semiconductor chip

5: encapsulation resin layer

6: terminal

In a semiconductor device according to an embodiment of the present invention,

Board;

A first semiconductor chip mounted on the substrate at a thickness of 0.25 mm or less through a flip chip connection at a distance of 0.055 mm or less from the substrate;

A conductive connection member for electrically connecting the first semiconductor chip to the substrate; And

A molding resin layer disposed on the substrate to cover the first semiconductor chip and formed of a cured resin compound including 75-92 wt% of an inorganic filler and 0.5-1.5 wt% of carbon black; The thickness of the portion facing the substrate is 0.15 mm or less, and the 99% by weight of the inorganic filler has a longest diameter of 35 µm or less, an average longest diameter of 15 µm or less, and a longest diameter of 10 µm or less. ) Is limited to within the range of 30 to 50% by weight based on the total weight of the inorganic filler-

It includes.

A semiconductor device according to another embodiment of the present invention,

Board;

A first semiconductor chip mounted on the substrate;

A first wire having a diameter of 28 μm or less and electrically connecting the first semiconductor chip to the substrate; And

A molding resin layer disposed on the substrate to cover the first semiconductor chip and formed of a cured resin compound including 75-92 wt% of an inorganic filler and 0.5-1.5 wt% of carbon black; The thickness of the part facing the substrate is 0.2 mm or less, and the 99% by weight of the inorganic filler has a longest diameter of 35 m or less, an average longest diameter of 15 m or less, and a content of the fine filler having a longest diameter of 10 m or less. Limited to within the range of 30-50% by weight based on the total weight of the inorganic filler-

It includes.

Embodiments according to the present invention are described in detail below with reference to the drawings.

2 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

In the semiconductor device shown below, the semiconductor chip 4 is mounted on the surface of the substrate 1 via the conductive connecting member 2. The substrate 1 is made of polyimide tape or ceramic and provided below the terminal 6 for external connection.

Although not shown in the figure, the conductive connecting member 2 is composed of a bump for the semiconductor chip 4 and a bump for a wiring circuit terminal of the substrate 1. These bumps are for example tin / silver solder, gold, tin / lead solder, tin, tin / silver / copper solder. It is formed of tin / zinc solder, tin / bismuth solder or nickel. The terminal 6 for external connection is formed, for example, of tin / silver solder, tin / lead solder or tin.

The encapsulating resin layer 5 is disposed on the top and side surfaces of the semiconductor chip 4, on the top surface of the substrate 1, and in the space between the substrate 1 and the semiconductor chip 4.

In the semiconductor device shown in FIG. 2, the height of the space between the substrate 1 and the semiconductor chip 4 is 0.055 mm or less, and the thickness of the semiconductor chip 4 is 0.25 mm or less. Moreover, the thickness of a part of the encapsulating resin layer 5 opposite to the substrate is 0.15 m or less. In this case, the thickness of a part of the encapsulating resin layer 5 disposed over the semiconductor chip 4 is 0.15 mm or less. These dimensions are limited as described above to minimize the thickness of the entire semiconductor device.

The overall height (distance measured from the external connection terminal 6 to the upper surface of the molding resin layer 5) of the semiconductor device is preferably 0.500 mm or less. Moreover, part of the encapsulating resin layer 5 disposed over the semiconductor chip 4 is preferably limited to a thickness about three times the height of the space.

In order to form a molding resin layer and to prevent the generation of voids in a narrow space of 0.055 mm or less, it is required to employ a molding resin compound having excellent fluidity and molding ability. Therefore, in order to obtain an optimal molding resin compound, various studies have been made by the inventors.

The molding resin compound includes an inorganic filler, an epoxy resin, a phenol resin, a curing accelerator, and carbon black.

With respect to the epoxy resins, there are no specific restrictions and are therefore selected from those comprising two or more epoxy groups per molecule. Specific examples of such epoxy resins include, for example, orthocresol novolac epoxy resins, dicylopentadiene-modified epoxy resins, triphenol methane type epoxy resins, biphenyl type epoxy resins and epi -Pi-bis type epoxy resins are included. These epoxy resins are employed singly or in combination.

As for the phenol resin, there are no specific limitations as long as two or more phenol hydroxyl group groups are provided which can serve as epoxy groups of the epoxy resin. Specific examples of such phenolic resins include, for example, phenol novolak resins, phenol aralkyl resins, naphthol aralkyl resins and dichloropentadiane-modified phenolic resins. These epoxy resins are employed singly or in combination.

As the curing accelerator, various kinds of curing accelerators such as phosphorus curing accelerators, imidazolic curing accelerators, DBU type curing accelerators and the like are employed. These curing accelerators are employed singly or in combination. The mixing ratio of these curing accelerators is preferably in the range of 0.01 to 5% of the weight based on the total weight of the resin compound. If this mixing ratio is less than 0.01% by weight, the gelling time of the resin compound is extended, and at the same time the curing property of the resin compound is degraded. On the other hand, if this mixing ratio exceeds 5% by weight, the fluidity of the resin compound is greatly deteriorated, leading to deterioration in electrical properties and also in humidity resistance of the molding resin layer.

The carbon black is integrated with it for the purpose of preventing the malfunction of the semiconductor chip caused by the transmission of light, so that it can be any of the predetermined types generally employed as a sealing or encapsulating material.

The fluidity of the molding resin compound largely depends on the kind of inorganic filler to be integrated. For the purpose of comparison, as shown in Table 1 below, eight types of molding resin compounds are provided using different types of fused silica as inorganic fillers.

Thereafter, the semiconductor device shown in FIG. 2 is manufactured using each of these molding resin compounds. In this case, the filling property which fills the space between these molding resin compounds with the board | substrate 1 and the semiconductor chip 4 is investigated. In this evaluation, a molding resin compound in which no voids occur in this space is represented by "0", and a molding resin compound in which voids are generated in that space is represented by "X".

Incidentally, at least 30 samples are irradiated and the void is defined as having at least 0.20 mm in the longer diameter.

Resin number Configuration Longest diameter (μm) Average diameter (㎛) Content (wt%) Filler properties One Crushed 105 30 86 X 2 rectangle 75 16 86 X 3 rectangle 75 9 86 X 4 rectangle 75 6 86 X 5 rectangle 75 6 82 X 6 rectangle 35 9 86 O 7 rectangle 35 6 86 O 8 rectangle 35 6 82 O

The longest diameter refers to the length of the longest part of the particles of the inorganic filler, and the average diameter refers to the average value of the longest diameter of the filler particles.

As shown in Table 1, the molding resin mixtures indicated by Resins Nos. 6 and 7 were excellent in filler properties. Thus, the inorganic fillers useful in the examples of the present invention were defined as having the longest diameter of 35 μm or less and the average diameter of 15 μm or less. Incidentally, in the embodiment of the present invention, particles of 99% or more by weight of the inorganic filler need to satisfy the above-mentioned conditions regarding the longest diameter. The particle content of the inorganic filler that satisfies the above-mentioned conditions is preferably 99.9% or more by weight, and more preferably 99.99% or more by weight.

In the fused silica used in these resins Nos. 6, 7, and 8, the proportion of the fine filler having the longest diameter of 10 µm or less is defined within the range of 30 to 50% by weight based on the total weight of the fused silica.

In addition, it was found when the content of the inorganic filler was 75% by weight or less and the reflow resistance and packaging reliability of the semiconductor device were deteriorated. In addition, the upper limit of content of an inorganic filler was restrict | limited to 92% weight for the convenience of manufacture of molding resin.

In view of the foregoing, the inorganic filler to be incorporated into the molding resin mixture used in the embodiments of the present invention is defined to have the following characteristics:

(1) the longest diameter is 35 μm or less;

(2) the average diameter is 15 µm or less;

(3) the content of the fine filler having the longest diameter of 10 µm or less is defined within the range of 30 to 50% by weight;

(4) The content of the inorganic filler is limited within the range of 75 to 92% by weight.

In the above description, the fused silica is described as an example of the inorganic filler. However, as long as the above conditions are met, pulverized silica or the like can also be used.

The molding resin mixture, in which the properties of the inorganic filler to be contained therein are defined as described above, is excellent in terms of fluidity and moldability. Therefore, the above-mentioned molding resin mixture can be easily introduced into a narrow space when performing the above-mentioned overall resin encapsulation, and can suppress pore generation. In addition, since the generation of pores can be suppressed in this manner, cracking in the chip due to the pressure to be applied when the molding resin mixture is filled in a narrow space can be prevented, thereby increasing the reliability of the semiconductor device to be manufactured. Can be improved. Moreover, it is possible to manufacture a semiconductor device with a minimum thickness. Since peeling of a resin layer does not generate | occur | produce, the long-term reliability of a semiconductor device improves.

In addition, since the above-mentioned molding resin mixture is excellent in fluidity, it is no longer necessary to increase the filling pressure of the resin mixture when encapsulating the semiconductor device. Thus, the semiconductor device will not be overlooked by the pressure used during resin filling.

In addition, in the embodiment of the present invention, the content of the carbon black to be mixed in the molding resin mixture is defined within the range of 0.5 to 1.5% by weight.

The range of content of carbon black was determined as follows. First, several types of molding resin mixtures were prepared by varying the content of carbon black. Next, the semiconductor device was manufactured by using each of these molding resin mixtures, and the light transmittance of the final semiconductor device was measured. In this case, the overall height of the semiconductor device was set to 0.450 mm and the wavelength of light was limited within the range of 1000 to 2000 nm.

As a result, it was found that the light transmittance of the encapsulated semiconductor device was 0.20% or less by using a molding resin containing 0.50% or more by weight of carbon black. In addition, as long as the light transmittance of the semiconductor device is limited to 0.20% or less, it has been confirmed that the occurrence of malfunction of the semiconductor chip can be substantially prevented. In addition, the capacity resistivity of the molding resin mixture can be maintained at 10 ⁸ Ω · cm or more at room temperature.

On the other hand, when the content of the carbon black exceeds 1.5% by weight, the capacity saving rate of the molding resin mixture is lowered, so that the semiconductor device to be manufactured will malfunction. Therefore, the upper limit of the carbon black content should be limited to 1.5% by weight.

The content of carbon black is limited within the range of 0.50 to 1.5% by weight, which is for preventing the occurrence of malfunction of the semiconductor chip and suppressing light transmittance even when the resin encapsulation is relatively thin.

Since the inorganic filler and the carbon black are included in the molding resin mixture in the above-described manner, the semiconductor device according to the embodiment of the present invention is excellent in reliability and at the same time, malfunctions due to light transmittance can be prevented.

That is, the molding resin layer of the semiconductor device according to the embodiment of the present invention is formed by curing of a molding resin mixture having an inorganic filler of 75-92% by weight and carbon black of 0.5-1.5% by weight. In particular, the 99% weight of the inorganic filler has a longest diameter of 35 μm or less, the average longest diameter of the inorganic filler is 15 μm or less, and the content of the fine filler having the longest diameter of 10 μm or less is determined by the total weight of the inorganic filler. It is limited within the range of 30-50% weight based on the basis.

The semiconductor device shown in FIG. 2 may be modified in various ways.

For example, as shown in FIG. 3, the adhesive layer 7 may be interposed between the substrate 1 and the semiconductor chip 4. The adhesive layer 7 sandwiched between the substrate 1 and the semiconductor chip 4 serves to reduce internal stress. Therefore, the provision of the adhesive layer is particularly effective when the size of the semiconductor device is relatively large, for example, 7 mm square or more, or when the size of the semiconductor chip 4 is relatively large, for example 6 mm square or more.

In addition, as shown in FIG. 4, the second semiconductor chip 4b may be stacked on the first semiconductor chip 4a. The second semiconductor chip 4b is connected to the substrate 1 via the through-conductive portion 9 formed to penetrate the first semiconductor chip 4a and the conductive connecting member 2.

The second semiconductor chip 4b may be connected to the substrate 1 via wiring as shown in FIG. 5. In the semiconductor device shown in FIG. 5, the second semiconductor chip 4b is disposed on the first semiconductor chip 4a through an adhesive layer 7b interposed therebetween, and the substrate 1 is formed by the second wiring 8b. Is connected to. This second wiring 8b may be formed of a gold wiring having a diameter of about 28 mu m.

6 is a cross-sectional view illustrating a semiconductor device in accordance with another embodiment of the present invention.

In the semiconductor device shown in FIG. 6, the semiconductor chip 4 is mounted on the substrate 1 via an adhesive layer 7. This semiconductor chip 4 is electrically connected to the terminal of the wiring circuit (not shown) of a board | substrate by using the gold wiring 8 whose diameter is 28 micrometers or less. With regard to the material of the substrate 1, the same materials described above can be used.

The molding resin layer 5 is disposed on the upper surface and side surfaces of the semiconductor chip 4 and on the upper surface of the substrate 1. This molding resin layer 5 can be formed by curing a molding resin mixture configured to satisfy the conditions described above with respect to the inorganic material and carbon black.

In the semiconductor device shown in FIG. 6, in order to minimize the overall thickness of the semiconductor device, a part thickness of the molding resin layer 5 facing the substrate 1 is limited to 0.2 mm or less. In this case, the part thickness of the molding resin layer 5 deposited on the semiconductor chip 4 is limited to 0.2 mm or less.

In the case of a conventional semiconductor device in which a semiconductor chip is connected with a substrate via wiring, the wiring may be deformed during the process of encapsulation due to the influence of the shearing force generated by the molding resin mixture. In this case, since the wirings can be connected to each other, an electrical malfunction of the semiconductor device can occur.

On the other hand, in the case of the semiconductor device shown in Fig. 6, the semiconductor device is encapsulated by using a molding resin mixture excellent in fluidity and molding, which allows the wiring to be deformed.

The semiconductor device shown in FIG. 6 may be configured as a two-ply stacked structure as shown in FIGS. 4 and 5. 7 and 8 illustrate this variant.

The semiconductor device shown in FIG. 7 is configured in the same manner as the semiconductor device shown in FIG. 4 except that the first semiconductor chip 4a is connected to the substrate 1 via the wiring 8a. The semiconductor device shown in FIG. 8 is configured in the same manner as the semiconductor device shown in FIG. 5 except that the first semiconductor chip 4a is connected to the substrate 1 via the wiring 8a. As shown in FIGS. 5 and 8, the second wiring 8b in which the second semiconductor chip 4b is connected to the substrate 1 is longer than the first wiring 8a. Since a molding resin mixture excellent in fluidity is used in the embodiment of the present invention, even this long wiring can be prevented from being deformed.

Incidentally, the third semiconductor chip may be laminated on the second semiconductor chip 4b to form a three-ply stacked structure.

The present invention can be variously modified within the spirit.

Additional advantages and modifications will readily occur to those skilled in the art. Accordingly, the invention in its broader sense is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

The present invention has the effect of improving the reliability of the semiconductor device.

Claims (20)

In a semiconductor device, Board; A first semiconductor chip mounted on the substrate at a thickness of 0.25 mm or less through a flip chip connection at a distance of 0.055 mm or less from the substrate; A conductive connection member for electrically connecting the first semiconductor chip to the substrate; And A molding resin layer disposed on the substrate to cover the first semiconductor chip and formed of a cured resin compound including 75-92 wt% of an inorganic filler and 0.5-1.5 wt% of carbon black; The thickness of the portion facing the substrate is 0.15 mm or less, and the 99% by weight of the inorganic filler has a longest diameter of 35 μm or less, an average longest diameter of 15 μm or less, and a content of the fine filler having a longest diameter of 10 μm or less. Limited to within the range of 30-50% by weight based on the total weight of the inorganic filler- A semiconductor device comprising a. The method of claim 1, wherein the substrate is formed between the substrate and the first semiconductor chip, formed of a cured resin compound containing 75-92% by weight of the inorganic filler and 0.5-1.5% by weight of carbon black, 99% by weight of The inorganic filler has a longest diameter of 35 μm or less, an average longest diameter of 15 μm or less, and a content of the fine filler having a longest diameter of 10 μm or less is limited within the range of 30 to 50 wt% based on the total weight of the inorganic filler. A semiconductor device further comprising a molding resin layer. The semiconductor device according to claim 1, further comprising an adhesive layer interposed between the substrate and the first semiconductor chip. The semiconductor device according to claim 1, wherein the thickness of said molding resin layer portion disposed on said first semiconductor chip does not exceed three times the distance between said substrate and said first semiconductor chip. The semiconductor device according to claim 1, wherein the conductive connecting member is formed of a material containing tin / silver solder. The semiconductor device according to claim 1, wherein the conductive connecting member is formed of a material containing gold. The semiconductor device according to claim 1, wherein the conductive connecting member is formed of a material containing tin / lead solder. The semiconductor device according to claim 1, wherein the conductive connecting member is formed of a material containing tin, tin / silver / copper solder, tin / zinc solder, tin / bismuth solder, or nickel. The semiconductor device of claim 1, further comprising a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the substrate and is covered together with the first semiconductor chip by the molding resin. A semiconductor device, characterized in that. The semiconductor device according to claim 9, wherein the second semiconductor chip is electrically connected to the substrate through bumps. The semiconductor device according to claim 9, wherein the second semiconductor chip is electrically connected to the substrate via a wire. The semiconductor device according to claim 11, wherein the wire is formed of a material containing gold. The semiconductor device according to claim 12, wherein the wire is 28 mu m in diameter. In a semiconductor device, Board; A first semiconductor chip mounted on the substrate; A first wire having a diameter of 28 μm or less and electrically connecting the first semiconductor chip to the substrate; And A molding resin layer disposed on the substrate to cover the first semiconductor chip and formed of a cured resin compound including 75-92 wt% of an inorganic filler and 0.5-1.5 wt% of carbon black; The thickness of the part facing the substrate is 0.2 mm or less, and the 99% by weight of the inorganic filler has a longest diameter of 35 m or less, an average longest diameter of 15 m or less, and a content of the fine filler having a longest diameter of 10 m or less. Limited to within the range of 30-50% by weight based on the total weight of the inorganic filler- A semiconductor device comprising a. The semiconductor device according to claim 14, further comprising an adhesive layer interposed between the substrate and the first semiconductor chip. The semiconductor device of claim 14, further comprising a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the substrate and is coated together with the first semiconductor chip by the molding resin. A semiconductor device, characterized in that. 17. The semiconductor device according to claim 16, wherein said second semiconductor chip is electrically connected to said substrate via bumps. The semiconductor device according to claim 16, wherein the second semiconductor chip is electrically connected to the substrate via a second wire. 19. The semiconductor device of claim 18, wherein the second wire is formed of a material containing gold. The semiconductor device according to claim 19, wherein the second wire has a diameter of 28 mu m.