CN101783331A - System-in-package structure and package method - Google Patents
System-in-package structure and package method Download PDFInfo
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- CN101783331A CN101783331A CN200910045978.9A CN200910045978A CN101783331A CN 101783331 A CN101783331 A CN 101783331A CN 200910045978 A CN200910045978 A CN 200910045978A CN 101783331 A CN101783331 A CN 101783331A
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- insulating medium
- medium layer
- package
- die pad
- inductor coil
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- Coils Or Transformers For Communication (AREA)
Abstract
The invention discloses a system-in-package structure and a package method. The system-in-package structure comprises a lead frame, wherein the lead frame comprises a tube core pad and leads positioned around the tube core pad; an inductor coil is formed in the tube core pad; and the tail end of the inductor coil is connected with one lead. The system-in-package structure also comprises an insulating medium layer formed on the tube core pad, a conductive plunger running through the insulating medium layer and communicated with the starting end of the inductor coil, a soldering-pan positioned on the insulating medium layer and connected with the conductive plunger, and a metal layer positioned on the insulating medium layer and connecting the soldering-pan with the leads. The system-in-package structure reduces the interference of electrical signals among the leads and improves a quality (Q) factor of an inductor.
Description
Technical field
The present invention relates to the semiconductor packages field, particularly a kind of system-in-package structure and method for packing.
Background technology
Along with portable electronic component becomes more and more littler, must dwindle the size of the semiconductor packages of electronic component.In order to achieve the above object, using system level encapsulation technology widely, its reason are because the system in package technology can increase the capacity of semiconductor packages.
(system in package SIP) not only can assemble a plurality of chips to system in package in a semiconductor package, various types of devices and circuit chip can also be stacked, and is built into more complicated, complete system.
The technology of the system in package that provided in 200710127363 the Chinese patent application is provided application number, as shown in Figure 1, packaging body 10 comprises the substrate 20 that has first surface 30 and second surface 40 respectively, and wherein substrate 20 can be lead frame (lead frame), printed circuit board (PCB) (PCB) or other package substrates of knowing.A plurality of solder ball 110 can be arranged at the first surface 30 of substrate 20, to couple other substrate (not shown).The second surface of substrate 20 has a winding zygonema bolt 130, and wherein closing line bolt 130 can adopt traditional line to engage or bump process, be formed in the substrate 20, and the closing line bolt can be gold, copper, aluminium or their alloy.Closing line bolt 130, was formed on the joint sheet of substrate 20 before substrate 20 at the applying chip.On the second surface 40 of substrate 20, form after the winding zygonema bolt 130,, fit in substrate 20 tops, to reduce package dimension the mode of first semiconductor chip 55 with upside-down mounting.First semiconductor chip 55 has the second surface of first surface and relative first surface, the first surface of first semiconductor chip 55 wherein, second surface 40 via a plurality of solder bump 60 applying substrates 20, solder bump 60 can be scolding tin, gold, copper, electric conducting material, or other electric conducting material is formed.In the gap of first semiconductor chip 55 and substrate 20, form after the packing material,, fit in the second surface of first semiconductor chip 55 cohesive material of second semiconductor chip 85 via for example epoxides.By traditional line joint technology, the closing line bolt 130 in closing line 90 electric property couplings, second semiconductor chip 85 and the substrate 20.Afterwards, encapsulated substance 100 encapsulates first semiconductor chip 55 and second semiconductor chip 85, closing line 90 and closing line bolt 130.
The superiority of said system level encapsulation technology comprises: how new function can be provided, and the kinds of processes compatibility is good, and flexibility and adaptability are strong, and cost is low, is easy to piecemeal test, and the construction cycle is short etc.Advantages such as system in package adopts over past ten years fast-developing face-down bonding technique, compares with the lead-in wire bonding, and face-down bonding technique has that the direct current pressure drop is low, interconnection density is high, stray inductance is little, thermal characteristics and electric property are good, but expense is higher.
Existing carrying out in the system in package process, when especially inductor being encapsulated, inductor is formed on the chip usually, can because with chip on semiconductor device coupling/crosstalk and cause quality (Q) factor of inductor to descend; In addition, the inductor electric field can impel electric current to flow in substrate or the dielectric layer around, further causes the loss of stored energy and the inductor Q factor to descend.
Summary of the invention
The problem that the present invention solves provides a kind of system-in-package structure and method for packing, prevents that the inductor Q factor from descending.
For addressing the above problem, a kind of system-in-package structure of the present invention comprises lead frame, and described lead frame comprises: die pad and be positioned at lead-in wire around the die pad, be formed with inductor coil in the described die pad, wherein the end of inductor coil is connected with lead-in wire; Described system-in-package structure also comprises: be formed at the insulating medium layer on the die pad, the conductive plunger that runs through insulating medium layer and the conducting of inductor top, be positioned at the pad that is connected with conductive plunger on the insulating medium layer, be positioned at the metal level that on the insulating medium layer pad is connected with lead-in wire.
Optionally, described inductor coil is a helical structure.Described inductor coil is square, hexagon, octagon or circle.
Optionally, the material of lead frame is a metal or alloy.
Optionally, described system-in-package structure further comprises: be positioned at the chip on the metal level.
Optionally, described system-in-package structure further comprises: be positioned at the chip on the die pad.
A kind of system-in-a-package method comprises: lead frame is provided, and described lead frame goes between around comprising die pad and being positioned at die pad; On die pad, form insulating medium layer; The etching die pad forms inductor coil to exposing insulating medium layer, and inductor coil is terminal directly to be connected with lead-in wire; Form the conductive plunger that runs through insulating medium layer in insulating medium layer, described conductive plunger is connected with the top of inductor coil; On insulating medium layer, form pad that is connected with conductive plunger and the metal level that pad is connected with lead-in wire.
Optionally, described inductor coil is a helical structure.Described inductor coil is square, hexagon, octagon or circle.
Optionally, the material of lead frame is a metal or alloy.
Optionally, the material of described insulating medium layer is metal oxide, alloyed oxide, silicon dioxide, phosphorous or fluorine silica or tetraethoxysilane.The thickness of described insulating medium layer is 0.5 micron～3 microns.
Optionally, described system-in-a-package method also comprises: adhere to chip on metal level.
Optionally, described system-in-a-package method also comprises: adhere to chip on die pad.
Compared with prior art, the present invention has the following advantages: directly die pad is carried out etching and forms inductor, and need be on chip in addition depositing metal layers reduced crosstalking of the signal of telecommunication between lead to form inductor.In addition, inductor is directly formed by die pad, avoided being formed on the substrate and dielectric layer on and situation that the electric current that causes flows in substrate or dielectric layer prevents the loss of stored energy, and then improves the inductor Q factor.
Further, what depositing metal layers will be thick on the material metal of die pad or the alloy ratio chip is many, and resistance is lower, has improved quality (Q) factor of inductor.
Description of drawings
Fig. 1 adopts existing technology to form the schematic diagram of system-in-package structure;
Fig. 2 is the flow chart that the present invention forms the embodiment of system in package;
Fig. 3 to Fig. 8 is the first embodiment schematic diagram that forms system in package with the inventive method;
Fig. 4 a is the upward view of Fig. 4;
Fig. 5 a is the upward view of Fig. 5;
Fig. 6 a is the upward view of Fig. 6;
Fig. 7 a is the upward view of Fig. 7;
Fig. 9 is the second embodiment schematic diagram with the system-in-package structure of the inventive method formation.
Embodiment
A kind of system-in-package structure, comprise lead frame, described lead frame comprises: die pad and be positioned at lead-in wire around the die pad, described die pad is an inductor coil, wherein first electrode end that is positioned at inductor coil is connected with lead-in wire, second electrode is positioned at inductor coil top, be formed with insulating medium layer on the die pad, conductive plunger runs through the insulating medium layer and second electrode conduction, be positioned at the pad that is connected with conductive plunger on the insulating medium layer, be positioned at the metal wire that on the insulating medium layer pad is connected with lead-in wire.
The idiographic flow that forms the said system class encapsulation structure as shown in Figure 2, execution in step S1 provides lead frame, described lead frame comprises die pad and is positioned at lead-in wire around the die pad; Execution in step S2 forms insulating medium layer on die pad; Execution in step S3, the etching die pad forms inductor coil to exposing insulating medium layer, and inductor coil is terminal directly to be connected with lead-in wire; Execution in step S4 forms the conductive plunger that runs through insulating medium layer in insulating medium layer, described conductive plunger is connected with the top of inductor coil; Execution in step S5 forms pad that is connected with conductive plunger and the metal level that pad is connected with lead-in wire on insulating medium layer.
The present invention directly carries out etching to die pad and forms inductor, and need be on chip in addition depositing metal layers reduced crosstalking of the signal of telecommunication between lead to form inductor.In addition, inductor is directly formed by die pad, avoided being formed on the substrate and dielectric layer on and situation that the electric current that causes flows in substrate or dielectric layer prevents the loss of stored energy, and then improves the inductor Q factor.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 3 to Fig. 6 is the first embodiment schematic diagram that forms system in package with the inventive method.As shown in Figure 3, provide a lead frame 200, described lead frame 200 comprises die pad 202 and is positioned at the lead-in wire 201 of die pad 202 peripheries that lead-in wire 201 stretches out with comb shape and separates with die pad 202; Wherein, the material of lead frame 200 can be metal or alloy etc.; On the first surface of die pad 202, form insulating medium layer 210, the method of described formation insulating medium layer 210 can be a chemical vapour deposition technique, its thickness is 0.5 micron～3 microns, and the material of insulating medium layer 210 is metal oxide, alloyed oxide, silicon dioxide, phosphorous or fluorine silica or tetraethoxysilane.
Shown in Fig. 4 and Fig. 4 a, on the second surface of die pad 202, form first photoresist layer 212 with spin-coating method, through exposure imaging technology, on first photoresist layer 212, define inductor patterns; Then, be mask with first photoresist layer 212, to exposing insulating medium layer 210, form inductor coil 202a along inductor patterns etching die pad 202.
Shown in Fig. 5 and Fig. 5 a, remove first photoresist layer 212 with ashing method, and then remove the first residual photoresist layer 212 with the wet etching method, expose inductor coil 202a.Wherein the end of inductor coil 202a is the first electrode 203a, directly is connected with one of them lead-in wire 201 by connecting line 201a, and the top of coil central authorities is the second electrode 203b of inductor coil.On insulating medium layer 210, form second photoresist layer (not shown) with spin-coating method, adopt photoetching technique that via hole image is transferred on second photoresist layer; And then the employing developing process, on second photoresist layer, define via hole image.With second photoresist layer is mask, to the second electrode 203b that exposes inductor coil 202a, forms through hole 214 along via hole image etching insulating medium layer 210.
With reference to figure 6 and Fig. 6 a, on insulating medium layer 210, reach through hole 214 inwalls with chemical vapour deposition technique and form diffusion impervious layer (not shown), the material of described diffusion impervious layer is titanium nitride or tantalum nitride.On diffusion impervious layer, form conductive layer with galvanoplastic or sputtering method, and conductive layer is filled full through hole; Grind conductive layer to exposing diffusion impervious layer with chemical mechanical polishing method, form first conductive plunger 215 and the second conductive plunger 215b.
Continuation is with reference to figure 6 and Fig. 6 a, on first conductive plunger 215, form first pad 216, on the second conductive plunger 215b, form second pad, the technology of described formation first pad 216 and second pad is those skilled in the art's known technology, and concrete technology is as follows: form pad layer on diffusion impervious layer; On pad layer, apply photoresist layer (not shown); With photoetching technique and developing process, on photoresist layer, define land pattern; With the photoresist layer is mask, along land pattern etching pad layer, forms first pad 216 and second pad; Remove photoresist layer.
Continuation forms metal level 217 with reference to figure 7 and Fig. 7 a with galvanoplastic or sputtering method on diffusion impervious layer, the material of described metal level 217 is a copper, and first pad 216, second pad are connected with lead-in wire 201.
As shown in Figure 8, adhere to chip 204 on metal level 217, the basal surface of its chips is sticking mutually with metal level 217; Then, the pad on the chip 204 206 is connected with lead-in wire 201 by metal wire 208.
Another embodiment as shown in Figure 9, adheres to chip 204 on inductor coil 202a, the basal surface of its chips is sticking mutually with inductor coil 202a surface; Then, the pad on the chip 204 206 is connected with lead-in wire 201 by metal wire 208.
System-in-package structure based on above-mentioned first embodiment forms comprises: lead frame 200, described lead frame 200 comprise die pad and are positioned at lead-in wire 201 around the die pad, wherein go between 201 to stretch out and separate with die pad 202 with comb shape; Inductor coil 202a is formed in the die pad; The first electrode 203a is positioned at the end of inductor coil 202a; The second electrode 202b is positioned at inductor coil 202a top; Insulating medium layer 210 is positioned on the inductor coil 202a; First conductive plunger 215 runs through insulating medium layer 210 and is electrically connected with the first electrode 203a; The second conductive plunger 215b is positioned at the inductance coil 202a outside and runs through insulating medium layer 210; First pad 216 is positioned on the insulating medium layer 210, is communicated with first conductive plunger 215; Second pad is positioned on the insulating medium layer 210, is communicated with the second conductive plunger 215b; Metal wire 208 is positioned on the insulating medium layer 210, and with first pad 216 and second pad and go between and 201 be connected; Chip 204 adheres on the metal material line 208, is connected with lead-in wire 201 by line 208.
Wherein in a second embodiment, chip 204 adheres on the inductor coil 202a, is positioned at the apparent surface of inductor coil 202a with insulating medium layer 210.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (14)
1. a system-in-package structure comprises lead frame, and described lead frame comprises: die pad and be positioned at lead-in wire around the die pad is characterized in that be formed with inductor coil in the described die pad, wherein the end of inductor coil is connected with going between; Described system-in-package structure also comprises: be formed at the insulating medium layer on the die pad, the conductive plunger that runs through insulating medium layer and the conducting of inductor top, be positioned at the pad that is connected with conductive plunger on the insulating medium layer, be positioned at the metal level that on the insulating medium layer pad is connected with lead-in wire.
2. system-in-package structure according to claim 1 is characterized in that described inductor coil is a helical structure.
3. as system-in-package structure as described in the claim 2, it is characterized in that described inductor coil is square, hexagon, octagon or circle.
4. system-in-package structure according to claim 1 is characterized in that the material of lead frame is a metal or alloy.
5. system-in-package structure according to claim 1 is characterized in that described system-in-package structure further comprises: be positioned at the chip on the metal level.
6. system-in-package structure according to claim 1 is characterized in that described system-in-package structure further comprises: be positioned at the chip on the die pad.
7. a system-in-a-package method is characterized in that, comprising:
Lead frame is provided, and described lead frame goes between around comprising die pad and being positioned at die pad;
On die pad, form insulating medium layer;
The etching die pad forms inductor coil to exposing insulating medium layer, and inductor coil is terminal directly to be connected with lead-in wire;
Form the conductive plunger that runs through insulating medium layer in insulating medium layer, described conductive plunger is connected with the top of inductor coil;
On insulating medium layer, form pad that is connected with conductive plunger and the metal level that pad is connected with lead-in wire.
8. as system-in-a-package method as described in the claim 7, it is characterized in that described inductor coil is a helical structure.
9. as system-in-a-package method as described in the claim 8, it is characterized in that described inductor coil is square, hexagon, octagon or circle.
10. as system-in-a-package method as described in the claim 7, it is characterized in that the material of lead frame is a metal or alloy.
11., it is characterized in that the material of described insulating medium layer is metal oxide, alloyed oxide, silicon dioxide, phosphorous or fluorine silica or tetraethoxysilane as system-in-a-package method as described in the claim 7.
12., it is characterized in that the thickness of described insulating medium layer is 0.5 micron～3 microns as system-in-a-package method as described in the claim 11.
13., it is characterized in that described system-in-a-package method also comprises: on metal level, adhere to chip as system-in-a-package method as described in the claim 7.
14., it is characterized in that described system-in-a-package method also comprises: on die pad, adhere to chip as system-in-a-package method as described in the claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910045978.9A CN101783331A (en) | 2009-01-19 | 2009-01-19 | System-in-package structure and package method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910045978.9A CN101783331A (en) | 2009-01-19 | 2009-01-19 | System-in-package structure and package method |
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| CN101783331A true CN101783331A (en) | 2010-07-21 |
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| CN200910045978.9A Pending CN101783331A (en) | 2009-01-19 | 2009-01-19 | System-in-package structure and package method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022000A (en) * | 2011-09-27 | 2013-04-03 | 中芯国际集成电路制造(上海)有限公司 | Planar inductor and manufacturing method thereof, and semiconductor device and manufacturing method thereof |
| WO2019007322A1 (en) * | 2017-07-03 | 2019-01-10 | 无锡华润上华科技有限公司 | Stacked spiral inductor |
| CN109891592A (en) * | 2016-12-30 | 2019-06-14 | 德州仪器公司 | Lead frame inductor |
| CN111106525A (en) * | 2019-12-25 | 2020-05-05 | 浙江工业大学 | VECSEL laser chip packaging structure and method capable of avoiding magnetic field interference |
-
2009
- 2009-01-19 CN CN200910045978.9A patent/CN101783331A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022000A (en) * | 2011-09-27 | 2013-04-03 | 中芯国际集成电路制造(上海)有限公司 | Planar inductor and manufacturing method thereof, and semiconductor device and manufacturing method thereof |
| CN103022000B (en) * | 2011-09-27 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Planar inductor and manufacturing method thereof, and semiconductor device and manufacturing method thereof |
| CN109891592A (en) * | 2016-12-30 | 2019-06-14 | 德州仪器公司 | Lead frame inductor |
| CN109891592B (en) * | 2016-12-30 | 2024-03-15 | 德州仪器公司 | Lead frame inductor |
| WO2019007322A1 (en) * | 2017-07-03 | 2019-01-10 | 无锡华润上华科技有限公司 | Stacked spiral inductor |
| US12009129B2 (en) | 2017-07-03 | 2024-06-11 | Csmc Technologies Fab2 Co., Ltd. | Stacked spiral inductor |
| CN111106525A (en) * | 2019-12-25 | 2020-05-05 | 浙江工业大学 | VECSEL laser chip packaging structure and method capable of avoiding magnetic field interference |
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Effective date of registration: 20121109 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |