CN101656219B - System-in-package method - Google Patents
System-in-package method Download PDFInfo
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- CN101656219B CN101656219B CN2008100418303A CN200810041830A CN101656219B CN 101656219 B CN101656219 B CN 101656219B CN 2008100418303 A CN2008100418303 A CN 2008100418303A CN 200810041830 A CN200810041830 A CN 200810041830A CN 101656219 B CN101656219 B CN 101656219B
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Abstract
The invention relates to a system-in-package method, which comprises the following steps: providing a wafer, wherein interlayer dielectric layers and bonding pans are formed on the wafer in turn, and through holes are formed in the interlayer dielectric layers and the wafer; forming insulating dielectric layers in the interlayer dielectric layers and the through holes, and exposing the bonding pans; forming metal layers on the insulating dielectric layers and the bonding pans; forming organic layers on the metal layers which are filled in through holes; forming salient points connected with the metal layers in the organic layers; and etching the metal layers and the organic layers until the insulating dielectric layers are exposed, and forming a metal connection point matrix. The system-in-package method improves the reliability of a semiconductor device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to the method for system in package.
Background technology
Along with portable electronic component becomes more and more littler, must dwindle the size of the semiconductor packages of electronic component.In order to achieve the above object, using system level encapsulation technology widely, its reason are because the system in package technology can increase the capacity of semiconductor packages.
System in package (system in package, SIP) in a semiconductor package, not only can assemble a plurality of chips, various types of devices and circuit chip can also be stacked, be built into more complicated, complete system, as the technical scheme of application number for being provided in 200710127363 the Chinese patent application.
The superiority of system in package technology comprises: how new function can be provided, and the kinds of processes compatibility is good, and flexibility and adaptability are strong, and cost is low, is easy to piecemeal test, and the construction cycle is short etc.Advantages such as system in package adopts over past ten years fast-developing face-down bonding technique, compares with the lead-in wire bonding, and face-down bonding technique has that the direct current pressure drop is low, interconnection density is high, stray inductance is little, thermal characteristics and electric property are good, but expense is higher.
The technology of existing formation system in package as shown in Figure 1 to Figure 3.With reference to figure 1, a wafer 10 is provided, include semiconductor device (not shown) and interlayer dielectric layer 12 on the described wafer 10, wherein, comprise metal level in the interlayer dielectric layer 12, conduct electricity connection by metal level between semiconductor device; Be formed with the pad 17 that is connected with metal level by conductive plunger on the interlayer dielectric layer 12.Form through hole 16 in interlayer dielectric layer 12 and wafer 10, the method that forms through hole 16 is dry etching or wet etching method.Then, reach the through hole 16 inboard insulating medium layers 14 that form with chemical vapour deposition technique on wafer 10, the material of described insulating medium layer 14 is a silica.Then, on insulating medium layer 14, apply first photoresist layer (not shown), through exposure imaging technology, definition and pad corresponding opening pattern; With first photoresist layer is mask, along patterns of openings etching insulating medium layer 14 to exposed pad 17.Form Seed Layer 18 on insulating medium layer 14 and pad 17, the material of described Seed Layer 18 is tantalum, titanium, nickel or copper etc., and it act as the adhesive capacity of strengthening between the rete.
As shown in Figure 2, form metal level 19 with galvanoplastic on Seed Layer 18, and metal level 19 is filled in the full through hole 16, described metal level 19 is copper or gold.On metal level 19, form second photoresist layer (not shown), through exposure imaging technology, definition array of packages pattern; With second photoresist layer is mask, and etching sheet metal 19 and Seed Layer 18 form the metal connection point array to exposing insulating medium layer 14.
As shown in Figure 3, on metal level 19 and insulating medium layer 14, form the 3rd photoresist layer (not shown),, on the 3rd photoresist layer, form opening through exposure imaging technology; Electroplate the eutectic metal in opening, form salient point 20 through refluxing, the material of described eutectic metal is specially signal bronze, silver-colored ashbury metal, tin platinum alloy, bazar metal or nickeltin etc.
Then, wafer 10 and other wafer are welded, form system in package by salient point 20.
When existing technology forms system in package, in through hole, filling in the process of full metal level,, therefore can produce internal stress, and then cause the generation of microcrack, influencing the performance of semiconductor device owing to thermal coefficient of expansion between different film materials in the through hole is variant.
Summary of the invention
The problem that the present invention solves provides a kind of system-in-a-package method, produces internal stress when preventing to fill metal level in through hole.
For addressing the above problem, the invention provides a kind of system-in-a-package method, comprising: a wafer is provided, is formed with interlayer dielectric layer and pad on the wafer successively, in interlayer dielectric layer and the wafer through hole is arranged; In interlayer dielectric layer and through hole, form insulating medium layer, and expose pad; On insulating medium layer and pad, form metal level; Form organic layer on metal level, described organic layer is filled full through hole; In organic layer, form the salient point that is connected with metal level; Etching sheet metal and organic layer form the metal connection point array to exposing insulating medium layer.
Optionally, the material of described metal level is titanium/titanium nitride/copper, titanium/titanium nitride/tungsten or titanium/titanium nitride/aluminium.
Optionally, the method for formation metal level is a physical vaporous deposition.Described metal layer thickness is 1000 dusts～10000 dusts.
Optionally, the material of described organic layer is polyimides, epoxy resin, polymer or silicate glass.The method of described formation organic layer is a spin-coating method.The thickness of described organic layer on metal level is 0.5 μ m～10 μ m.
Optionally, the material of described salient point is the eutectic metal.Described eutectic metal is signal bronze, silver-colored ashbury metal, tin platinum alloy, bazar metal or nickeltin.
Optionally, form the salient point that is connected with metal level in organic layer, also comprise step: the etching organic layer forms the contact hole opening to exposing metal level; The etching organic layer forms the contact hole opening to exposing metal level; After forming photoresist layer on metal level and the organic layer, in photoresist, form groove opening with the contact hole open communication; In contact hole opening and groove opening, fill the eutectic metal; Backflow eutectic metal.
Optionally, form the salient point that is connected with metal level in organic layer, also comprise step: the etching organic layer forms the contact hole opening to exposing metal level; The etching organic layer forms contact hole opening and metal dots and connects array to exposing metal level; After forming photoresist layer on metal level and the organic layer, in photoresist, form groove opening with the contact hole open communication; In contact hole opening and groove opening, fill the eutectic metal; Backflow eutectic metal.
Compared with prior art, the present invention has the following advantages: at the inboard metal level that forms of through hole, and not with the full through hole of metal level complete filling, and in through hole, fill full organic layer, because organic layer has the characteristic of buffering stress, therefore, make through hole internal cause deposition different materials thermal expansion coefficient difference and the internal stress that produces reduces, and then improved the reliability of semiconductor device.
In addition, the material of described organic layer is polyimides, epoxy resin, polymer or silicate glass, has improved luminous sensitivity, has improved the efficient of technology.
Description of drawings
Fig. 1 to Fig. 3 is the schematic diagram that existing technology forms system in package;
Fig. 4 is the embodiment flow chart that the present invention forms system in package;
Fig. 5 to Fig. 8 is the first embodiment schematic diagram that the present invention forms system in package;
Fig. 9 to Figure 12 is the second embodiment schematic diagram that the present invention forms system in package.
Embodiment
The present invention is at the inboard metal level that forms of through hole, and not with the full through hole of metal level complete filling, and in through hole, fill full organic layer, because organic layer has the characteristic of buffering stress, therefore, the internal stress that makes through hole internal cause deposition different materials thermal expansion coefficient difference and produce reduces, and then has improved the reliability of semiconductor device.In addition, the material of described organic layer is polyimides, epoxy resin, polymer or silicate glass, and the luminous sensitivity that has improved has improved the efficient of technology.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 4 is the embodiment flow chart that the present invention forms system in package.Execution in step S101 provides a wafer, is formed with interlayer dielectric layer and pad on the wafer successively, in interlayer dielectric layer and the wafer through hole is arranged; Execution in step S102 forms insulating medium layer in interlayer dielectric layer and through hole, and exposes pad; Execution in step S103 forms metal level on insulating medium layer and pad; Execution in step S104 forms organic layer on metal level, described organic layer is filled full through hole; Execution in step S105 forms the salient point that is connected with metal level in organic layer; Execution in step S106, etching sheet metal and organic layer form the metal connection point array to exposing insulating medium layer.
Fig. 5 to Fig. 8 is the first embodiment schematic diagram that the present invention forms system in package.As shown in Figure 5, provide a wafer 100, include semiconductor device (not shown) and interlayer dielectric layer 102 on the described wafer 100, the material of described interlayer dielectric layer 102 can be the material that silica or silicon oxynitride etc. have the effect of insulation; Comprise metal level 109 in the interlayer dielectric layer 102, conduct electricity connection by metal level 109 between semiconductor device; Also be formed with conductive plunger 110 in the interlayer dielectric layer 102, be connected with metal level 109.
On interlayer dielectric layer 102, form pad 108, be electrically connected with metal level 109 by conductive plunger 110; Then, on interlayer dielectric layer 102 and pad 108, form first photoresist layer (not shown), through exposure imaging technology, the definition via hole image; With first photoresist layer is mask, along via hole image etching interlayer dielectric layer 102 and wafer 100, forms through hole 106, and the lithographic method that formation through hole 106 is adopted is the dry etching method; After ashing method is removed first photoresist layer, at interlayer dielectric layer 102, pad 108 and through hole 106 inboard formation thickness is the insulating medium layer 104 of 500 dusts～10000 dusts, the material of described insulating medium layer 104 is a silica etc., and the formation method can be chemical vapour deposition technique or physical vaporous deposition etc.
As shown in Figure 6, on insulating medium layer 104, apply second photoresist layer (not shown), through exposure imaging technology, definition and pad corresponding opening pattern; With second photoresist layer is mask, along patterns of openings etching insulating medium layer 104 to exposed pad 108.Ashing method is removed second photoresist layer, and then removes the second residual photoresist layer with the wet etching method; Forming thickness on insulating medium layer 104 and pad 108 is the metal level 112 of 1000 dusts～10000 dusts, the material of described metal level 112 is titanium/titanium nitride/copper, titanium/titanium nitride/tungsten or titanium/titanium nitride/aluminium etc., and the method that forms metal level 112 is a physical vaporous deposition etc.On metal level 112, form organic layer 114 with spin-coating method, make organic layer 114 fill full through hole 106 through refluxing, the thickness of described organic layer 114 on metal level 112 is 0.5 μ m～10 μ m, and the material of organic layer 114 is organic materials such as polyimides, epoxy resin, polymer or silicate glass.
In the present embodiment, the thickness of described metal level 112 is specially 1000 dusts, 2000 dusts, 3000 dusts, 4000 dusts, 5000 dusts, 6000 dusts, 7000 dusts, 8000 dusts, 9000 dusts or 10000 dusts etc.
In the present embodiment, the thickness of described organic layer 114 on metal level 112 is specially 0.5 μ m, 1 μ m, 2 μ m, 3 μ m, 4 μ m, 5 μ m, 6 μ m, 7 μ m, 8 μ m, 9 μ m or 10 μ m etc.
Except that present embodiment, can also be formed with Seed Layer between insulating medium layer 104 and the metal level 112, the material of described Seed Layer can be tantalum, titanium, nickel or copper etc., it act as the adhesive capacity of strengthening between the rete.
As shown in Figure 7, on organic layer 114, form the 3rd photoresist layer (not shown),, define contact hole graph through exposure imaging technology with spin-coating method; With the 3rd photoresist layer is mask, to exposing metal level 112, forms contact hole opening 117 with dry etching method etching organic layer 114; Ashing method is removed the 3rd photoresist layer, and then removes the 3rd residual photoresist layer with the wet etching method; On metal level 112 and organic layer 114, apply the 4th photoresist layer 116,, form the groove opening 115 that is communicated with contact hole opening 117 through exposure imaging technology.
As shown in Figure 8, fill eutectic metal 118 with galvanoplastic in groove opening and contact hole opening, described eutectic metal 118 can be alloy materials such as signal bronze, silver-colored ashbury metal, tin platinum alloy, bazar metal or nickeltin; Ashing method is removed the 4th photoresist layer 116, and then removes the 4th residual photoresist layer 116 with the wet etching method; Spin coating the 5th photoresist layer (not shown) on organic layer 114 through exposure imaging technology, defines metal dots and connects array pattern; With the 5th photoresist layer is mask, and etching organic layer 114 and metal level 112 form metal dots and connect array to exposing insulating medium layer 104.
Then, eutectic metal 118 is carried out reflux technique, form salient point, wafer 100 and other wafer are welded, form system in package by salient point.
Fig. 9 to Figure 12 is the second embodiment schematic diagram that the present invention forms system in package.As shown in Figure 9, provide a wafer 200, include semiconductor device (not shown) and interlayer dielectric layer 202 on the described wafer 200; Comprise metal level 209 in the interlayer dielectric layer 202, conduct electricity connection by metal level 209 between semiconductor device; Also be formed with conductive plunger 210 in the interlayer dielectric layer 202, be connected with metal level 209.
On interlayer dielectric layer 202, form pad 208, be electrically connected with metal level 209 by conductive plunger 210; Then, on interlayer dielectric layer 202 and pad 208, form first photoresist layer (not shown), through exposure imaging technology, the definition via hole image; With first photoresist layer is mask, along via hole image etching interlayer dielectric layer 202 and wafer 200, forms through hole 206; After removing first photoresist layer, be the insulating medium layer 204 of 500 dusts～10000 dusts at interlayer dielectric layer 202, pad 208 and through hole 206 inboard formation thickness.
As shown in figure 10, on insulating medium layer 204, apply second photoresist layer (not shown), through exposure imaging technology, definition and pad corresponding opening pattern; With second photoresist layer is mask, along patterns of openings etching insulating medium layer 204 to exposed pad 208.Remove second photoresist layer; Then, forming thickness on insulating medium layer 204 and pad 208 is the metal level 212 of 1000 dusts～10000 dusts, the material of described metal level 212 is titanium/titanium nitride/copper, titanium/titanium nitride/tungsten or titanium/titanium nitride/aluminium etc., and the method that forms metal level 212 is a physical vaporous deposition etc.On metal level 212, form organic layer 214 with spin-coating method, make organic layer 214 fill full through hole 206 through refluxing, the thickness of described organic layer 214 on metal level 212 is 0.5 μ m～10 μ m, and the material of organic layer 214 is organic materials such as polyimides, epoxy resin, polymer or silicate glass.
In the present embodiment, the thickness of described metal level 212 is specially 1000 dusts, 2000 dusts, 3000 dusts, 4000 dusts, 5000 dusts, 6000 dusts, 7000 dusts, 8000 dusts, 9000 dusts or 10000 dusts etc.
In the present embodiment, the thickness of described organic layer 214 on metal level 212 is specially 0.5 μ m, 1 μ m, 2 μ m, 3 μ m, 4 μ m, 5 μ m, 6 μ m, 7 μ m, 8 μ m, 9 μ m or 10 μ m etc.
Except that present embodiment, can also be formed with Seed Layer between insulating medium layer 204 and the metal level 212, the material of described Seed Layer can be tantalum, titanium, nickel or copper etc., it act as the adhesive capacity of strengthening between the rete.
As shown in figure 11, on organic layer 214, form the 3rd photoresist layer (not shown),, define contact hole graph and be connected array pattern with metal dots through exposure imaging technology with spin-coating method; With the 3rd photoresist layer is mask,, forms contact hole opening 217 and metal dots and connects array to exposing metal level 212 with dry etching method etching organic layer 214; After ashing method is removed the 3rd photoresist layer, on metal level 212 and organic layer 214, apply the 4th photoresist layer 216,, form the groove opening 215 that is communicated with contact hole opening 217 through exposure imaging technology.
As shown in figure 12, fill eutectic metal 218 with galvanoplastic in groove opening and contact hole opening, described eutectic metal 218 can be alloy materials such as signal bronze, silver-colored ashbury metal, tin platinum alloy, bazar metal or nickeltin; Remove the 4th photoresist layer 216; Spin coating the 5th photoresist layer (not shown) on organic layer 214 through exposure imaging technology, defines metal dots and connects array pattern; With the 5th photoresist layer is mask, and etching organic layer 214 and metal level 212 form metal dots and connect array to exposing insulating medium layer 204.
Then, eutectic metal 218 is carried out reflux technique, form salient point, wafer 200 and other wafer are welded, form system in package by salient point.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (11)
1. a system-in-a-package method is characterized in that, comprising:
One wafer is provided, is formed with interlayer dielectric layer and pad on the wafer successively, in interlayer dielectric layer and the wafer through hole is arranged;
In interlayer dielectric layer and through hole, form insulating medium layer, and expose pad;
On insulating medium layer and pad, form metal level;
Form organic layer on metal level, described organic layer is filled full through hole;
In organic layer, form the salient point that is connected with metal level;
Etching sheet metal and organic layer form the metal connection point array to exposing insulating medium layer.
2. according to the described system-in-a-package method of claim 1, it is characterized in that, comprising: the material of described metal level is titanium/titanium nitride/copper, titanium/titanium nitride/tungsten or titanium/titanium nitride/aluminium.
3. according to the described system-in-a-package method of claim 2, it is characterized in that, comprising: the method that forms metal level is a physical vaporous deposition.
4. according to the described system-in-a-package method of claim 3, it is characterized in that, comprising: described metal layer thickness is 1000 dusts～10000 dusts.
5. according to the described system-in-a-package method of claim 1, it is characterized in that, comprising: the material of described organic layer is polyimides, epoxy resin or silicate glass.
6. according to the described system-in-a-package method of claim 5, it is characterized in that, comprising: the method for described formation organic layer is a spin-coating method.
7. according to the described system-in-a-package method of claim 6, it is characterized in that, comprising: the thickness of described organic layer on metal level is 0.5 μ m～10 μ m.
8. according to the described system-in-a-package method of claim 1, it is characterized in that, comprising: the material of described salient point is the eutectic metal.
9. described according to Claim 8 system-in-a-package method is characterized in that, comprising: described eutectic metal is signal bronze, silver-colored ashbury metal, tin platinum alloy, bazar metal or nickeltin.
10. according to the described system-in-a-package method of claim 1, it is characterized in that, in organic layer, form the salient point that is connected with metal level, also comprise step:
The etching organic layer forms the contact hole opening to exposing metal level;
After forming photoresist layer on metal level and the organic layer, in photoresist, form groove opening with the contact hole open communication;
In contact hole opening and groove opening, fill the eutectic metal;
Backflow eutectic metal.
11., it is characterized in that according to the described system-in-a-package method of claim 1, in organic layer, form the salient point that is connected with metal level, also comprise step:
The etching organic layer forms contact hole opening and metal dots and connects array to exposing metal level;
After forming photoresist layer on metal level and the organic layer, in photoresist, form groove opening with the contact hole open communication;
In contact hole opening and groove opening, fill the eutectic metal;
Backflow eutectic metal.
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| CN2008100418303A CN101656219B (en) | 2008-08-18 | 2008-08-18 | System-in-package method |
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| CN2008100418303A CN101656219B (en) | 2008-08-18 | 2008-08-18 | System-in-package method |
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| CN101656219B true CN101656219B (en) | 2011-03-23 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106128998A (en) * | 2016-07-21 | 2016-11-16 | 上海交通大学 | Semiconductor vertical copper-connection is filled the preparation method of the TSV structure of organic polymer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206542A (en) * | 2016-07-21 | 2016-12-07 | 上海交通大学 | Semiconductor vertical copper-connection is filled TSV structure and the forming method of organic polymer |
| CN106229268B (en) * | 2016-07-21 | 2020-07-14 | 上海交通大学 | Method for filling organic polymer in conductor or semiconductor micropore |
| CN111146147B (en) * | 2019-12-30 | 2023-04-28 | 中芯集成电路（宁波）有限公司 | Semiconductor device integrated structure and method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106128998A (en) * | 2016-07-21 | 2016-11-16 | 上海交通大学 | Semiconductor vertical copper-connection is filled the preparation method of the TSV structure of organic polymer |
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Effective date of registration: 20180531 Address after: No. 18 Zhangjiang Road, Pudong New Area, Shanghai Co-patentee after: Core integrated circuit (Ningbo) Co., Ltd. Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: No. 18 Zhangjiang Road, Pudong New Area, Shanghai Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |