CN111146147B - Semiconductor device integrated structure and method - Google Patents

Abstract

The invention discloses a semiconductor device integrated structure and a method, wherein the integrated method comprises the following steps: providing a first structure, wherein the first structure comprises from top to bottom: the device comprises a first dielectric layer, a first organic film layer and a substrate, wherein a plurality of second electronic devices are embedded in the substrate, a through hole and a region of a set range of the periphery of the through hole are defined as a first region, and the first dielectric layer of the first region is removed; forming a second organic film layer in the first region, wherein the absolute value of the difference between the thermal expansion coefficients of the second organic film layer and the first organic film layer is smaller than that of the first dielectric layer, and the flexibility of the second organic film layer is larger than that of the first dielectric layer; forming a through hole penetrating the second organic film layer and the first organic film layer, wherein the bottom of the through hole exposes the second electronic device; a conductive plug is formed in the via, the conductive plug connecting the second electronic device.

Description

A semiconductor device integration structure and method

technical field

The invention relates to the field of semiconductor device manufacturing, in particular to an integrated structure and method of a semiconductor device.

Background technique

With the development of market demand for semiconductor power devices, ultra-small and ultra-thin chips, 3D stacked small-profile and high-integration packages are the development trend.

Among them, 3D packaging refers to a packaging technology in which two or more chips are stacked vertically in the same package without changing the size of the package. In terms of size and weight, 3D design instead of single-chip packaging reduces device size and weight. Compared with traditional packaging, the use of 3D technology can reduce the size and weight by 40-50 times; in terms of speed, the power saved by 3D technology can make 3D components operate at a faster switching speed per second without increasing energy consumption, parasitic Capacitance and inductance can be reduced; 3D packaging more effectively utilizes the effective area of the silicon chip.

One of the design difficulties of packaging is to realize the stacking of chips. DAF (Die Attach Film) is an ultra-thin film adhesive used to connect semiconductor chips and packaging substrates, chips and chips in the semiconductor packaging process. With its excellent reliability and convenient process, it can realize semiconductor packaging. Lamination and thinning.

Stress can be induced between thin films of integrated circuit devices during package fabrication and in the application environment. For example, stress may occur due to different material properties between different layers in an integrated circuit device. At this point, cracks may start to propagate within the integrated circuit device to relieve the stress. This fracture can lead to electrical failure or functional failure, which can affect manufacturing yield and reliability. In order to increase yield, it is necessary to prevent the occurrence and propagation of cracks due to stress.

In the packaging process, the via hole is a common structure in semiconductor devices. The via hole is opened in the dielectric layer and penetrates the DAF film layer. It is generally used to realize the conductive connection between multiple devices after RDL rewiring, so that multiple devices become one Functional whole.

However, when there is an organic film such as DAF in the lower layer of the dielectric layer, when the subsequent processing wafer is heated, due to the difference in thermal expansion coefficient, the organic film layer has a larger thermal expansion coefficient, resulting in a greater volume change, which will generate a force on the upper dielectric film layer. role. In order to relieve the stress, the upper dielectric film layer is prone to fracture. Especially when the positions of the two through holes are relatively close, the upper dielectric film is more likely to break.

Therefore, how to solve the problem of film layer breakage caused by through holes in the dielectric layer above the organic film layer is a subject of current research.

Contents of the invention

The object of the present invention is to provide a semiconductor device integration structure and method, which can solve the problem of film layer breakage caused by the through hole of the dielectric layer above the organic film layer.

In order to achieve the above object, the present invention provides a semiconductor device integration method, comprising:

A first structure is provided, and the first structure includes from top to bottom: a first dielectric layer, a first organic film layer, and a substrate, and a plurality of second electronic devices are embedded in the substrate;

Defining the through hole and the area of the set range around the through hole as the first area, removing the first dielectric layer in the first area;

A second organic film layer is formed in the first region, the thermal expansion coefficient of the second organic film layer is between the first dielectric layer and the first organic film layer, and the second organic film layer has a thermal expansion coefficient between the first dielectric layer and the first organic film layer. the flexibility is greater than the flexibility of the first dielectric layer;

forming a through hole through the second organic film layer and the first organic film layer, and the bottom of the through hole exposes the second electronic device;

Conductive plugs are formed in the through holes, the conductive plugs are connected to the second electronic device.

The present invention also provides an integrated structure of semiconductor devices, the integrated structure includes from top to bottom:

a first dielectric layer and a plurality of first electronic devices embedded in the first dielectric layer;

a second organic film layer located between the first dielectric layers;

The first organic film layer is located on the lower surface of the first dielectric layer and the second organic film layer, and the thermal expansion coefficient of the second organic film layer is between the first dielectric layer and the first organic film layer. Between, the flexibility of the second organic film layer is greater than the flexibility of the first dielectric layer;

a substrate, located on the lower surface of the first organic film layer, and a plurality of second electronic devices are embedded in the substrate;

A conductive structure, the conductive structure connects the first electronic device and the second electronic device through the second organic film layer and the first organic film layer.

The beneficial effect of the present invention is that the first dielectric layer on the outer periphery of the through hole is replaced with the second organic film layer whose thermal expansion coefficient is close to that of the first organic film layer, and the second organic film layer The flexibility of the second organic film layer is greater than that of the first dielectric layer. In the case of heat, compared with the first dielectric layer, the second organic film layer is not easy to generate stress, which reduces the problem of fracture of the first dielectric film layer, especially when the positions of two adjacent through holes are relatively close, through Problems with cracking of the first dielectric film layer near the hole.

Description of drawings

FIG. 1 is a flow chart of the steps of a semiconductor device integration method according to an embodiment of the present invention.

2 to 14 are structural schematic diagrams corresponding to different steps in the manufacturing process of the semiconductor device integration method in an embodiment of the present invention.

FIG. 15 is a schematic diagram of an integrated structure of a semiconductor device according to an embodiment of the present invention.

Explanation of reference signs:

10-substrate; 11-second electronic device; 20-first organic film layer; 30-first dielectric layer; 31-first electronic device; 32-second organic film layer; 33-through hole; 331-first hole; 332—second hole; 34—conductive plug; 35—conductive structure; 101—first substrate; 102—device wafer.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and accompanying drawings, the advantages and characteristics of the present invention will be clearer, however, it should be noted that the concept of the technical solution of the present invention can be implemented in many different forms, and is not limited to the specific implementation set forth herein. example. The drawings are all in very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. layer. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

If the methods herein comprise a series of steps, the order of these steps presented herein is not necessarily the only order in which the steps can be performed, and some steps may be omitted and/or some other steps not described herein may be added to the this method. If the components in a certain drawing are the same as those in other drawings, although these components can be easily identified in all the drawings, in order to make the description of the drawings clearer, this specification will not use all the same components Reference numerals are indicated in each figure.

An embodiment of the present invention provides a semiconductor device integration method. Please refer to FIG. 1. FIG. 1 is a flow chart of the steps of a semiconductor device integration method in an embodiment of the present invention. The integration method includes:

S01: Provide a first structure, the first structure includes from top to bottom: a first dielectric layer, a first organic film layer, and a substrate, a plurality of first electronic devices are embedded in the first dielectric layer, the A plurality of second electronic devices are embedded in the substrate;

S02: Define an area including at least two adjacent through holes and a set range around the two through holes as a first area, and remove the first dielectric layer in the first area;

S03: Form a second organic film layer in the first region, the thermal expansion coefficient of the second organic film layer is between the first dielectric layer and the first organic film layer, and the second organic film layer the flexibility of the layer is greater than the flexibility of the first dielectric layer;

S04: forming a through hole, penetrating through the second organic film layer and the first organic film layer, the bottom of the through hole exposing the second electronic device;

S05: Form a conductive plug in the through hole, where the conductive plug is connected to the second electronic device.

Please refer to FIG. 2 to FIG. 14 below to describe the semiconductor device integration method. 2 to 6 are structural schematic diagrams corresponding to each step in an embodiment of the semiconductor device integration method of the present invention.

Referring to FIG. 2 , a first structure is provided. The first structure includes from top to bottom: a first dielectric layer 30, a first organic film layer 20, and a substrate 10. A plurality of first dielectric layers 30 are embedded in the first dielectric layer 30. An electronic device 31 , a plurality of second electronic devices 11 are embedded in the substrate 10 .

The material of the first dielectric layer 30 includes silicon nitride or silicon dioxide, the thermal expansion coefficient of silicon dioxide is about 0.5 ppm, and the thermal expansion coefficient of silicon nitride is about 3 ppm. The material of the first organic film layer 20 includes polyvinyl chloride, acrylate, dry film or polyimide, and the coefficient of thermal expansion of the first organic film layer 20 is 40-50 ppm. According to the above data, it can be seen that the thermal expansion coefficients of the first dielectric layer 30 and the first organic film layer 20 differ greatly. Due to the difference in thermal expansion coefficients between the two, when the first structure is heated, the first organic film layer 20 generates stress on the first dielectric layer 30, and the first dielectric layer 30 is prone to breakage in order to relieve the stress, especially when When the first dielectric layer 30 is thin and the first organic film layer 20 is thick, the first dielectric layer 30 is more likely to be broken. When a through hole is formed in the first dielectric layer 30, the fractured area is usually located on the periphery of the through hole. When a plurality of through holes are formed, the first dielectric layer 30 between two adjacent through holes is prone to appear Fracture, especially when two through holes are relatively close, the first dielectric layer 30 near the through holes is more prone to fracture.

In this embodiment, the substrate 10 is a device wafer, and the second electronic device 11 is located inside the device wafer. The second electronic device includes diodes, triodes, resistors, capacitors, etc., and the first electronic device 31 includes various chips with certain functions.

With reference to Fig. 3 and Fig. 4, define at least two adjacent through-holes 33, and the area of two through-holes 33 peripheral setting ranges is the first area (area in the dotted line frame), remove the first area The first dielectric layer 30 .

The first area is the through hole 33 and the area range where the first dielectric layer 11 on the periphery of the through hole 33 is prone to fracture, the size of the first area range and the size of the through hole 33, the distance between the two through holes 33, The thickness of the first dielectric layer 30 is related to the thickness of the first organic film layer 20 . It can be set according to the actual situation. Generally, the distance from the boundary of the first region to the edge of the through hole 33 is not less than one-third of the diameter of the through hole 33 , such as the radius of the through hole 33 . Referring to FIG. 3 , in this embodiment, the first area is an entire area, including the area where the two through holes 33 are located, the periphery of the through holes 33 , and the area between the two through holes 33 . Referring to Fig. 4, in another embodiment, the first region is divided into two independent parts, each part is centered on the through hole 33, and the outer boundary is not less than one-third of the diameter of the through hole 33 from the edge of the through hole 33 , such as the radius of the through hole 33 . This embodiment is described with two through holes. It should be understood that for the case of multiple through holes, the first region can be integrated or divided into independent parts, and each independent part can include one or more through holes. hole. The shape of the first area is not limited, and may be circular or polygonal.

Referring to FIG. 5 , a second organic film layer 32 is formed in the first region, and the thermal expansion coefficient of the second organic film layer 32 is between the first dielectric layer 30 and the first organic film layer 20 .

In this embodiment, the method for forming the second organic film layer 32 in the first region includes: spin-coating a second organic material on the first region and the upper surface of the first dielectric layer 30, The second organic material is exposed and developed to remove the second organic material outside the first region to form the second organic film layer 32 located in the first region. The material of the second organic film layer 32 includes polyimide or poly-p-phenylene benzobisoxazole, and the coefficient of thermal expansion of the second organic film layer 32 is adjustable, generally greater than 10ppm, compared to the first The thermal expansion coefficient of the dielectric layer 30 and the second organic film layer 32 is similar to that of the first organic film layer 20 . When the external temperature changes, deformation and stress are less likely to occur between the second organic film layer 32 and the first organic film layer 20 , and the flexibility of the second organic film layer 32 is greater than that of the first dielectric layer 30 . When subjected to stress, the second organic film layer 32 is less likely to break. In this embodiment, after removing the second organic material outside the first region, it also includes performing a planarization process on the surface of the organic material in the first region, so that the surface of the second organic film layer 32 and the surface of the first dielectric layer 30 The surface is flush.

Referring to FIG. 6 , a through hole 33 is formed through the second organic film layer 32 and the first organic film layer 20 , and the bottom of the through hole 33 exposes the second electronic device 11 .

The method of forming the through hole 33 includes: laser drilling, mechanical drilling, etching process or photolithography process.

In this embodiment, the first organic film layer 20 and the second organic film layer 32 are made of the same material, which is polyimide, and the through hole 33 can be formed by one etching process. Specifically, the etching gas used is a mixed gas of argon, oxygen and carbon fluoride, the set temperature range is 15-25 degrees Celsius, and the pressure is 8-12 mTorr. It should be noted that, usually, since both the first organic film layer 20 and the second organic film layer 32 have organic materials, their chemical constitutions are similar, and carbon, hydrogen, oxygen and nitrogen are the main elements. Even if they are not the same material, they may The same etching gas can be used for etching. There is no need to perform two etching processes to respectively etch the first organic film layer 20 and the second organic film layer 32 . Of course, when the materials of the two are quite different and different etching gases are required, the etching can also be performed in two steps.

Referring to FIG. 7 , in another embodiment, the through hole 33 is formed by a combination of photolithography (exposure, development) process and etching process. Specifically, when forming the second organic film layer 32 (when removing the organic material outside the first region) or after forming the second organic film layer 32, by exposing and developing the second organic film layer 32, the A first hole 331 is formed on the second organic film layer 32 , and the first hole 331 is located above the second electronic device 11 to expose the first organic film layer 20 . Referring to FIG. 8, the first organic film layer 20 below the first hole 331 is removed by an etching process to form a second hole 332, and the second hole 332 exposes the second electronic device 11, so The first hole 331 and the second hole 332 together form the through hole 33 .

Referring to FIG. 9 , a conductive plug 34 is formed in the through hole 33 , and the conductive plug 34 is connected to the second electronic device 11 .

The method for forming the conductive plug 34 includes: depositing a conductive film on the upper surface of the second organic film layer 32, the through hole 33, and the first dielectric layer 30 by evaporation or magnetron sputtering, and the material of the conductive film can be molybdenum ( Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium ( Ti), gold (Au), osmium (Os), rhenium (Re), palladium (Pd), platinum, nickel and other metals or made of the above alloys. The conductive thin film outside the through hole 33 is removed by mechanical grinding or CMP process, and the conductive thin film inside the through hole 33 constitutes the conductive plug 34 .

In this embodiment, the substrate 10 is a device wafer, and forming the first structure includes:

Referring to FIG. 10 , a first substrate 101 is provided, and the first electronic device 31 is formed on the surface of the first substrate 101 .

The material of the first substrate 101 can be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs ), indium phosphide (InP) or other III/V compound semiconductors, ceramic substrates such as alumina, quartz or glass substrates, etc. The first electronic device 31 is temporarily bonded on the surface of the first substrate 101 , and the first electronic device 31 includes various chips with certain functions.

Referring to FIG. 11 , a first dielectric layer 30 is formed, the first dielectric layer 30 covers the first substrate 101 , and the first electronic device 31 is completely embedded in the first dielectric layer 30 .

The first dielectric layer 30 is formed on the surface of the first substrate 101 by chemical vapor deposition or physical vapor deposition, and the first dielectric layer 30 wraps the first electronic device 31 therein. The material of the first dielectric layer 30 may be silicon dioxide or silicon nitride.

Referring to FIG. 12 , a device wafer 102 is provided in which the second electronic device 11 is formed.

The second electronic device 11 includes active devices and passive devices, such as diodes, triodes, resistors, capacitors and the like.

Referring to FIG. 13 , the first organic film layer 20 is provided, and the first dielectric layer 30 is bonded to the device wafer 102 .

The first organic film layer 20 is covered on the surface of the device wafer 102, and then the first dielectric layer 30 faces the first organic film layer 20, and the first dielectric layer 30 and the device wafer 102 pass through the first organic film The layers 20 are bonded together, and the material of the first organic film layer 20 refers to the above.

Referring to FIG. 14, the first substrate 102 is removed.

In this embodiment, the first substrate 102 is removed by mechanical grinding, and in other embodiments, the first substrate 102 may also be removed by CMP.

In another embodiment, the substrate 10 is a device wafer, and the first structure may also be formed through the following steps. The main steps are briefly described below, and please refer to the previous embodiment for details. The main steps are as follows:

S11: providing the device wafer, in which the second electronic device is formed;

S12: forming the first organic film layer on the upper surface of the device wafer;

S13: paste the first electronic device on the upper surface of the first organic film layer;

S14: forming the first dielectric layer, covering the first organic film layer, and fully embedding the first electronic device in the first dielectric layer.

An embodiment of the present invention also provides an integrated structure of a semiconductor device. FIG. 15 shows an integrated structure of a semiconductor device according to an embodiment of the present invention. Please refer to FIG. 15. The integrated structure of a semiconductor device includes from top to bottom:

A first dielectric layer 30, and a plurality of first electronic devices 31 embedded in the first dielectric layer 30;

The second organic film layer 32 is located between the first dielectric layers 30;

The first organic film layer 20 is located on the lower surface of the first dielectric layer 30 and the second organic film layer 32, and the thermal expansion coefficient of the second organic film layer 32 is between the first dielectric layer 30 and the second organic film layer. Between the first organic film layers 20, the flexibility of the second organic film layer 32 is greater than that of the first dielectric layer 30;

a substrate 10, located on the lower surface of the first organic film layer 20, and a plurality of second electronic devices 11 are embedded in the substrate 10;

The conductive structure 35 connects the first electronic device 31 and the second electronic device 11 through the second organic film layer 35 and the first organic film layer 20 .

The conductive structure 35 includes conductive plugs penetrating through the first organic film layer 20 and the second organic film layer 32 , and interconnection lines connecting the conductive plugs. The interconnection wire is connected to the first electronic device 31 , and the conductive plug is electrically connected to the second electronic device 11 . In this embodiment, the second organic film layer 32 is arranged above the area where the outer periphery of the conductive plug is located, and the distance from the outer edge of the second organic film layer 32 to the outer edge of the conductive plug is not less than one third of the diameter of the conductive plug. , such as the radius of the conductive plug. The second organic film layer 32 may be a whole, including at least two conductive plugs inside the whole, or the second organic film layer 32 may include a plurality of independent parts isolated from each other, and each independent part includes at least one conductive plug.

The material of the second organic film layer includes: polyimide or poly-p-phenylenebenzobisoxazole, and the coefficient of thermal expansion of the second organic film layer is greater than 10 ppm. The material of the first organic film layer includes: polyvinyl chloride, acrylate, dry film or polyimide, and the thermal expansion coefficient of the first organic film is about 40-50ppm. The material of the first dielectric layer includes nitride Silicon or silicon dioxide, the thermal expansion coefficient of silicon nitride is about 3ppm, and the thermal expansion coefficient of silicon dioxide is about 0.5ppm. In this embodiment, the substrate 10 is a device wafer, and the second electronic device 11 is located inside the device wafer.

It should be noted that each embodiment in this specification is described in a related manner, the same and similar parts of each embodiment can be referred to each other, each embodiment focuses on the differences from other embodiments . In particular, for the structural embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for relevant parts, please refer to the part of the description of the method embodiments.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the protection scope of the claims.

Claims (17)

1. A semiconductor device integration method, characterized in that, comprising: A first structure is provided, and the first structure includes from top to bottom: a first dielectric layer, a first organic film layer, and a substrate, and a plurality of second electronic devices are embedded in the substrate; Defining the through hole and the area of the set range around the through hole as the first area, removing the first dielectric layer in the first area; A second organic film layer is formed in the first region, and the absolute value of the difference between the thermal expansion coefficients of the second organic film layer and the first organic film layer is smaller than that of the first dielectric layer and the first organic film layer. The absolute value of the difference between the thermal expansion coefficients of the layers, the flexibility of the second organic film layer is greater than the flexibility of the first dielectric layer; forming a through hole through the second organic film layer and the first organic film layer, and the bottom of the through hole exposes the second electronic device; Conductive plugs are formed in the through holes, the conductive plugs are connected to the second electronic device. 2. The semiconductor device integration method according to claim 1, wherein the set range includes an area between two adjacent through holes, or the distance between the boundary of the set range and the through hole The edge is not less than one-third of the diameter of the through hole. 3. The semiconductor device integration method according to claim 1, wherein the substrate is a device wafer, the first dielectric layer includes a first electronic device, and forming the first structure includes: providing a first substrate, forming the first electronic device over a surface of the first substrate; forming a first dielectric layer, the first dielectric layer covers the first substrate, and completely embeds the first electronic device in the first dielectric layer; providing a device wafer in which the second electronic device is formed; providing the first organic film layer, bonding the first dielectric layer to the device wafer; The first substrate is removed. 4. The semiconductor device integration method according to claim 1, wherein the substrate is a device wafer, the first dielectric layer includes a first electronic device, and forming the first structure includes: providing the device wafer in which the second electronic device is formed; forming the first organic film layer on the upper surface of the device wafer; sticking the first electronic device on the upper surface of the first organic film layer; The first dielectric layer is formed to cover the first organic film layer, and the first electronic device is completely embedded in the first dielectric layer. 5. The semiconductor device integration method according to claim 1, wherein the method for forming the second organic film layer comprises: spin-coating a second organic material on the first region and the upper surface of the first dielectric layer, exposing and developing the second organic material to form the second organic film layer located in the first region . 6. The semiconductor device integration method according to claim 1, wherein the material of the second organic film layer comprises: Polyimide or poly-p-phenylenebenzobisoxazole, the coefficient of thermal expansion of the second organic film layer is 40-50ppm. 7. The semiconductor device integration method according to claim 1, wherein the material of the first organic film layer comprises: polyvinyl chloride, acrylate, dry film or polyimide, and the first organic film The coefficient of thermal expansion is greater than 10ppm. 8 . The semiconductor device integration method according to claim 1 , wherein the material of the first dielectric layer comprises: silicon nitride or silicon dioxide, and the coefficient of thermal expansion of the first dielectric layer is less than 3 ppm. 9 . The semiconductor device integration method according to claim 1 , wherein the method for forming the through hole comprises: laser drilling or mechanical drilling. 10. The semiconductor device integration method according to claim 1, wherein the method for forming the through hole comprises: The second organic film layer and the first organic film layer are sequentially etched by an etching process, and the etching gas used includes: a mixed gas of argon, oxygen and fluorinated hydrocarbon. 11. The semiconductor device integration method according to claim 4, wherein the method for forming the through hole comprises: A first hole above the second electronic device is formed on the second organic film layer through exposure and development processes, and the first hole exposes the first organic film layer; Removing the first organic film layer under the first hole through an etching process to form a second hole, the second hole exposes the second electronic device, the first hole and the second hole form the through hole. 12. The semiconductor device integration method according to claim 3 or 4, further comprising: after forming the conductive plugs: An interconnection line is formed on the first dielectric layer and the second organic film layer, and the interconnection line is electrically connected to the conductive plug and the first electronic device. 13. An integrated structure of a semiconductor device, characterized in that it comprises, from top to bottom: a first dielectric layer and a plurality of first electronic devices embedded in the first dielectric layer; a second organic film layer located between the first dielectric layers; The first organic film layer is located on the lower surface of the first dielectric layer and the second organic film layer, and the thermal expansion coefficient of the second organic film layer is between the first dielectric layer and the first organic film layer. Between, the flexibility of the second organic film layer is greater than the flexibility of the first dielectric layer; a substrate, located on the lower surface of the first organic film layer, and a plurality of second electronic devices are embedded in the substrate; A conductive structure, the conductive structure connects the first electronic device and the second electronic device through the second organic film layer and the first organic film layer. 14. The semiconductor device integration structure according to claim 13, wherein the substrate is a device wafer, and the second electronic device is located inside the device wafer. 15. The semiconductor device integrated structure according to claim 13, wherein the material of the second organic film layer comprises: Polyimide or poly-p-phenylenebenzobisoxazole, the coefficient of thermal expansion of the second organic film layer is 40-50ppm. 16. The semiconductor device integrated structure according to claim 13, wherein the material of the first organic film layer comprises: polyvinyl chloride, acrylate, dry film or polyimide, and the first organic film The coefficient of thermal expansion of the layer is greater than 10 ppm. 17. The semiconductor device integration structure according to claim 13, wherein the conductive structure comprises a conductive plug and an interconnection wire electrically connected to the conductive plug.

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