CN111146147B - Semiconductor device integrated structure and method - Google Patents
Semiconductor device integrated structure and method Download PDFInfo
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- CN111146147B CN111146147B CN201911397206.1A CN201911397206A CN111146147B CN 111146147 B CN111146147 B CN 111146147B CN 201911397206 A CN201911397206 A CN 201911397206A CN 111146147 B CN111146147 B CN 111146147B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a semiconductor device integrated structure and a method, wherein the integrated method comprises the following steps: providing a first structure, wherein the first structure comprises from top to bottom: the device comprises a first dielectric layer, a first organic film layer and a substrate, wherein a plurality of second electronic devices are embedded in the substrate, a through hole and a region of a set range of the periphery of the through hole are defined as a first region, and the first dielectric layer of the first region is removed; forming a second organic film layer in the first region, wherein the absolute value of the difference between the thermal expansion coefficients of the second organic film layer and the first organic film layer is smaller than that of the first dielectric layer, and the flexibility of the second organic film layer is larger than that of the first dielectric layer; forming a through hole penetrating the second organic film layer and the first organic film layer, wherein the bottom of the through hole exposes the second electronic device; a conductive plug is formed in the via, the conductive plug connecting the second electronic device.
Description
Technical Field
The present disclosure relates to semiconductor device manufacturing, and more particularly, to an integrated structure and method of semiconductor device.
Background
With the development of market demands of semiconductor power devices, ultra-small and ultra-thin chips and 3D stacked small-outline high-integration packages are the trend of development.
The 3D package refers to a package technology in which two or more chips are stacked in a vertical direction in the same package without changing the size of the package. In terms of size and weight, 3D designs replace single chip packages reducing device size and weight. Compared with the traditional packaging, the 3D technology can shorten the size and reduce the weight by 40-50 times; in terms of speed, the power savings of 3D technology may enable 3D components to run at faster switching speeds per second without increasing energy consumption, parasitic capacitance and inductance are reduced; the 3D package more effectively utilizes the active area of the silicon die.
One design difficulty with packaging is achieving stacking of chips. DAF (Die Attach Film) is an ultra-thin film adhesive for connecting a semiconductor chip to a package substrate or a chip to a chip in a semiconductor packaging process, and can realize lamination and thinning of a semiconductor package by virtue of excellent reliability and convenient workability.
Stresses may be induced between integrated circuit device films during package fabrication and in the application environment. For example, stress may occur due to different material properties between different layers in an integrated circuit device. At this point, a fracture (ack) may begin to propagate within the integrated circuit device to relieve the stress. Such breakage may lead to electrical failure or functional failure, which in turn affects manufacturing yield and reliability. In order to increase the yield, it is necessary to prevent occurrence and propagation of fracture due to stress.
In the packaging process, through holes are common structures in semiconductor devices, are formed in dielectric layers, penetrate through DAF film layers and are generally used for realizing conductive communication among a plurality of devices after RDL rewiring, so that the plurality of devices become a functional whole.
However, when the organic film such as DAF exists under the dielectric layer, under the condition that the subsequent processing wafer is heated, the volume change is larger due to the larger thermal expansion coefficient of the organic film layer, and the action of force can be generated on the upper dielectric film layer. In order to relieve the stress, the upper dielectric film layer is easy to break. Especially when two through holes are relatively similar in position, the upper dielectric film layer is more prone to breaking.
Therefore, how to solve the problem of film fracture caused by the through holes in the dielectric layer above the organic film is the subject of current research.
Disclosure of Invention
The invention aims to provide a semiconductor device integrated structure and a method, which solve the problem of film breakage caused by a dielectric layer through hole above an organic film layer.
In order to achieve the above object, the present invention provides a semiconductor device integration method including:
providing a first structure, the first structure comprising, from top to bottom: the device comprises a first dielectric layer, a first organic film layer and a substrate, wherein a plurality of second electronic devices are embedded in the substrate;
defining a through hole and a region of a set range of the periphery of the through hole as a first region, and removing the first dielectric layer of the first region;
forming a second organic film layer in the first region, wherein the thermal expansion coefficient of the second organic film layer is between that of the first dielectric layer and that of the first organic film layer, and the flexibility of the second organic film layer is larger than that of the first dielectric layer;
forming a through hole penetrating through the second organic film layer and the first organic film layer, wherein the bottom of the through hole exposes the second electronic device;
and forming a conductive plug in the through hole, wherein the conductive plug is connected with the second electronic device.
The invention also provides a semiconductor device integrated structure, which comprises the following components in sequence from top to bottom:
the first dielectric layer and the plurality of first electronic devices embedded in the first dielectric layer;
the second organic film layer is positioned between the first dielectric layers;
the first organic film layer is positioned on the lower surfaces of the first dielectric layer and the second organic film layer, the thermal expansion coefficient of the second organic film layer is between that of the first dielectric layer and that of the first organic film layer, and the flexibility of the second organic film layer is larger than that of the first dielectric layer;
the substrate is positioned on the lower surface of the first organic film layer, and a plurality of second electronic devices are embedded in the substrate;
and the conductive structure penetrates through the second organic film layer and the first organic film layer to connect the first electronic device and the second electronic device.
The invention has the beneficial effects that: the first dielectric layer with larger difference between the thermal expansion coefficients of the first organic film layer and the lower first organic film layer at the periphery of the original through hole is replaced by a second organic film layer with the thermal expansion coefficient close to that of the first organic film layer, and the flexibility of the second organic film layer is larger than that of the first dielectric layer. Under the condition of being heated, compared with the first dielectric layer, the second organic film layer is not easy to generate stress, so that the problem that the first dielectric film layer breaks is solved, and particularly, when two adjacent through holes are relatively close in position, the first dielectric film layer near the through holes breaks.
Drawings
Fig. 1 is a flowchart illustrating a method for integrating a semiconductor device according to an embodiment of the present invention.
Fig. 2 to 14 are schematic structural diagrams corresponding to different steps in the manufacturing process of the method for integrating a semiconductor device according to an embodiment of the present invention.
Fig. 15 is a schematic view illustrating an integrated structure of a semiconductor device according to an embodiment of the present invention.
Reference numerals illustrate:
10-a substrate; 11-a second electronic device; 20-a first organic film layer; 30-a first dielectric layer; 31-a first electronic device; 32-a second organic film layer; 33-through holes; 331-first hole; 332-second holes; 34-a conductive plug; a 35-conductive structure; 101-a first substrate; 102-device wafer.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description and drawings, however, it should be understood that the inventive concept may be embodied in many different forms and is not limited to the specific embodiments set forth herein. The drawings are in a very simplified form and are to non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
If the method herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some steps may be omitted and/or some other steps not described herein may be added to the method. If a component in one drawing is identical to a component in another drawing, the component will be easily recognized in all drawings, but in order to make the description of the drawings clearer, the specification does not refer to all the identical components in each drawing.
Referring to fig. 1, fig. 1 is a flowchart showing steps of a semiconductor device integration method according to an embodiment of the present invention, where the integration method includes:
s01: providing a first structure, the first structure comprising, from top to bottom: the organic light emitting diode comprises a first medium layer, a first organic film layer and a substrate, wherein a plurality of first electronic devices are embedded in the first medium layer, and a plurality of second electronic devices are embedded in the substrate;
s02: defining a region which at least comprises two adjacent through holes and a set range of the peripheries of the two through holes as a first region, and removing the first dielectric layer of the first region;
s03: forming a second organic film layer in the first region, wherein the thermal expansion coefficient of the second organic film layer is between that of the first dielectric layer and that of the first organic film layer, and the flexibility of the second organic film layer is larger than that of the first dielectric layer;
s04: forming a through hole penetrating through the second organic film layer and the first organic film layer, wherein the bottom of the through hole exposes the second electronic device;
s05: and forming a conductive plug in the through hole, wherein the conductive plug is connected with the second electronic device.
The semiconductor device integration method is described below with reference to fig. 2 to 14. Fig. 2 to 6 are schematic structural diagrams corresponding to each step in an embodiment of the method for integrating a semiconductor device according to the present invention.
Referring to fig. 2, a first structure is provided, the first structure comprising, from top to bottom: the substrate comprises a first dielectric layer 30, a first organic film layer 20 and a substrate 10, wherein a plurality of first electronic devices 31 are embedded in the first dielectric layer 30, and a plurality of second electronic devices 11 are embedded in the substrate 10.
The material of the first dielectric layer 30 includes silicon nitride or silicon dioxide, the silicon dioxide has a thermal expansion coefficient of about 0.5ppm, and the silicon nitride has a thermal expansion coefficient of about 3ppm. The material of the first organic film layer 20 includes polyvinyl chloride, acrylic ester, dry film or polyimide, and the thermal expansion coefficient of the first organic film layer 20 is 40-50ppm. As is clear from the above, the difference between the thermal expansion coefficients of the first dielectric layer 30 and the first organic film layer 20 is large. Due to the difference of the thermal expansion coefficients of the two, the first structure generates stress on the first dielectric layer 30 when the first organic film layer 20 is heated, and the first dielectric layer 30 is easy to break in order to relieve the stress, especially when the first dielectric layer 30 is thinner and the first organic film layer 20 is thicker, the first dielectric layer 30 is more easy to break. When the through holes are formed in the first dielectric layer 30, the broken area is usually located at the periphery of the through holes, and when a plurality of through holes are formed, the first dielectric layer 30 between two adjacent through holes is likely to break, especially when the two through holes are relatively close to each other, the first dielectric layer 30 near the through holes is more likely to break.
In this embodiment, the substrate 10 is a device wafer, and the second electronic device 11 is located inside the device wafer. The second electronic device includes a diode, a transistor, a resistor, a capacitor, and the like, and the first electronic device 31 includes various chips having a certain function.
Referring to fig. 3 and 4, a first region (region in a dashed box) is defined as a region including at least two adjacent through holes 33 and a set range of the outer circumferences of the two through holes 33, and the first dielectric layer 30 of the first region is removed.
The first region is a region where the through holes 33 and the first dielectric layer 11 on the outer periphery of the through holes 33 are easily broken, and the size of the first region is related to the size of the through holes 33, the distance between the two through holes 33, the thickness of the first dielectric layer 30, and the thickness of the first organic film layer 20. Can be set according to actual conditions. Typically, the boundary of the first region is not less than one third of the diameter of the through hole 33, such as the radius of the through hole 33, from the edge of the through hole 33. Referring to fig. 3, the first area in the present embodiment is an integral area, and includes an area where two through holes 33 are located, an outer periphery of the through holes 33, and an area between the two through holes 33. Referring to fig. 4, in another embodiment, the first region is divided into two separate parts, each centered on the through hole 33, with the outer boundary being no less than one third of the diameter of the through hole 33, such as the radius of the through hole 33, from the edge of the through hole 33. The present embodiment is illustrated with two through holes, it being understood that in the case of a plurality of through holes, the first region may be integral or divided into separate portions, each of which may include 1 or more through holes. The shape of the first region is not limited and may be circular or polygonal.
Referring to fig. 5, a second organic film layer 32 is formed in the first region, and a thermal expansion coefficient of the second organic film layer 32 is between the first dielectric layer 30 and the first organic film layer 20.
In this embodiment, the method for forming the second organic film layer 32 in the first region includes: and spin-coating a second organic material on the upper surface of the first dielectric layer 30 in the first region, exposing and developing the second organic material, and removing the second organic material outside the first region to form the second organic film layer 32 located in the first region. The second organic film layer 32 is made of polyimide or poly-p-phenylene benzobisoxazole, and the thermal expansion coefficient of the second organic film layer 32 is more tunable, generally more than 10ppm, and compared with the first dielectric layer 30, the thermal expansion coefficient of the second organic film layer 32 is similar to that of the first organic film layer 20. When the external temperature changes, deformation and stress are not easy to occur between the second organic film layer 32 and the first organic film layer 20, and in addition, the flexibility of the second organic film layer 32 is greater than that of the first dielectric layer 30. The second organic film layer 32 is less prone to fracture when subjected to stress. In this embodiment, after removing the second organic material outside the first region, a planarization process is further performed on the surface of the organic material in the first region, so that the surface of the second organic film layer 32 is flush with the surface of the first dielectric layer 30.
Referring to fig. 6, a via hole 33 is formed through the second organic film layer 32 and the first organic film layer 20, and the bottom of the via hole 33 exposes the second electronic device 11.
The method of forming the through hole 33 includes: laser drilling, mechanical drilling, etching processes or photolithography processes.
In this embodiment, the materials of the first organic film layer 20 and the second organic film layer 32 are the same and are polyimide, and the through hole 33 can be formed by one etching process. Specifically, the etching gas is a mixed gas of argon, oxygen and carbon fluoride, the set temperature range is 15-25 ℃, and the pressure is 8-12mTorr. In general, since the first organic film layer 20 and the second organic film layer 32 are made of organic materials and have similar chemical structures, they are made of hydrocarbon oxygen nitrogen as a main element, and the same etching gas may be used for etching even if they are not made of the same material. The first organic film layer 20 and the second organic film layer 32 are not required to be etched separately by performing the etching process twice. Of course, when the difference of the materials is large and different etching gases are needed, the two-step etching can be performed.
Referring to fig. 7, in another embodiment, the via hole 33 is formed using a combination of a photolithography (exposure, development) process and an etching process. Specifically, when the second organic film layer 32 is formed (when the organic material outside the first region is removed) or after the second organic film layer 32 is formed, the first hole 331 is formed on the second organic film layer 32 by performing an exposure and development process on the second organic film layer 32, and the first hole 331 is located above the second electronic device 11, and the first organic film layer 20 is exposed. Referring to fig. 8, the first organic film layer 20 under the first hole 331 is removed by an etching process to form a second hole 332, the second hole 332 exposes the second electronic device 11, and the first hole 331 and the second hole 332 together form the through hole 33.
Referring to fig. 9, a conductive plug 34 is formed in the through hole 33, the conductive plug 34 connecting the second electronic device 11.
The method of forming the conductive plugs 34 includes: the conductive film is deposited on the upper surfaces of the second organic film layer 32, the through hole 33 and the first dielectric layer 30 by vapor deposition or magnetron sputtering, and the conductive film may be made of one of metals such as molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), palladium (Pd), platinum gold, nickel, or an alloy thereof. The conductive film outside the through hole 33 is removed by mechanical polishing or CMP process, and the conductive film inside the through hole 33 constitutes the conductive plug 34.
In this embodiment, the substrate 10 is a device wafer, and forming the first structure includes:
referring to fig. 10, a first substrate 101 is provided, and the first electronic device 31 is formed over a surface of the first substrate 101.
The material of the first substrate 101 may be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors, and may also be a ceramic substrate such as alumina, quartz or glass substrate. The first electronic device 31 is temporarily bonded to the surface of the first substrate 101, and the first electronic device 31 includes various chips having a certain function.
Referring to fig. 11, a first dielectric layer 30 is formed, the first dielectric layer 30 covering the first substrate 101 and having the first electronic device 31 fully embedded in the first dielectric layer 30.
A first dielectric layer 30 is formed on the surface of the first substrate 101 by chemical vapor deposition or physical vapor deposition, and the first dielectric layer 30 encapsulates the first electronic device 31 therein. The material of the first dielectric layer 30 may be silicon dioxide or silicon nitride.
Referring to fig. 12, a device wafer 102 is provided, and the second electronic device 11 is formed in the device wafer 102.
The second electronic device 11 comprises active devices and passive devices such as diodes, transistors, resistors, capacitors etc.
Referring to fig. 13, the first organic film layer 20 is provided to adhere the first dielectric layer 30 to the device wafer 102.
The first organic film layer 20 is covered on the surface of the device wafer 102, and then the first dielectric layer 30 is oriented to the first organic film layer 20, the first dielectric layer 30 and the device wafer 102 are bonded together through the first organic film layer 20, and the material of the first organic film layer 20 is referred to above.
Referring to fig. 14, the first substrate 102 is removed.
In this embodiment, the first substrate 102 is removed by mechanical polishing, and in other embodiments, the first substrate 102 may be removed by CMP.
In another embodiment, the substrate 10 is a device wafer, and the first structure may be formed by the following steps. The main steps are briefly described below, and reference is made to the above embodiment for specific details. The method mainly comprises the following steps:
s11: providing the device wafer, wherein the second electronic device is formed in the device wafer;
s12: forming the first organic film layer on the upper surface of the device wafer;
s13: pasting the first electronic device on the upper surface of the first organic film layer;
s14: and forming the first dielectric layer, covering the first organic film layer, and enabling the first electronic device to be completely embedded in the first dielectric layer.
An embodiment of the present invention further provides a semiconductor device integrated structure, fig. 15 shows a semiconductor device integrated structure according to an embodiment of the present invention, referring to fig. 15, the semiconductor device integrated structure includes, in order from top to bottom:
a first dielectric layer 30, and a plurality of first electronic devices 31 embedded in the first dielectric layer 30;
a second organic film layer 32 located between the first dielectric layers 30;
the first organic film layer 20 is located on the lower surfaces of the first dielectric layer 30 and the second organic film layer 32, the thermal expansion coefficient of the second organic film layer 32 is between the first dielectric layer 30 and the first organic film layer 20, and the flexibility of the second organic film layer 32 is greater than that of the first dielectric layer 30;
a substrate 10 located on the lower surface of the first organic film layer 20, where a plurality of second electronic devices 11 are embedded in the substrate 10;
a conductive structure 35, wherein the conductive structure 35 passes through the second organic film layer 35 and the first organic film layer 20 to connect the first electronic device 31 and the second electronic device 11.
The conductive structure 35 includes conductive plugs penetrating the first organic film layer 20 and the second organic film layer 32, and interconnection lines connecting the conductive plugs. The interconnect lines are connected to the first electronic device 31 and the conductive plugs are electrically connected to the second electronic device 11. In this embodiment, the second organic film layer 32 is disposed above the region of the periphery of the conductive plug, and the distance between the outer edge of the second organic film layer 32 and the outer edge of the conductive plug is not less than one third of the diameter of the conductive plug, for example, the radius of the conductive plug. The second organic film layer 32 may be a unitary body including at least two conductive plugs therein, or the second organic film layer 32 may include a plurality of separate portions isolated from each other, each separate portion including at least one conductive plug.
The second organic film layer comprises the following materials: polyimide or poly-p-phenylene benzobisoxazole, and the thermal expansion coefficient of the second organic film layer is more than 10ppm. The first organic film layer comprises the following materials: polyvinyl chloride, acrylic, dry film, or polyimide, the first organic film having a coefficient of thermal expansion of about 40-50ppm and the material of the first dielectric layer comprising silicon nitride or silicon dioxide, the silicon nitride having a coefficient of thermal expansion of about 3ppm, the silicon dioxide having a coefficient of thermal expansion of about 0.5ppm. In this embodiment, the substrate 10 is a device wafer, and the second electronic device 11 is located inside the device wafer.
It should be noted that, in the present specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. In particular, for structural embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and reference is made to the description of method embodiments for relevant points.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (17)
1. A semiconductor device integration method, comprising:
providing a first structure, the first structure comprising, from top to bottom: the device comprises a first dielectric layer, a first organic film layer and a substrate, wherein a plurality of second electronic devices are embedded in the substrate;
defining a through hole and a region of a set range of the periphery of the through hole as a first region, and removing the first dielectric layer of the first region;
forming a second organic film layer in the first region, wherein the absolute value of the difference between the thermal expansion coefficients of the second organic film layer and the first organic film layer is smaller than that of the first dielectric layer, and the flexibility of the second organic film layer is larger than that of the first dielectric layer;
forming a through hole penetrating through the second organic film layer and the first organic film layer, wherein the bottom of the through hole exposes the second electronic device;
and forming a conductive plug in the through hole, wherein the conductive plug is connected with the second electronic device.
2. The method according to claim 1, wherein the set range includes a region between adjacent two of the through holes, or a boundary of the set range is not less than one third of a diameter of the through hole from an edge of the through hole.
3. The method of claim 1, wherein the substrate is a device wafer, the first dielectric layer includes a first electronic device therein, and forming the first structure includes:
providing a first substrate, and forming the first electronic device above the surface of the first substrate;
forming a first dielectric layer, wherein the first dielectric layer covers the first substrate and enables the first electronic device to be completely embedded in the first dielectric layer;
providing a device wafer, wherein the second electronic device is formed in the device wafer;
providing the first organic film layer, and bonding the first dielectric layer and the device wafer;
and removing the first substrate.
4. The method of claim 1, wherein the substrate is a device wafer, the first dielectric layer includes a first electronic device therein, and forming the first structure includes:
providing the device wafer, wherein the second electronic device is formed in the device wafer;
forming the first organic film layer on the upper surface of the device wafer;
pasting the first electronic device on the upper surface of the first organic film layer;
and forming the first dielectric layer, covering the first organic film layer, and enabling the first electronic device to be completely embedded in the first dielectric layer.
5. The method of claim 1, wherein the method of forming the second organic film layer comprises:
and spin-coating a second organic material on the upper surfaces of the first region and the first dielectric layer, exposing and developing the second organic material to form the second organic film layer positioned in the first region.
6. The method of claim 1, wherein the material of the second organic film layer comprises:
polyimide or poly-p-phenylene benzobisoxazole, and the thermal expansion coefficient of the second organic film layer is 40-50ppm.
7. The method of claim 1, wherein the material of the first organic film layer comprises: polyvinyl chloride, acrylate, dry film or polyimide, the first organic film having a coefficient of thermal expansion greater than 10ppm.
8. The method of claim 1, wherein the material of the first dielectric layer comprises: silicon nitride or silicon dioxide, and the thermal expansion coefficient of the first dielectric layer is less than 3ppm.
9. The semiconductor device integration method according to claim 1, wherein the method of forming the via hole comprises: laser drilling or mechanical drilling.
10. The semiconductor device integration method according to claim 1, wherein the method of forming the via hole comprises:
the second organic film layer and the first organic film layer are etched in sequence through an etching process, and the adopted etching gas comprises the following components: argon, oxygen and fluorinated hydrocarbons.
11. The semiconductor device integration method according to claim 4, wherein the method of forming the via hole comprises:
forming a first hole above the second electronic device on the second organic film layer through exposure and development processes, wherein the first hole exposes the first organic film layer;
and removing the first organic film layer below the first hole through an etching process to form a second hole, wherein the second hole exposes the second electronic device, and the first hole and the second hole form the through hole.
12. The method of integrating a semiconductor device according to claim 3 or 4, further comprising, after forming the conductive plug:
and forming interconnection lines on the first dielectric layer and the second organic film layer, wherein the interconnection lines are electrically connected with the conductive plugs and the first electronic device.
13. A semiconductor device integrated structure, comprising, in order from top to bottom:
the first dielectric layer and the plurality of first electronic devices embedded in the first dielectric layer;
the second organic film layer is positioned between the first dielectric layers;
the first organic film layer is positioned on the lower surfaces of the first dielectric layer and the second organic film layer, the thermal expansion coefficient of the second organic film layer is between that of the first dielectric layer and that of the first organic film layer, and the flexibility of the second organic film layer is larger than that of the first dielectric layer;
the substrate is positioned on the lower surface of the first organic film layer, and a plurality of second electronic devices are embedded in the substrate;
and the conductive structure penetrates through the second organic film layer and the first organic film layer to connect the first electronic device and the second electronic device.
14. The semiconductor device integrated structure of claim 13, wherein the substrate is a device wafer and the second electronic device is located inside the device wafer.
15. The semiconductor device integrated structure of claim 13, wherein the material of the second organic film layer comprises:
polyimide or poly-p-phenylene benzobisoxazole, and the thermal expansion coefficient of the second organic film layer is 40-50ppm.
16. The semiconductor device integrated structure of claim 13, wherein the material of the first organic film layer comprises: polyvinyl chloride, acrylic, dry film or polyimide, the coefficient of thermal expansion of the first organic film layer being greater than 10ppm.
17. The semiconductor device integrated structure of claim 13, wherein the conductive structure comprises a conductive plug and an interconnect line electrically connected to the conductive plug.
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