CN109860125A - Chip-packaging structure and packaging method - Google Patents
Chip-packaging structure and packaging method Download PDFInfo
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- CN109860125A CN109860125A CN201811643404.7A CN201811643404A CN109860125A CN 109860125 A CN109860125 A CN 109860125A CN 201811643404 A CN201811643404 A CN 201811643404A CN 109860125 A CN109860125 A CN 109860125A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000004065 semiconductor Substances 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 238000007731 hot pressing Methods 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000004927 fusion Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000009832 plasma treatment Methods 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 2
- 239000000945 filler Substances 0.000 abstract description 5
- 230000007774 longterm Effects 0.000 abstract description 5
- 239000012766 organic filler Substances 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- ICXAPFWGVRTEKV-UHFFFAOYSA-N 2-[4-(1,3-benzoxazol-2-yl)phenyl]-1,3-benzoxazole Chemical compound C1=CC=C2OC(C3=CC=C(C=C3)C=3OC4=CC=CC=C4N=3)=NC2=C1 ICXAPFWGVRTEKV-UHFFFAOYSA-N 0.000 description 1
- PEPBFCOIJRULGJ-UHFFFAOYSA-N 3h-1,2,3-benzodioxazole Chemical compound C1=CC=C2NOOC2=C1 PEPBFCOIJRULGJ-UHFFFAOYSA-N 0.000 description 1
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229920000265 Polyparaphenylene Polymers 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- -1 polyparaphenylene Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a kind of chip-packaging structure and packaging methods, wherein encapsulating structure, comprising: chip, front have the first pad area and the first oxide layer area；Semiconductor substrate, has first surface and a second surface opposite with first surface, first surface have fitting corresponding with the first pad area the second pad area and with corresponding the second oxide layer area being bonded, the first oxide layer area, the multiple blind holes of second surface tool；Layer is drawn, is arranged on the second surface of semiconductor substrate, is electrically connected by blind hole with the second pad area；The first surface of semiconductor substrate is arranged in encapsulated layer, encapsulates chip and first surface.Projection cube structure is formed in semiconductor substrate, realize that draw layer is electrically connected with pad area, filler i.e. between projection cube structure is equivalent to semiconductor substrate, can be to avoid in the prior art between projection cube structure using thermal expansion coefficient difference brought by organic filler filling the problem of, improve the long-term reliability of chip package.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, and in particular to a kind of chip-packaging structure and packaging method.
Background technique
Traditional two dimension (2D) chip package setting is connected with each other in the same plane and by package substrate.However,
Two traditional encapsulation are limited for improving system integration density capability.And by intermediary layer (2.5D), realize three-dimensional interconnection
Package technique not only increases packaging density, reduces packaging cost, while also reducing the interconnection length of chip chamber, improves
The speed of service, more and more attention has been paid to.
Currently, in the 2.5D system integration, the interconnection of chip and pinboard adds bottom to fill out using convex block (Bump) welding procedure
Material protection, Bump welding procedure there are certain requirements the pitch between Bump, currently, cannot be less than 40um.Bump has been welded
Cheng Hou, needs the gap between use bottom filler filling chip and pinboard, and bottom filler belongs to organic material, thermal expansion coefficient
There are larger differences between silicon, it is not easily possible to the long-term reliability of chip package.
Summary of the invention
Therefore, the present invention provides a kind of chip-packaging structure, improves the property sub- reliably and with long-term of chip package.
According in a first aspect, the embodiment of the invention provides a kind of chip-packaging structures, comprising: chip, front have the
One pad area and the first oxide layer area；Semiconductor substrate has first surface and the second surface opposite with the first surface,
The first surface has the second pad area of fitting corresponding with first pad area and corresponding with first oxide layer area
Second oxide layer area of fitting, the second surface have multiple blind holes；Layer is drawn, the second table of the semiconductor substrate is set
On face, it is electrically connected by the blind hole with second pad area；The first table of the semiconductor substrate is arranged in encapsulated layer
The chip and the first surface are encapsulated in face.
Optionally, second pad area and second oxide layer area are generally aligned in the same plane.
Optionally, first pad area is bonded with second pad area, first oxide layer area and described second
The fusion of oxide layer area.
Optionally, inside the semiconductor substrate there is the multiple layer metal being electrically connected with second pad area mutually to link
Structure, the blind hole is deeply to the metal interconnection structure.
Optionally, the metal interconnection structure is less than or equal to four layers.
Optionally, the extraction layer includes: wiring layer, fills the table of semiconductor substrate described in the blind hole and covering part
Face；The surface of the wiring layer is arranged in dielectric layer, has multiple via holes for being connected to the wiring layer；Pin is arranged in institute
It states in via hole, is connect with the wiring layer.
Base area second aspect, the embodiment of the invention provides a kind of packaging methods of chip, comprising: passes through chip true
On a semiconductor substrate, the semiconductor substrate has the second pad area of fitting corresponding with first pad area for empty hot pressing upside-down mounting
The second oxide layer area of corresponding fitting with first oxide layer area；There is the first table of chip in the semiconductor substrate upside-down mounting
Face forms encapsulated layer；Multiple blind holes are made in the semiconductor substrate second surface opposite with the first surface；Described second
Surface, which is formed, draws layer, and the extraction layer is electrically connected by the blind hole with second pad area.
It optionally, include: to serve as a contrast the semiconductor before the hot pressing upside-down mounting on a semiconductor substrate by chip vacuum
Plasma treatment is done on bottom and the surface of chip.
Optionally, in the first surface formation encapsulated layer for having chip in the semiconductor substrate upside-down mounting and in semiconductor substrate
It include: that the semiconductor substrate is thinned to preset thickness between the second surface production blind hole opposite with the first surface.
Optionally, described to form that draw layer include: second surface in the semiconductor substrate in the second surface
Predeterminable area makes wiring layer, and the wiring layer fills the second surface of semiconductor substrate described in the blind hole and covering part；
Dielectric layer is made in the wiring layer surface and formation is connected to the via hole of the wiring layer；Pin is formed in the via hole.
Technical solution of the present invention has the advantages that
1. the pad area of chip is bonded with the pad area of semiconductor substrate, the of the oxide layer area of chip and semiconductor substrate
The fitting of one surface oxide layer area, opens up blind hole on a semiconductor substrate, using layer is drawn, blind hole is filled, in semiconductor substrate
Projection cube structure is formed, realizes that draw layer is electrically connected with pad area, i.e., the filler between projection cube structure is equivalent to semiconductor lining
Bottom can be brought in this way to avoid making projection cube structure between chip and substrate in the prior art and being filled using organic filler
Thermal expansion coefficient difference the problem of, improve the long-term reliability of chip package.
2. second pad area of semiconductor substrate first surface and second oxide layer area are generally aligned in the same plane.And
And first pad area is bonded with second pad area, first oxide layer area and the fusion of second oxide layer area,
There is no gap structure between chip and semiconductor substrate to be formed, improves the reliability of encapsulating structure.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the exemplary structure chart in chip package section provided in an embodiment of the present invention；
Fig. 2~Fig. 9 is that chip packaging method provided in an embodiment of the present invention specifically shows flow chart.
Appended drawing reference:
10, chip；11, the first pad area；12, the first oxide layer area；20, semiconductor substrate；21, the second pad area；22,
Second oxide layer area；23, metal interconnection structure；24, blind hole；30, layer is drawn；31, wiring layer；32, dielectric layer；321, via hole；
33, pin；40, encapsulated layer.
Specific embodiment
Technical solution of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation
Example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
As long as in addition, the non-structure each other of technical characteristic involved in invention described below different embodiments
It can be combined with each other at conflict.
The embodiment of the present invention provides a kind of chip-packaging structure, as shown in Figure 1, the encapsulating structure includes: chip 10, front
With the first pad area 11 and the first oxide layer area 12；Semiconductor substrate 20, have first surface and with the first surface phase
Pair second surface, the first surface have fitting corresponding with first pad area 11 the second pad area 21 and with it is described
Second oxide layer area 22 of the corresponding fitting in the first oxide layer area 12, the second surface have multiple blind holes 24；Draw layer 30, setting
On the second surface of the semiconductor substrate 20, it is electrically connected by the blind hole 24 with second pad area 21；Encapsulated layer
40, the first surface of the semiconductor substrate 20 is set, the chip 10 and the first surface are encapsulated.
The pad area of chip-packaging structure provided in this embodiment, chip 10 is bonded with the pad area of semiconductor substrate 20,
The oxide layer area of chip 10 is bonded with the first surface oxide layer area of semiconductor substrate 20, opens up blind hole in semiconductor substrate 20
24, using layer 30 is drawn, blind hole 24 is filled, forms projection cube structure in semiconductor substrate 20, realizes and draws layer 30 and pad area
Electrical connection, i.e., the filler between projection cube structure is equivalent to semiconductor substrate 20, in this way can be to avoid in the prior art in core
The problem of making projection cube structure between piece 10 and substrate and filling brought thermal expansion coefficient difference using organic filler, is promoted
The long-term reliability that chip 10 encapsulates.
To guarantee reliably to be bonded between semiconductor substrate 20 and chip 10, in an alternate embodiment of the invention, semiconductor substrate
Second pad area 21 of 20 first surfaces and second oxide layer area 22 are generally aligned in the same plane.And first pad
Area 11 is bonded with second pad area 21, and first oxide layer area 12 and second oxide layer area 22 are merged, in this reality
It applies in example, can be realized by vacuum hot-pressing process.In the present embodiment, the first oxide layer and the second oxide layer all can be oxygen
SiClx, the first pad and the second pad all can be copper, the first oxide layer and the second oxygen can be realized by vacuum hot-pressing process
Change layer reliably to merge, the first pad and the second pad reliably merge bonding, to form chip 10 and semiconductor substrate 20
Between there is no gap structure, improve the reliability of encapsulating structure.
Have inside semiconductor substrate 20 in an alternate embodiment of the invention to improve 33 quantity of pin that the encapsulation of chip 10 is drawn
There is the multilevel metal interconnection structure 23 being electrically connected with second pad area 21, the blind hole 24 deeply mutually links to the metal
Structure 23.The quantity of the extraction of pin 33 can be improved by multilayer interconnection structure, in the present embodiment, used metal mutually links
The number of plies of structure 23 is less than or equal to four layers, the illustrative explanation that the above-mentioned number of plies carries out merely for convenience of description, Geng Duohuo
Less 23 number of plies of metal interconnection structure is suitable for the present embodiment.In this embodiment, metal interconnection structure 23 can be according to tool
The function and 33 quantity of pin of body chip 10 are prepared in advance.When preparing metal interconnection structure 23, first surface can be with
Reserve oxidation layer region corresponding with 10 oxide layer of chip, welding disking area corresponding with 10 pad of chip.Also, oxide layer area
Domain and welding disking area are in same plane, and difference in height is less than preset value.Can preferably guarantee with chip 10 merge welding or
Bonding.
As optional embodiment, drawing layer 30 includes: wiring layer 31, and the wiring layer 31 is filled the blind hole 24 and covered
The surface of semiconductor substrate 20 described in cover, 31 overlay area of wiring layer can be used as the region for drawing the connection of pin 33.
The surface of the wiring layer 31 is arranged in dielectric layer 32, has multiple via holes for being connected to the wiring layer 31；In the present embodiment
In, alleged dielectric layer 32 can for polyparaphenylene's benzo dioxazole fiber (Poly-p-phenylene benzobisoxazole,
PBO), the organic dielectric materials such as polyimide material can be formed by modes such as spin coatings, corresponding cloth is opened up on dielectric layer 32
The via hole of line layer 31 is provided with pin 33 in via hole, which can be spherical pin, or pillar-shaped leads.
A kind of chip packaging method is present embodiments provided, in conjunction with Fig. 2-Fig. 9, by the detailed system for introducing the encapsulating structure
Make process, the production method of the encapsulating structure may include steps of:
Step S1: providing semi-conductive substrate 20, which has first surface and opposite with the first surface the
Two surfaces, the first surface have fitting corresponding with first pad area 11 the second pad area 21 and with first oxygen
Second oxide layer area 22 of the corresponding fitting in the area Hua Ceng 12, inside has the multiple layer metal being electrically connected with second pad area 21 mutual
Link structure 23.In the present embodiment, the schematic diagram of slide glass can be structure as shown in Figure 2.
S2. plasma treatment is done on the surface of the semiconductor substrate 20 and chip 10.After Surface Treatment with Plasma,
The oxide for removing semiconductor substrate 20 and chip 10 surface contaminant and pad area surface, can be improved in subsequent hot pressing
The tightness degree of fitting prevents outlet rosin joint or cavity between chip 10 and semiconductor substrate 20, improves the reliability of encapsulation.
S3. chip 10 is inverted in semiconductor substrate 20 by vacuum hotpressing.After vacuum hotpressing the first pad area 11 with
Second pad area 21 is bonded, and first oxide layer area 12 and second oxide layer area 22 are merged.In the present embodiment,
Semiconductor substrate 20 can be silicon substrate or other semiconductor material substrates, be formed in the present embodiment by executing step S3
Structure shown in Fig. 3.
S4. the first surface of chip 10 forms encapsulated layer 40 in 20 upside-down mounting of semiconductor substrate.Encapsulate the chip
10 and the first surface, in the present embodiment, structure shown in Fig. 4, the material of encapsulated layer 40 are formed by executing step S4
It can be epoxy resin, however, it is not limited to this in other embodiments, can be other capsulation materials.
Step S5: the semiconductor substrate 20 is thinned to preset thickness.It can be thicker using thickness when step starts
Substrate, be not easy to send out fragmentation, improve the yield of product.Structure shown in fig. 5 is formed by executing step S5.
S6. multiple blind holes 24 are made in the second surface opposite with the first surface of semiconductor substrate 20.The blind hole
24, deeply to the metal interconnection structure 23, can specifically perform etching inorganic medium by selective etch mutual to metal
23 layers of structure of connection.Structure shown in fig. 6 is formed by executing step S6.
S7. wiring layer 31 is made in the predeterminable area of the second surface of the semiconductor substrate 20.The wiring layer 31 is filled out
Fill the second surface of semiconductor substrate 20 described in the blind hole 24 and covering part.In the present embodiment, in semiconductor substrate 20
Surface can form wiring layer 31 by yellow light, sputtering, electroplating technology.Structure shown in Fig. 7 is formed by executing step S7.
S8. dielectric layer 32 is made on 31 surface of wiring layer and formation is connected to the via hole 321 of the wiring layer 31.?
In the present embodiment, dielectric layer 32 can be made by spin coating PI/PBO class organic dielectric material mode, and via hole 321 can pass through light
It carves or the mode of laser boring is realized.Specifically, forming structure as shown in Figure 8 after executing step S8.
S9. pin 33 is formed in the via hole.It can be in via hole interplantation ball to form pin, in optional embodiment
In, pillar-shaped leads can also be implanted into via hole.Specifically, forming structure as shown in Figure 9 after executing step S9.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And thus amplify out it is obvious variation or
It changes still within the protection scope of the invention.
Claims (10)
1. a kind of chip-packaging structure characterized by comprising
Chip, front have the first pad area and the first oxide layer area；
Semiconductor substrate, have first surface and the second surface opposite with the first surface, the first surface have with
Second pad area of the corresponding fitting of first pad area and the second oxide layer area of fitting corresponding with first oxide layer area,
The second surface has multiple blind holes；
Layer is drawn, is arranged on the second surface of the semiconductor substrate, is electrically connected by the blind hole and second pad area
It connects；
The first surface of the semiconductor substrate is arranged in encapsulated layer, encapsulates the chip and the first surface.
2. chip-packaging structure as described in claim 1, which is characterized in that second pad area and second oxide layer
Area is generally aligned in the same plane.
3. chip-packaging structure as claimed in claim 2, which is characterized in that first pad area and second pad area
Bonding, first oxide layer area and the fusion of second oxide layer area.
4. chip-packaging structure as claimed in claim 3, which is characterized in that have inside the semiconductor substrate and described the
The multilevel metal interconnection structure of two pad areas electrical connection, the blind hole is deeply to the metal interconnection structure.
5. chip-packaging structure as claimed in claim 4, which is characterized in that the metal interconnection structure is less than or equal to four
Layer.
6. chip-packaging structure described in -5 any one according to claim 1, which is characterized in that the extraction layer includes: cloth
Line layer fills the surface of semiconductor substrate described in the blind hole and covering part；
The surface of the wiring layer is arranged in dielectric layer, has multiple via holes for being connected to the wiring layer；
Pin is arranged in the via hole, connect with the wiring layer.
7. a kind of packaging method of chip characterized by comprising
On a semiconductor substrate by vacuum hotpressing upside-down mounting by chip, the semiconductor substrate has and first pad area pair
The second oxide layer area of the second pad area and fitting corresponding with first oxide layer area should be bonded；
There is the first surface of chip to form encapsulated layer in the semiconductor substrate upside-down mounting；
Multiple blind holes are made in the semiconductor substrate second surface opposite with the first surface；
It is formed in the second surface and draws layer, the extraction layer is electrically connected by the blind hole with second pad area.
8. chip packaging method as claimed in claim 7, which is characterized in that partly led in described be inverted in chip vacuum hot pressing
Include: before in body substrate
Plasma treatment is done on the surface of the semiconductor substrate and chip.
9. chip-packaging structure as claimed in claim 8, which is characterized in that having the of chip in the semiconductor substrate upside-down mounting
One surface forms encapsulated layer and between the semiconductor substrate second surface production blind hole opposite with the first surface
The semiconductor substrate is thinned to preset thickness.
10. the chip packaging method as described in claim 7-9 any one, which is characterized in that described in the second surface
Forming extraction layer includes:
Wiring layer is made in the predeterminable area of the second surface of the semiconductor substrate, the wiring layer is filled the blind hole and covered
The second surface of semiconductor substrate described in cover；
Dielectric layer is made in the wiring layer surface and formation is connected to the via hole of the wiring layer；
Pin is formed in the via hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811643404.7A CN109860125A (en) | 2018-12-29 | 2018-12-29 | Chip-packaging structure and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811643404.7A CN109860125A (en) | 2018-12-29 | 2018-12-29 | Chip-packaging structure and packaging method |
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| Publication Number | Publication Date |
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| CN109860125A true CN109860125A (en) | 2019-06-07 |
Family
ID=66893353
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| CN201811643404.7A Pending CN109860125A (en) | 2018-12-29 | 2018-12-29 | Chip-packaging structure and packaging method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111146147A (en) * | 2019-12-30 | 2020-05-12 | 中芯集成电路（宁波）有限公司 | Semiconductor device integration structure and method |
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| CN209374430U (en) * | 2018-12-29 | 2019-09-10 | 华进半导体封装先导技术研发中心有限公司 | Chip-packaging structure |
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2018
- 2018-12-29 CN CN201811643404.7A patent/CN109860125A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20160247758A1 (en) * | 2015-02-23 | 2016-08-25 | Invensas Corporation | Microelectronic assemblies formed using metal silicide, and methods of fabrication |
| CN107195594A (en) * | 2016-03-14 | 2017-09-22 | 美光科技公司 | The semiconductor packages and its manufacture method of redistribution layer intermediary layer are protected with side wall |
| CN209374430U (en) * | 2018-12-29 | 2019-09-10 | 华进半导体封装先导技术研发中心有限公司 | Chip-packaging structure |
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| CN111146147A (en) * | 2019-12-30 | 2020-05-12 | 中芯集成电路（宁波）有限公司 | Semiconductor device integration structure and method |
| CN111146147B (en) * | 2019-12-30 | 2023-04-28 | 中芯集成电路（宁波）有限公司 | Semiconductor device integrated structure and method |
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