DE102018123499A1 - Process control for package manufacturing - Google Patents

Abstract

A method comprises the steps of: bonding a first and a second device dies to a third device die; Forming a plurality of gap-filling layers extending between the first and second device die; and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap fill layers serves to terminate the first etch process. The opening is then extended by the first etch stop layer. A second etch process is performed to extend the opening through a second dielectric layer located below the first etch stop layer. The second etching process terminates on a second etch stop layer in the plurality of gap fill layers. The method further includes extending the opening through the second etch stop layer and filling the opening with a conductive material to make a via.

Description

Priority claim and cross reference

This application claims the benefit of US Provisional Patent Application No. 62 / 586,305, filed on Nov. 15, 2017, and entitled "Process Control for SoIC Formation", which is incorporated by reference.

Background of the invention

Integrated circuit packages are becoming more and more complex, with more device dies being capped in the same package to provide more functionality. For example, a package structure has been developed that includes a plurality of device dies, such as processors and memory cubes, in the same package. The package structure can bond die-dies, which are manufactured with different processes and have different functions, to the same device die, thus creating a system. As a result, manufacturing costs can be saved and the device performance can be optimized.

list of figures

• Die 1 bis 13 sind Schnittansichten von Zwischenstufen bei der Herstellung eines Packages gemäß einigen Ausführungsformen.
• 14 ist eine Schnittansicht eines Packages gemäß einigen Ausführungsformen.
• Die 15 und 16 zeigen Schnittansichten von Packages, die weitere Package-Strukturen einbetten, gemäß einigen Ausführungsformen.
• 17 zeigt einen Prozessablauf zum Herstellen einer Package-Struktur gemäß einigen Ausführungsformen.

Aspects of the present invention will be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to common practice in the industry, various elements are not drawn to scale. Rather, for the sake of clarity of the discussion, the dimensions of the various elements can be arbitrarily increased or reduced.

• The 1 to 13 FIG. 5 are sectional views of intermediate stages in the manufacture of a package according to some embodiments. FIG.
• 14 FIG. 10 is a sectional view of a package according to some embodiments. FIG.
• The 15 and 16 show sectional views of packages that embed further package structures, according to some embodiments.
• 17 FIG. 10 illustrates a process flow for fabricating a package structure according to some embodiments.

Detailed description

The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Hereinafter, specific examples of components and arrangements will be described in order to simplify the present invention. Of course these are just examples and should not be limiting. For example, the manufacture of a first element over or on a second element in the description below may include embodiments in which the first and second elements are made in direct contact, and may also include embodiments in which additional elements are interposed between the first and second elements the second element can be made so that the first and the second element are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for simplicity and clarity and as such does not dictate any relationship between the various embodiments and / or configurations discussed.

Moreover, spatially relative terms such as "underlying", "below", "lower" / "lower", "above", "upper", "upper", and the like, may be simply used Description of the relationship of an element or a structure to one or more other elements or structures are used, which are shown in the figures. The spatially relative terms are intended to encompass, in addition to the orientation shown in the figures, other orientations of the device in use or in operation. The device may be reoriented (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may also be interpreted accordingly.

A package and method of making the same according to various exemplary embodiments are provided. The intermediate stages of manufacturing the package will be explained according to some embodiments. In addition, some modifications of some embodiments will be discussed. In all illustrations and illustrative embodiments, similar reference symbols are used to denote similar elements.

The 1 to 13 12 show sectional views of intermediate stages in the manufacture of a package according to some embodiments of the present invention. The in the 1 to 13 Steps shown are also in the process flow 200 indicated schematically in FIG 17 is shown.

1 shows a sectional view in the manufacture of a wafer 2 , The corresponding step is as a step 202 specified in the process flow, which in 17 is shown. For some Embodiments of the present invention is the wafer 2 a device wafer having active devices, such as transistors and / or diodes, and optionally, passive devices, such as capacitors, inductors, resistors, or the like. The device wafer 2 can be a plurality of chips 4 having only one of the chips 4 is shown. The chips 4 are hereinafter alternatively referred to as (component) Dies. In some embodiments of the present invention, the device die 4 a logic die, a CPU die (CPU: central processing unit), a mobile application die, a MCU die (MCU: microcontroller unit), an input-output (I / O) die, a baseband (BB ) -The or an application processor (AP) -That may be. The component die 4 may also be a memory die, such as a DRAM (Dynamic Random Access Memory) or an SRAM (SRAM) static random access memory (SRAM).

In alternative embodiments of the present invention, a package component 2 passive components (without active components) on. In the discussion below, a device wafer will be considered as an exemplary package component 2 discussed. The embodiments of the present invention may also be used for other types of package components, such as interposer wafers.

In some embodiments of the present invention, the exemplary wafer 2 a semiconductor substrate 20 and structural elements disposed on an upper surface of the semiconductor substrate 20 are made. The semiconductor substrate 20 may consist of crystalline silicon, crystalline germanium, crystalline silicon germanium and / or a III-V compound semiconductor, such as GaAsP, AlInAs, AlGaAs, GalnAs, GalnP, GaInAsP and the like. The semiconductor substrate 20 may also be a bulk silicon substrate or a silicon on insulator (SOI) substrate. In the semiconductor substrate 20 For example, STI regions (STI: shallow trench isolation) (not shown) may be fabricated to cover the active regions in the semiconductor substrate 20 to separate. Vias (not shown) may be made to enter the semiconductor substrate 20 extend, wherein the vias are used to the structural elements on opposite sides of the wafer 2 electrically connect with each other.

In some embodiments of the present invention, the wafer 2 integrated circuit elements 22 on top of the semiconductor substrate 20 are made. Exemplary integrated circuit elements 22 are CMOS transistors (CMOS: complementary metal-oxide-semiconductor), resistors, capacitors, diodes and the like. The details of the integrated circuit elements 22 will not be explained here. In alternative embodiments, the wafer becomes 2 used to make interposers, the substrate 20 may be a semiconductor substrate or a dielectric substrate.

Above the semiconductor substrate 20 becomes an interlayer dielectric (ILD) 24 which forms a gap between gate stacks of transistors (not shown) in the integrated circuit elements 22 crowded. In some example embodiments, the ILD exists 24 phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), tetraethyl orthosilicate (TEOS) or the like. The ILD 24 can be prepared by spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition or the like. In some embodiments of the present invention, the ILD 24 with a deposition method such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) or the like.

In the ILD 24 become contact pins 28 made for electrically connecting the integrated circuit elements 22 be used with overlying metal lines and vias. In some embodiments of the present invention, the contact pins are made 28 of a conductive material selected from the group consisting of tungsten, aluminum, copper, titanium, tantalum, titanium amide, tantalum nitride, alloys thereof and / or multilayers thereof. The production of the contact pins 28 may include: generating contact openings in the ILD 24 ; Filling one or more conductive materials in the contact openings; and performing planarization, such as chemical mechanical polishing (CMP), around the tops of the contact pins 28 at the same height as the top of the ILD 24 bring to.

About the ILD 24 and the contact pins 28 there is a connection structure 30 , The connection structure 30 has metal lines 34 and vias 36 on that in dielectric layers 32 are made. The dielectric layers 32 are hereinafter alternatively referred to as intermetal dielectric layers (IMD layers) 32 designated. In some embodiments of the present invention, at least the lower layers of the dielectric layers exist 32 of a low-k dielectric material having a dielectric constant (k value) that is less than about 3.0, about 2.5 or even smaller. The dielectric layers 32 can be obtained from Black Diamond® (registered trademark of Applied Materials), a low-k carbonaceous dielectric material, hydrogen silsesquioxane (HSQ), methyl Silsesquioxane (MSQ) or the like exist. In alternative embodiments of the present invention, some or all of the dielectric layers exist 32 dielectric non-low-k materials such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxide carbonitride (SiOCN), or the like. In some embodiments of the present invention, the fabrication of the dielectric layers comprises 32 depositing a porous dielectric material and then performing a curing process to drive out the porogen so that the remaining dielectric layers 32 are porous. Between the IMD layers 32 For example, etch stop layers (which are not shown for the sake of simplicity) are prepared which may be silicon carbide, silicon nitride, or the like.

The metal pipes 34 and the vias 36 be in the dielectric layers 32 manufactured. The metal pipes 34 On the same level, hereinafter collectively referred to as a metal layer. In some embodiments of the present invention, the connection structure 30 a plurality of metal layers through the vias 36 connected to each other. The metal pipes 34 and the vias 36 can be made of copper or copper alloys, but they can also be made of other metals. The production can be carried out with single-damascene and dual damascene processes. In an exemplary single damascene process, first in one of the dielectric layers 32 creates a trench, which is then filled with a conductive material. Subsequently, a planarization process, such as a CMP process, is performed to remove excess portions of the conductive material higher than the top of the IMD layer so that a metal line remains in the trench. In a dual damascene process, a trench and a via opening are formed in an IMD layer with the via opening under and connected to the trench. Then, the conductive material is filled in the trench and the via hole to make a metal line and a via, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metallic material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium amide, tantalum, tantalum nitride or the like.

1 shows a dielectric surface layer 38 according to some embodiments of the present invention. The dielectric surface layer 38 consists of a dielectric non-low-k material, such as silicon oxide. The dielectric surface layer 38 Alternatively, it is referred to as a passivation layer because it has the function of protecting the underlying low-k dielectric layers (if present) from the adverse effects of harmful chemicals and moisture. The dielectric surface layer 38 may also have a composite structure with more than one layer, which may consist of silicon oxide, silicon nitride, undoped silicate glass (USG) or the like. The component die 4 may also include metal pads, such as aluminum or aluminum copper pads, a Post-Passivation Interconnect (PPI), or the like, which are not shown for the sake of simplicity.

In the dielectric surface layer 38 become bondpads 40A and 40B made collectively or individually as bond pads 40 be designated. In some embodiments of the present invention, the bond pads become 40A and 40B fabricated with a single damascene process, and may also include barrier layers and a copper-containing material deposited over the barrier layers. In alternative embodiments of the present invention, the bond pads 40A and 40B be prepared with a dual damascene process.

In some embodiments of the present invention, no organic dielectric material, such as a polymer layer, is incorporated in the wafer 2 used. Organic dielectric layers typically have a high thermal expansion coefficient (CTE), e.g. 10 ppm / ° C or higher. This is significantly higher than the CTE of a silicon substrate (such as the substrate 20 ), which is about 3 ppm / ° C. Therefore, organic dielectric layers often cause sagging of the wafer 2 , By not using organic materials in the wafer 2 becomes the CTE discrepancy between the layers in the wafer 2 advantageously reduced, and thereby the deflection is reduced. In addition, the non-use of organic materials in the wafer allows 2 the production of metal lines with small pitches (such as metal lines 72 in 10 ) and high density bond pads, thereby improving the passability.

The upper dielectric surface layer 38 and the bondpads 40 are planarized so that their tops are coplanar, what with the CMP in making the bond pads 40 can be reached.

Then become component dies 42A and 42B to the wafer 2 bonded, as in 2 is shown. The corresponding step is as a step 204 specified in the process flow, which in 17 is shown. In some embodiments of the present invention, the device dies 42A and 42B each may be a logic die, which may be a CPU die, an MCU die, an I / O die, a baseband die, or an AP die. The component dies 42A and 42B can also be memory dies. The component dies 42A and 42B may be different types of dies chosen from the aforementioned species. In addition, the component dies 42A and 42B with different technologies, such as 45nm technology, 28nm technology, 20nm technology or the like. Also, one of the component dies 42A and 42B one digital circuit die while the other may be an analog circuit die. The Dies 4 . 42A and 42B work together as a system. By dividing the functions and circuits of a system into different dies, such as the Dies 4 . 42A and 42B , the production of this can be optimized and the manufacturing costs can be reduced.

The component dies 42A and 42B have a semiconductor substrate 44A or. 44B which may be a silicon substrate. Substrate vias (TSVs) 46A and 46B , which are sometimes referred to as semiconductor vias or vias, are fabricated to pass through the semiconductor substrate 44A or. 44B pass. The TSVs 46A and 46B serve to connect the devices and metal lines that are on the front side (the underside shown) of the semiconductor substrates 44A and 44B are made with the back. In addition, the component dies 42A and 42B a connection structure 48A or. 48B for connecting to the active and passive devices in the device dies 42A and 42B on. The connection structures 48A and 48B have metal lines and vias (not shown).

The component die 42A has bond pads 50A and a dielectric layer 52A at the illustrated bottom of the component dies 42A on. The undersides of bond pads 50A are coplanar with the bottom of the dielectric layer 52A , The component die 42B has bond pads 50B and a dielectric layer 52B on the illustrated underside. The undersides of bond pads 50B are coplanar with the bottom of the dielectric layer 52B , In some embodiments of the present invention, all device dies, such as the device dies, are 42A and 42B , free of organic dielectric materials, such as polymers.

The bonding can be done by hybrid bonding. For example, the bond pads 50A and 50B by metal-metal direct bonding to the bond pads 40A bonded. In some embodiments of the present invention, the metal-to-metal direct bond is a copper-copper direct bond. In addition, the dielectric layers become 52A and 52B to the dielectric surface layer 38 Bonded, so that, for example, Si-O-Si bonds arise.

To realize the hybrid bonding, the device dies 42A and 42B first to the dielectric layer 38 and the bondpads 40A pre-bonded by the component dies 42A and 42B easily against the die 4 be pressed. Although only two component dies 42A and 42B For example, hybrid bonding may be performed at the wafer level, and multiple device-die groups may be identified with the die group that represents the device dies 42A and 42B are identical, are prebound and arranged as rows and columns.

After all the component dies 42A and 42B annealing is performed to prevent interdiffusion of the metals in the bond pads 40A and the corresponding bond pads above 50A and 50B to effect. The annealing temperature may be in the range of about 200 ° C to about 400 ° C and, in some embodiments, may be in the range of about 300 ° C to about 400 ° C. The annealing time may be in the range of about 1.5 hours to about 3.0 hours and, in some embodiments, may be in the range of about 1.5 hours to about 2.5 hours. In hybrid bonding, the bond pads become 50A and 50B by the direct metal bonding brought about by the intermediate metal diffusion to the corresponding bond pads 40A bonded. The bondpads 50A and 50B can detectable interfaces with the corresponding bond pads 40A form.

The dielectric layer 38 can also be attached to the dielectric layers 52A and 52B bonded, creating bonds between them. For example, atoms (such as oxygen atoms) form in one of the dielectric layers 38 and 52A / 52B chemical or covalent bonds with atoms (such as silicon atoms) in another of the dielectric layers 38 and 52A / 52B , The resulting bonds between the dielectric layers 38 and 52A / 52B are dielectric-dielectric bonds. The bondpads 50A and 50B may have sizes greater than or equal to or less than the sizes of the respective bond pads 40A are. Between adjacent component dies 42A and 42B stay column 53 back.

We stay with you 2 where a backside sanding can be done to the component dies 42A and 42B For example, to thin to a thickness of about 15 microns to about 30 microns. In 2 are dashed lines 44A - BS1 and 44B - BS1 shown the backs of the component dies 42A or. 42B schematically before the back grinding. 44A-BS2 and 44B-BS2 are the back sides of the device dies 42A or. 42B after the back sanding. By thinning the component dies 42A and 42B is the aspect ratio of the column 53 between adjacent component dies 42A and 42B reduced to perform the gap filling. Otherwise, the gap filling may be due to the otherwise high aspect ratio of the column 53 to be difficult. After the back grinding, the TSVs 46A and 46B be exposed. Alternatively, the TSVs 46A and 46B will not be exposed at this time, and the back grinding will be terminated if there is a thinner layer of the substrate containing the TSVs 46A and 46B covered. In these embodiments, the TSVs 46A and 46B in the 4 be revealed step. In other embodiments, where the aspect ratio of the column 53 is not too high for the gap filling, the back grinding is omitted.

3 FIG. 12 shows the fabrication of a plurality of gap fill layers including dielectric layers and the underlying etch stop layers. FIG. The corresponding step is as a step 206 specified in the process flow, which in 17 is shown. In some embodiments of the present invention, the gap fill layers include an etch stop layer 54 , a dielectric layer 56 over and in contact with the etch stop layer 54 , an etch stop layer 58 over and in contact with the dielectric layer 56 and a dielectric layer 60 over and in contact with the etch stop layer 58 , The layers 54 . 56 and 58 can be sequentially deposited by conformal deposition methods such as atomic layer deposition (ALD) or chemical vapor deposition (CVD).

The etch stop layer 54 is made of a dielectric material that has good adhesion to the sidewalls of the device dies 42A and 42B and the tops of the dielectric layer 38 and the bondpads 40B Has. In some embodiments of the present invention, the etch stop layer is 54 of a nitride-containing material, such as silicon nitride. A thickness T1 (the T1A and T1B includes) the etch stop layer 54 may be about 500 Å to about 1000 Å. It is clear that the values given throughout the description are only examples and that other values may be used. The etch stop layer 54 runs on the sidewalls of the component dies 42A and 42B and contact them. The etch stop layer 54 For example, it may be a conformal layer, the thickness T1A the horizontal parts and the thickness T1B the vertical parts are substantially the same size, with the difference ( T1A - T1B ), for example, has an absolute value less than about 20% or less than about 10% of the two thicknesses T1A and T1B is.

The dielectric layer 56 is made of a different material than the etch stop layer 54 , In some embodiments of the present invention, the dielectric layer is 56 silicon oxide, which may be made of TEOS, but other dielectric materials such as silicon carbide, silicon oxynitride, silicon oxynitride, or the like may be used if there is adequate etch selectivity (e.g., greater than about 50) between the dielectric layer 56 and the etch stop layer 54 gives. The etch selectivity is the ratio of the etch rate of the dielectric layer 56 to the etch rate of the etch stop layer 54 when the dielectric layer 56 etched in a later process. The fat T2 the dielectric layer 56 may be about 15 kÅ (1.5 μm) to about 25 kÅ (2.5 μm). The dielectric layer 56 may also be a conformal layer, with the thicknesses of the horizontal and vertical parts being substantially equal.

The etch stop layer 58 is made of a different material than the dielectric layer 56 , The materials of the etch stop layer 58 and the etch stop layer 54 may be the same or different. In some embodiments of the present invention, the etch stop layer is 58 silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbonitride or the like. A thickness T3 the etch stop layer 58 may be about 3 kÅ to about 5 kÅ. The etch stop layer 58 may also be a conformal layer, with the thicknesses of the horizontal and vertical parts being substantially equal. The fat T3 the etch stop layer 58 can also be greater than, equal to or less than the thickness T1 the etch stop layer 54 be what depends on whether a thickness T4 ( 4 ) greater than, equal to or less than the thickness T1 is. Because in some embodiments of the present invention, the thickness T2 smaller than the thickness T4 ( 4 ) and the etching of openings 66 on the etch stop layer 58 has been synchronized, the thickness can be T1 the etch stop layer 54 smaller than the thickness T3 the etch stop layer 58 without sacrificing the etch stop capability of the etch stop layer 54 goes.

The dielectric layer 60 is made of a different material than the etch stop layer 58 , In some embodiments of the present invention, the dielectric layer is 60 silicon oxide, which may be made of TEOS, but other dielectric materials such as silicon carbide, silicon oxynitride, silicon oxynitride, PSG, BSG, BPSG, or the like may be used if there is adequate etch selectivity (e.g., greater than about 50 is) between the dielectric layer 60 and the etch stop layer 58 gives. The etch selectivity is the ratio of the etch rate of the dielectric layer 60 to the etch rate of the etch stop layer 58 when the dielectric layer 60 etched in a later process. The dielectric layer 60 can be prepared by CVD, high density plasma chemical vapor deposition (HDPCVD), flowable chemical vapor deposition (FCVD), spin coating or the like. The dielectric layer 60 fills the remaining column 53 Completed ( 2 ), and in the dielectric layer 60 There are no seams and cavities.

In 4 For example, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess portions of the gap-filling layers 60 . 58 . 56 and 54 to remove so that the component dies 42A and 42B be exposed. The corresponding step is as a step 208 specified in the process flow, which in 17 is shown. The vias 46A and 46B are also exposed. The remaining parts of the layers 54 . 56 . 58 and 60 collectively become (gap-filling) separation areas 65 designated. The resulting thickness T4 the dielectric layer 60 can be about 60% to about 90% of the height H1 the separation areas 65 be. In some embodiments of the present invention, the height is H1 the separation areas 65 greater than about 18 microns, and may be about 20 microns to about 30 microns.

5 shows the etching of the dielectric layer 60 to the openings 66 to create. The corresponding step is as a step 210 specified in the process flow, which in 17 is shown. In some embodiments of the present invention, a photoresist is formed 68 manufactured and structured, and the dielectric layer 60 is made using the photoresist 68 etched as an etch mask. This creates the openings 66 pointing down to the etch stop layer 58 which functions as the etch stop layer. In some embodiments of the present invention, the dielectric layer 60 an oxide, and the etching can be done by dry etching. The etching gas may be a mixture of NF ₃ and NH ₃ or a mixture of HF and NH ₃ . By using the etch stop layer 58 for stopping the etching to produce the openings 66 can extend several openings 66 down on one and the same wafer 2 synchronize at the same intermediate level so that the faster etched openings wait for the slower etched openings before extending down again.

It is clear that the wafer 2 has a sag that can be so significant that it causes different openings 66 extend to different levels. When the height H1 The separation ranges greater than a certain value (which is influenced by various factors, such as the technology and the material of the separation areas 65 ), the etching causes the openings to be created 66 to problems when a single dielectric layer and a single etch stop layer are made, and some openings may reach the etch stop layer while other openings may not reach the etch stop layer. Since the vias made in the vias that do not reach the single etch stop layer and do not pass therethrough form an open circuit, a via problem arises. This problem can not be solved by prolonging the over-etching time, as this leads to further problems. In some embodiments of the present invention, the two etch stop layers become 54 and 58 and the two dielectric layers 56 and 60 made, so the thickness T4 the dielectric layer 60 less than the height H1 is. The fat T4 is chosen so that the etching of the dielectric layer 60 within the corresponding process window and all openings 66 the etch stop layer 58 reachable.

In 6 becomes the etch stop layer 58 etched so the openings 66 down to the dielectric layer 56 run. The corresponding step is as a step 212 specified in the process flow, which in 17 is shown. In some embodiments of the present invention, the etch stop layer 58 Silicon nitride, and the etching is carried out by dry etching. The etching gas may be a mixture of CF ₄ , O ₂ and N ₂ , a mixture of NF ₃ and O ₂ , SF ₆ or a mixture of SF ₆ and O ₂ . In addition, there is a high etch selectivity between the etch stop layer 58 and the dielectric layer 56 , and therefore the etching on the dielectric layer ends 56 , also called an etch stop layer for etching the etch stop layer 58 acts.

7 shows the etching of the dielectric layer 56 to the openings 66 further down to the etch stop layer 54 extend as the etch stop layer for the etching of the dielectric layer 56 acts. The corresponding step is as a step 214 specified in the process flow, which in 17 is shown. In some embodiments of the present invention, the dielectric layer 60 an oxide on. The etching can be done by dry etching. The etching gas may be a mixture of NF ₃ and NH ₃ or a mixture of HF and NH ₃ .

In 8th becomes the etch stop layer 54 etched further so that the openings 66 down to the bond pads 40B run out to the openings 66 be exposed. The appropriate step is as a step 216 specified in the process flow, which in 17 is shown. The etching can also be done with a dry etching process. In some embodiments of the present invention, the etch stop layer is 54 made of silicon nitride, and the etching is carried out by dry etching. The etching gas may be a mixture of CF ₄ , O ₂ and N ₂ , a mixture of NF ₃ and O ₂ , SF ₆ or a mixture of SF ₆ and O ₂ . Subsequently, the photoresist 68 away.

In alternative embodiments of the present invention, the layers become 56 and 54 etched in a common etching process using the same etching gases, wherein the etching gases are selected so that both layers 56 and 54 etched and the etch selectivity between the layer 56 and the etch stop layer 54 is relatively small and is, for example, about 2 to about 10 or about 5 to about 10. Therefore, although the etch rate for the layer 54 is relatively small when the layer 54 thinner than the layers above it, the layer 54 still using the same etching gas we used for the etching of the layer 56 be etched.

9 shows the production of vias 70 so the openings 66 ( 8th ) and connect to the bond pads 40B will be produced. The corresponding step is as a step 218 specified in the process flow, which in 17 is shown. In some embodiments of the present invention, the fabrication of the vias comprises 70 a plating process such as electrochemical plating or electroless plating. The vias 70 may include a metallic material such as tungsten, aluminum, copper or the like. In addition, under the metallic material, a conductive barrier layer (such as titanium, titanium amide, tantalum, tantalum nitride or the like) can be produced. Planarization, such as a CMP, is performed to remove excess portions of the plated metallic material, and the remaining portions of the metallic material form the vias 70 , The vias 70 can have essentially straight and vertical side walls. In addition, the vias can 70 have a conical profile, where the upper widths are slightly larger than the respective lower widths.

In alternative embodiments, the TSVs 46A and 46B not in the component dies 42A and 42B prefabricated. Rather, they are only made after the component dies 42A and 42B to the die 4 have been bonded. For example, the device dies 42A and 42B either before or after creating the openings 66 ( 8th ) etched to more openings (those of the illustrated TSVs 46A and 46B be occupied). The other openings in the component dies 42A and 42B and the openings 66 can be filled at the same time to the TSVs 46A and 46B and the vias 70 manufacture. The resulting vias 46A and 46B can have upper parts that are wider than the respective lower parts, as in 9 is shown. Conversely, in some embodiments where the TSVs 46A and 46B prefabricated before bonding, the TSVs 46A and 46B have upper widths that are smaller than the respective lower widths (which by dashed lines 71 is shown schematically), the vias 70 are opposite.

In 10 be Redistribution Lines (RDLs) 72 and a dielectric layer 74 manufactured. The corresponding step is as a step 220 specified in the process flow, which in 17 is shown. In some embodiments of the present invention, the dielectric layer is 74 of an oxide such as silicon oxide, a nitride such as silicon nitride, or the like. The RDLs 72 can be made by a damascene process, which includes the following steps: etching the dielectric layer 74 to create openings; Depositing a conductive barrier layer into the openings; Plating a metallic material such as copper or a copper alloy; and performing a planarization to remove excess portions of the RDLs 72 to remove.

11 shows the fabrication of passivation layers, metal pads and overlying dielectric layers. Over the dielectric layer 74 becomes a passivation layer 76 (sometimes referred to as passivation-i) and in the passivation layer 76 become vias 78 Made to work with the RDLs 72 are electrically connected. Above the passivation layer 76 become metal pads 80 made through the vias 78 with the RDLs 72 be electrically connected. The corresponding step is also a step 220 specified in the process flow, which in 17 is shown. The metal pads 80 may be aluminum pads or aluminum copper pads, but other metallic materials may be used.

Like also in 11 is shown above the passivation layer 76 a passivation layer 82 (occasionally used as passivation 2 is designated). The passivation layers 76 and 82 may each be a single layer or a composite layer and consist of a non-porous material. In some embodiments of the present invention, the passivation layers are 76 and or 82 each a compound layer comprising a silicon oxide layer (not shown individually) and a silicon nitride layer (not individually shown) over the silicon oxide layer includes. The passivation layers 76 and 82 may also be made of other non-porous dielectric materials, such as undoped silicate glass (USG), silicon oxynitride, or the like.

Then the passivation layer becomes 82 structured so that some parts of the passivation layer 82 the edge parts of the metal pads 80 cover and some parts of the metal pads 80 through the openings in the passivation layer 82 be exposed. Then a polymer layer 84 made, which is structured so that the metal pads 80 be exposed. The polymer layer 84 may be polyimide, polybenzoxazole (PBO) or the like.

In some embodiments of the present invention, that is among the metal pads 80 structure free of organic materials (such as polymer layers), so that the structures under the metal pads 80 the method used to fabricate device dies may be used, and thereby RDLs (such as the RDLs 72 ) can be achieved with small pitches and small line widths.

In 12 are compounds after passivation (PPIs) 86 manufactured. The manufacturing method comprises forming a metallic seed layer and a patterned mask layer (not shown) over the metallic seed layer and plating the PPIs 86 in the structured mask layer. The corresponding step is also a step 220 specified in the process flow, which in 17 is shown. The patterned masking layer and the portions of the metallic seed layer that are covered by the patterned masking layer are then removed in etching processes. Subsequently, a polymer layer 88 prepared, which may consist of PBO, polyimide or the like.

In 13 will be metallizations under the contact mound (UBMs) 90 produced, the UBMs 90 in the polymer layer 88 reach out to them with the PPIs 86 connect to. The corresponding step is also a step 220 specified in the process flow, which in 17 is shown. In some embodiments of the present invention, the UBMs 90 each a barrier layer (not shown) and a seed layer (not shown) over the barrier layer. The barrier layer may be a titanium layer, a titanium amide layer, a tantalum layer, a tantalum nitride layer or a layer consisting of a titanium alloy or a tantalum alloy. The materials for the seed layer may be copper or a copper alloy. Other metals, such as silver, gold, aluminum, palladium, nickel, nickel alloys, tungsten alloys, chromium or chromium alloys, and combinations thereof may also be used for the UBMs 90 be used.

Like also in 13 Shown are electrical connectors 92 manufactured. The corresponding step is also a step 220 specified in the process flow, which in 17 is shown. An exemplary manufacturing process for the UBMs 90 and the electrical connection elements 92 includes the following steps: depositing an UBM protective layer; and fabricating and patterning a mask (which may be a photoresist, not shown) with portions of the UBM protective layer exposed through the opening in the mask. After the production of the UBMs 90 For example, the illustrated package is placed in a plating bath (not shown), and plating is performed to seal the electrical connection elements 92 on the UBMs 90 manufacture. In some exemplary embodiments of the present invention, the electrical connectors 92 Solderless parts (not shown), which are not melted in subsequent Aufschmelzprozessen. The solder-free parts may be made of copper and are therefore referred to hereinafter as copper bumps, but they may also be made of other solder-free materials. The electrical connection elements 92 may also each comprise one or more capping layers (not shown), which may be a nickel layer, a nickel alloy layer, a palladium layer, a gold layer, a silver layer or multilayers thereof. The capping layers are made over the copper bumps. The electrical connection elements 92 may also include solder caps, which may consist of a Sn-Ag alloy, a Sn-Cu alloy, a Sn-Ag-Cu alloy or the like and may be lead-free or leaded. The structure produced in the previous steps is called composite wafer 94 designated. On the composite wafer 94 a die-sawing process (die-singulation process) is performed to form the composite wafer 94 in a plurality of packages 96 to cut up. The corresponding step is as a step 222 specified in the process flow, which in 17 is shown.

14 shows the composite wafer 94 and the packages 96 in alternative embodiments. These embodiments are in the 13 similar to the embodiments shown, with the exception that also has an etch stop layer 62 and a dielectric layer 64 getting produced. These embodiments are used when the thickness of the separation areas 65 too big and the two etch stop layers 54 and 58 can not solve the via problem. The etch stop layer 62 may be made of a material similar to that in Questioning materials as for the preparation of Ätzstoppschichten 54 and 58 is selected. The dielectric layer 64 may be made of a material made of similar candidate materials as for the preparation of the dielectric layers 56 and 60 is selected. The generation of the openings 66 ( 8th ) therefore also includes a further etching process for etching the dielectric layer 64 using the etch stop layer 62 to terminate the etch and etch the etch stop layer 62 using the dielectric layer 60 to stop the etching. In some embodiments of the present invention, the etching of each of the layers occurs 64 . 62 . 60 . 58 and 56 using the respective underlying layer as an etch stop layer. In alternative embodiments, the etching of each of the layers ends 64 and 62 on the shift 62 or the layer 60 , wherein for some of the underlying dielectric layers 60 and 56 and the corresponding etch stop layers underneath 58 and 54 common processes can be used. For example, for the layers 60 and 58 a common etch process using a common etchant gas may or may not be used, and the etch may be on the layer 56 which acts as an etch stop layer. For the layers 60 and 56 For example, a common etch process using a common etch gas may or may not be used, and the etch may be on the layer 56 which acts as an etch stop layer. For the layers 56 and 54 For example, a common etch process using a common etch gas may or may not be used, and the etch may be on the metal pads 40B which act as an etch stop layer.

15 shows a package 98 into which the package 96 ( 13 and 14 ) is embedded. The package 98 has memory cubes 100 which comprise a plurality of stacked memory dies (not shown individually). The package 96 and the memory cubes 100 are in an encapsulation material 102 encapsulated, which can be a molding material. Dielectric layers and RDLs (collectively with 104 are designated) are under the package 96 and the memory cubes 100 and are connected to them.

16 shows a package-on-package structure (PoP structure) 106 who have an integrated fan-out package (InFO package) 108 has that on an upper package 110 is bonded. The InFO package 108 also has the embedded package 96 on. The package 96 and vias 112 are in an encapsulation material 114 encapsulated, which can be a molding material. The package 96 is bonded to dielectric layers and RDLs collectively with 116 are designated.

The embodiments of the present invention have several advantages. By producing a plurality of etch stop layers, the etching of separation areas on an intermediate level can be synchronized before the etching process continues. This allows multiple openings on the same wafer to reach the bottom of the separation areas, which have a large thickness / height. Therefore, the deflection of the wafers does not affect the yield of the vias in the separation areas.

In some embodiments of the present invention, a method comprises the steps of: bonding a first and a second device dies to a third device die; Forming a plurality of gap-filling layers extending between the first and second device die; and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap fill layers serves to terminate the first etch process. The opening is then extended by the first etch stop layer. A second etch process is performed to extend the opening through a second dielectric layer located below the first etch stop layer. The second etching process terminates on a second etch stop layer in the plurality of gap fill layers. The method further includes extending the opening through the second etch stop layer and filling the opening with a conductive material to make a via. In one embodiment, the bonding of the first device die and the second device die comprises hybrid bonding. In an embodiment, the second etch stop layer comprises a silicon nitride layer. In one embodiment, the second etch stop layer, the second dielectric layer, and the first etch stop layer are conformal dielectric layers. In one embodiment, extending the opening through the first etch stop layer includes etching the first etch stop layer using the second dielectric layer as an etch stop layer. In one embodiment, prior to forming the plurality of gap fill layers, the method further comprises thinning the first device dies and the second device dies. In one embodiment, prior to fabricating the plurality of gap fill layers, the method further comprises planarizing the first device die and the second device die to expose vias in the first device die and the second device die. In one embodiment, the first device die, the second device die, the third device die, and the plurality of gap fill layers are free of organic dielectric materials. In an embodiment, the method further comprises establishing a redistribution line over the first device die and the second device die, wherein the redistribution line is electrically connected to the via.

In some embodiments of the present invention, a method comprises the steps of: bonding a plurality of device dies to a device wafer; Establishing separation areas between the plurality of device dies; Etching the separation regions to create a first opening and a second opening passing through the separation regions, exposing bond pads of the device wafer to the first opening and the second opening and, during the etching of the separation regions, exposing the second etch stop layer to complete the etching is used; and filling the first opening and the second opening with a conductive material to produce a first via and a second via. The forming of the isolation regions comprises: forming a first etch stop layer having sidewall portions contacting the plurality of device dies and a bottom portion contacting an upper surface of the device wafer; Forming a first dielectric layer over the first etch stop layer; Forming a second etch stop layer over the first dielectric layer; and forming a second dielectric layer over the second etch stop layer. In one embodiment, the first etch stop layer, the first dielectric layer, and the second etch stop layer are formed by a conformal deposition process. In one embodiment, the first etch stop layer, the first dielectric layer, and the second etch stop layer are formed by chemical vapor deposition. In one embodiment, the first etch stop layer is made to be thinner than the second etch stop layer. In one embodiment, bonding the plurality of device dies to the device wafer comprises hybrid bonding. In an embodiment, the method further comprises: etching the plurality of device dies to create further openings; and filling the further openings to create vias that pass through semiconductor substrates of the plurality of device dies, wherein the further openings and the first and second openings are filled simultaneously.

In some embodiments of the present invention, a package comprises: a first device die; a second device die and a third device die bonded to the first device die; a separation area between the second device die and the third device die; and a via that passes through the isolation region to electrically connect to the first device die. The separation region includes: a first etch stop layer having sidewall portions contacting the first and second device die and a bottom portion contacting an upper surface of the first device die; a first dielectric layer over the first etch stop layer; a second etch stop layer over the first dielectric layer; and a second dielectric layer over the second etch stop layer. In one embodiment, the via passes through all of the dielectric layers in the isolation region. In one embodiment, the via tapers, with upper portions becoming progressively wider than respective lower portions. In one embodiment, the first etch stop layer has a thickness that is less than a thickness of the second etch stop layer. In one embodiment, the first etch stop layer, the first dielectric layer, and the second etch stop layer are conformal layers.

Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same objects and / or advantages of the same as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent interpretations do not depart from the spirit and scope of the present invention and that they may make various changes, substitutions and alterations here without departing from the spirit and scope of the present invention.

Claims (20)

A method comprising the steps of: bonding a first device die and a second device die to a third device die; Producing a plurality of gap filling layers extending between the first device die and the second device die; Performing a first etching process to etch a first dielectric layer in the plurality of gap fill layers to form an opening, wherein a first etch stop layer associated with the plurality of gap fill layers and located below the first dielectric layer is for terminating the first etch process ; Extending the opening through the first etch stop layer; Performing a second etch process to extend the opening through a second dielectric layer associated with the plurality of gap fill layers and located below the first etch stop layer, wherein the second etch process is on a second etch process Etching stop layer in the plurality of gap filling layers ends, extending the opening through the second etching stop layer; and filling the opening with a conductive material to make a via. Method according to Claim 1 wherein the bonding of the first device die and the second device die comprises hybrid bonding. Method according to Claim 1 or 2 wherein the second etch stop layer comprises a silicon nitride layer. The method of any one of the preceding claims, wherein the second etch stop layer, the second dielectric layer, and the first etch stop layer are conformal dielectric layers. The method of claim 1, wherein extending the opening through the first etch stop layer comprises etching the first etch stop layer using the second dielectric layer as an etch stop layer. The method of claim 1, further comprising thinning the first device die and the second device die before producing the plurality of gap fill layers. The method of claim 1, further comprising planarizing the first device die and the second device die prior to forming the plurality of gap fill layers to expose vias in the first device die and the second device die. The method of any one of the preceding claims, wherein the first device die, the second device die, the third device die, and the plurality of gap fill layers are free of organic dielectric materials. The method of claim 1, further comprising establishing a redistribution line over the first device die and the second device die, wherein the redistribution line is electrically connected to the via. Procedure with the following steps: Bonding a plurality of device dies to a device wafer; Producing separation regions between the plurality of device dies, wherein producing the separation regions comprises: Forming a first etch stop layer having sidewall portions contacting the plurality of device dies and a bottom portion contacting an upper surface of the device wafer, Producing a first dielectric layer over the first etch stop layer, Forming a second etch stop layer over the first dielectric layer, and Forming a second dielectric layer over the second etch stop layer; Etching the separation regions to create a first opening that passes through the isolation regions, exposing bond pads of the device wafer to the first opening, and during the etching of the isolation regions, serving the second etch stop layer to complete the etching; and Filling the first opening with a conductive material to produce a first via and a second via. Method according to Claim 10 wherein the first etch stop layer, the first dielectric layer and the second etch stop layer are formed by a conformal deposition method. Method according to Claim 10 or 11 wherein the first etch stop layer, the first dielectric layer, and the second etch stop layer are formed by chemical vapor deposition. Method according to one of Claims 10 to 12 wherein the first etch stop layer is made to be thinner than the second etch stop layer. Method according to one of Claims 10 to 13 wherein bonding the plurality of device dies to the device wafer comprises hybrid bonding. Method according to one of Claims 10 to 14 , further comprising: etching the plurality of device dies to create a second opening; and filling the second opening to make vias to pass through semiconductor substrates of the plurality of device dies, wherein the first opening and the second opening are filled simultaneously. Package comprising: a first component die; a second device die and a third device die bonded to the first device die; a separation region between the second device die and the third device die, the isolation region comprising: a first etch stop layer, the sidewall parts contacting the first device die and the second device die, and a bottom part comprising a top surface of the first device die, a first dielectric layer over the first etch stop layer, a second etch stop layer over the first dielectric layer, and a second dielectric layer over the second etch stop layer; and a via that passes through the isolation region to electrically connect to the first device die. Package after Claim 16 wherein the via passes through all of the dielectric layers in the isolation region. Package after Claim 16 or 17 , wherein the via tapers, wherein upper parts are increasingly wider than respective lower parts. Package after one of Claims 16 to 18 wherein the first etch stop layer has a thickness that is less than a thickness of the second etch stop layer. Package after one of Claims 16 to 19 wherein the first etch stop layer, the first dielectric layer, and the second etch stop layer are conformal layers.

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