TW201738974A - Interposer manufacturing method for semiconductor device reduces phenomenon of cracking the interposer due to heating or pressurizing so as to effectively enhance the yield - Google Patents

Abstract

The disclosure relates to an interposer manufacturing method for semiconductor device, and more particularly to a method for manufacturing interposer on non-wafer substrate. The method includes steps of: providing a carrier board, forming a buffer layer on an upper surface of the carrier board, forming a conductive channel on the buffer layer, forming an insulating isolation layer on the buffer layer, forming a wire redistribution layer, forming an electrode channel on the surface of the wire redistribution layer, and releasing the carrier board. In this way, after the released carrier board is pre-formed with a conductive channel, an insulating isolation layer covering the conductive channel is formed by utilizing the technique of the deposition or coating so that the interposer of this invention does not have substrates of wafer, glass or organic layer to allow the conductive channel to be more accurate and more micronized. The quantity and density of pins can be greatly enhanced, and there is no need to thin the interposer through chemical mechanical grinding. Therefore, the working hours of grinding procedure can be completely saved to improve the production speed of the interposer, and the structure of the interposer can be prevented from being damaged and cracked due to hole drilling and grinding process, capable of effectively improving the yield and reducing manufacturing costs.

Description

Interposer manufacturing method of semiconductor device

The invention belongs to the technical field of an intermediate layer of a semiconductor device, and specifically relates to a method for fabricating an interposer without using a wafer substrate, thereby achieving the purpose of ultra-thinning of the interposer and satisfying more signal connections of the semiconductor device. The demand for the foot has the effect of improving yield and reducing costs.

According to the booming development of the electronics industry, electronic products tend to be thin and light in shape, so their semiconductor wafers are gradually becoming more and more high-performance, high-function, and high-speed research and development. In general, the most direct method of miniaturization of semiconductor wafers relies on the advancement of lithography. However, lithography has gradually approached its physical limit, so the solution has to be shifted from horizontal to vertical. In addition, multi-function electronic products For example, mobile phones are composed of various key modules. Therefore, in terms of product design, not only must the single component be refined, but also the heterogeneous integration of components and the overall performance, so that there is a three-dimensional integrated circuit ( The development of 3D IC).

At the same time, as the circuit pattern of the semiconductor wafer is reduced to a size of several tens of nanometers, the fabricated wafer integrates more computing functions and a larger number of transistor components, so that the number of signal pins (I/O) is also impatient. Multiplication, and associated with the traditional chip packaging technology encounters extremely stringent challenges. In traditional chip packaging technology, for example, wire bonding is used for packaging. The number of wires required for the package structure is greatly increased, which makes the wire drawing difficult, and the heat dissipation problem of the wafer occurs due to the increase of the multiple wire resistance. In addition, for example, Flip Chip technology can only cope with the single-layer wafer package, and can not cope with the increase in the number of packaged chips.

The aforementioned conventional wire bonding technology and flip chip packaging technology can be classified into a two-dimensional integrated circuit (2D IC), and wire bonding is used to connect the electrical signals of each module horizontally between the chip modules; and an ideal 3D IC The modules will be packaged in a stacked package. The vertical connection can also reduce the length of the conduction channel and increase the efficiency. This process tests the process technology and the heterogeneous integration between components. On the road to 3D IC, there is also the development of 2.5D IC in the current transition period, regardless of the development of 3D IC or 2.5D IC, mainly through the interposer to connect printed circuit boards and semiconductor wafers. Inter-signal, this interposer acts as a channel connecting the nanometer and millimeter world, and increases the packing density of the product. Common intervening layers are such as Si Interposer, Glass Interposer and organic interposer. Organic Interposer) and so on.

The structure of the interposer has perforations on the wafer substrate (tantalum, glass, organic material, ...), such as through-silicone via (TSV), through-glass traverse (TGV) or perforation of organic layers. (Through Organic Via, TOV), and a redistribution layer (RDL) disposed on the top end of the crucible, so that the bottom end of the crucible is covered by a conductive substrate with a conductive pad a solder pad, and the uppermost layer of the circuit redistribution layer has an electrode pad for electrically connecting the electrical connection pads (I/O pins) of the semiconductor wafer with a small pitch by solder bumps to form an encapsulant The package substrate can be combined with a semiconductor wafer having a high wiring density electrical connection pad to achieve integrated high wiring The purpose of density semiconductor wafers. Such a technique is widely used in the industry, such as the invention patents No. 093132237, No. 099143617, and Chinese invention patents No. 200910130333.5 and 201210592167.2.

The existing interposer manufacturing method, the key process of 3D IC is the most representative of the TSV technology, and the related steps are as shown in the first figure, which includes drilling holes on the wafer (by etching or laser). Technology), filling conductive materials to form conductive channels, adhering to the carrier (adhesive or electrostatic adsorption on the glass carrier), wafer thinning (by chemical mechanical polishing), forming a line of redistribution (sputtering, etching) ) and the release of the carrier plate. Due to the influence of the miniaturization of the semiconductor wafer and the increase in the number of contacts, the future demand for the interposer in the industry includes the thinner the better, the higher the density of the pins (the smaller the Pitch, the better), and the finer the wires, the better. (Line/Space is as small as possible). Therefore, the drilling on the wafer substrate is more and more difficult, and the aperture, the pitch and the accuracy of the hole position are extremely challenging, and the drilling process may cause structural damage of the wafer substrate. Cracks, even in the subsequent process, are broken by heat or pressure, resulting in an increase in the defect rate. Furthermore, in order to reduce the thickness of the wafer substrate having a thickness of about 600 to 700 micrometers to 25 to 200 micrometers, the back surface of the wafer substrate is ground by chemical mechanical polishing to reduce the thickness thereof, which needs to be removed. A wafer substrate of a considerable thickness can take a considerable amount of time; and it may cause defects in the wafer substrate after polishing, which may cause partial or overall thickness unevenness, or damage to the edge of the wafer. Product yield rate is reduced.

Further, since the wafer substrate after polishing is relatively thin and warpage occurs, it is relatively difficult to subsequently process the thinned wafer substrate, and the probability of occurrence of wafer substrate fragmentation is greatly increased. In the prior art, Temporary Bonding technology will be used before thinning and polishing, and thinning will be achieved by means of adhesives (such as UV Tape, UV curing film, UV curing liquid adhesive) or electrostatic adsorption. The rear wafer substrate is attached to a carrier (such as glass) for processing, so that the wafer substrate can be supported by the carrier to provide sufficient support. Even so, if the thickness of the wafer substrate after polishing is too thin, it is still easy to break in subsequent dissociation or process. Moreover, since the adhesive used can withstand only a temperature of about 200 degrees Celsius, it cannot be processed in a high temperature furnace tube, and a high temperature tempering process cannot be performed. In addition, the wafer substrate and the carrier which are adhered to each other are not integrally formed, or the adhesion is poor (for example, there is a bubble), and the wafer is likely to be cracked in a high temperature environment. At the same time, after the carrier is removed, since the through-silicone interposer is easily broken, the subsequent flip-chip bonding process becomes difficult, and many of the penetrating perforated interposers are lost due to destruction.

It can be seen that the above-mentioned conventional perforated interposer has obvious inconveniences and defects in terms of manufacturing, structure and use, and needs to be further improved.

The reason is that in order to solve the above problems, the relevant manufacturers do not bother to find a solution, but the design that has not been applied for a long time has been developed. Therefore, the present inventors have intensively discussed the problems faced by the existing interposer, and have succeeded in developing a semiconductor that does not use a wafer substrate through continuous improvement and trial work through years of research and development and manufacturing experience in related industries. The method for fabricating the interposer of the device can effectively solve the inconvenience and troubles caused by the use of the wafer substrate for the perforation.

Therefore, the main object of the present invention is to provide a fablesless substrate The interposer manufacturing method of the semiconductor device can form the conductive channel of the interposer without using the puncture perforation technology, so that the conductive channel is more refined, and the number and density of the pins are greatly improved.

Moreover, a second primary object of the present invention is to provide an interposer manufacturing method for a semiconductor device capable of maneuvering thickness adjustment, which can control the thickness of the interposer, and can adjust the thickness of the interposer and the electrode pattern in accordance with the manufacturer's required mobility. (Pattern) design.

In addition, another primary object of the present invention is to provide a method for fabricating an interposer for fabricating a semiconductor device having a high yield, which does not require a conductive via to be formed by perforation as in the prior art, and does not need to be thinned by grinding. Simplify equipment and processes, significantly reducing the cost of manufacturing and building.

Furthermore, another main object of the present invention is to provide an interposer manufacturing method for a semiconductor device capable of reducing process loss, which can prevent the interposer from being deformed by a stress caused by drilling or grinding, or The chipping can be performed in a high temperature furnace tube or a high temperature tempering process, so that the subsequent flip chip bonding process becomes simpler, so that the interposer is not destroyed by subsequent processes.

Based on the above, the present invention mainly achieves the foregoing objects and effects through the following technical means, including: a, a step of providing a carrier plate, the light transmittance of the transparent carrier plate can reach 60% or more And the carrier has a thickness of 300 μm to 950 μm, and the carrier is mainly a circular disk of 6 inches to 18 inches; b, a step of forming a buffer layer on the surface of the carrier; c, a Forming a conductive path on the buffer layer, the conductive path comprising a plurality of conductive pads formed on the buffer layer and formed on each of the conductive pads a step of forming an insulating isolation layer on the buffer layer, forming an insulating isolation layer on the buffer layer and filling between the conductive pad and the inner conductive line of the adjacent conductive path, wherein the insulating isolation layer is exposed The upper surface of the inner wire; e, a step of forming a circuit redistribution layer, forming one or more layers of the circuit redistribution layer on the upper surface of the insulating isolation layer, each of the circuit redistribution layers comprising a plurality of electrically connected conductive paths a wire pattern on the surface of the wire, a dielectric layer covering the surface of the wire pattern and the insulating spacer layer, and a plurality of gaps formed on the dielectric layer and exposing a portion of the wire pattern; f, forming an electrode channel in the line redistribution layer a step of forming an electrode channel on an upper surface of the uppermost layer redistribution layer, the electrode channel comprising a plurality of electrode pads electrically connected to the wire pattern via the inner layer of the redistribution layer, and each of the electrodes The upper surface of the pad is exposed on the surface of the dielectric layer of the circuit redistribution layer; and g, a step of detaching the carrier plate, the technique of heating or vaporizing the buffer layer on the carrier plate, so that the The stamping layer is disengaged such that the insulating spacer and the conductive pad of the conductive via are detached from the surface of the carrier.

Therefore, through the realization of the above specific technical means, the present invention forms an insulating isolation layer by using a deposition or coating technique after the conductive path is formed in advance on the carrier, so that the interposer of the present invention does not have a wafer, a glass or an organic layer. The layer can be formed into a conductive channel of the interposer without using the technique of perforation as in the prior art, so that the conductive channel is more precise and finer, and the number and density of the pins are greatly improved, without the need for conventional techniques. By chemical mechanical polishing to thin the interposer, the labor of the grinding process can be completely saved, and the production speed of the interposer can be increased, and the present invention can Subsequent processing is simpler, so that the interposer does not cause structural damage and cracks caused by drilling and grinding, and reduces the phenomenon that the interposer is broken by heating or pressurization in subsequent processes, which can effectively improve the yield and reduce the manufacturing. cost.

The preferred embodiments of the present invention are set forth in the accompanying drawings, and in the claims

(S01)‧‧‧ Provide carrier board

(S02)‧‧‧ Forming a buffer layer on the surface of the carrier

(S03) ‧‧ ‧ forming conductive channels on the buffer layer

(S04) ‧ ‧ forming an insulating barrier on the buffer layer

(S05) ‧ ‧ forming line redistribution

(S06) ‧ ‧ forming electrode channels on the surface of the redistribution layer

(S07) ‧ ‧ detach the carrier

(10) ‧‧‧ Carrier Board

(20) ‧‧‧buffer layer

(30)‧‧‧Electrical path

(31)‧‧‧Electrical mat

(32) ‧ ‧ inner conductor

(40) ‧‧‧Insulation barrier

(50) ‧‧‧Line redistribution

(51)‧‧‧Wire pattern

(52) ‧‧‧Dielectric layer

(53) ‧‧‧ gap

(60) ‧‧‧electrode channel

(61)‧‧‧electrode pads

(80)‧‧‧Printed circuit boards

(90)‧‧‧Semiconductor wafer

The first picture: a schematic diagram of the cross-sectional structure of the existing interposer during the production process.

Fig. 2 is a schematic view showing the manufacturing process of the interposer manufacturing method provided by the present invention; and the third to eighth graphs showing the cross-sectional structure of the interposer in the process of the present invention.

Figure 9 is a schematic view showing the cross-sectional structure of the interposer completed by the manufacturing method of the present invention.

The present invention is directed to a method of fabricating an interposer for a semiconductor device. The technical contents of the present invention are described in the following specific embodiments, and those skilled in the art can easily understand the advantages and effects of the present invention from the disclosure of the present specification. The invention may be embodied or applied by other different embodiments. Therefore, with reference to the specific embodiments of the invention and the components thereof, all of the front and rear, left and right, top and bottom, upper and lower, and horizontal and vertical references are for convenience of description and are not limiting. The present invention also does not limit its components to any position or spatial orientation. The dimensions specified in the drawings and instructions are Variations in the design and needs of the specific embodiments of the invention are possible without departing from the scope of the invention.

As for the manufacturing process of the interposer manufacturing method of the semiconductor device of the present invention, as disclosed in the second figure, the method includes a supply carrier (S01), a buffer layer formed on the surface of the carrier (S02), and a formation. The conductive path is on the buffer layer (S03), an insulating isolation layer is formed on the buffer layer (S04), a line redistribution layer (S05) is formed, an electrode channel is formed on the surface redistribution layer surface (S06), and a The carrier is detached (S07). Thereby forming an interposer of the semiconductor device of the waferless substrate; and the details of each manufacturing step are as follows, please refer to the third to eighth figures at the same time, this part of the figure shows that the invention is made in the crystal A cross-sectional view of the structure of each step in the interposer process of the circular substrate.

(a) performing the step of providing a carrier (S01): preparing a carrier (10) having a surface for forming a ceramic optical film, a metal film or a non-metal film, in a preferred embodiment of the present invention, The carrier board (10) may be selected from a light-transmitting material, and the light-transmitting carrier board (10) has a light transmittance of more than 60%. The light-transmitting carrier board (10) of the present invention has a light transmittance of 90%. More than or equal to quartz glass, borosilicate glass, sodium bismuth glass or sapphire glass is a preferred embodiment, and the carrier (10) has a thickness of 300 μm to 950 μm, and the carrier (10) of the present invention is selected from 600 μm to 750 μm. In a preferred embodiment, the carrier plate (10) is mainly a circular disk of 6 inches to 18 inches, and the carrier plate (10) of the present invention is a circular disk of 8 inches or 12 inches. a preferred embodiment; (b) a step of forming a buffer layer on the surface of the carrier (S02): as shown in the third figure, a buffer is formed on one of the surfaces of the carrier (10) The layer (20), the buffer layer (20) can be selectively heated or vaporized to dissociate, such as laser light, and the material of the buffer layer (20) can be selected from a ceramic optical film, a metal film or a non-metal film. In some embodiments of the ceramic optical film, a ceramic optical film such as gallium nitride (GaN), aluminum nitride (AlN), aluminum oxide (AlO) or zinc oxide (ZnO) may be selected to form the buffer layer (20); Or in some embodiments of the non-metal thin film, a non-metal film such as tantalum nitride (SixNx), bismuth oxide (SixOx), bismuth (Si) or tantalum carbide (SiC) may be selected to form the buffer layer (20). . Or in some embodiments of the metal thin film, titanium (Ti), titanium tungsten (TiW), nickel (Ni), aluminum (Al), copper (Cu), gold (Au), silver (Ag) may be selected. a material metal film to form a buffer layer (20), and the buffer layer (20) has a thickness of 300 to 4000 Å (Angstrom) as a preferred embodiment; (c), forming a conductive path on the buffer layer (S03) Step: As shown in the fourth figure, a plurality of conductive pads (31) are formed on the upper surface of the buffer layer (20) for substrate or printing through the solder ball joints with a large electrical connection pitch. a soldering pad of a circuit board (PCB), and an inner wire (32) is formed on an upper surface of each of the conductive pads (31), and the inner wire (32) formed on the upper surface of the conductive pad (31) has a columnar shape The structure can be used as a function such as a conventional TGV (Through Glass Via), a TSV (Through Silicon Via) or a TOV (Through Organic Via). And each of the conductive pads (31) and the corresponding inner leads (32) respectively form a conductive path (30); (d), the step of forming an insulating isolation layer on the buffer layer (S04): see the fifth Figure, then form An insulating isolation layer (40) is disposed on the buffer layer (20), and the insulating isolation layer (40) is filled in the adjacent conductive path (30) Between the adjacent conductive pads (31) and the adjacent inner leads (32), and the formed insulating spacer (40) does not cover the upper surface of the inner leads (32) of the conductive paths (30), The upper surface of the inner wire (32) is exposed. In some embodiments, the material of the insulating isolation layer (40) and related processes may be varied according to the needs of the manufacturer, for example, a dielectric material (Dielectric), a passivation material, or a photosensitive insulation. An insulating spacer (40) is formed of a semiconductor material such as a photosensitive Isolation polymer. In an embodiment, when the insulating isolation layer (40) is selected to be composed of a germanium material, the step of forming the insulating spacer layer (40) further includes depositing a germanium layer on the buffer layer (20) and the conductive via (30). Above, the ruthenium layer is then polished, such as by chemical mechanical polishing, until the upper surface of the inner conductor (32) of the conductive via (30) is exposed. In this embodiment, the inner conductor (32) that is connected to the crucible layer can be used as a conventional through-hole wiring (TSV). In another embodiment, when the insulating isolation layer (40) is selected to be composed of a glass material, the step of forming the insulating isolation layer (40) further comprises coating a glass layer on the upper surface of the buffer layer (20), and A layer of glass is filled between the inner conductor (32) of the adjacent conductive via (30) and the conductive pad (31), wherein the glass layer exposes the upper surface of the inner conductor (32). In this embodiment, the inner lead (32) formed through the glass layer can be used as a conventional glass through-hole connection (TGV). In another embodiment, when the insulating isolation layer (40) is selected to be composed of an organic material, the step of forming the insulating isolation layer (40) further comprises coating the organic material layer on the upper surface of the buffer layer (20), and Filled between the inner conductor (32) of the adjacent conductive path (30) and the conductive pad (31), wherein the organic material layer exposes the upper surface of the inner wire (32). In this embodiment, the inner conductor (32) formed through the organic material layer can be used as a conventional organic layer via connection (TOV, Through). Organic Via) use; (e), the steps of forming the circuit redistribution layer (S05): please refer to the sixth figure, and then use the technology of RDL (redistribution layer) to form one or more lines. The cloth layer (50), each circuit redistribution layer (50) comprises a wire pattern (51) electrically connected to the upper surface of the wire (32) in the conductive path (30), a wire pattern (51) and an insulating isolation layer (40) a dielectric layer (52) on the surface and a plurality of inner notches (53) exposing a portion of the conductor pattern (51), electrically connecting the conductive path (30) and an electrode formed in the subsequent step (f) Channel (60) (as shown in Figure 7), wherein the dielectric layer (52) of the line redistribution layer (50) closest to the electrode channel (60) may be a dielectric protective material such as a dielectric material (Dielectric) ), Passivation Material or Photosensitive Isolation Polymer. As shown in (A) to (C) of the sixth embodiment, a preferred embodiment of the present invention can form a three-layer line redistribution layer (50), which is defined as a first line redistribution layer (50A), respectively. a second line redistribution layer (50B) and a third line redistribution layer (50C), wherein the first line redistribution layer (50A) includes a conductor pattern (51A) formed on an upper surface of the insulating isolation layer (40) to connect a wire (32) within the conductive path (30). Forming a dielectric layer (52A) on the insulating isolation layer (40) to cover the insulating isolation layer (40) and the wiring pattern (51A), and forming a gap (53A) in the corresponding wiring pattern (51A) to the dielectric Layer (52A) to expose a portion of the conductor pattern (51A) for another line re-layer (50) (as shown in (B), (C) of Figure 6) or an electrode channel (60) Connection (as shown in Figure 7). And as shown in FIG. 6(B), after the dielectric layer (52A) of the first line redistribution layer (50A) is formed; then, the second redistribution process (RDL) is performed on the first line. Overlay layer (50A) upper shape a second line redistribution layer (50B), the second line redistribution layer (50B) wire pattern (51B) on the first circuit redistribution layer (50A) dielectric layer (52A), and through the first The inner notch (53A) of the line redistribution layer (50A) (as shown in FIG. 6(A)) is electrically connected to the wire pattern (51A) of the first line redistribution layer (50A), and then forms a second The dielectric layer (52B) of the line redistribution layer (50B) is on its conductor pattern (51B), the second line is re-layered (50B) and a plurality of inner gaps (53B) are formed on the dielectric layer (52B). To expose a portion of the second line redistribution layer (50B) conductor pattern (51B) for another line re-layer (50) (as shown in Figure 6 (C)) or an electrode channel (60) Connection (as shown in Figure 7). Thereafter, a third redistribution process (RDL) is performed, and a third line redistribution layer (50C) is formed on the second line redistribution layer (50B), and the third line redistribution layer (50C) wire pattern (51C) ) on the dielectric layer (52B) of the second line redistribution layer (50B), and via the second line re-layer (50B) inner notch (53B) (as shown in (B) of the sixth figure) a wire pattern (51B) connected to the second line redistribution layer (50B), and then a third circuit redistribution layer (50C) dielectric layer (52C) is formed on the conductor pattern (51C), the third line The redistribution layer (50C) and a plurality of inner notches (53C) are formed on the dielectric layer (52C) to expose a portion of the third line redistribution layer (50C) conductor pattern (51C). In particular, the number of times of the above redistribution process can be adjusted as needed. With different package specifications, a larger number of line redistribution layers (50) can be fabricated; step (f), the steps of forming electrode channels on the surface redistribution layer surface (S06): see the seventh figure, followed by formation An electrode channel (60) is disposed on an upper surface of the uppermost layer redistribution layer (50), and the electrode channel (60) has a plurality of the inner notches (53) electrically connected thereto via the circuit redistribution layer (50) Wire diagram The electrode pad (61) of the case (51), and the upper surface of each of the electrode pads (61) are exposed on the surface of the dielectric layer (52) of the circuit redistribution layer (50), where the electrode pads (61) In the subsequent packaging process, the electrical pads (I/O pins) of the semiconductor wafer having a small pitch can be electrically coupled by solder bumps. In the preferred embodiment of the present invention, the electrode channel (60) is formed with an electrode pad (61) on each of the inner notches (53C) of the third circuit redistribution layer (50C) dielectric layer (52C). And each of the electrode pads (61) is electrically connected to the wire pattern (51) of the third circuit redistribution layer (50C), and the upper surface of each of the electrode pads (61) is exposed to the third line. The surface of the dielectric layer (52C) of the layer (50C) is electrically connected to the electrical connection pads (I/O pins) of the semiconductor wafer; and the step (g) is performed to detach the carrier (S07). Step: After the electrode pad (61) of the electrode channel (60) is fabricated, according to the material of the buffer layer (20) and the related process, a corresponding dissociation technique can be selected, for example, dissipating by heating or heating or laser irradiation. The buffer layer (20) enables the carrier (10) to be separated from the lower surface of the insulating spacer (40) and the conductive pad (31) of the conductive via (30) to form an interposer structure, as shown in FIG. In some embodiments of the present invention, the carrier (10) is selected from the group of light transmissive carriers (10), as shown in the eighth figure, from the lower surface of the light transmissive carrier (10). The carrier plate (10) is irradiated with laser light and penetrates to the buffer layer (20), and the buffer layer (20) is vaporized and dissociated to make the insulating spacer (40) and the conductive pad of the conductive path (30) (31). ) detached from the upper surface of the light-transmissive carrier (10), even if the interposed layer is detached from the light-transmissive carrier (10), as shown in FIG. The laser used here can be selected from DUV Laser, UV Laser, visible laser or IR Laser. Since the carrier (10) is translucent, the laser light can pass through The light-transmissive carrier (10) is irradiated onto the buffer layer (20) to cause vaporization and dissociation of the buffer layer (20). It is worth noting that the laser light selected to dissociate the buffer layer (20) also varies with the material of the light-transmitting carrier (10), for example, when the light-transmitting carrier (10) is Quartz glass or sapphire glass can be used as deep ultraviolet laser (DUV), ultraviolet laser (UV), visible laser or infrared laser (IR). When the light transmissive carrier (10) is composed of borosilicate glass or sodium bismuth glass, ultraviolet laser (UV), visible laser or infrared laser (IR) may be used. When the light-transmissive carrier (10) is composed of a tantalum substrate or a tantalum carbide substrate, an infrared laser (IR) may be employed. Furthermore, depending on the material of the buffer layer (20), suitable laser light can be selected to enhance the effect of the vaporization dissociation buffer layer (20), for example, when the buffer layer 20 is made of, for example, gallium nitride (GaN) or aluminum nitride. When a ceramic optical film such as (AlN), alumina (AlO) or zinc oxide (ZnO) is used, a deep ultraviolet laser (DUV) can be selected. When the buffer layer (20) is composed of a metal film such as titanium (Ti), titanium tungsten (TiW), nickel (Ni), aluminum (Al), copper (Cu), gold (Au) or silver (Ag) , you can choose deep ultraviolet laser (DUV) or ultraviolet laser (UV). As for the deep ultraviolet laser (DUV), when the buffer layer (20) is composed of a non-metal film such as germanium (Si), tantalum carbide (SiC), tantalum nitride (SixNx) or bismuth oxide (SixOx). ) or ultraviolet laser (UV). In a preferred embodiment, the light transmissive carrier (10) is selected from quartz glass or sapphire glass, and the quartz glass or sapphire glass has high hardness and highness compared to borosilicate glass or sodium bismuth glass. Light transmittance, high temperature resistance, strong acid and alkali resistance, so it can be used in high temperature process. In still another preferred embodiment, the light transmissive carrier (10) is selected from quartz glass. Compared to borosilicate glass or sodium strontium glass, quartz glass has better light transmittance when the laser wavelength is When it is less than 300 nm, it can effectively penetrate the quartz glass and illuminate the buffer. The effect of vaporization dissociation is achieved on layer (20). In particular, when the buffer layer (20) is composed of aluminum nitride, it needs to be vaporized and dissociated by deep ultraviolet laser (DUV) due to its light transmitting property, so quartz glass having a good light transmittance is selected to constitute Translucent carrier (10). In another preferred embodiment, the material of the buffer layer (20) is titanium metal. Compared to aluminum nitride, titanium metal films are easier to fabricate and can be vaporized and dissociated by irradiation with ultraviolet laser (UV). Since the power required for vaporization to dissociate the metal film of titanium is low, the use of titanium metal to form the buffer layer (20), in addition to shortening the process time, can effectively reduce the thermal effect.

Finally, please refer to the ninth diagram, which shows the cross-sectional structure of the interposer made according to the manufacturing method of the present invention. As described above, the conductive pads (31) of the conductive vias (30) on the lower surface of the interposer and the electrode pads (61) of the electrode vias (60) on the upper surface can be electrically connected to each other in a subsequent package process. A substrate of a package substrate or a printed circuit board (80) and an electrical connection pad of a semiconductor wafer (90) having a small electrical spacing. And through the wire pattern (51) of each of the circuit redistribution layers (50), the package substrate can be combined with the semiconductor wafer having the high wiring density electrical connection pad to achieve the purpose of integrating the semiconductor wafer with high wiring density.

In summary, the interposer manufacturing method of the semiconductor device of the fablesless substrate provided by the present invention has considerable advantages, thereby increasing the added value of the product and improving the economic efficiency thereof.

First, after the conductive vias (30) are formed on the carrier (10), the insulating isolation layer (40) is formed by a deposition or coating technique, so that the interposer of the present invention does not have a wafer substrate, glass or The organic layer can form an intermediary without the need to use the technique of perforation, glass perforation or perforation of the organic layer as in the prior art. The conductive channels of the layers make the conductive channels more precise and finer, greatly increasing the number and density of their pins. At the same time, the interposer of the invention does not cause structural damage or cracks due to drilling processing, and reduces the disruption of the interposer by heating or pressurization in subsequent processes, which can effectively improve the yield.

Secondly, the present invention is mainly implemented in a semiconductor process. Compared with the phenomenon of grinding thinning and thinning warpage, the present invention can make subsequent processing simpler, reduce the probability of occurrence of fragmentation, and overcome the existing partial or The defect of uneven overall thickness further improves product yield.

Furthermore, the insulating spacer layer (40) of the present invention is formed by a deposition or coating technique, and the method of the present invention can eliminate the grinding and thinning, without the need for the prior art to thin the wafer substrate by chemical mechanical polishing. The program can completely save the labor of the grinding program and increase the production speed of the interposer.

Secondly, since the interposer of the fableless substrate of the present invention is directly processed on the light-transmissive carrier on the carrier, it can be made thinner and less stressful according to the specifications of the manufacturer. Ultra-thin interposer. At the same time, the thickness of the interposer can be controlled, and the thickness of the interposer and the design of the electrode pattern can be adjusted according to the maneuverability of the manufacturer.

In addition, the present invention clearly has the advantage of being more environmentally friendly and saving material cost compared to materials in the prior art that require grinding to remove a considerable thickness of the wafer substrate. In particular, the light-transmitting carrier in the present invention can be reused, so that the production cost can be further reduced. What's more, since the present invention does not need to form a conductive path by perforation as in the conventional method, it does not need to be thinned by grinding, which can not only greatly shorten the working time, but also simplify the equipment and process, and further reduce its manufacturing and construction. the cost of

Further, the present invention can avoid the occurrence of an intermediary layer such as a habit Because of the deformation or chipping caused by the stress caused by drilling or grinding, it can be processed in a high-temperature furnace tube, and can also be subjected to a high-temperature tempering process, so that the subsequent flip-chip bonding processing becomes simpler and enables the intermediary. The layer is not destroyed or lost due to subsequent processes.

In this way, it can be understood that the present invention is an excellent creation, in addition to effectively solving the problems faced by the practitioners, and greatly improving the efficiency, and the same or similar product creation or public use is not seen in the same technical field. At the same time, it has the effect of improving the efficiency. Therefore, the present invention has met the requirements for "novelty" and "progressiveness" of the invention patent, and is filed for patent application according to law.

(S01)‧‧‧ Provide carrier board

(S02)‧‧‧ Forming a buffer layer on the surface of the carrier

(S03) ‧‧ ‧ forming conductive channels on the buffer layer

(S04) ‧ ‧ forming an insulating barrier on the buffer layer

(S05) ‧ ‧ forming line redistribution

(S06) ‧ ‧ forming electrode channels on the surface of the redistribution layer

(S07) ‧ ‧ detach the carrier

Claims (9)

A method for manufacturing an interposer for a semiconductor device, comprising at least the following steps: a, a step of providing a carrier, selected from a transmissive carrier, the transmissive carrier having a transmittance of more than 60% And the carrier has a thickness of 300 μm to 950 μm, and the carrier is mainly a circular disk of 6 inches to 18 inches; b, a step of forming a buffer layer on the surface of the carrier; c, a a step of forming a conductive path on the buffer layer, the conductive path comprising a plurality of conductive pads formed on the buffer layer and inner leads formed on each of the conductive pads; d, forming an insulating isolation layer on the buffer layer to form an insulation The isolation layer is on the buffer layer and is filled between the conductive pad and the inner wire of the adjacent conductive channel, wherein the insulating isolation layer exposes the upper surface of the inner wire; e, a step of forming a circuit redistribution layer, One or more circuit redistribution layers are formed on the upper surface of the insulating isolation layer, and each of the circuit redistribution layers comprises a plurality of electrical patterns electrically connecting the upper surface of the conductive lines in the conductive path, and a dielectric covering the surface of the conductive pattern and the insulating isolation layer. Layer and complex formation Forming a gap in a portion of the wire pattern on the dielectric layer; f, forming an electrode channel on the surface of the circuit redistribution layer, forming an electrode channel on the upper surface of the uppermost layer redistribution layer, the electrode channel The electrode pads including the plurality of inner notches electrically connected to the wire pattern through the line redistribution layer, and the upper surface of each of the electrode pads is exposed on the surface of the dielectric layer of the circuit redistribution layer; and The step of separating the carrier plate, heating or vaporizing the buffer layer on the carrier plate The technique dissociates the buffer layer such that the insulating spacer and the conductive pad of the conductive via are detached from the surface of the carrier. The method for manufacturing an interposer for a semiconductor device according to claim 1, wherein the step of detaching the carrier is to irradiate the buffer layer with a laser from a lower surface of the transparent carrier to vaporize the buffer layer. Dissociating, the conductive pad and the insulating isolation layer are separated from the upper surface of the light transmissive carrier. The method for manufacturing an interposer for a semiconductor device according to the second aspect of the invention, wherein the translucent carrier plate may be quartz glass, borosilicate glass, sodium bismuth glass or sapphire glass having a light transmittance of 90% or more. The thickness of the carrier plate is 600 μm to 750 μm, and the thickness of the buffer layer is 300 to 4000 Å (angstrom). The method for fabricating a wafer-free substrate interposer according to claim 3, wherein the buffer layer is made of a ceramic optical film, a metal film or a non-metal film. The method for fabricating a wafer-free substrate interposer according to claim 3, wherein the material of the insulating isolation layer is selected from a dielectric material, a passivation material or a photosensitive insulating polymer material. The method for fabricating a wafer-free substrate interposer according to claim 3, wherein the laser can be selected from a DUV laser, a UV laser, a visible laser or an infrared. Light laser (IR Laser). The method for fabricating a wafer-free substrate interposer according to claim 3, wherein the step of forming the insulating spacer layer on the buffer layer further comprises depositing a germanium layer on the upper surface of the buffer layer and filling the phase Between the conductive pad of the adjacent conductive channel and the inner wire, wherein the insulating isolation layer exposes the upper surface of the inner wire. The method for fabricating a wafer-free substrate interposer according to claim 3, wherein the step of forming the insulating spacer layer on the buffer layer further comprises coating a glass layer on the upper surface of the buffer layer and filling the phase Between the conductive pad of the adjacent conductive channel and the inner wire, wherein the insulating isolation layer exposes the upper surface of the inner wire. The method for fabricating a wafer-free substrate interposer according to claim 3, wherein the step of forming the insulating spacer layer on the buffer layer further comprises coating an organic material layer on the upper surface of the buffer layer and filling the surface layer. Between the conductive pad of the adjacent conductive path and the inner wire, wherein the insulating isolation layer exposes the upper surface of the inner wire.