TWI492340B - Package structure and manufacturing method of the same - Google Patents

Description

Package structure and manufacturing method thereof

The present disclosure relates to a package structure and a method of fabricating the same, and more particularly to a package structure having a silicon interposer and a method of fabricating the same.

With the gradual shrinking of electronic system products, the current development trend has gradually moved from the traditional circuit board to various components, and gradually moved to the way of shrinking multiple components into a single package structure. In the wafer. One of the commonly used methods is to integrate different wafers into a whole set of wafers (usually with wafer thinning) in a bump stacking manner. Since the multilayer wafers are stacked by bump bonding, the complexity of the structure is increased. Moreover, after a plurality of wafers are stacked by bumps, thermal stresses may be generated between the respective wafers and bumps due to differences in thermal expansion coefficients of different wafers, or external forces or gravity may also cause mechanical stress, and the reliability problem arises. .

At present, the conventional method is to thin the wafer to increase the thermal expansion coefficient of the wafer, and to reduce the difference between the thermal expansion coefficient of the copper heat sink and the wafer. However, the step of thinning the wafer in turn raises other yield issues. Therefore, how to provide a chip package structure which has high reliability with respect to thermal stress and can still maintain good yield is one of the subjects of the related industry.

The disclosure relates to a package structure and a method of fabricating the same. borrow Forming the germanium interposer between the wafer and the heat sink can buffer and reduce the stress generated by the difference in thermal expansion coefficient between the wafer and the heat sink of different materials, thereby improving the reliability of the package structure.

According to an embodiment of the present disclosure, a package structure is proposed. The package structure includes a substrate, a wafer, a silicon interposer, a copper layer, and an integrated heat spreader (IHS). The wafer is disposed on the substrate, the interposer is formed on the wafer, the heat sink is formed on the germanium interposer, and the copper layer is formed between the germanium interposer and the wafer. The ruthenium interposer has a plurality of through silicon vias (TSVs), and the ruthenium perforations are filled with a conductive material.

According to another embodiment of the present disclosure, a method of fabricating a package structure is presented. The manufacturing method of the package structure comprises: forming an interposer, the interposer having a plurality of crucibles, the perforation is filled with a conductive material, the interposer having a first surface and a second surface; forming a heat sink a first surface of the interposer; forming a first copper layer on the second surface of the interposer; forming a second copper layer on a wafer; and bonding the interposer on the interposer by thermal compression a copper layer and a second copper layer on the wafer; and bonding the other side of the wafer relative to the second copper layer to a substrate.

In order to better understand the above and other aspects of the present disclosure, the preferred embodiments are described below in detail with reference to the accompanying drawings.

In an embodiment of the disclosure, in the package structure, the interposer layer is formed between the wafer and the heat sink, which can buffer and reduce stress generated by different materials of the wafer and the heat sink due to the difference in thermal expansion coefficient, thereby improving the package structure. Reliability. Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals are used to designate the same or similar parts. It is to be noted that the drawings have been simplified to illustrate the details of the embodiments, and the detailed description of the embodiments is for illustrative purposes only and is not intended to limit the scope of the disclosure. Those having ordinary knowledge may modify or change the structures as needed in accordance with the actual implementation.

FIG. 1 is a schematic diagram of a package structure according to an embodiment of the disclosure. Please refer to Figure 1. The package structure 100 includes a substrate 110, a wafer 120, a silicon interposer 130, and an integrated heat spreader (IHS) 140. In an embodiment, as shown in FIG. 1, the package structure 100 further includes a copper layer 150 formed between the germanium interposer 130 and the wafer 120 to further facilitate efficient conduction of heat. The wafer 120 is disposed on the substrate 110, the germanium interposer 130 is formed on the wafer 120, and the heat sink 140 is formed on the germanium interposer 130. The germanium interposer 130 has a plurality of through silicon vias (TSVs) 133 that are filled with a conductive material. In an embodiment, the electrically conductive material is, for example, copper metal. In the embodiment, the germanium interposer 130 is formed between the wafer 120 and the heat sink 140, and can buffer and reduce the stress generated by the difference between the thermal expansion coefficients of the wafer 120 and the heat sink 140 of different materials, without thinning the wafer 120. The reliability of the package structure 100 can be improved.

In the embodiment, the material of the substrate 110 is, for example, tantalum, ceramic or polymer. material. In an embodiment, the surface of the wafer 120 facing the substrate 110 may include an active circuit layer (not shown).

In the embodiment, as shown in Fig. 1, the height H of the perforation 133 is, for example, 1 to 50 μm, and the diameter D _{TSV of the} perforation 133 is, for example, 0.5 to 20 μm. The distance between the centers of any two adjacent turns 133, that is, the pitch P of the turns 133, is, for example, 1.25 to 250 microns. In the embodiment, the germanium interposer 130 does not have an electrical function. In other words, the germanium via 133 is not electrically connected to any of the components.

In the embodiment, as shown in FIG. 1, the ruthenium interposer 130 further includes a ruthenium dioxide layer 135 formed on the inner wall of the ruthenium perforation 133. In the embodiment, the thickness T _{SiO2 of the} ceria layer 135 is, for example, 0.2 to 2 μm.

Figure 2 is a graph showing the simulation results of the equivalent coefficient of thermal expansion of the interposer in one embodiment of the present disclosure. Please refer to Figure 2. The curves S1 to S3 respectively indicate the relationship between the equivalent thermal expansion coefficient of the tantalum interposer 130 and the distance P between the tantalum perforations 133 when the thickness T _SiO2 of the ceria layer 135 is 0.2, 0.5 and 1 μm. As shown in Fig. 2, when the distance P between the turns 133 is less than 50 μm, the equivalent thermal expansion coefficient of the ruthenium interposer 130 rises to about 10 ppm/K. By adjusting the diameter D _TSV and the pitch P of the _turns 133, the equivalent thermal expansion coefficient of the ruthenium interposer 130 can be controlled. In one embodiment, the equivalent thermal expansion coefficient of the germanium interposer 130 is, for example, 4 to 12 ppm/K. In the embodiment, the equivalent thermal expansion coefficient of the germanium interposer 130 is between 16~18 ppm/K of copper metal and 2.3 ppm/K of the germanium wafer, so that the germanium wafer and the copper heat sink 140 can be effectively reduced. The problem of stress reliability due to the large difference in thermal expansion coefficient.

Figure 3 is a graph showing the simulation results of the equivalent thermal conductivity of the tantalum layer of one embodiment of the present disclosure. Please refer to FIG. 3, which shows the relationship between the equivalent heat transfer coefficient K1 of the germanium interposer 130 in the horizontal direction and the equivalent heat transfer coefficient K2 of the vertical direction with respect to the distance P between the turns 133. The horizontal direction referred to herein is vertical. In the direction in which the perforation 133 extends, the vertical direction is parallel to the direction in which the perforation 133 extends. In the embodiment, the heat dissipation effect of the germanium interposer 130 is anisotropic, and the equivalent heat transfer coefficient varies depending on the direction of heat conduction.

In 2011, Chien et al. published a paper presented at the IMPACT (International Microsystems, Packaging, Assembly and Circuits Technology Conference) conference (TW059-1, pp. 152-155), which proposed the equivalent thermal conductivity of the ruthenium interposer in the horizontal direction. The equivalent heat transfer coefficient K2 of K1 and the vertical direction is expressed as follows: K1=(90.T _SiO2 ^-0.33 ). (D _TSV /P). H ^0.1 +160. T _SiO2 ^0.07

K2=128. Exp(D _TSV /P)

Of which 0.2 (micron) T _SiO2 0.5 (micron), 10 (micron) D _TSV 50 (micron), H 20 (micron), 0.1 D _TSV /P 0.77.

The simulation results shown in Fig. 3 are derived according to the above formula, and the diameter D _TSV = 30 μm of the tantalum perforation 133, the thickness T _{SiO2 of the} ceria layer 135 = 2 μm, and the height of the perforated perforation 133 H = Take 60 microns as an example. In the embodiment, as shown in FIG. 3, when the distance P between the turns 133 is less than 50 μm, the equivalent heat transfer coefficient K1 of the tantalum interposer 130 in the horizontal direction is, for example, 80 to 100 W/m/K, vertical direction, and the like. The effective heat transfer coefficient K2 is, for example, 260 to 330 W/m/K. As shown in Fig. 3, the vertical equivalent heat transfer coefficient K2 of the germanium interposer 130 is greatly improved compared to the original heat transfer coefficient (about 140 W/m/K) of the germanium wafer, and the equivalent heat transfer coefficient K1 in the horizontal direction is increased. Although the original heat transfer coefficient of the germanium wafer is lower than that of the conventional thermal interface material (TIM), the common thermal interface material is indium, and its thermal conductivity is about 82~86 W/ m/K).

In the embodiment, as shown in FIG. 1 , the germanium interposer 130 is disposed between the wafer 120 and the heat sink 140 , and the germanium interposer 130 directly contacts the wafer 120 and the heat sink 140 , for example. In the embodiment, the material of the wafer 120 is, for example, tantalum, the heat sink 140 is made of, for example, copper, or the heat sink 140 includes, for example, a surface copper layer adjacent to the tantalum interposer 130. In this way, the equivalent thermal expansion coefficient of the germanium interposer 130 is between the thermal expansion coefficients of the copper and germanium wafers, and the germanium interposer 130 directly contacts the copper material and the germanium wafer of the heat sink 140, thereby effectively reducing the germanium wafer and the heat sink. The problem of stress reliability between the copper materials of 140 due to the large difference in thermal expansion coefficient. Moreover, the germanium interposer 130 has a good vertical equivalent heat transfer coefficient K2, and the germanium interposer 130 directly contacts the copper material and the germanium wafer of the heat sink 140, and can effectively transfer the heat generated by the wafer 120 to the heat sink 140 for discharge.

In an embodiment, as shown in FIG. 1 , the package structure 100 further includes a plurality of solder bumps 160 electrically connecting the wafer 120 and the substrate 110 . In an embodiment, as shown in FIG. 1 , the package structure 100 further includes a bottom seal 170 , and the bottom seal 170 covers the solder bumps 160 to increase the stress intensity between the wafer 120 and the solder bumps 160 . Improve reliability.

FIG. 4 illustrates a package structure of another embodiment of the disclosure. schematic diagram. Please refer to Figure 4. The difference between the embodiment and the embodiment of FIG. 1 is that the package structure 200 further includes a plurality of solder bumps 260 electrically connecting the wafer 120 and the copper layer 150 on the germanium interposer 130. In the embodiment, the package structure 200 further includes a bottom seal 270, and the bottom sealant 270 covers the solder bumps 260, which can increase the stress intensity between the wafer 120 and the solder bumps 260, thereby improving reliability. In this embodiment, the germanium interposer 130 does not have an electrical function. In other words, the germanium via 133 is not electrically connected to any of the components. The same components as those in the foregoing embodiments are denoted by the same reference numerals, and the related descriptions of the same components are referred to the foregoing, and are not described herein again.

The following is a method for fabricating a package structure 100 of the embodiments, which are for illustrative purposes only and are not intended to limit the invention. Those having ordinary knowledge may modify or change the steps as needed according to the actual implementation. Please refer to pictures 5A to 5H. 5A to 5H are schematic views showing a manufacturing method of a package structure according to an embodiment of the present invention.

Referring to FIG. 5A, an interposer 130 is formed. The interposer 130 has a plurality of crucibles 133, and the vias 133 are filled with a conductive material. In an embodiment, the electrically conductive material is, for example, copper metal. In an embodiment, the method of forming the germanium interposer 130 includes, for example, the steps of providing a germanium layer 131, forming a plurality of germanium vias 133 in the germanium layer 131, and filling the conductive material within the germanium vias 133.

In an embodiment, a layer of ruthenium dioxide is formed on the inner wall of the ruthenium perforation 133 (as shown in FIG. 1) before filling the conductive material in the ruthenium perforation 133. In the embodiment, after filling the conductive material inside the crucible through hole 133, the germanium interposer 130 can be thinned.

Referring to FIGS. 5B-5C, the heat sink 140 is formed on the buffer interposer 130. In an embodiment, the germanium interposer 130 has a first surface and a second surface, and a heat sink is formed on the first surface of the germanium interposer 130.

In one embodiment, the heat sink 140 is made of, for example, copper, and the manufacturing method of forming the heat sink 140 on the germanium interposer 130 includes the following steps: as shown in FIG. 5B, forming a third copper layer 510 in the middle On the first surface of layer 130. Next, as shown in Fig. 5C, a heat sink 140' made of copper is provided, and then the third copper layer 510 is bonded to the heat sink 140' made of copper by thermal compression at a hot pressing temperature of about less than 300 °C. The heat sink 140 is formed on the germanium interposer 130 via copper to copper bonding, and the third copper layer 510 is combined with the copper heat sink 140' to form a part of the heat sink 140 during the process. Therefore, there is no other film layer (for example, an adhesive layer) between the heat sink 140 and the germanium interposer 130, and the overall heat dissipation property can be improved.

In another embodiment, the heat sink 140 includes, for example, a surface copper layer (not shown), and the manufacturing method for forming the heat sink 140 on the germanium interposer 130 includes, for example, the following steps: forming as shown in FIG. 5B The third copper layer 510 is on the germanium interposer 130. Next, the third copper layer 510 is bonded to the surface copper layer of the heat sink 140 by heat pressing. The heat sink 140 is formed on the germanium interposer 130 via copper to copper thermocompression bonding, and the third copper layer 510 is combined in the process to form a part of the surface copper layer of the heat sink 140, so that the surface copper layer of the heat sink 140 There is no other film layer (for example, an adhesive layer) between the ruthenium interposer 130, and the overall heat dissipation property can be improved.

Referring to FIGS. 5D-5E, the wafer 120 is disposed on the germanium interposer 130. In an embodiment, the manufacturer of the wafer 120 on the germanium interposer 130 is disposed. The method includes, for example, the step of forming a second copper layer 520 on the wafer 120 and forming a first copper layer 530 on the second surface of the germanium interposer 130 as shown in FIG. 5D. Next, as shown in FIG. 5E, the second copper layer 520 on the wafer 120 and the first copper layer 530 on the germanium interposer 130 are bonded in a thermal compression manner. In an embodiment, after the hot pressing, the second copper layer 520 and the first copper layer 530 are combined to form a copper layer 150 between the germanium interposer 130 and the wafer 120. The wafer 120 is disposed on the germanium interposer 130 via copper-on-copper bonding such that the germanium interposer 130 and the wafer 120 have only the copper layer 150 without other film layers (eg, adhesive layers), while the copper has good The heat transfer characteristics improve the overall heat dissipation.

In one embodiment, referring to FIG. 4, before the first copper layer 530 on the interposer 130 and the second copper layer 520 of the wafer 120 are bonded by thermocompression, a plurality of first solder bumps 260 are further formed. On the wafer 120.

In one embodiment, the method for fabricating the wafer 120 on the germanium interposer 130 may further include the following steps: Referring to FIG. 4, a copper layer 150 is formed on the germanium interposer 130, and then a plurality of solder bumps are formed. 260 electrically connects the wafer 120 and the copper layer 150 on the germanium interposer 130.

Referring to FIGS. 5F-5H, the other side of the wafer 120 opposite to the second copper layer 520 is bonded to the substrate 110. In an embodiment, the method of bonding the wafer 120 to the substrate 110 includes, for example, the step of forming a plurality of second solder bumps 160 on the wafer 120 as shown in FIG. 5F. Next, as shown in FIG. 5G, a plurality of wafers 120 are disposed on a large heat sink 140, and the interposer 130 and the fins 140 are cut according to the respective wafers 120. The cut components include the wafer 120 and the interposer. 130 and heat dissipation Slice 140. Next, as shown in FIG. 5H, the wafer 120 and the substrate 110 are bonded by the second solder bumps 160 to complete the electrical connection between the wafer 120 and the substrate 110.

In the embodiment, the interposer 130 and the heat sink 140 are cut, for example, by laser. Since the ruthenium interposer 130 does not have an electrical function, even if the edge of the component after the dicing is slightly peeled or cracked, and the reliability of the entire package structure 100 after completion is not affected, the process can be relaxed. Requirements to improve yield.

In an embodiment, the bottom sealant 170 is further formed to cover the second solder bumps 160. Thus far, the package structure 100 as shown in Fig. 5H (Fig. 1) is formed.

In summary, although the disclosure has been disclosed in the above embodiments, it is not intended to limit the scope of the disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the scope of protection of this disclosure is subject to the definition of the scope of the appended claims.

100,200‧‧‧Package structure

110‧‧‧Substrate

120‧‧‧ wafer

130‧‧‧矽 Intermediary

131‧‧‧矽

133‧‧‧矽 piercing

135‧‧ 二 二 layer

140‧‧‧ Heat sink

150, 250‧‧‧ copper layer

160, 260‧‧‧ solder bumps

170, 270‧‧‧ bottom sealant

510‧‧‧ Third copper layer

520‧‧‧Second copper layer

530‧‧‧First copper layer

D _TSV ‧‧‧diameter

H‧‧‧ Height

K1, K2‧‧‧ equivalent heat transfer coefficient

P‧‧‧ spacing

S1~S3‧‧‧ Curve

T _SiO2 ‧‧‧ thickness

FIG. 1 is a schematic diagram of a package structure according to an embodiment of the disclosure.

Figure 2 is a graph showing the simulation results of the equivalent coefficient of thermal expansion of the interposer in one embodiment of the present disclosure.

FIG. 3 is a schematic diagram showing an equivalent thermal conductivity of the interposer of an embodiment of the present disclosure. fruit.

FIG. 4 is a schematic diagram showing a package structure of another embodiment of the disclosure.

5A to 5H are schematic views showing a manufacturing method of a package structure according to an embodiment of the present invention.

100‧‧‧Package structure

110‧‧‧Substrate

120‧‧‧ wafer

130‧‧‧矽 Intermediary

133‧‧‧矽 piercing

135‧‧ 二 二 layer

140‧‧‧ Heat sink

150‧‧‧ copper layer

160‧‧‧ solder bumps

170‧‧‧Bottom sealant

D _TSV ‧‧‧diameter

H‧‧‧ Height

P‧‧‧ spacing

T _SiO2 ‧‧‧ thickness

Claims (17)

A package structure includes: a substrate; a wafer disposed on the substrate; a silicon interposer formed on the wafer, the germanium interposer having a plurality of through silicon vias (TSVs), The tantalum perforations are filled with a conductive material; a copper layer is formed between the tantalum interposer and the wafer; and an integrated heat spreader (IHS) is formed on the tantalum interposer. The package structure of claim 1, wherein the conductive material is copper. The package structure according to claim 1, wherein the equivalent coefficient of thermal expansion of the tantalum interposer is 4 to 12 ppm/K. The package structure according to claim 1, wherein the 矽 interposer has an equivalent thermal conductivity of 150 to 330 W/m/K in the vertical direction. The package structure of claim 1, wherein the diameter of the turns is 0.5 to 20 microns. The package structure of claim 1, wherein the distance between the centers of any two adjacent ones of the turns is 1.25 to 250 microns. The package structure of claim 1, wherein the heat sink further comprises a surface copper layer adjacent to the germanium interposer. The package structure of claim 1, further comprising a plurality of solder bumps electrically connecting the wafer and the substrate. A method for fabricating a package structure, comprising: forming a buffer layer having a plurality of turns, the plurality of turns are filled with a conductive material, the germanium layer having a first surface and a second surface; Forming a heat sink on the first surface of the germanium interposer; forming a first copper layer on the second surface of the germanium interposer; forming a second copper layer on a wafer; Compressing the first copper layer on the germanium interposer and the second copper layer on the wafer; and bonding the other side of the wafer relative to the second copper layer to a substrate. The method of manufacturing a package structure according to claim 9, wherein the conductive material is copper. The method for manufacturing a package structure according to claim 9, wherein the step of forming the ruthenium interposer comprises: providing a ruthenium layer; forming the ruthenium perforations in the ruthenium layer; and filling the conductive material in the Within the perforation. The method for manufacturing a package structure according to claim 11, wherein before filling the conductive material in the punctured perforations, the method further comprises: forming a cerium oxide layer on the inner wall of the punctured perforations. The manufacturer of the package structure as described in claim 9 The method further includes forming a plurality of first solder bumps on the wafer before the first copper layer on the germanium interposer and the second copper layer on the wafer are bonded by heat pressing. The method of manufacturing a package structure according to claim 9, wherein the surface of the heat sink comprises a surface copper layer, and the step of forming the heat sink on the germanium interposer comprises: forming a third copper layer thereon And affixing the third copper layer to the surface copper layer of the heat sink by heat pressing. The method of manufacturing a package structure according to claim 14, wherein the heat sink is made of copper. The manufacturing method of the package structure of claim 9, further comprising: forming a plurality of second solder bumps to electrically connect the wafer and the substrate. The manufacturing method of the package structure of claim 16, further comprising: forming a bottom underfill covering the second solder bumps.