TWI821085B - Interposer manufacturing method for electronic components - Google Patents
Interposer manufacturing method for electronic components Download PDFInfo
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- TWI821085B TWI821085B TW111150083A TW111150083A TWI821085B TW I821085 B TWI821085 B TW I821085B TW 111150083 A TW111150083 A TW 111150083A TW 111150083 A TW111150083 A TW 111150083A TW I821085 B TWI821085 B TW I821085B
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- interposer
- mold
- upper mold
- conductive pillars
- pillar
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 claims abstract description 155
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- 238000007730 finishing process Methods 0.000 claims abstract description 16
- 239000007888 film coating Substances 0.000 claims abstract description 11
- 238000009501 film coating Methods 0.000 claims abstract description 11
- 239000003292 glue Substances 0.000 claims description 36
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- 239000002390 adhesive tape Substances 0.000 claims description 29
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- 230000001070 adhesive effect Effects 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 8
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910000640 Fe alloy Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- IYRDVAUFQZOLSB-UHFFFAOYSA-N copper iron Chemical compound [Fe].[Cu] IYRDVAUFQZOLSB-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
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- 239000010931 gold Substances 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
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- 229920000728 polyester Polymers 0.000 claims description 3
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- 238000005507 spraying Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 238000005429 filling process Methods 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 claims description 2
- 239000002253 acid Substances 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
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- 238000011144 upstream manufacturing Methods 0.000 abstract description 6
- 238000007731 hot pressing Methods 0.000 abstract description 5
- 238000003475 lamination Methods 0.000 abstract description 3
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- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
本發明乃是一種電子元件之中介層製造方法,其步驟:1.清洗製程;2.整排製程;3.暫固製程;4.灌注製程;5.移除製程;6.開模製程;7.整理製程;及8.上膜製程。本發明具有簡化後段半導體晶片與電路板熱壓合製造流程,對於於上中下游晶片設計具高度保密性及廠家容易整合,半導體晶片設計業者無需交付詳細設計線路圖給中介層製造商,僅需透露半導體晶片腳位之點陣圖給下游代工廠商,即可層疊出多層立體電路板,有效分工並簡化熱壓層合製程,提升業界生產製造的效率及上下游生產機密之有效保護。The present invention is a method for manufacturing interposers of electronic components. The steps include: 1. Cleaning process; 2. Arrangement process; 3. Temporary fixing process; 4. Infusion process; 5. Removal process; 6. Mold opening process; 7. Finishing process; and 8. Film coating process. The invention simplifies the back-stage semiconductor chip and circuit board hot-pressing manufacturing process. It has high confidentiality for upstream, mid-stream and downstream chip designs and is easy for manufacturers to integrate. Semiconductor chip designers do not need to deliver detailed design circuit diagrams to interposer manufacturers. They only need to By revealing the dot pattern of semiconductor chip pins to downstream OEMs, multi-layer three-dimensional circuit boards can be stacked, effectively dividing labor and simplifying the hot-pressing lamination process, improving the industry's manufacturing efficiency and effectively protecting upstream and downstream production secrets.
Description
本發明涉及用於電子元件之中介層(interposer)及其製造方法,尤其是應用於半導體晶片連接到電路板的中介層其包括基底膠及嵌入在其中的導電柱。The present invention relates to an interposer for electronic components and a manufacturing method thereof, in particular to an interposer used for connecting a semiconductor chip to a circuit board. The interposer includes a base glue and conductive pillars embedded therein.
電子工業快速發展,其半導體晶片的發展趨勢是微型化及高效能。半導體晶粒的端子間距變窄,而安裝在其上的半導體晶粒的印刷電路板可以具有細間距的程度受到限制。更進一步,開發使用於高密度互連的中介層來連接半導體晶粒和印刷電路板技術是未來發展方向。先前技術針對一種半導體裝置之中介層製造方法研究,如中華民國專利號TWI689996B所揭露,一種無晶圓基板之中介層製造方法,包括一提供載板、一形成緩衝層於載板上表面、一形成導電通道於緩衝層上、一形成絕緣隔離層於緩衝層上、一形成線路重佈層、一形成電極通道於線路重佈層表面、以及一使載板脫離之步驟,藉此,使能被解離的載板上預先形成導電通路後,並利用沉積或塗佈之技術形成包覆導電通路之絕緣隔離層,該中介層不具有晶圓、玻璃或有機層等基板,而能使導電通道更精準、更微細化,大幅提高其接腳的數量與密度,且無需透過化學機械研磨來薄化中介層,因此可完全省下研磨程序的工時,而提高中介層的生產速度,並使中介層不致因鑽孔、研磨加工造成結構的破壞、裂痕,可有效的提高良率,並降低製造成本。The electronics industry is developing rapidly, and the development trend of its semiconductor chips is miniaturization and high performance. The terminal pitch of the semiconductor die becomes narrower, and the extent to which a printed circuit board on which the semiconductor die is mounted can have a fine pitch is limited. Furthermore, the development of interposers for high-density interconnection to connect semiconductor dies and printed circuit board technology is a future development direction. Previous technology has focused on research on an interposer manufacturing method for semiconductor devices. For example, the Republic of China Patent No. TWI689996B discloses an interposer manufacturing method for a waferless substrate, including providing a carrier board, forming a buffer layer on the upper surface of the carrier board, and The steps of forming a conductive channel on the buffer layer, forming an insulating isolation layer on the buffer layer, forming a circuit redistribution layer, forming an electrode channel on the surface of the circuit redistribution layer, and detaching the carrier board, thereby enabling After the conductive paths are pre-formed on the dissociated carrier, deposition or coating techniques are used to form an insulating isolation layer covering the conductive paths. The interposer does not have a substrate such as a wafer, glass or organic layer, and can make the conductive paths More precise and finer, the number and density of its pins are greatly increased, and there is no need to thin the interposer through chemical mechanical polishing. Therefore, the man-hours of the grinding process can be completely saved, thereby increasing the production speed of the interposer and making the interposer The interposer layer will not cause structural damage or cracks due to drilling and grinding processes, which can effectively improve yield and reduce manufacturing costs.
先前技術針對一種用於在兩個相對側設置半導體晶片和外部端子的中介層及其製造方法研究,如中華民國專利號TW202008547A所揭露,其中介層包括第一重佈線結構、設置在第一重佈線結構上並電性耦合到第一重佈線結構的第二重佈線結構、以及插設在第一重佈線結構和第二重佈線結構之間的主動裝置。半導體晶片設置在第一重佈線結構上並與第一重佈線結構電性連接。第一重佈線結構的第一導電圖案的尺寸小於第二重佈線結構的第二導電圖案的尺寸並且外部端子設置在第二重佈線結構上並電性連接到第二重佈線結構。主動裝置的主動表面與第一重佈線結構接觸且主動裝置藉由第一重佈線結構電性耦合到第二重佈線結構。The prior art is directed to research on an interposer for disposing a semiconductor chip and external terminals on two opposite sides and a manufacturing method thereof, as disclosed in the Republic of China Patent No. TW202008547A, in which the interposer includes a first rewiring structure, a second rewiring structure on the wiring structure and electrically coupled to the first rewiring structure, and an active device interposed between the first rewiring structure and the second rewiring structure. The semiconductor chip is disposed on the first redistribution structure and is electrically connected to the first redistribution structure. The size of the first conductive pattern of the first redistribution structure is smaller than the size of the second conductive pattern of the second redistribution structure and the external terminal is provided on the second redistribution structure and is electrically connected to the second redistribution structure. The active surface of the active device is in contact with the first redistribution structure and the active device is electrically coupled to the second redistribution structure through the first redistribution structure.
先前技術針對中介層用基板及其製造方法研究,如中華民國專利號TW201442168A所揭露,提供有用於半導體裝置的高放熱化、高速對應化(良高頻特性化),半導體晶片等之裝載容易,而且可强固接合在配線基板或半導體晶片之中介層用基板及其製造方法。其在板狀的單晶矽母材上,以化學蒸鍍法或物理蒸鍍法形成由氧化鋁、鑽石、氮化鋁或氮化矽所成之絕緣層,接著,將上述單晶矽母材形成為單晶矽基板,獲得在單晶矽基板上具有熱傳導性的絕緣層的中介層用基板。Previous technology has focused on research on interposer substrates and manufacturing methods, as disclosed in the Republic of China Patent No. TW201442168A, which provides high exothermic and high-speed response (good high-frequency characterization) for semiconductor devices, and easy loading of semiconductor wafers, etc. Furthermore, the interposer substrate can be strongly bonded to a wiring substrate or a semiconductor wafer and a method of manufacturing the same. It forms an insulating layer made of aluminum oxide, diamond, aluminum nitride or silicon nitride on a plate-shaped single crystal silicon base material by chemical evaporation or physical evaporation. Then, the above single crystal silicon base material is The material is formed into a single crystal silicon substrate, and an interposer substrate having a thermally conductive insulating layer on the single crystal silicon substrate is obtained.
先前技術針對一種中介片其製造方法研究,如中華民國專利號TWI482250B所揭露,其包括一基底,具有一接觸墊結構以及一柱釘,可操作的連結至接觸墊結構。一焊球/錫,置於接觸墊結構之上且形成環繞著柱釘。中介片的製造方法包括:形成一接觸墊結構於一基底之一第一側上;固定一柱釘於該接觸墊結構上;形成一焊球/錫,圍繞著至少一部份的該柱釘。The prior art focuses on research on the manufacturing method of an interposer, as disclosed in the Republic of China Patent No. TWI482250B, which includes a base with a contact pad structure and a stud operatively connected to the contact pad structure. A solder ball/tin is placed over the contact pad structure and formed around the stud. The manufacturing method of the interposer includes: forming a contact pad structure on a first side of a substrate; fixing a stud on the contact pad structure; forming a solder ball/tin surrounding at least a portion of the stud .
應用於半導體晶片連接到電路板的媒介即中介層,其包括基底膠及嵌入在其中的導電柱,本發明為一種電子元件之中介層製造方法,其步驟:1.清洗製程,該清洗製程是將導電柱、上模具及下模具做其表面清洗,上模具為一平板,且該平板之表面設置有大於該導電柱直徑之複數個貫穿孔洞,下模具有一底面,該底面與四週之支撐邊條圍繞形成一容置空間;2.整排製程,該整排製程將其上模具覆蓋於下模具上,且上模具之其下表面接觸下模具之支撐邊條之頂部,再將其複數導電柱置於上模具之表面,並以磁吸、震盪或扎針方式將複數導電柱填落入上模具之複數貫穿孔洞中;3.暫固製程,該暫固製程是將貫穿孔洞中填滿導電柱之上模具,其上模具之上表面覆蓋一層暫固膠帶,該暫固膠帶上方受壓後將導電柱更進一步壓入上模具之貫穿孔洞中,使該導電柱一側抵固住下模具之底面;4.灌注製程,該灌注製程是將基底膠於上模具之灌注開口灌入其容置空間內,該基底膠能從底部填充固定其導電柱之周圍,再將基底膠加熱固化使其導電柱能固定站立於下模具之底面;5.移除製程,該移除製程是將暫固膠帶撕除於上模具之外表面;6.開模製程,該開模製程是將上模具與下模具分離開,其容置空間內取出中介層半成品;7.整理製程,該整理製程是將中介層半成品之表面以電漿清洗,以去除表面雜質,清洗之後即為中介層成品;及8.上膜製程,該上膜製程是將保護膜覆蓋於中介層成品之表面,進行下一階段製程或出貨流程。另一種電子元件之中介層製造方法,其步驟:1.清洗製程,該清洗製程是將導電柱、上模具及下模具做其表面清洗,上模具為一平板,且該平板之表面設置有大於該導電柱直徑之複數個貫穿孔洞,下模具有一底面,該底面與四週之支撐邊條圍繞形成一容置空間;2.整排製程,該整排製程將其上模具覆蓋於下模具上,且上模具之其下表面接觸下模具之支撐邊條之頂部,再將其複數導電柱置於上模具之表面,並以磁吸、震盪或扎針方式將複數導電柱填落入上模具之複數貫穿孔洞中;3.暫固製程,該暫固製程是將貫穿孔洞中填滿導電柱之上模具,其上模具之上表面覆蓋一層暫固膠帶,該暫固膠帶黏附導電柱後將上模具移除,更進一步將暫固膠帶上方受壓使暫固膠帶黏附導電柱壓入下模具,使該導電柱一側抵固住下模具之底面;4.灌注製程,該灌注製程是將基底膠於導電柱之間隙灌入其容置空間內,該基底膠能從底部填充固定其導電柱之周圍,再將基底膠加熱固化使其導電柱能固定站立於下模具之底面;5.移除製程,該移除製程是將暫固膠帶撕除於上模具之外表面;6.開模製程,該開模製程是將下模具移除,其容置空間內取出中介層半成品;7.整理製程,該整理製程是將中介層半成品之表面以電漿清洗,以去除表面雜質,清洗之後即為中介層成品;及8.上膜製程,該上膜製程是將保護膜覆蓋於中介層成品之表面,進行下一階段製程或出貨流程。其中,清洗製程是經使用至少一水洗、酸洗及溶劑沖洗。其中,導電柱為至少一圓柱形、圓釘形、方柱形、六角柱形、多角柱形及半圓柱形。其中,其導電柱為使用至少一銅柱、銅鐵合金、經表面處理銅柱、錫柱、鉛柱、金柱、白金柱及碳柱。其中,其導電柱之最外圍線徑介於0.01微米~1500微米,導電柱之高度介於0.1微米~10微米,導電柱之於20°C環境下熱導度(Thermal Conductivity, k值)介於200 W/mK~400 W/mK。其中,整排製程將其上模具與下模具之內壁表面噴塗薄層脫膜劑。其中,暫固製程中置換與前整排製程相異之下模具,以更改該下模具之面積及高度。其中,暫固製程所使用之暫固膠帶具有一膠黏層,該膠黏層使用至少一受熱解除膠黏型和受光解除膠黏型之膠黏劑。其中,灌注製程所使用之基底膠為高熱導度(Thermal Conductivity, 高k值)之散熱材料。其中,灌注製程所填充之基底膠充滿上模具與下模具之容置空間。其中,移除製程是使用加熱或照光方式移除暫固膠帶。更進一步,整理製程將中介層半成品表面進行至少一電漿、蝕刻和研磨,使該中介層半成品表面平整。其中,上膜製程所使用之保護膜為至少一聚烯氫類和聚酯類保護膜。本發明具有簡化後段半導體晶片與電路板熱壓合製造流程,對於於上中下游晶片設計具高度保密性及廠家容易整合,半導體晶片設計業者無需交付詳細設計線路圖給中介層製造商,僅需透露半導體晶片腳位之點陣圖給下游代工廠商,即可層疊出多層立體電路板,有效分工並簡化熱壓層合製程,提升業界生產製造的效率及上下游生產機密之有效保護。本發明之製造方法有別於過去習知技藝具差異化,其新穎、進步及實用效益無誤。有關本創作所採用之技術、手段及其功效,茲舉一較佳實施例並配合圖式詳細說明於後,相信本創作上述之目的、構造及特徵,當可由之得一深入而具體的瞭解。The interposer is the medium used to connect the semiconductor chip to the circuit board, which includes a base glue and a conductive pillar embedded therein. The present invention is an interposer manufacturing method for electronic components. The steps are: 1. Cleaning process. The cleaning process is Clean the surface of the conductive pillar, the upper mold and the lower mold. The upper mold is a flat plate, and the surface of the flat plate is provided with a plurality of through holes larger than the diameter of the conductive pillar. The lower mold has a bottom surface, and the bottom surface and the surrounding support edges The strips surround it to form an accommodation space; 2. A whole-row process in which the upper mold is covered on the lower mold, and the lower surface of the upper mold contacts the top of the supporting edge strips of the lower mold, and then multiple conductive The pillars are placed on the surface of the upper mold, and a plurality of conductive pillars are filled into a plurality of through-holes in the upper mold by magnetic attraction, vibration or needle pricking; 3. Temporary fixing process. This temporary fixing process is to fill the through-holes with conductive The upper mold of the pillar is covered with a layer of temporary adhesive tape on the upper surface. After the upper part of the temporary adhesive tape is pressed, the conductive pillar is further pressed into the through hole of the upper mold, so that one side of the conductive pillar is pressed against the lower mold. The bottom surface; 4. The pouring process. This pouring process is to pour the base glue into the filling opening of the upper mold into its accommodation space. The base glue can be filled from the bottom to fix the surrounding conductive pillars, and then the base glue is heated and solidified. The conductive pillars can be fixed on the bottom surface of the lower mold; 5. Removal process, the removal process is to tear off the temporary adhesive tape on the outer surface of the upper mold; 6. Mold opening process, the mold opening process is to remove the upper mold Separate from the lower mold, and take out the interposer semi-finished product from its accommodation space; 7. Finishing process, which is to clean the surface of the interposer semi-finished product with plasma to remove surface impurities. After cleaning, it is the finished interposer layer; and 8. Film coating process. This film coating process covers the surface of the interposer finished product with a protective film to proceed to the next stage of manufacturing or shipping process. Another interposer manufacturing method for electronic components has the following steps: 1. Cleaning process. The cleaning process is to clean the surfaces of the conductive pillars, upper mold and lower mold. The upper mold is a flat plate, and the surface of the flat plate is provided with a surface larger than There are a plurality of through holes with a diameter of the conductive pillar, and the lower mold has a bottom surface. The bottom surface and the surrounding support strips form a receiving space; 2. The whole row process, the whole row process covers the upper mold on the lower mold. And the lower surface of the upper mold is in contact with the top of the supporting edge of the lower mold, and then a plurality of conductive pillars are placed on the surface of the upper mold, and the plurality of conductive pillars are filled into the plurality of upper mold by magnetic attraction, vibration or needle pricking. In the through hole; 3. Temporary solidification process, this temporary solidification process is to fill the through hole with the mold on the conductive pillar, and the upper surface of the upper mold is covered with a layer of temporary adhesive tape. After the temporary adhesive tape adheres to the conductive pillar, the upper mold will be Remove, and further apply pressure on the top of the temporary adhesive tape to make the temporary adhesive tape adhere to the conductive pillar and press it into the lower mold, so that one side of the conductive pillar can resist the bottom surface of the lower mold; 4. Infusion process, this infusion process is to apply the base glue Pour the base glue into the gap between the conductive pillars and into its accommodating space. The base glue can be filled from the bottom to fix the surroundings of the conductive pillars. The base glue is then heated and solidified so that the conductive pillars can be fixed and standing on the bottom surface of the lower mold; 5. Remove Process, the removal process is to tear off the temporary tape on the outer surface of the upper mold; 6. Mold opening process, the mold opening process is to remove the lower mold, and take out the intermediate layer semi-finished product from its accommodation space; 7. Finishing The finishing process is to clean the surface of the interposer semi-finished product with plasma to remove surface impurities. After cleaning, the finished interposer is obtained; and 8. The coating process is to cover the finished interposer with a protective film. On the surface, proceed to the next stage of manufacturing or shipping process. Among them, the cleaning process uses at least one of water washing, pickling and solvent washing. Wherein, the conductive pillar is at least one cylindrical, round nail-shaped, square cylindrical, hexagonal cylindrical, polygonal cylindrical and semi-cylindrical shape. Among them, the conductive pillar uses at least one copper pillar, copper-iron alloy, surface-treated copper pillar, tin pillar, lead pillar, gold pillar, platinum pillar and carbon pillar. Among them, the outermost diameter of the conductive pillars ranges from 0.01 microns to 1500 microns, and the height of the conductive pillars ranges from 0.1 microns to 10 microns. The thermal conductivity (k value) of the conductive pillars is in the 20°C environment. At 200 W/mK~400 W/mK. Among them, the entire process involves spraying a thin layer of release agent on the inner wall surfaces of the upper mold and the lower mold. Among them, the lower mold that is different from the previous entire row of processes is replaced during the temporary fixing process to change the area and height of the lower mold. Among them, the temporary adhesive tape used in the temporary adhesive process has an adhesive layer, and the adhesive layer uses at least one heat-releasable adhesive type and a light-releasable adhesive type. Among them, the base glue used in the infusion process is a heat dissipation material with high thermal conductivity (high k value). Among them, the base glue filled in the pouring process fills the accommodation space of the upper mold and the lower mold. Among them, the removal process uses heat or light to remove the temporary adhesive tape. Furthermore, in the finishing process, the surface of the interposer semi-finished product is subjected to at least one step of plasma, etching and grinding to make the surface of the interposer semi-finished product smooth. Wherein, the protective film used in the film coating process is at least one polyolefin type and polyester type protective film. The invention simplifies the back-stage semiconductor chip and circuit board hot-pressing manufacturing process. It has high confidentiality for upstream, mid-stream and downstream chip designs and is easy for manufacturers to integrate. Semiconductor chip designers do not need to deliver detailed design circuit diagrams to interposer manufacturers. They only need to By revealing the dot pattern of semiconductor chip pins to downstream OEMs, multi-layer three-dimensional circuit boards can be stacked, effectively dividing labor and simplifying the hot-pressing lamination process, improving the industry's manufacturing efficiency and effectively protecting upstream and downstream production secrets. The manufacturing method of the present invention is different from the conventional techniques in that it is novel, progressive and has practical benefits. Regarding the technology, means and effects used in this creation, a preferred embodiment is given below and explained in detail with diagrams. I believe that the above-mentioned purpose, structure and characteristics of this creation can be obtained through this in-depth and specific understanding. .
以下係藉由特定的具體實施例說明本創作之實施方式,熟習此技藝之人士可由本說明書所揭示之內容輕易地了解本創作之其他優點與功效。本創作亦可藉由其他不同的具體實施例加以施行或應用,本說明書中的各項細節亦可基於不同觀點與應用,在不悖離本創作之精神下進行各種修飾與變更。The following describes the implementation of the present invention through specific embodiments. Those familiar with this art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. This invention can also be implemented or applied through other different specific embodiments, and various details in this description can also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of this invention.
首先敬請閱第1圖係顯示本創作電子元件之中介層製造方法之流程圖,並參閱第2~4圖說明本發明為一種電子元件之中介層製造方法,其步驟:1.清洗製程101,該清洗製程101是將導電柱901、上模具1001及下模具1101做其表面清洗,上模具1001為一平板,且該平板之表面設置有大於該導電柱901直徑之複數個貫穿孔洞10011,下模具1101有一底面11011,該底面11011與四週之支撐邊條11012圍繞形成一容置空間110121,如第2圖中空心箭頭所指的空間處;2.整排製程201,該整排製程201將其上模具1001覆蓋於下模具1101上,且上模具1001之其下表面接觸下模具1101之支撐邊條11012之頂部,再將其複數導電柱901置於上模具1001之表面,並以磁吸、震盪或扎針方式將複數導電柱901填落入上模具1001之複數貫穿孔洞10011中;3.暫固製程301,該暫固製程301是將貫穿孔洞10011中填滿導電柱901之上模具1001,其上模具1001之上表面覆蓋一層暫固膠帶1201,該暫固膠帶1201上方受壓後將導電柱901更進一步壓入上模具1001之貫穿孔洞10011中,使該導電柱901一側抵固住下模具1101之底面11011;或另一暫固製程301是將貫穿孔洞10011中填滿導電柱901之上模具1001,其上模具1001之上表面覆蓋一層暫固膠帶1201,該暫固膠帶1201黏附導電柱901後將上模具1001移除,更進一步將暫固膠帶1201上方受壓使暫固膠帶1201黏附導電柱901壓入下模具1101,使該導電柱901一側抵固住下模具1101之底面11011;4.灌注製程401,該灌注製程401是將基底膠1301於上模具1001之灌注開口10013或導電柱901之間隙灌入其容置空間110121內,該基底膠1301能從底部填充固定其導電柱901之周圍,再將基底膠1301加熱固化使其導電柱901能固定站立於下模具1101之底面11011;5.移除製程501,該移除製程501是將暫固膠帶1201撕除於上模具1001之外表面10012;6.開模製程601,該開模製程601是將上模具1001與下模具1101分離開,其容置空間110121內取出中介層半成品1401;或另一開模製程601是將下模具1101移除,其容置空間110121內取出中介層半成品1401;7.整理製程701,該整理製程701是將中介層半成品1401之表面以電漿清洗,以去除表面雜質,清洗之後即為中介層成品1501;及8.上膜製程801,該上膜製程801是將保護膜1601覆蓋於中介層成品1501之表面,進行下一階段製程或出貨流程。First, please read Figure 1, which is a flow chart showing the interposer manufacturing method of the electronic component of the present invention, and refer to Figures 2 to 4 to illustrate that the present invention is an interposer manufacturing method of electronic components. The steps are: 1.
其中,清洗製程101是經使用至少一水洗、酸洗及溶劑沖洗。其中,導電柱901為至少一圓柱形、圓釘形、方柱形、六角柱形、多角柱形及半圓柱形。其中,其導電柱901為使用至少一銅柱、銅鐵合金、經表面處理銅柱、錫柱、鉛柱、金柱、白金柱及碳柱。其中,整排製程201將其上模具1001與下模具1101之內壁表面噴塗薄層脫膜劑。其中,暫固製程301中置換與前整排製程201相異之下模具1101,以更改該下模具1101之面積及高度。其中,暫固製程301所使用之暫固膠帶1201具有一膠黏層,該膠黏層使用至少一受熱解除膠黏型和受光解除膠黏型之膠黏劑。其中,灌注製程401所使用之基底膠1301為高熱導度(Thermal Conductivity, 高k值)之散熱材料。其中,灌注製程401所填充之基底膠1301充滿上模具1001與下模具1101之容置空間110121。其中,移除製程501是使用加熱或照光方式移除暫固膠帶1201。更進一步,整理製程701將中介層半成品1401表面進行至少一電漿、蝕刻和研磨,使該中介層半成品1401表面平整。其中,上膜製程801所使用之保護膜1601為至少一聚烯氫類和聚酯類保護膜1601。Among them, the
第2圖係顯示本創作電子元件之中介層製造方法中上模具1001、下模具1101與導電柱901之分解圖,進一步解釋其導電柱901為具有導電功能之柱狀物質,導電柱901為至少一圓柱形、圓釘形、方柱形、六角柱形、多角柱形及半圓柱形。其導電柱901為使用至少一銅柱、銅鐵合金、經表面處理銅柱、錫柱、鉛柱、金柱、白金柱及碳柱。其中,其導電柱901之最外圍線徑介於0.01微米~1500微米,導電柱901之高度介於0.1微米~10微米,導電柱901之於20°C環境下熱導度(Thermal Conductivity, k值)介於200 W/mK~400 W/mK。其上模具1001為一平板之結構,且該平板之表面設置有大於該導電柱901直徑之複數個貫穿孔洞10011,該貫穿孔洞10011提供導電柱901從上模具1001之外表面10012進入其上模具1001與下模具1101組成的容置空間110121內,並具有支撐導電柱901站立之作用;上模具1001之一側設置有一灌注開口10013,提供基底膠1301灌入其上模具1001與下模具1101組成的容置空間110121內。下模具1101有一底面11011,該底面11011與四週之支撐邊條11012圍繞形成一容置空間110121。當上模具1001覆蓋於下模具1101上,且上模具1001之其下表面部分接觸下模具1101之支撐邊條11012之頂部。Figure 2 shows an exploded view of the
為使審查委員更進一步了解本創作實際製造之情境,如第3圖係顯示本創作電子元件之中介層製造方法之示意圖,並參閱第1、2圖其說明經清洗製程101將導電柱901、上模具1001及下模具1101做其表面清洗後,繼續如第3圖所表示,其整排製程201是將其上模具1001之下表面與下模具1101之底部處,即內壁表面噴塗薄層脫膜劑,上模具1001覆蓋於下模具1101上,且上模具1001之其下表面接觸下模具1101之支撐邊條11012之頂部,下模具1101有一底面11011,該底面11011與四週之支撐邊條11012圍繞形成一容置空間110121,再將其複數導電柱901置於上模具1001之表面,並以磁吸、震盪或扎針方式將複數導電柱901填落入上模具1001之複數貫穿孔洞10011中。接續整排製程201後其暫固製程301是將貫穿孔洞10011中填滿導電柱901之上模具1001,其上模具1001之上表面覆蓋一層暫固膠帶1201,該暫固膠帶1201上方受壓後將導電柱901更進一步壓入上模具1001之貫穿孔洞10011中,使該導電柱901一側抵固住下模具1101之底面11011。接續整排製程201後其灌注製程401是將基底膠1301透由注膠器13011於上模具1001之灌注開口10013灌入其容置空間110121內,該基底膠1301能從底部填充固定其導電柱901之周圍,再將基底膠1301加熱固化使其導電柱901能固定站立於下模具1101之底面11011。接續灌注製程401後其移除製程501是將上模具1001之外表面10012上之暫固膠帶1201撕除。接續移除製程501後其開模製程601是將上模具1001與下模具1101分離開,其從容置空間110121內取出中介層半成品1401。接續開模製程601其整理製程701是將中介層半成品1401之表面以電漿清洗,以去除表面雜質,清洗之後即為中介層成品1501,示意圖中顯示其更進一步中將介層半成品表面進行至少一電漿、蝕刻和研磨,使該中介層半成品1401表面平整。接續整理製程701其上膜製程801是將保護膜1601覆蓋於中介層成品1501之表面,以保護中介層成品1501進行下一階段製程或出貨流程。In order to enable the review committee to further understand the actual manufacturing situation of this invention, Figure 3 is a schematic diagram showing the interposer manufacturing method of the electronic component of this invention, and refer to Figures 1 and 2 which illustrate the
第4圖係顯示本創作另一電子元件之中介層製造方法之示意圖,並參閱第1、2圖其說明經清洗製程101將導電柱901、上模具1001及下模具1101做其表面清洗後,繼續如第4圖所表示,其整排製程201是將其上模具1001覆蓋於下模具1101上,且上模具1001之其下表面接觸下模具1101之支撐邊條11012之頂部,下模具1101有一底面11011,該底面11011與四週之支撐邊條11012圍繞形成一容置空間110121,再將其複數導電柱901置於上模具1001之表面,並以磁吸、震盪或扎針方式將複數導電柱901填落入上模具1001之複數貫穿孔洞10011中。接續整排製程201後其暫固製程301是將貫穿孔洞10011中填滿導電柱901之上模具1001,其上模具1001之上表面覆蓋一層暫固膠帶1201,該暫固膠帶1201黏附導電柱901後將上模具1001移除,更進一步將暫固膠帶1201上方受壓使暫固膠帶1201黏附導電柱901壓入下模具1101,使該導電柱901一側抵固住下模具1101之底面11011。接續整排製程201後其灌注製程401是將基底膠1301透由注膠器13011於導電柱901之間隙灌入其容置空間110121內,該基底膠1301能從底部填充固定其導電柱901之周圍,再將基底膠1301加熱固化使其導電柱901能固定站立於下模具1101之底面11011。接續灌注製程401後其移除製程501是將上模具1001之外表面10012上之暫固膠帶1201撕除。接續移除製程501後其開模製程601是將下模具1101移除,其從容置空間110121內取出中介層半成品1401。接續開模製程601其整理製程701是將中介層半成品1401之表面以電漿清洗,以去除表面雜質,清洗之後即為中介層成品1501,示意圖中顯示其更進一步中將介層半成品表面進行至少一電漿、蝕刻和研磨,使該中介層半成品1401表面平整。接續整理製程701其上膜製程801是將保護膜1601覆蓋於中介層成品1501之表面,以保護中介層成品1501進行下一階段製程或出貨流程。本方法於暫固製程301中移除上模具1001,省去上模具1001之與下模具1101噴塗薄層脫膜劑造成導電柱901受脫膜劑污染之缺點。Figure 4 is a schematic diagram showing the interposer manufacturing method of another electronic component of the present invention. Refer to Figures 1 and 2. It illustrates that after the surface cleaning of the
以上製程說明為中介層之製造方法說明,後續將本發明之中介層熱壓於半導體晶片與電路板之間,透過半導體晶片的接腳與本發明中介層之導電柱901相互接合,其導電柱901之另一端與電路板之電路接合,即可形成一通導電路,多層堆疊其晶片/中介層/電路板即可型層立體電路,半導體晶片以導電柱901通導方式堆疊在,以及數群半導體晶片利用中介層相互連結,然後這些全部都在單一電子元件封裝中,半導體晶片與中介層的厚度介於0.2mm~0.7mm,整個電子元件封裝體積可以縮小,達到微小化電子元件之效果。The above process description is a description of the manufacturing method of the interposer. Subsequently, the interposer of the present invention is hot-pressed between the semiconductor chip and the circuit board, and the
本發明乃是一種電子元件之中介層製造方法其具有簡化後段半導體晶片與電路板熱壓合製造流程,對於於上中下游晶片設計具高度保密性及廠家容易整合,半導體晶片設計業者無需交付詳細設計線路圖給中介層製造商,僅需透露半導體晶片腳位之點陣圖給下游代工廠商,即可層疊出多層立體電路板,有效分工並簡化熱壓層合製程,提升業界生產製造的效率及上下游生產機密之有效保護。本發明製造方法特徵,有別於過去習知技藝具差異化,其新穎、進步及實用效益無誤。故可有效改進習知缺失,使用上有相當大之實用性。The present invention is an interposer manufacturing method for electronic components. It simplifies the manufacturing process of hot pressing of semiconductor wafers and circuit boards in the back-end. It has high confidentiality for upstream, mid-stream and downstream wafer designs and is easy for manufacturers to integrate. Semiconductor wafer designers do not need to deliver detailed information. Design the circuit diagram to the interposer manufacturer, and only need to disclose the lattice pattern of the semiconductor chip pins to the downstream foundry to stack up a multi-layer three-dimensional circuit board. This effectively divides labor and simplifies the hot-press lamination process, improving the manufacturing quality of the industry. Efficiency and effective protection of upstream and downstream production secrets. The characteristics of the manufacturing method of the present invention are different from the conventional techniques in the past, and its novelty, progress and practical benefits are unmistakable. Therefore, it can effectively improve the lack of common knowledge and has considerable practicality in use.
綜觀上述,本創作實施例所揭露之具體構造,確實能提供電子元件之中介層製造之應用,以其整體製造方法及結構而言,既未曾見諸於同類產品中,申請前亦未見公開,誠已符合專利法之法定要件,爰依法提出發明專利申請。In summary, the specific structure disclosed in the embodiments of this invention can indeed provide applications for interposer manufacturing of electronic components. In terms of its overall manufacturing method and structure, it has not been seen in similar products, nor has it been disclosed before the application. , has since complied with the statutory requirements of the Patent Law, and has filed an invention patent application in accordance with the law.
惟以上所述者,僅為本創作之一較佳實施例而已,當不能以此限定本創作實施之範圍,即大凡依本創作申請專利範圍及創作說明書內容所作之等效變化與修飾,皆應仍屬本創作專利涵蓋之範圍內。However, the above is only one of the preferred embodiments of this invention, and it should not be used to limit the scope of the implementation of this invention. That is, all equivalent changes and modifications made based on the patent scope of this invention and the content of the invention description are all It should still be within the scope of this creative patent.
101:清洗製程 201:整排製程 301:暫固製程 401:灌注製程 501:移除製程 601:開模製程 701:整理製程 801:上膜製程 901:導電柱 1001:上模具 10011:貫穿孔洞 10012:外表面 10013:灌注開口 1101:下模具 11011:底面 11012:支撐邊條 110121:容置空間 1201:暫固膠帶 1301:基底膠 13011:注膠器 1401:中介層半成品 1501:中介層成品 1601:保護膜101: Cleaning process 201: Whole row process 301: Temporary solidification process 401: Infusion process 501:Remove process 601: Mold opening process 701: Finishing process 801: Film coating process 901:Conductive pillar 1001: Upper mold 10011:Through holes 10012:Outer surface 10013:Pouring opening 1101: Lower the mold 11011: Bottom 11012: Support side strip 110121: Accommodation space 1201: Temporary fixing tape 1301: Base glue 13011: Glue injection device 1401: Interposer semi-finished product 1501: Finished interposer layer 1601:Protective film
第1圖係顯示本創作電子元件之中介層製造方法之流程圖。 第2圖係顯示本創作電子元件之中介層製造方法中上模具、下模具與導電柱之分解圖。 第3圖係顯示本創作電子元件之中介層製造方法之示意圖。 第4圖係顯示本創作另一電子元件之中介層製造方法之示意圖。 Figure 1 is a flow chart showing the interposer manufacturing method of the electronic component of the present invention. Figure 2 shows an exploded view of the upper mold, lower mold and conductive pillars in the interposer manufacturing method of the electronic component of this invention. Figure 3 is a schematic diagram showing the interposer manufacturing method of the electronic component of this invention. Figure 4 is a schematic diagram showing an interposer manufacturing method of another electronic component of the present invention.
101:清洗製程 101: Cleaning process
201:整排製程 201: Whole row process
301:暫固製程 301: Temporary solidification process
401:灌注製程 401: Infusion process
501:移除製程 501:Remove process
601:開模製程 601: Mold opening process
701:整理製程 701: Finishing process
801:上膜製程 801: Film coating process
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TW201445654A (en) * | 2013-03-14 | 2014-12-01 | Invensas Corp | Low cost interposer and method of fabrication |
TW201539697A (en) * | 2013-05-23 | 2015-10-16 | Ind Tech Res Inst | Semiconductor device and manufacturing method thereof |
TWI689996B (en) * | 2016-04-28 | 2020-04-01 | 李志雄 | Method for manufacturing interlayer of semiconductor device |
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TW200711813A (en) * | 2005-09-05 | 2007-04-01 | Hon Hai Prec Ind Co Ltd | Mold and process for producing the mold |
TW201445654A (en) * | 2013-03-14 | 2014-12-01 | Invensas Corp | Low cost interposer and method of fabrication |
TW201539697A (en) * | 2013-05-23 | 2015-10-16 | Ind Tech Res Inst | Semiconductor device and manufacturing method thereof |
TWI689996B (en) * | 2016-04-28 | 2020-04-01 | 李志雄 | Method for manufacturing interlayer of semiconductor device |
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