WO2015099431A1 - Align socket unit of semiconductor device and semiconductor device checking apparatus comprising same - Google Patents

Align socket unit of semiconductor device and semiconductor device checking apparatus comprising same Download PDF

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Publication number
WO2015099431A1
WO2015099431A1 PCT/KR2014/012768 KR2014012768W WO2015099431A1 WO 2015099431 A1 WO2015099431 A1 WO 2015099431A1 KR 2014012768 W KR2014012768 W KR 2014012768W WO 2015099431 A1 WO2015099431 A1 WO 2015099431A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
guide
socket unit
alignment socket
insertion body
Prior art date
Application number
PCT/KR2014/012768
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French (fr)
Korean (ko)
Inventor
김기민
윤용희
Original Assignee
주식회사 아이에스시
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Publication of WO2015099431A1 publication Critical patent/WO2015099431A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433Sockets for IC's or transistors
    • G01R1/0441Details
    • G01R1/0466Details concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2855Environmental, reliability or burn-in testing
    • G01R31/286External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863Contacting devices, e.g. sockets, burn-in boards or mounting fixtures

Definitions

  • the present invention is for conducting a conductive test for a memory or non-memory semiconductor device, and more particularly, a stable alignment of the probe pin when conducting a conductive test for a semiconductor device having a relatively large number of ball terminals.
  • the present invention relates to a semiconductor device alignment socket unit and a semiconductor device inspection apparatus including the same.
  • semiconductor devices such as ICs are inspected for defects by inspecting electrical characteristics during the manufacturing process, and the electrical characteristics inspection of the semiconductor devices includes a contact point (bump) and a printed circuit board (PCB) of the semiconductor device. Is performed through a probe pin interposed between the contacts (pads) of the test board.
  • a contact point bump
  • PCB printed circuit board
  • the electrical characteristic inspection of the semiconductor device is performed in the state where the semiconductor device is inserted into the inspected carrier.
  • the inspection of the conventional semiconductor device is performed by the electrical contact between the ball terminal of the semiconductor device mounted on the object carrier and the probe pin supported on the socket assembly.
  • very small ball terminals and probe pins are arranged at a narrow pitch, so highly accurate alignment is required during the test.
  • the alignment of the ball terminals and the probe pins is necessary to align the alignment holes of the specimen carrier and the socket guide. This is achieved through the alignment of the pins.
  • the alignment pins and the alignment holes are increased in margin through repeated coupling and disconnection. As a result, this increase in margin causes a problem of mismatching or offset of the ball terminal and the probe pin.
  • This problem can cause damage to expensive semiconductor devices due to collisions between semiconductor devices and probe pins when conducting conductivity tests on thousands of semiconductor devices, or the ball terminals of broken semiconductor devices may remain in the equipment. In this case, a problem arises in that replacement or repair should be performed while the conductivity test is stopped.
  • the present invention has been made to solve the above-mentioned problems, and more specifically, a semiconductor device alignment socket unit having improved accuracy according to contact by precisely matching the mutual alignment of the ball terminal and the probe pin of the semiconductor device. And a semiconductor device inspection apparatus.
  • the semiconductor device alignment socket unit of the present invention for achieving the above object, the insertion body having an opening for receiving the semiconductor device for testing the packaged semiconductor device; A guide sheet for aligning the insertion position of the ball terminal provided on the bottom surface of the insertion body and provided in the semiconductor device; A base part including a plurality of probe pins disposed on a lower surface of the insertion body and facing each other with the ball terminal; And a guide pad in close contact with a lower surface of the guide sheet and having a guide hole partially inserted at an upper end of the probe pin to guide the position of the probe pin to a constant position at all times.
  • the semiconductor device may have the ball terminal disposed between at least 500 balls and 2000 balls.
  • the guide sheet may include a conductive pad including conductive particles in a silicon rubber; A first guide sheet positioned in close contact with an upper surface of the conductive pad and having a first guide hole formed at a position corresponding to the ball terminal; It may include a second guide sheet which is positioned in close contact with the lower surface of the conductive pad and has a second guide hole in which an end portion of the probe pin is partially inserted.
  • the conductive pad may be a polyamide film or any one of FR4 or FR5 or XPC.
  • the guide pad may have a thickness relatively thicker than the thickness of the guide sheet.
  • the guide pad may be an insulating material having electrical insulation.
  • the guide pad may be a flexible printed circuit board (FPCB).
  • FPCB flexible printed circuit board
  • the insertion body includes a coupling protrusion projecting downward toward an upper surface of the base portion, and the base portion is formed with an insertion hole opened at a position corresponding to the coupling protrusion so that the coupling protrusion is formed. The state coupled to the insertion hole may be maintained.
  • the base part may include a guide member positioned on an inner side of the semiconductor device to face each other and in contact with an outer side of the insertion body to maintain a fixed position.
  • the guide member may be any one of rubber, silicon, and plastic.
  • the insertion body may include an insertion groove formed at a position corresponding to the guide member and into which the guide member is inserted.
  • the semiconductor device inspection apparatus of the present invention for achieving the above object is aligned with the insertion position of the insertion main body having an opening for accommodating the semiconductor device, and the insertion position of the ball terminal provided inside the insertion body and provided in the semiconductor device.
  • a base portion including a guide sheet for mounting, a lower surface of the insertion body and a plurality of probe pins disposed at positions facing the ball terminal, and a top portion of the probe pin in close contact with the lower surface of the guide sheet.
  • An alignment socket unit having a guide pad inserted therein to guide the position of the probe pin to the home position at all times;
  • a loading unit in which a plurality of alignment socket units are installed;
  • a pusher installed at a position facing the upper portion of the alignment socket unit and pressing the plurality of semiconductor devices moved to the upper portion of the alignment socket unit to the inside of the insertion body;
  • a controller for controlling the presence or absence of abnormalities of the plurality of semiconductor devices during the conduction test on the semiconductor device pressurized by the pusher at a predetermined pressure.
  • the semiconductor device alignment socket unit according to the present invention can improve workability and work efficiency through a stable conductivity test of a plurality of semiconductor devices, and conduct a conductivity test of a semiconductor device having a relatively large number of ball terminals. There is an advantage that can be easily carried out.
  • the alignment socket unit In the semiconductor device alignment socket unit according to the present invention, only a plurality of semiconductor devices are transferred, and the alignment socket unit can perform work in a state where it is located in the loading apparatus, and thus, workability is remarkably improved.
  • the semiconductor device alignment socket unit according to the present invention has an advantage of conducting a conductive test on a semiconductor device while stably aligning an upper end of a probe pin so as to exactly match the alignment of the plurality of ball terminals.
  • FIG. 1 is an exploded perspective view of a semiconductor device alignment socket unit according to an exemplary embodiment of the present inventive concept.
  • FIG. 2 is a plan view of a semiconductor device alignment socket unit according to an exemplary embodiment of the present inventive concept.
  • FIG 3 is an exploded cross-sectional perspective view of a semiconductor device alignment socket unit according to an exemplary embodiment of the present inventive concept.
  • FIG. 4 is a front view briefly showing a semiconductor device inspection apparatus according to an embodiment of the present invention.
  • 5 to 6 are diagrams illustrating a use state of a semiconductor device alignment socket unit according to an embodiment of the present invention.
  • the alignment socket unit 1 includes an insertion body 100 having an opening 110 in which the semiconductor device 10 is accommodated for testing the packaged semiconductor device 10, and It is installed on the lower surface of the insertion body 100 and the guide sheet 200 for alignment with the insertion position of the ball terminal 12 of the semiconductor device 10, and the lower surface of the insertion body 100 is seated and the ball
  • a base portion 300 including a plurality of probe pins 302 disposed at positions facing the terminal 12;
  • a guide pad 400 that is in close contact with the bottom surface of the guide sheet 200 and partially inserts an upper end of the probe pin 302 to guide the position of the probe pin 302 at a constant position at all times.
  • the alignment socket unit 1 is for conducting a conductive test on the semiconductor device 10 used in a CPU in which the ball terminals 12 are relatively numbered from 500 balls to 2000 balls. For example, it is used to conduct a conductive test on a relatively large semiconductor device 10 such as a CPU installed in a PC.
  • the insert body 100 includes an inclined surface 120 in which the opening 110 is opened upward to allow the semiconductor device 10 to be stably inserted, and the inside of the opening 110 is inclined downward. do.
  • the inclined surface 120 is formed to stably insert the semiconductor device 10 toward the opening 110.
  • the insertion body 100 includes an insertion groove 104 formed at a position corresponding to the guide member 310 to be described later and into which the guide member 310 is inserted, and the guide member 310 and the insertion groove 104. A detailed description thereof will be given below with reference to the base unit 300.
  • the guide sheet 200 includes a conductive pad 210 positioned below the insertion body 100 and first and second guide sheets 220 and 230.
  • the conductive pad 210 includes a conductive portion 211 and an insulating portion 212.
  • the conductive portion 211 is formed in a shape in which a plurality of conductive particles are arranged in the thickness direction in the insulating elastic material, the conductive portion 211 is in contact with the ball terminal 12 to energize the probe pin 302 while the semiconductor The conduction state of the plurality of ball terminals 12 installed in the device 10 can be checked.
  • the conductive portion 211 is the conductive particles are positioned at a position corresponding to the first, second guide holes (222, 232) to be described later. Specifically, when the conductive portion 211 is disposed at positions corresponding to the first and second guide holes 222 and 232, and the ball terminal 12 of the semiconductor device 10 presses the conductive portion to a predetermined pressure, The ball terminal 12 is energized to the probe pin 302 through the conductive portion.
  • the insulating elastic material constituting the conductive part 211 is preferably made of silicone rubber, but is not limited thereto. Any rubber material having good elasticity may be used.
  • the insulating part 212 is integrally coupled with the conductive part 211 around the plurality of conductive parts 211 to insulate while supporting the conductive part 211. Electrical insulation is enabled only in the thickness direction by the insulation part 212.
  • the insulating part 212 may be made of the same material as the insulating elastic material constituting the conductive part 211, but is not limited thereto. Any one of a polyamide film, FR4, FR5, and XPC may be used.
  • the first guide sheet 220 is positioned in close contact with the upper surface of the conductive pad 210 and the first guide hole 222 is formed at a position corresponding to the ball terminal 12.
  • the first guide hole 222 is opened in the entire region of the first guide sheet 220, and in the drawing according to the present embodiment, the first guide hole 222 is not shown as a whole, but is partially shown only at the central position.
  • the first guide hole 222 is not shown as a whole, but is partially shown only at the central position.
  • the first guide hole 222 is disposed at a distance of 0.4 mm from the center of the neighboring first guide hole, and at least 1000 ball terminals 12 are simultaneously disposed in the first guide hole 222 and the second guide hole.
  • Probe pins 302 positioned at positions corresponding to the ball terminals 12 via 232 are aligned to conduct conductivity tests on the semiconductor device 10.
  • the second guide sheet 230 is positioned in close contact with the bottom surface of the conductive pad 210, and a second guide hole 232 is formed to partially insert the end of the probe pin 302.
  • the second guide hole 232 is formed to align the plurality of probe pins 302 differently from the first guide hole 222 described above, and the top of the probe pins 302 is partially inserted. maintain.
  • the first and second guide holes 222 and 232 are opened at the same position, and in this embodiment, a plurality of probe pins 302 are provided by installing a guide pad 400 for more accurate alignment of the probe pins 302. Conduct an alignment on
  • the guide pad 400 is made of a thickness relatively thicker than the thickness of the guide sheet 200 described above, the top of the probe pin 302 is more stably coupled.
  • FPCB is used for the guide pad 400. Since the FPCB is excellent in electrical insulation and strong in heat resistance, bending resistance, and chemical resistance, a predetermined external force is applied by the semiconductor device 10 in the guide sheet 200. Edo stably supported and is maintained in a stable state without being separated even when a plurality of probe pins 302 are coupled.
  • the guide pad 400 has a portion of the upper end of the probe pin 302 inserted into the guide hole 410.
  • the number of the ball terminals 12 is 1000 balls or more
  • an upper end of the probe pins 302 may be formed in the guide hole 410.
  • the conductive pins are electrically aligned with the probe pins 302 through the conductive particles aligned without dislocations and distributed on the conductive pads 210.
  • the probe pin 302 is a well-known configuration, detailed description thereof will be omitted.
  • the base part 300 has an insertion hole 301 formed at a position corresponding to the coupling protrusion 130 protruding from the lower side of the insertion body 100 to insert the body 100. Primary coupling is performed, and the guide member 310 is brought into contact with the outside of the insertion body 100 to maintain a fixed position.
  • the guide member 310 may be any one of rubber, silicon, or plastic is selectively used.
  • the guide member 310 is disposed to face each other on the left and right sides of the base part 300 on the basis of the drawing, and is inserted into the insertion groove 104. Is inserted.
  • the insertion groove 104 is formed in a shape corresponding to the shape of the guide member 310 when the insertion body 100 is coupled to the inside of the base portion 300, the guide member 310 is easily inserted groove 104 To be inserted).
  • the guide member 310 is protruded in the form of a spherical shape toward the outside of the base portion 300, it is noted that it is possible to change to another shape that is coupled to the insertion groove 104 and the male and female form.
  • the base portion 300 includes a first base portion 320 to which the lower end of the probe pin 302 is coupled, and a second base portion 330 in close contact with the upper portion of the first base portion 320.
  • the first and second base parts 320 and 330 stably support the lower portion of the probe pin 302.
  • socket unit 1 is the same as in FIG.
  • the semiconductor device inspecting apparatus 1a relates to an inspecting apparatus for testing a semiconductor device using the above-described alignment socket unit 1, and the semiconductor device 10 is accommodated.
  • a guide sheet for alignment with an insertion position of the insertion body 100 having an opening 110 formed therein, and an insertion position of the ball terminal 12 provided inside the insertion body 100 and provided in the semiconductor device 10 200 and a base portion 300 including a plurality of probe pins 302 disposed at positions where the lower surface of the insertion body 100 faces the ball terminal 12 and faces each other, and the guide sheet (
  • the guide hole 410 is closely attached to the lower surface of the 200, and the upper end of the probe pin 302 is partially inserted to guide the position of the probe pin 302 to a constant position when a test is performed on the semiconductor device 10.
  • Formed Alignment socket unit 1 having an id pad 400, a loading unit 2 having a plurality of alignment socket units 1 installed thereon, and a position facing the upper portion of the alignment socket unit 1
  • a pusher (3) installed and pressing the plurality of semiconductor devices (10) moved to the upper portion of the alignment socket unit (1) to the inside of the insertion body (100);
  • a controller 4 for controlling the presence or absence of abnormalities of the plurality of semiconductor devices 10 during the conducting inspection of the semiconductor device 10 pressed by the pusher 3 at a predetermined pressure.
  • the loading unit 2 has 30 to 50 alignment socket units 1 installed therein to conduct conductivity tests of the plurality of semiconductor devices 10. It can be carried out at one time, and in this case, the operator can conduct the conductivity test on the plurality of semiconductor devices 10 more conveniently and quickly, thereby improving workability and having an abnormality for the plurality of semiconductor devices at a faster time. You can check.
  • the pusher 3 is composed of a hydraulic cylinder and a piston and is installed to simultaneously press all of the semiconductor device 10 at a predetermined pressure toward the inside of the insertion body 100, and the pressing force of the pusher 3 is pneumatically. It is operated so that the operator can easily set it to any pressure.
  • the controller 4 determines whether a conductive state input through the plurality of semiconductor devices 10 inserted into the plurality of alignment socket units 1 is stable, and outputs a current signal input from the specific alignment socket unit 1. Sensing and classifying the malfunctioning semiconductor device, and controls only the semiconductor device that is operating normally.
  • the semiconductor device 10 is moved by the pusher 3 to the opening 110 of the insertion body 100, and the 1000 or more ball terminals 12 are removed. 1 is accurately inserted into the first guide hole 222 formed in the guide sheet 220.
  • an electrical signal is simultaneously applied to the plurality of ball terminals 12 and pressed by the pusher toward the lower side of the insertion body 100, thereby conducting the conductive portion of the conductive pad 210.
  • the ball terminal 12 is pressed by the ball terminal 12 so that an electrical signal is conducted to the probe pin 302 located at a position corresponding to each ball terminal 12 to conduct a conductivity test of the semiconductor device 10.
  • the ball terminal 12 of the present invention is stably aligned by the first guide hole 222, and the plurality of probe pins 302 have an upper end accurately by the second guide hole 232 and the guide hole 410. It is located under the ball terminal 12.
  • the upper end of the probe pin 302 is stably aligned with respect to the ball terminal 12, so that the top of the probe pin 302 may be always aligned in the right position regardless of the movement caused by the falling of the ball terminal 12. Therefore, precise conductivity test can be performed.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Connecting Device With Holders (AREA)
  • Measuring Leads Or Probes (AREA)

Abstract

Disclosed is an align socket unit of a semiconductor device. The align socket unit of the semiconductor device according to one embodiment of the present invention comprises: an insertion body having an opening which receives the semiconductor device so as to test a packaged semiconductor device; a guide sheet which is installed in the lower surface of the insertion body, and which is provided for an alignment of an insertion position of a ball terminal provided in the semiconductor device; a base part to which the lower surface of the insertion body is seated, and which comprises a plurality of probe pins disposed in a position facing the ball terminal; and a guide pad which is in close contact with the lower surface of the guide sheet, and which has guide holes where the upper ends of the probe pins are inserted partially so as to always guide the position of the probe pins to the right position.

Description

반도체 디바이스 얼라인 소켓유닛 및 이를 포함하는 반도체 디바이스 검사장치Semiconductor device alignment socket unit and semiconductor device inspection apparatus including same
본 발명은 메모리 또는 비 메모리 반도체 디바이스에 대한 도전성 검사를 실시하기 위한 것으로서, 보다 상세하게는 상대적으로 볼 단자가 많이 구비된 반도체 디바이스에 대한 도전성 검사를 실시할 때 프루브 핀의 안정적인 얼라인(align)을 실시하기 위한 반도체 디바이스 얼라인 소켓유닛 및 이를 포함하는 반도체 디바이스 검사장치에 관한 것이다.The present invention is for conducting a conductive test for a memory or non-memory semiconductor device, and more particularly, a stable alignment of the probe pin when conducting a conductive test for a semiconductor device having a relatively large number of ball terminals. The present invention relates to a semiconductor device alignment socket unit and a semiconductor device inspection apparatus including the same.
일반적으로 IC와 같은 반도체 디바이스는 그 제조공정 중에 전기적 특성을 검사하여 그 불량 여부를 검사하고 있으며 상기 반도체 디바이스의 전기적 특성 검사는 반도체 디바이스의 피검사접점(범프)과 인쇄회로기판(PCB)을 포함하는 테스트 보드의 접점(패드) 사이에 개재된 프루브 핀을 통하여 수행된다. In general, semiconductor devices such as ICs are inspected for defects by inspecting electrical characteristics during the manufacturing process, and the electrical characteristics inspection of the semiconductor devices includes a contact point (bump) and a printed circuit board (PCB) of the semiconductor device. Is performed through a probe pin interposed between the contacts (pads) of the test board.
또한, 반도체 디바이스의 전기적 특성검사는 반도체 디바이스를 피검사체 캐리어에 삽입한 상태에서 수행된다. 종래의 반도체 디바이스의 검사는 피검사체 캐리어에 탑재된 반도체 디바이스의 볼 단자와 소켓 어셈블리에 지지된 프루브 핀의 전기적 접촉으로 수행된다. 이때 매우 작은 크기의 볼 단자와 프루브 핀은 좁은 피치로 배치되어 있기 때문에 테스트시에 매우 고정밀도의 정렬이 요구되는데, 볼 단자와 프루브 핀의 정렬은 피검사체 캐리어의 얼라인공과 소켓가이드의 얼라인 핀의 상호 정렬을 통해 이루어진다.In addition, the electrical characteristic inspection of the semiconductor device is performed in the state where the semiconductor device is inserted into the inspected carrier. The inspection of the conventional semiconductor device is performed by the electrical contact between the ball terminal of the semiconductor device mounted on the object carrier and the probe pin supported on the socket assembly. At this time, very small ball terminals and probe pins are arranged at a narrow pitch, so highly accurate alignment is required during the test.The alignment of the ball terminals and the probe pins is necessary to align the alignment holes of the specimen carrier and the socket guide. This is achieved through the alignment of the pins.
상기 피검사체 캐리어는 테스트 시에 소켓가이드와 결합과 분리를 반복해야 하기 때문에, 얼라인 핀과 얼라인 구멍은 반복적인 결합과 분리를 통해 여유도가 늘어나게 된다. 결과적으로 이러한 여유도 증가는 볼 단자와 프루브 핀의 미스매칭 또는 옵셋(offset)을 초래하는 문제점을 유발하였다.Since the subject carrier has to repeat the coupling and disconnection with the socket guide during the test, the alignment pins and the alignment holes are increased in margin through repeated coupling and disconnection. As a result, this increase in margin causes a problem of mismatching or offset of the ball terminal and the probe pin.
이와 같은 문제점은 수 천개 이상의 반도체 디바이스에 대한 도전성 테스트를 실시할 때 반도체 디바이스와 프루브 핀과의 충돌로 인해 고가의 반도체 디바이스에 대한 파손을 유발하거나, 파손된 반도체 디바이스의 볼 단자가 장비에 잔존할 경우 도전성 테스트를 중단한 상태에서 교체 내지 수리를 실시해야 하는 문제점이 유발되었다.This problem can cause damage to expensive semiconductor devices due to collisions between semiconductor devices and probe pins when conducting conductivity tests on thousands of semiconductor devices, or the ball terminals of broken semiconductor devices may remain in the equipment. In this case, a problem arises in that replacement or repair should be performed while the conductivity test is stopped.
본 발명은 상술한 문제점을 해결하기 위하여 창출된 것으로서, 더욱 상세하게는 반도체 디바이스의 볼 단자와 프루브 핀에 대한 상호 얼라인을 정확하게 일치시켜 접촉(contact)에 따른 정밀도를 향상된 반도체 디바이스 얼라인 소켓유닛 및 반도체 디바이스 검사장치를 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and more specifically, a semiconductor device alignment socket unit having improved accuracy according to contact by precisely matching the mutual alignment of the ball terminal and the probe pin of the semiconductor device. And a semiconductor device inspection apparatus.
상술한 목적을 달성하기 위한 본 발명의 반도체 디바이스 얼라인 소켓유닛은, 패키지화된 반도체 디바이스에 대한 테스트를 위해 상기 반도체 디바이스가 수용되는 개구부가 형성된 삽입본체; 상기 삽입본체의 하면에 설치되고 상기 반도체 디바이스에 구비된 볼 단자의 삽입 위치에 대한 정렬을 위한 가이드 시트; 상기 삽입본체의 하면이 안착되고 상기 볼 단자와 서로 마주보는 위치에 배치된 다수개의 프루브 핀을 포함하는 베이스 부; 및 상기 가이드 시트의 하면에 밀착되고 상기 프루브 핀의 상단이 부분 삽입되어 상기 프루브 핀의 위치를 항시 정 위치로 가이드 하는 가이드 홀이 형성된 가이드 패드를 포함한다.The semiconductor device alignment socket unit of the present invention for achieving the above object, the insertion body having an opening for receiving the semiconductor device for testing the packaged semiconductor device; A guide sheet for aligning the insertion position of the ball terminal provided on the bottom surface of the insertion body and provided in the semiconductor device; A base part including a plurality of probe pins disposed on a lower surface of the insertion body and facing each other with the ball terminal; And a guide pad in close contact with a lower surface of the guide sheet and having a guide hole partially inserted at an upper end of the probe pin to guide the position of the probe pin to a constant position at all times.
상기 반도체 디바이스 얼라인 소켓유닛에서, 상기 반도체 디바이스는 상기 볼 단자가 적어도 500볼 ~ 2000볼 사이로 배치될 수 있다.In the semiconductor device alignment socket unit, the semiconductor device may have the ball terminal disposed between at least 500 balls and 2000 balls.
상기 반도체 디바이스 얼라인 소켓유닛에서, 상기 가이드 시트는 실리콘 러버에 도전성 입자가 포함된 도전성 패드; 상기 도전성 패드의 상면에 밀착된 상태로 위치되고 상기 볼 단자와 대응되는 위치에 제1 가이드 홀이 형성된 제1 가이드 시트; 상기 도전성 패드의 하면에 밀착된 상태로 위치되고 상기 프루브 핀의 단부가 부분 삽입되는 제2 가이드 홀이 형성된 제2 가이드 시트를 포함할 수 있다.In the semiconductor device alignment socket unit, the guide sheet may include a conductive pad including conductive particles in a silicon rubber; A first guide sheet positioned in close contact with an upper surface of the conductive pad and having a first guide hole formed at a position corresponding to the ball terminal; It may include a second guide sheet which is positioned in close contact with the lower surface of the conductive pad and has a second guide hole in which an end portion of the probe pin is partially inserted.
상기 반도체 디바이스 얼라인 소켓유닛에서, 상기 도전성 패드는 폴리아미드 필름 또는 FR4 또는 FR5 또는 XPC 중의 어느 하나가 선택적으로 사용될 수 있다.In the semiconductor device alignment socket unit, the conductive pad may be a polyamide film or any one of FR4 or FR5 or XPC.
상기 반도체 디바이스 얼라인 소켓유닛에서, 상기 가이드 패드는 상기 가이드 시트의 두께보다 상대적으로 두꺼운 두께로 이루어질 수 있다.In the semiconductor device alignment socket unit, the guide pad may have a thickness relatively thicker than the thickness of the guide sheet.
상기 반도체 디바이스 얼라인 소켓유닛에서, 상기 가이드 패드는 전기적 절연성을 가지는 절연소재가 사용될 수 있다.In the semiconductor device alignment socket unit, the guide pad may be an insulating material having electrical insulation.
상기 반도체 디바이스 얼라인 소켓유닛에서, 상기 가이드 패드는 FPCB(Flexible Printed Circuit Board)가 사용될 수 있다.In the semiconductor device alignment socket unit, the guide pad may be a flexible printed circuit board (FPCB).
상기 반도체 디바이스 얼라인 소켓유닛에서, 상기 삽입본체는 상기 베이스 부의 상면을 향해 하측으로 돌출된 결합돌기를 포함하고, 상기 베이스 부는 상기 결합돌기와 대응되는 위치에 개구된 삽입 홀이 형성되어 상기 결합돌기가 상기 삽입 홀에 결합된 상태가 유지될 수 있다.In the semiconductor device alignment socket unit, the insertion body includes a coupling protrusion projecting downward toward an upper surface of the base portion, and the base portion is formed with an insertion hole opened at a position corresponding to the coupling protrusion so that the coupling protrusion is formed. The state coupled to the insertion hole may be maintained.
상기 반도체 디바이스 얼라인 소켓유닛에서, 상기 베이스 부는 내측면에 서로 마주보며 위치되고, 상기 삽입 본체의 외측과 접촉되어 정 위치 상태를 유지시키는 가이드 부재를 포함할 수 있다.In the semiconductor device alignment socket unit, the base part may include a guide member positioned on an inner side of the semiconductor device to face each other and in contact with an outer side of the insertion body to maintain a fixed position.
상기 반도체 디바이스 얼라인 소켓유닛에서, 상기 가이드 부재는 고무, 실리콘, 플라스틱 중의 어느 하나가 선택적으로 사용될 수 있다.In the semiconductor device alignment socket unit, the guide member may be any one of rubber, silicon, and plastic.
상기 반도체 디바이스 얼라인 소켓유닛에서, 상기 삽입본체는 상기 가이드 부재와 대응되는 위치에 형성되고 상기 가이드 부재가 삽입되는 삽입 홈을 포함할 수 있다.In the semiconductor device alignment socket unit, the insertion body may include an insertion groove formed at a position corresponding to the guide member and into which the guide member is inserted.
상술한 목적을 달성하기 위한 본 발명의 반도체 디바이스 검사장치는 반도체 디바이스가 수용되는 개구부가 형성된 삽입본체와, 상기 삽입본체의 내측에 설치되고 상기 반도체 디바이스에 구비된 볼 단자의 삽입 위치에 대한 정렬을 위한 가이드 시트와, 상기 삽입본체의 하면이 안착되고 상기 볼 단자와 서로 마주보는 위치에 배치된 다수개의 프루브 핀을 포함하는 베이스 부와, 상기 가이드 시트의 하면에 밀착되고 상기 프루브 핀의 상단이 부분 삽입되어 상기 반도체 디바이스에 대한 테스트가 이루어질 때 상기 프루브 핀의 위치를 항시 정 위치로 가이드 하는 가이드 패드를 가지는 얼라인 소켓유닛; 상기 얼 라인 소켓유닛이 다수개가 설치된 로딩유닛; 상기 얼 라인 소켓유닛의 상부와 마주보는 위치에 설치되고 상기 얼라인 소켓유닛의 상부로 이동된 다수개의 반도체 디바이스를 상기 삽입본체의 내측으로 가압하는 푸셔; 및 상기 푸셔에 의해 소정의 압력으로 가압된 반도체 디바이스에 대한 도전 성 검사가 이루어지는 동안 다수개의 반도체 디바이스의 이상 유무를 제어하는 제어부를 포함한다.The semiconductor device inspection apparatus of the present invention for achieving the above object is aligned with the insertion position of the insertion main body having an opening for accommodating the semiconductor device, and the insertion position of the ball terminal provided inside the insertion body and provided in the semiconductor device. A base portion including a guide sheet for mounting, a lower surface of the insertion body and a plurality of probe pins disposed at positions facing the ball terminal, and a top portion of the probe pin in close contact with the lower surface of the guide sheet. An alignment socket unit having a guide pad inserted therein to guide the position of the probe pin to the home position at all times; A loading unit in which a plurality of alignment socket units are installed; A pusher installed at a position facing the upper portion of the alignment socket unit and pressing the plurality of semiconductor devices moved to the upper portion of the alignment socket unit to the inside of the insertion body; And a controller for controlling the presence or absence of abnormalities of the plurality of semiconductor devices during the conduction test on the semiconductor device pressurized by the pusher at a predetermined pressure.
본 발명에 따른 반도체 디바이스 얼라인 소켓유닛은, 다수개의 반도체 디바이스에 대한 안정적인 도전성 테스트를 통해 작업성 향상과 작업 능률을 향상시킬 수 있으며, 상대적으로 볼 단자의 개수가 많은 반도체 디바이스에 대한 도전성 테스트를 손쉽게 실시할 수 있는 장점이 있다.The semiconductor device alignment socket unit according to the present invention can improve workability and work efficiency through a stable conductivity test of a plurality of semiconductor devices, and conduct a conductivity test of a semiconductor device having a relatively large number of ball terminals. There is an advantage that can be easily carried out.
본 발명에 따른 반도체 디바이스 얼라인 소켓유닛은, 다수개의 반도체 디바이스만 이송되고 얼라인 소켓유닛은 로딩 장치에 위치된 상태에서 작업을 실시할 수 있으므로 작업성이 현저하게 향상될 수 있는 장점이 있다.In the semiconductor device alignment socket unit according to the present invention, only a plurality of semiconductor devices are transferred, and the alignment socket unit can perform work in a state where it is located in the loading apparatus, and thus, workability is remarkably improved.
본 발명에 따른 반도체 디바이스 얼라인 소켓유닛은, 프루브 핀의 상단을 안정적으로 얼라인 하여 다수개의 볼 단자와의 정렬을 정확하게 일치시킨 상태로 반도체 디바이스에 대한 도전성 테스트를 실시할 수 있는 장점이 있다.The semiconductor device alignment socket unit according to the present invention has an advantage of conducting a conductive test on a semiconductor device while stably aligning an upper end of a probe pin so as to exactly match the alignment of the plurality of ball terminals.
도 1은 본 발명의 일 실시 예에 따른 반도체 디바이스 얼라인 소켓유닛의 분해 사시도.1 is an exploded perspective view of a semiconductor device alignment socket unit according to an exemplary embodiment of the present inventive concept.
도 2는 본 발명의 일 실시 예에 따른 반도체 디바이스 얼라인 소켓유닛의 평면도.2 is a plan view of a semiconductor device alignment socket unit according to an exemplary embodiment of the present inventive concept.
도 3은 본 발명의 일 실시 예에 따른 반도체 디바이스 얼라인 소켓유닛의 단면 분해 사시도.3 is an exploded cross-sectional perspective view of a semiconductor device alignment socket unit according to an exemplary embodiment of the present inventive concept.
도 4는 본 발명의 일 실시 예에 의한 반도체 디바이스 검사장치를 간략히 도시한 정면도.4 is a front view briefly showing a semiconductor device inspection apparatus according to an embodiment of the present invention.
도 5 내지 도 6은 본 발명의 일 실시 예에 따른 반도체 디바이스 얼라인 소켓유닛의 사용 상태도.5 to 6 are diagrams illustrating a use state of a semiconductor device alignment socket unit according to an embodiment of the present invention.
본 발명의 일 실시 예에 따른 반도체 디바이스 얼라인 소켓유닛의 구성에 대해 도면을 참조하여 설명한다.A configuration of a semiconductor device alignment socket unit according to an embodiment of the present invention will be described with reference to the drawings.
본 발명의 일 실시 예에 의한 얼라인 소켓유닛(1)은 패키지화된 반도체 디바이스(10)에 대한 테스트를 위해 상기 반도체 디바이스(10)가 수용되는 개구부(110)가 형성된 삽입본체(100)와, 상기 삽입본체(100)의 하면에 설치되고 상기 반도체 디바이스(10) 볼 단자(12)의 삽입 위치에 대한 정렬을 위한 가이드 시트(200)와, 상기 삽입본체(100)의 하면이 안착되고 상기 볼 단자(12)와 서로 마주보는 위치에 배치된 다수개의 프루브 핀(302)을 포함하는 베이스 부(300); 및 상기 가이드 시트(200)의 하면에 밀착되고 상기 프루브 핀(302)의 상단이 부분 삽입되어 상기 프루브 핀(302)의 위치를 항시 정 위치로 가이드 하는 가이드 패드(400)를 포함한다.The alignment socket unit 1 according to an embodiment of the present invention includes an insertion body 100 having an opening 110 in which the semiconductor device 10 is accommodated for testing the packaged semiconductor device 10, and It is installed on the lower surface of the insertion body 100 and the guide sheet 200 for alignment with the insertion position of the ball terminal 12 of the semiconductor device 10, and the lower surface of the insertion body 100 is seated and the ball A base portion 300 including a plurality of probe pins 302 disposed at positions facing the terminal 12; And a guide pad 400 that is in close contact with the bottom surface of the guide sheet 200 and partially inserts an upper end of the probe pin 302 to guide the position of the probe pin 302 at a constant position at all times.
본 실시 예에 의한 얼라인 소켓 유닛(1)은 상대적으로 볼 단자(12)가 500볼 ~ 2000볼 사이의 개수를 가지고 패키지화된 CPU에 사용되는 반도체 디바이스(10)에 대한 도전성 검사를 실시하기 위해 사용되며, 일 예로 PC에 설치되는 CPU와 같이 상대적으로 크기가 큰 반도체 디바이스(10)에 대한 도전성 검사를 실시하기 위해 사용된다.The alignment socket unit 1 according to the present embodiment is for conducting a conductive test on the semiconductor device 10 used in a CPU in which the ball terminals 12 are relatively numbered from 500 balls to 2000 balls. For example, it is used to conduct a conductive test on a relatively large semiconductor device 10 such as a CPU installed in a PC.
본 실시 예에 의한 삽입본체(100)는 전술한 반도체 디바이스(10)가 안정적으로 삽입되도록 개구부(110)가 상부를 향해 개구되어 있으며, 개구부(110) 내측이 하향 경사진 경사면(120)을 포함한다. 상기 경사면(120)은 반도체 디바이스(10)가 개구부(110)를 향해 안정적으로 삽입되기 위해 형성된다.The insert body 100 according to the present exemplary embodiment includes an inclined surface 120 in which the opening 110 is opened upward to allow the semiconductor device 10 to be stably inserted, and the inside of the opening 110 is inclined downward. do. The inclined surface 120 is formed to stably insert the semiconductor device 10 toward the opening 110.
삽입본체(100)는 후술할 가이드 부재(310)와 대응되는 위치에 형성되고 상기 가이드 부재(310)가 삽입되는 삽입 홈(104)을 포함하며, 상기 가이드 부재(310)와 삽입 홈(104)에 대한 상세한 설명은 베이스 부(300)를 설명하면서 하기로 한다.The insertion body 100 includes an insertion groove 104 formed at a position corresponding to the guide member 310 to be described later and into which the guide member 310 is inserted, and the guide member 310 and the insertion groove 104. A detailed description thereof will be given below with reference to the base unit 300.
본 발명의 일 실시 예에 의한 가이드 시트에 대해 설명한다.A guide sheet according to an embodiment of the present invention will be described.
가이드 시트(200)는 삽입본체(100)의 하부에 위치된 도전성 패드(210)와, 제1,2 가이드 시트(220,230)를 포함한다.The guide sheet 200 includes a conductive pad 210 positioned below the insertion body 100 and first and second guide sheets 220 and 230.
상기 도전성 패드(210)는 도전부(211)와 절연부(212)로 이루어진다. 이때 도전부(211)는 절연성 탄성물질 내에 다수의 도전성 입자가 두께방향으로 배열되는 형태로 이루어지고, 상기 도전부(211)가 볼 단자(12)와 접촉되어 프루브 핀(302)과 통전되면서 반도체 디바이스(10)에 설치된 다수개의 볼 단자(12)에 대한 도전 상태를 확인할 수 있다.The conductive pad 210 includes a conductive portion 211 and an insulating portion 212. In this case, the conductive portion 211 is formed in a shape in which a plurality of conductive particles are arranged in the thickness direction in the insulating elastic material, the conductive portion 211 is in contact with the ball terminal 12 to energize the probe pin 302 while the semiconductor The conduction state of the plurality of ball terminals 12 installed in the device 10 can be checked.
이때 도전부(211)는 후술할 제1,2 가이드 홀(222,232)과 대응되는 위치에 도전성 입자가 위치된다. 구체적으로는 제1,2 가이드 홀(222, 232)와 대응되는 위치마다 도전부(211)가 배치되어 있어서 반도체 디바이스(10)의 볼 단자(12)가 상기 도전부를 소정의 압력으로 가압하면, 상기 볼 단자(12)가 도전부를 통하여 프루브 핀(302)에 통전된다.At this time, the conductive portion 211 is the conductive particles are positioned at a position corresponding to the first, second guide holes (222, 232) to be described later. Specifically, when the conductive portion 211 is disposed at positions corresponding to the first and second guide holes 222 and 232, and the ball terminal 12 of the semiconductor device 10 presses the conductive portion to a predetermined pressure, The ball terminal 12 is energized to the probe pin 302 through the conductive portion.
상기 도전부(211)를 구성하는 절연성 탄성물질은 실리콘 고무를 사용하는 것이 바람직하나, 이에 한정되는 것은 아니며 탄력성이 좋은 고무소재라면 무엇이나 가능하다.The insulating elastic material constituting the conductive part 211 is preferably made of silicone rubber, but is not limited thereto. Any rubber material having good elasticity may be used.
한편, 상기 절연부(212)는 다수의 도전부(211)의 주위에 상기 도전부(211)와 일체적으로 결합되어 상기 도전부(211)를 지지하면서 절연시키는 것이다. 이러한 절연부(212)에 의하여 전기적 흐름이 두께방향으로만 가능하게 되는 것이다. 이러한 절연부(212)는 상기 도전부(211)를 구성하는 절연성 탄성물질과 동일한 소재로 이루어지나, 이에 한정되는 것은 아니며 폴리미이드 필름, FR4, FR5, XPC 중 어느 하나가 사용될 수 있다.Meanwhile, the insulating part 212 is integrally coupled with the conductive part 211 around the plurality of conductive parts 211 to insulate while supporting the conductive part 211. Electrical insulation is enabled only in the thickness direction by the insulation part 212. The insulating part 212 may be made of the same material as the insulating elastic material constituting the conductive part 211, but is not limited thereto. Any one of a polyamide film, FR4, FR5, and XPC may be used.
제1 가이드 시트(220)는 도전성 패드(210)의 상면에 밀착된 상태로 위치되고 상기 볼 단자(12)와 대응되는 위치에 제1 가이드 홀(222)이 형성된다.The first guide sheet 220 is positioned in close contact with the upper surface of the conductive pad 210 and the first guide hole 222 is formed at a position corresponding to the ball terminal 12.
상기 제1 가이드 홀(222)은 제1 가이드 시트(220)의 전 영역에 개구되며 본 실시 예에 의한 도면에서는 상기 제1 가이드 홀(222)을 전체적으로 모두 도시하지 않고 중앙 위치에만 부분 도시된 상태로 설명한다.The first guide hole 222 is opened in the entire region of the first guide sheet 220, and in the drawing according to the present embodiment, the first guide hole 222 is not shown as a whole, but is partially shown only at the central position. Explain.
제1 가이드 홀(222)은 일 예로 이웃한 제1 가이드 홀의 중심과 0.4mm로 이격된 간격을 가지고 배치되며 1000개 이상의 볼 단자(12)가 동시에 제1 가이드 홀(222)과 제2 가이드 홀(232)을 경유하여 상기 볼 단자(12)와 대응되는 위치에 위치된 프루브 핀(302)이 얼라인되어 반도체 디바이스(10)에 대한 도전성 검사가 이루어진다.For example, the first guide hole 222 is disposed at a distance of 0.4 mm from the center of the neighboring first guide hole, and at least 1000 ball terminals 12 are simultaneously disposed in the first guide hole 222 and the second guide hole. Probe pins 302 positioned at positions corresponding to the ball terminals 12 via 232 are aligned to conduct conductivity tests on the semiconductor device 10.
제2 가이드 시트(230)는 상기 도전성 패드(210)의 하면에 밀착된 상태로 위치되고 상기 프루브 핀(302)의 단부가 부분 삽입되는 제2 가이드 홀(232)이 형성된다. 상기 제2 가이드 홀(232)은 전술한 제1 가이드 홀(222)과 상이하게 다수개의 프루브 핀(302)의 얼라인을 위해 형성되며, 상기 프루브 핀(302)의 상단이 부분 삽입된 상태가 유지된다.The second guide sheet 230 is positioned in close contact with the bottom surface of the conductive pad 210, and a second guide hole 232 is formed to partially insert the end of the probe pin 302. The second guide hole 232 is formed to align the plurality of probe pins 302 differently from the first guide hole 222 described above, and the top of the probe pins 302 is partially inserted. maintain.
상기 제1,2 가이드 홀(222,232)은 서로 동일 위치에 개구되어 있으며, 본 실시 예에서는 프루브 핀(302)의 보다 정확한 얼라인을 위해 가이드 패드(400)를 설치하여 다수개의 프루브 핀(302)에 대한 얼라인을 실시한다.The first and second guide holes 222 and 232 are opened at the same position, and in this embodiment, a plurality of probe pins 302 are provided by installing a guide pad 400 for more accurate alignment of the probe pins 302. Conduct an alignment on
가이드 패드(400)는 전술한 가이드 시트(200)의 두께보다는 상대적으로 두꺼운 두께로 이루어지므로 프루브 핀(302)의 상단이 보다 안정적으로 결합된 상태가 유지된다. 가이드 패드(400)는 FPCB가 사용되며, 상기 FPCB는 전기적 절연성이 우수하고 내열성과, 내곡성 및 내약품성이 강하므로 가이드 시트(200)에서 반도체 디바이스(10)에 의해 소정의 외력이 가해지는 경우에도 안정적으로 지지되고 다수개의 프루브 핀(302)이 결합된 상태에서도 이탈되지 않고 안정적으로 결합된 상태가 유지된다.Since the guide pad 400 is made of a thickness relatively thicker than the thickness of the guide sheet 200 described above, the top of the probe pin 302 is more stably coupled. FPCB is used for the guide pad 400. Since the FPCB is excellent in electrical insulation and strong in heat resistance, bending resistance, and chemical resistance, a predetermined external force is applied by the semiconductor device 10 in the guide sheet 200. Edo stably supported and is maintained in a stable state without being separated even when a plurality of probe pins 302 are coupled.
가이드 패드(400)는 프루브 핀(302)의 상단 일부가 가이드 홀(410)에 삽입된다. 일 예로 볼 단자(12)의 개수가 1000볼 이상인 경우 푸셔에 의해 반도체 디바이스(10)가 프루브 핀(302)을 향해 순간적으로 이동되는 경우 상기 프루브 핀(302)의 상단이 가이드 홀(410)에 의해 위치 변동 없이 얼라인되고 도전성 패드(210)에 분포된 도전성 입자를 통해 프루브 핀(302)으로 통전되어 도전성 테스트가 이루어진다. 참고로 프루브 핀(302)은 공지의 구성이므로 상세한 설명은 생략한다.The guide pad 400 has a portion of the upper end of the probe pin 302 inserted into the guide hole 410. For example, when the number of the ball terminals 12 is 1000 balls or more, when the semiconductor device 10 is momentarily moved toward the probe pins 302 by the pusher, an upper end of the probe pins 302 may be formed in the guide hole 410. As a result, the conductive pins are electrically aligned with the probe pins 302 through the conductive particles aligned without dislocations and distributed on the conductive pads 210. For reference, since the probe pin 302 is a well-known configuration, detailed description thereof will be omitted.
본 발명의 일 실시 예에 의한 베이스 부에 대해 도면을 참조하여 설명한다.A base unit according to an embodiment of the present invention will be described with reference to the drawings.
첨부된 도 1 또는 도 3을 참조하면, 베이스 부(300)는 삽입본체(100)의 하측에 돌출된 결합돌기(130)와 대응되는 위치에 삽입 홀(301)이 형성되어 삽입본체(100)에 대한 일차적인 결합을 실시하고, 가이드 부재(310)에 의해 상기 삽입본체(100)의 외측과 접촉되어 정 위치 상태를 유지시킨다.Referring to FIG. 1 or FIG. 3, the base part 300 has an insertion hole 301 formed at a position corresponding to the coupling protrusion 130 protruding from the lower side of the insertion body 100 to insert the body 100. Primary coupling is performed, and the guide member 310 is brought into contact with the outside of the insertion body 100 to maintain a fixed position.
상기 가이드 부재(310)는 고무 또는 실리콘 또는 플라스틱 중의 어느 하나가 선택적으로 사용되며, 본 실시 예에서는 도면 기준으로 베이스 부(300)의 좌측과 우측에 각각 서로 마주보며 배치되어 삽입 홈(104)에 삽입된다. 상기 삽입 홈(104)은 상기 가이드 부재(310)의 형상과 대응되는 형태로 이루어져 상기 삽입본체(100)가 베이스 부(300)의 내측에 결합될 때 가이드 부재(310)가 손쉽게 삽입 홈(104)에 삽입되게 한다.The guide member 310 may be any one of rubber, silicon, or plastic is selectively used. In the present embodiment, the guide member 310 is disposed to face each other on the left and right sides of the base part 300 on the basis of the drawing, and is inserted into the insertion groove 104. Is inserted. The insertion groove 104 is formed in a shape corresponding to the shape of the guide member 310 when the insertion body 100 is coupled to the inside of the base portion 300, the guide member 310 is easily inserted groove 104 To be inserted).
가이드 부재(310)는 베이스 부(300)의 외측으로 단부가 구 형태로 돌출되었으나, 상기 삽입 홈(104)과 암수 형태로 결합되는 다른 형태로의 변경도 가능함을 밝혀둔다.The guide member 310 is protruded in the form of a spherical shape toward the outside of the base portion 300, it is noted that it is possible to change to another shape that is coupled to the insertion groove 104 and the male and female form.
베이스 부(300)는 프루브 핀(302)의 하단이 결합되는 제1 베이스 부(320)와, 상기 제1 베이스 부(320)의 상부에 밀착된 제2 베이스 부(330)를 포함하고, 상기 제1,2 베이스 부(320,330)는 프루브 핀(302)의 하부를 안정적으로 지지한다.The base portion 300 includes a first base portion 320 to which the lower end of the probe pin 302 is coupled, and a second base portion 330 in close contact with the upper portion of the first base portion 320. The first and second base parts 320 and 330 stably support the lower portion of the probe pin 302.
본 발명의 일 실시 예에 의한 반도체 디바이스 검사장치에 대해 도면을 참조하여 설명한다. 참고로 소켓유닛(1)은 도 1과 동일함을 밝혀둔다.A semiconductor device inspection apparatus according to an embodiment of the present invention will be described with reference to the drawings. Note that the socket unit 1 is the same as in FIG.
본 발명의 일 실시 예에 의한 반도체 디바이스 검사장치(1a)는 전술한 얼라인 소켓유닛(1)을 이용하여 반도체 디바이스에 대한 테스트를 실시하기 위한 검사장치에 대한 것으로서, 반도체 디바이스(10)가 수용되는 개구부(110)가 형성된 삽입본체(100)와, 상기 삽입본체(100)의 내측에 설치되고 상기 반도체 디바이스(10)에 구비된 볼 단자(12)의 삽입 위치에 대한 정렬을 위한 가이드 시트(200)와, 상기 삽입본체(100)의 하면이 안착되고 상기 볼 단자(12)와 서로 마주보는 위치에 배치된 다수개의 프루브 핀(302)을 포함하는 베이스 부(300)와, 상기 가이드 시트(200)의 하면에 밀착되고 상기 프루브 핀(302)의 상단이 부분 삽입되어 상기 반도체 디바이스(10)에 대한 테스트가 이루어질 때 상기 프루브 핀(302)의 위치를 항시 정 위치로 가이드 하는 가이드 홀(410)이 형성된 가이드 패드(400)를 가지는 얼라인 소켓유닛(1)과, 상기 얼 라인 소켓유닛(1)이 다수개가 설치된 로딩유닛(2)과, 상기 얼 라인 소켓유닛(1)의 상부와 마주보는 위치에 설치되고 상기 얼라인 소켓유닛(1)의 상부로 이동된 다수개의 반도체 디바이스(10)를 상기 삽입본체(100)의 내측으로 가압하는 푸셔(3); 및 상기 푸셔(3)에 의해 소정의 압력으로 가압된 반도체 디바이스(10)에 대한 도전성 검사가 이루어지는 동안 다수개의 반도체 디바이스(10)의 이상 유무를 제어하는 제어부(4)를 포함한다.The semiconductor device inspecting apparatus 1a according to an embodiment of the present invention relates to an inspecting apparatus for testing a semiconductor device using the above-described alignment socket unit 1, and the semiconductor device 10 is accommodated. A guide sheet for alignment with an insertion position of the insertion body 100 having an opening 110 formed therein, and an insertion position of the ball terminal 12 provided inside the insertion body 100 and provided in the semiconductor device 10 ( 200 and a base portion 300 including a plurality of probe pins 302 disposed at positions where the lower surface of the insertion body 100 faces the ball terminal 12 and faces each other, and the guide sheet ( The guide hole 410 is closely attached to the lower surface of the 200, and the upper end of the probe pin 302 is partially inserted to guide the position of the probe pin 302 to a constant position when a test is performed on the semiconductor device 10. ) Formed Alignment socket unit 1 having an id pad 400, a loading unit 2 having a plurality of alignment socket units 1 installed thereon, and a position facing the upper portion of the alignment socket unit 1 A pusher (3) installed and pressing the plurality of semiconductor devices (10) moved to the upper portion of the alignment socket unit (1) to the inside of the insertion body (100); And a controller 4 for controlling the presence or absence of abnormalities of the plurality of semiconductor devices 10 during the conducting inspection of the semiconductor device 10 pressed by the pusher 3 at a predetermined pressure.
얼라인 소켓유닛(1)은 이미 전술하였으므로 상세한 설명은 생략하며, 로딩유닛(2)은 30개 내지 50개의 얼라인 소켓유닛(1)이 설치되어 다수개의 반도체 디바이스(10)에 대한 도전성 검사를 한 번에 실시할 수 있으며, 이 경우 작업자가 보다 편리하고 신속하게 다수개의 반도체 디바이스(10)에 대한 도전성 검사를 실시할 수 있으므로 작업성이 향상되고 보다 빠른 시간에 다수개의 반도체 디바이스에 대한 이상 유무를 확인할 수 있다.Since the alignment socket unit 1 has already been described above, a detailed description thereof will be omitted, and the loading unit 2 has 30 to 50 alignment socket units 1 installed therein to conduct conductivity tests of the plurality of semiconductor devices 10. It can be carried out at one time, and in this case, the operator can conduct the conductivity test on the plurality of semiconductor devices 10 more conveniently and quickly, thereby improving workability and having an abnormality for the plurality of semiconductor devices at a faster time. You can check.
푸셔(3)는 유압 실린더 및 피스톤으로 구성되어 상기 반도체 디바이스(10)를 삽입본체(100)의 내측을 향해 소정의 압력으로 모두 동시에 가압하기 위해 설치되고, 상기 푸셔(3)의 가압력은 공압으로 작동되므로 작업자가 임의의 압력으로 손쉽게 셋팅하여 사용할 수 있다.The pusher 3 is composed of a hydraulic cylinder and a piston and is installed to simultaneously press all of the semiconductor device 10 at a predetermined pressure toward the inside of the insertion body 100, and the pressing force of the pusher 3 is pneumatically. It is operated so that the operator can easily set it to any pressure.
제어부(4)는 다수개의 얼라인 소켓유닛(1)에 삽입된 다수개의 반도체 디바이스(10)를 통해 입력되는 도전 상태가 안정적인지 판단하고, 특정 얼라인 소켓유닛(1)에서 입력되는 전류 신호를 감지하여 오작동되는 반도체 디바이스에 대해 분류하여 정상 작동되는 반도체 디바이스만 선별 제어한다.The controller 4 determines whether a conductive state input through the plurality of semiconductor devices 10 inserted into the plurality of alignment socket units 1 is stable, and outputs a current signal input from the specific alignment socket unit 1. Sensing and classifying the malfunctioning semiconductor device, and controls only the semiconductor device that is operating normally.
이와 같이 구성되는 본 발명의 일 실시 예에 의한 반도체 디바이스 얼라인 소켓유닛의 사용 상태에 대해 도면을 참조하여 설명한다.A use state of the semiconductor device alignment socket unit according to the exemplary embodiment of the present invention configured as described above will be described with reference to the accompanying drawings.
첨부된 도 1 또는 도 5 내지 도 6을 참조하면, 반도체 디바이스(10)는 푸셔(3)에 의해 삽입본체(100)의 개구부(110)로 이동되고, 1000개 이상의 볼 단자(12)는 제1 가이드 시트(220)에 형성된 제1 가이드 홀(222)로 정확하게 삽입된다.1 or 5 to 6, the semiconductor device 10 is moved by the pusher 3 to the opening 110 of the insertion body 100, and the 1000 or more ball terminals 12 are removed. 1 is accurately inserted into the first guide hole 222 formed in the guide sheet 220.
그리고 상기 반도체 디바이스(10)에 전기적 신호가 입력되면 다수개의 볼 단자(12)에 동시에 전기 신호가 인가되고, 푸셔에 의해 삽입본체(100)의 하측으로 가압되면서 도전성 패드(210)의 도전부(211)를 볼단자(12)가 가압하여 각각의 볼 단자(12)와 대응되는 위치에 위치된 프루브 핀(302)에 전기 신호가 전도되어 상기 반도체 디바이스(10)에 대한 도전성 테스트가 이루어진다.When an electrical signal is input to the semiconductor device 10, an electrical signal is simultaneously applied to the plurality of ball terminals 12 and pressed by the pusher toward the lower side of the insertion body 100, thereby conducting the conductive portion of the conductive pad 210. The ball terminal 12 is pressed by the ball terminal 12 so that an electrical signal is conducted to the probe pin 302 located at a position corresponding to each ball terminal 12 to conduct a conductivity test of the semiconductor device 10.
예를 들어 한 개의 얼라인 소켓유닛(1)에는 수 백개의 반도체 디바이스(10)가 시간차를 두고 연속적으로 삽입본체(100)의 내측에 반복 삽입되고 이 경우 볼 단자(12)와 프루브 핀(302)과의 얼라인은 항시 정확하게 일치되어야만 반도체 디바이스(10)에 대한 도전성 테스트를 실시할 때 오류가 발생되지 않는다.For example, in one alignment socket unit 1, hundreds of semiconductor devices 10 are repeatedly inserted into the insertion body 100 successively with a time difference. In this case, the ball terminal 12 and the probe pin 302 ) Must always be exactly coincident so that no error occurs when conducting a conductivity test on the semiconductor device 10.
본 발명의 볼 단자(12)는 제1 가이드 홀(222)에 의해 안정적으로 얼라인되고, 다수개의 프루브 핀(302)은 상단이 제2 가이드 홀(232)과 가이드 홀(410)에 의해 정확하게 볼 단자(12)의 하측에 위치된다. The ball terminal 12 of the present invention is stably aligned by the first guide hole 222, and the plurality of probe pins 302 have an upper end accurately by the second guide hole 232 and the guide hole 410. It is located under the ball terminal 12.
이에 따라서 프루브 핀(302)의 상단이 안정적으로 볼 단자(12)에 대하여 얼라인되어 상기 볼 단자(12)의 하강에 따른 이동과 상관없이 언제나 정 위치에 얼라인된 상태를 유지할 수 있으며, 이에 따라서 정밀한 도전성 검사를 실시할 수 있다.Accordingly, the upper end of the probe pin 302 is stably aligned with respect to the ball terminal 12, so that the top of the probe pin 302 may be always aligned in the right position regardless of the movement caused by the falling of the ball terminal 12. Therefore, precise conductivity test can be performed.
이상, 본 발명의 일 실시 예에 대하여 설명하였으나, 해당 기술 분야에서 통상의 지식을 가진 자라면 특허청구범위에 기재된 본 발명의 사상으로부터 벗어나지 않는 범위 내에서, 구성 요소의 부가, 변경, 삭제 또는 추가 등에 의해 본 발명을 다양하게 수정 및 변경시킬 수 있을 것이며, 이 또한 본 발명의 권리범위 내에 포함된다고 할 것이다.As mentioned above, although an embodiment of the present invention has been described, those skilled in the art may add, change, delete, or add components within the scope not departing from the spirit of the present invention described in the claims. The present invention may be modified and changed in various ways, etc., which will also be included within the scope of the present invention.

Claims (12)

  1. 패키지화된 반도체 디바이스에 대한 테스트를 위해 상기 반도체 디바이스가 수용되는 개구부가 형성된 삽입본체;An insert body having an opening for receiving the semiconductor device for testing a packaged semiconductor device;
    상기 삽입본체의 하면에 설치되고 상기 반도체 디바이스에 구비된 볼 단자의 삽입 위치에 대한 정렬을 위한 가이드 시트;A guide sheet for aligning the insertion position of the ball terminal provided on the bottom surface of the insertion body and provided in the semiconductor device;
    상기 삽입본체의 하면이 안착되고 상기 볼 단자와 서로 마주보는 위치에 배치된 다수개의 프루브 핀을 포함하는 베이스 부; 및A base part including a plurality of probe pins disposed on a lower surface of the insertion body and facing each other with the ball terminal; And
    상기 가이드 시트의 하면에 밀착되고 상기 프루브 핀의 상단이 부분 삽입되어 상기 프루브 핀의 위치를 항시 정 위치로 가이드 하는 가이드 홀이 형성된 가이드 패드를 포함하는 반도체 디바이스 얼라인 소켓유닛.And a guide pad in close contact with a lower surface of the guide sheet and having a guide hole formed at an upper end of the probe pin to partially guide the position of the probe pin.
  2. 제1 항에 있어서,According to claim 1,
    상기 반도체 디바이스는,The semiconductor device,
    상기 볼 단자가 적어도 500볼 ~ 2000볼 사이로 배치된 것을 특징으로 하는 반도체 디바이스 얼라인 소켓유닛.And the ball terminal is arranged between at least 500 and 2000 balls.
  3. 제1 항에 있어서,According to claim 1,
    상기 가이드 시트는,The guide sheet,
    실리콘 러버에 도전성 입자가 포함된 도전성 패드;Conductive pads containing conductive particles in silicon rubber;
    상기 도전성 패드의 상면에 밀착된 상태로 위치되고 상기 볼 단자와 대응되는 위치에 제1 가이드 홀이 형성된 제1 가이드 시트;A first guide sheet positioned in close contact with an upper surface of the conductive pad and having a first guide hole formed at a position corresponding to the ball terminal;
    상기 도전성 패드의 하면에 밀착된 상태로 위치되고 상기 프루브 핀의 단부가 부분 삽입되는 제2 가이드 홀이 형성된 제2 가이드 시트를 포함하는 반도체 디바이스 얼라인 소켓유닛.And a second guide sheet positioned in close contact with a lower surface of the conductive pad and having a second guide hole partially inserted into an end portion of the probe pin.
  4. 제3 항에 있어서,The method of claim 3, wherein
    상기 도전성 패드는,The conductive pad,
    폴리아미드 필름 또는 FR4 또는 FR5 또는 XPC 중의 어느 하나가 선택적으로 사용되는 반도체 디바이스 얼라인 소켓유닛.A semiconductor device alignment socket unit in which either a polyamide film or FR4 or FR5 or XPC is optionally used.
  5. 제1 항에 있어서,According to claim 1,
    상기 가이드 패드는,The guide pad,
    상기 가이드 시트의 두께보다 상대적으로 두꺼운 두께로 이루어진 것을 특징으로 하는 반도체 디바이스 얼라인 소켓유닛.The semiconductor device alignment socket unit, characterized in that made of a thickness relatively thicker than the thickness of the guide sheet.
  6. 제1 항에 있어서,According to claim 1,
    상기 가이드 패드는,The guide pad,
    전기적 절연성을 가지는 절연소재가 사용되는 반도체 디바이스 얼라인 소켓유닛.A semiconductor device alignment socket unit in which an insulating material having electrical insulation is used.
  7. 제1 항에 있어서,According to claim 1,
    상기 가이드 패드는,The guide pad,
    FPCB(Flexible Printed Circuit Board)가 사용되는 반도체 디바이스 얼라인 소켓유닛.Semiconductor device alignment socket unit using FPCB (Flexible Printed Circuit Board).
  8. 제1 항에 있어서,According to claim 1,
    상기 삽입본체는,The insert body,
    상기 베이스 부의 상면을 향해 하측으로 돌출된 결합돌기를 포함하고, 상기 베이스 부는 상기 결합돌기와 대응되는 위치에 개구된 삽입 홀이 형성되어 상기 결합돌기가 상기 삽입 홀에 결합된 상태가 유지되는 반도체 디바이스 얼라인 소켓유닛.The semiconductor device includes a coupling protrusion protruding downward toward an upper surface of the base portion, wherein the base portion is formed with an insertion hole opened at a position corresponding to the coupling protrusion to maintain the coupling protrusion coupled to the insertion hole. Socket unit.
  9. 제1 항에 있어서,According to claim 1,
    상기 베이스 부는,The base part,
    내측면에 서로 마주보며 위치되고, 상기 삽입 본체의 외측과 접촉되어 정 위치 상태를 유지시키는 가이드 부재를 포함하는 반도체 디바이스 얼라인 소켓유닛.And a guide member positioned on an inner surface of the insert body so as to face each other and in contact with an outer side of the insertion body to maintain a fixed position.
  10. 제9 항에 있어서,The method of claim 9,
    상기 가이드 부재는,The guide member,
    고무, 실리콘, 플라스틱 중의 어느 하나가 선택적으로 사용되는 반도체 디바이스 얼라인 소켓유닛.A semiconductor device alignment socket unit in which any one of rubber, silicon and plastic is optionally used.
  11. 제9 항에 있어서,The method of claim 9,
    상기 삽입본체는,The insert body,
    상기 가이드 부재와 대응되는 위치에 형성되고 상기 가이드 부재가 삽입되는 삽입 홈을 포함하는 반도체 디바이스 얼라인 소켓유닛.And a insertion groove formed at a position corresponding to the guide member and into which the guide member is inserted.
  12. 반도체 디바이스가 수용되는 개구부가 형성된 삽입본체와, 상기 삽입본체의 내측에 설치되고 상기 반도체 디바이스에 구비된 볼 단자의 삽입 위치에 대한 정렬을 위한 가이드 시트와, 상기 삽입본체의 하면이 안착되고 상기 볼 단자와 서로 마주보는 위치에 배치된 다수개의 프루브 핀을 포함하는 베이스 부와, 상기 가이드 시트의 하면에 밀착되고 상기 프루브 핀의 상단이 부분 삽입되어 상기 반도체 디바이스에 대한 테스트가 이루어질 때 상기 프루브 핀의 위치를 항시 정 위치로 가이드 하는 가이드 패드를 가지는 얼라인 소켓유닛;An insertion body having an opening for accommodating a semiconductor device, a guide sheet for aligning an insertion position of a ball terminal provided inside the insertion body and provided in the semiconductor device, and a lower surface of the insertion body is seated and the ball A base portion including a plurality of probe pins disposed at positions facing each other of the terminal, and a bottom portion of the guide sheet and partially inserted into an upper end of the probe pin to test the semiconductor device. An alignment socket unit having a guide pad for guiding the position at all times;
    상기 얼 라인 소켓유닛이 다수개가 설치된 로딩유닛;A loading unit in which a plurality of alignment socket units are installed;
    상기 얼 라인 소켓유닛의 상부와 마주보는 위치에 설치되고 상기 얼라인 소켓유닛의 상부로 이동된 다수개의 반도체 디바이스를 상기 삽입본체의 내측으로 가압하는 푸셔; 및A pusher installed at a position facing the upper portion of the alignment socket unit and pressing the plurality of semiconductor devices moved to the upper portion of the alignment socket unit to the inside of the insertion body; And
    상기 푸셔에 의해 소정의 압력으로 가압된 반도체 디바이스에 대한 도전 성 검사가 이루어지는 동안 다수개의 반도체 디바이스의 이상 유무를 제어하는 제어부를 포함하는 반도체 디바이스 검사장치.And a control unit for controlling the presence or absence of abnormality of the plurality of semiconductor devices during the conductivity test on the semiconductor device pressed by the pusher at a predetermined pressure.
PCT/KR2014/012768 2013-12-24 2014-12-23 Align socket unit of semiconductor device and semiconductor device checking apparatus comprising same WO2015099431A1 (en)

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