WO2015096381A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2015096381A1
WO2015096381A1 PCT/CN2014/078506 CN2014078506W WO2015096381A1 WO 2015096381 A1 WO2015096381 A1 WO 2015096381A1 CN 2014078506 W CN2014078506 W CN 2014078506W WO 2015096381 A1 WO2015096381 A1 WO 2015096381A1
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Prior art keywords
layer
source
data line
drain
thin film
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PCT/CN2014/078506
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English (en)
French (fr)
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徐向阳
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US14/428,450 priority Critical patent/US9406701B2/en
Priority to EP14861175.9A priority patent/EP3089214B1/en
Publication of WO2015096381A1 publication Critical patent/WO2015096381A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and the A method of fabricating an array substrate, and a display device including the array substrate.
  • the display panel of the display device includes an array substrate including interlaced a plurality of gate lines and a plurality of data lines, the gate lines and the data lines dividing the array substrate into a plurality of A pixel unit is provided with a thin film transistor in each pixel unit.
  • Traditional array substrate The thin film transistor is usually an amorphous silicon thin transistor, and the mobility of the amorphous silicon thin film transistor Generally around 0.5cmW ⁇ S.
  • the frequency of driving circuits continues to increase.
  • the existing amorphous silicon thin film transistor mobility is difficult to meet the demand.
  • the drive frequency should be 120Hz, in this case It is required that the mobility of the thin film transistor is above 1 cmW ⁇ S, and therefore, the amorphous silicon thin film crystal is now available.
  • the mobility of the body tube is clearly difficult to meet the above requirements.
  • Oxide thin film transistor has high mobility, uniformity, transparency, and fabrication process Simple and other advantages, can better meet the needs of large-size display for thin film transistor mobility begging.
  • Shown in Figure 1 is an array substrate typically comprising an oxide thin film transistor. Cutaway view. Since hydrogen bonding has a large influence on an active layer made of a metal oxide, As shown in FIG. 1, the array substrate includes an active layer 10 located on an oxide thin film transistor. The upper etch stop layer 20, the source 30 and the drain 40 of the oxide thin film transistor pass The via hole passing through the etch barrier layer 20 is connected to the active layer 10 of the oxide thin film transistor, It is possible to prevent the etching solution from penetrating while etching the source and the drain of the oxide thin film transistor. Into the active layer.
  • an etch stop layer 20 is usually formed using silicon dioxide. but Yes, due to the poor compactness of silicon dioxide, the source and drain metal layers of the thin film transistor There is a bubble-like gap between the etch barrier layers 20. When etching the source/drain metal layer, The etching solution penetrates into the gap between the data line 50 and the etch stop layer 20 along the bubble-like gap. Touching the face, which results in a portion of the data line 50 that is connected to the source 30 of the thin film transistor. The parts are etched, thereby reducing the overall quality of the array substrate.
  • An object of the present invention is to provide an array substrate and a method of manufacturing the same, and the same A display device for an array substrate. a data line in the array substrate and a source of the thin film transistor The parts in contact are not easily corroded.
  • an array base comprising a plurality of data lines, a plurality of gate lines, and a plurality of oxide thin film transistors, A plurality of the data lines and a plurality of the gate lines are interdigitated and the array substrate is divided into a plurality of pixel units, each of which is provided with the oxide thin film crystal a tube, wherein the array substrate further includes at least the data line and the gate line a metal oxide layer under the overlapping portion, an upper surface of the metal oxide layer and the The lower surface of the data line is in contact.
  • the metal may be disposed at an intersection of each of the data lines and the gate lines An oxide layer, the metal oxide layer having a width equal to a width of the data line, The length of the metal oxide layer may be the same as the width of the gate line.
  • the size of the metal oxide layer may correspond to the data line size.
  • the metal oxide layer and the active layer of the oxide thin film transistor may be the same Made of materials.
  • An etch may be disposed over the active layer of the oxide thin film transistor Barrier layer.
  • the metal oxide layer may be made of ZnO, InZnO, ZnSnO, GaInZnO, Made of any one of ZrInZnO.
  • the source and the drain of the oxide thin film transistor may be Located above the active layer of the oxide thin film transistor, and the oxide thin film crystal
  • the source and the drain of the tube may pass through the first via and the first through the etch stop layer respectively
  • Two vias are connected to the active layer, and the data lines can be formed at least partially through
  • the etched barrier layer is in contact with the metal oxide layer.
  • the active layer of the thin film transistor may Include a source footprint, a drain footprint, and the source footprint and the drain overlay An etch barrier between the regions, the metal oxide layer comprising the active layer a source oxide layer connected to one side and to the source footprint, located on the active layer a drain oxide layer connected to the drain footprint and located under the data line And a data line oxide layer in contact with the lower surface of the data line.
  • Thin film transistor a portion of the lower surface of the source may be in contact with the source coverage area, and another portion may Contacting the source oxide layer, a portion of a lower surface of a drain of the thin film transistor May be in contact with the drain footprint and another portion may be connected to the drain oxide Alternatively, the lower surface of the etch stop layer may be in contact only with the etch stop layer footprint.
  • a method of fabricating an array substrate includes the steps of: forming a pattern including gate lines; forming including a thin film crystal a pattern of an active layer of the tube; forming a pattern including a metal oxide layer; and forming a number including a pattern of source and drain of the line and the thin film transistor, wherein the metal oxide layer is Less disposed below a portion where the data line overlaps the gate line, and the metal The upper surface of the oxide layer is in contact with the lower surface of the data line.
  • the metal oxide layer may be located with an active layer of the oxide thin film transistor In the same layer, the metal oxide layer may be associated with an active layer of the oxide thin film transistor Made of the same material and can be formed in the same step of the patterning process including the oxide thin A pattern of the active layer of the film transistor and the metal oxide layer.
  • the manufacturing method may further include the steps of: forming an etch barrier layer a pattern, the etch stop layer is located above the active layer; and forming a first via, a second via hole and a data line groove, wherein the first via hole and the second via hole both pass through the etching a barrier layer reaches an active layer of the oxide thin film transistor, and the data line groove passes through the The etch stop layer reaches the metal oxide layer.
  • the source may pass through the first via
  • the active layers are connected, and the drain may be in phase with the active layer through the second via Connected, the data line is located in the data line groove, and the lower surface of the data line The metal oxide layer is in contact.
  • the active layer of the thin film transistor may Include a source footprint, a drain footprint, and the source footprint and the drain overlay An etch barrier between the regions, the metal oxide layer comprising the active layer a source oxide layer connected to one side and to the source footprint, located on the active layer a drain oxide layer connected to the drain footprint and located under the data line And a data line oxide layer in contact with the lower surface of the data line.
  • the source of the table below A portion of the face may be in contact with the source footprint and another portion may be associated with the source oxygen Contacting the layer, a portion of the lower surface of the drain may be connected to the drain coverage region Touch, another portion may be in contact with the drain oxide layer.
  • the manufacturing method further includes the step of forming an etch barrier layer a pattern, the etch stop layer is over the active layer, and the etch stop layer is only Covering the etch stop coverage area.
  • the metal oxide layer may be made of ZnO, InZnO, or It is made of any one of ZnSnO, GaInZnO, and ZrInZnO.
  • a display device is provided, the display device package The above array substrate provided by the embodiment of the invention is included.
  • the source and the drain of the tube are made of metal (for example, any one of aluminum, molybdenum, and copper).
  • the corrosion resistance of the metal oxide layer is stronger than that of the metal material, so a metal oxide layer is disposed on a portion of the data line connected to the source of the oxide thin film transistor Below, that is, below the portion where the data line and the gate line overlap, can be formed in the etching including the source Prevents the source of the data line and the oxide thin film transistor when patterning the drain, drain, and data lines a lower surface of a portion where the poles are connected, that is, a lower surface of a portion where the data line and the gate line overlap Corroded by the etching solution.
  • the data line can be prevented due to the metal layer and the etch barrier layer
  • the existence of a bubble-like gap is corroded by the etching liquid, thereby improving the overallity of the array substrate quality.
  • FIG. 1 is a cross-sectional view of a portion of an array substrate in the prior art
  • FIG. 2 is a top plan view of a first embodiment of an array substrate according to an embodiment of the present invention
  • Figure 3 is a cross-sectional view of the array substrate shown in Figure 2 taken along line A-A;
  • FIG. 4 is a top plan view of a second embodiment of an array substrate according to an embodiment of the present invention.
  • Figure 5 is a cross-sectional view of the array substrate shown in Figure 4 taken along line B-B.
  • an array substrate in an embodiment of the present invention, the array substrate The invention includes a plurality of data lines 50, a plurality of gate lines 92 and a plurality of oxide thin film transistors, and a plurality of numbers
  • the line 50 and the plurality of gate lines 92 are interdigitated to divide the array substrate into a plurality of pixel sheets
  • the oxide thin film transistor is disposed in each of the pixel units.
  • the array The substrate further includes an oxidation disposed at least under a portion where the data line 50 overlaps the gate line 92
  • the object layer 60, and the upper surface of the oxide layer 60 is in contact with the lower surface of the data line 50.
  • the data line 50, the source 30 of the oxide thin film transistor, and the drain 40 are all made of metal (for example, any one of aluminum, molybdenum, and copper), the corrosion resistance of the oxide layer 60
  • the force is stronger than the metal material, so by setting the oxide layer 60 in the data Below the portion where the line 50 is connected to the source 30 of the oxide thin film transistor, that is, the data line 50 below the portion overlapping the gate line 92, which may be formed by etching including the source 30 and the drain
  • the portion where the data line 50 is connected to the source 30 is prevented.
  • a portion, that is, a lower surface of a portion where the data line 50 overlaps the gate line 92 is etched by the etching liquid, Thereby improving the overall quality of the array substrate.
  • the orientation words "upper and lower” as used in the present invention refer to FIG. 3. And the "up and down” directions in Figure 5.
  • the pattern of the gate line 92 includes The pattern of the gate electrode 90 is used, but the invention is not limited thereto.
  • only the portion where the data line 50 overlaps the gate line 92 may be An oxide layer 60 is disposed under the minute. In addition, it can overlap each of the data lines and the gate lines An oxide layer is disposed at a portion, the width of the oxide layer being the same as the width of the data line, The length of the oxide layer is the same as the width of the gate line.
  • the oxide layer 60 may be disposed under the entire data line 50 and The size of the oxide layer 60 corresponds to the size of the data line 50, as shown in FIG. Better protection of the lower surface of the data line 50 from corrosion, improving the overall quality of the array substrate.
  • the specific material of the oxide layer there is no particular limitation on the specific material of the oxide layer. As long as the oxide layer is more resistant to corrosion than the metal forming the data line 50.
  • the active layer 10 is made of the same material to form the oxide layer 60. For example, you can use ZnO, Any one of InZnO, ZnSnO, GaInZnO, and ZrInZnO is made active
  • the layer 10 has better corrosion resistance than the metal material from which the data line 50 is formed. It is corrosive, and the above materials also have good flexibility.
  • an etch stop layer 20 may be disposed over the active layer 10 to avoid engraving When the source and the drain of the oxide thin film transistor are etched, the etching liquid penetrates into the active layer.
  • oxide layer 60 and the active layer 10 are made of the same material, The oxide layer 60 and the active layer 10 are simultaneously formed in the same step patterning process.
  • the specific structure of the oxide thin film transistor is not There are special restrictions.
  • the oxide thin film transistor The source 30 and the drain 40 are located above the active layer 10 of the oxide thin film transistor, And the source 30 and the drain 40 of the oxide thin film transistor are respectively blocked by penetration etching
  • the first via 31 and the second via 41 of the layer 20 are connected to the active layer 10, and the data line 50 is shaped Formed on the upper surface of the oxide layer 60, the data line 50 is formed at least partially through the engraving
  • the recess of the barrier layer 20 is in contact with the oxide layer 60.
  • FIG. 3 is only a schematic diagram, and adaptively indicates an etch barrier layer,
  • the positional relationship between the active layers of the oxide layer is not an etch barrier layer or an oxide layer active layer
  • the oxide thin film transistor has a bottom a gate structure, therefore, the gate 90 is disposed under the active layer 10, the gate 90 and the active layer 10
  • a gate insulating layer 91 is disposed between the active layer 10 and the oxide layer 60 disposed on the gate insulating layer
  • the upper surface of 91, and the etch stop layer 20 covers the entire substrate.
  • the data line 50 Contacting the oxide layer 60 and forming an oxidation by passing through the recess of the etch stop layer 20 On the upper surface of the object layer 60, the data line 50 is connected to the source 30 of the oxide thin film transistor Pick up.
  • the etch stop layer 20 may also cover only the active layer 10.
  • the common electrode 70 and the pixel electrode in FIG. 3 are omitted in FIG. 80 and passivation layer 81. Also, in the embodiment shown in FIG. 3, the common electrode 70 Located above the pixel electrode 80, the pixel electrode 80 directly leaks with the oxide thin film transistor The pole 40 is connected. Both the gate insulating layer 91 and the etch stop layer 20 may be made of a silicon dioxide material. production.
  • the thin film transistor has The source layer 10 may include a source footprint 11 , a drain footprint 13 , and a source footprint An etch barrier between the 11 and the drain footprint 13 covers the region 12, and the oxide layer is included a source oxide layer 61 on one side of the active layer 10 and connected to the source cover region 11 a drain oxide layer 62 on the other side of the source layer 10 and connected to the drain footprint 13 and located at a data line oxide layer 63 below the data line and in contact with the lower surface of the data line, A portion of the lower surface of the source 30 of the thin film transistor is in contact with the source footprint 11 .
  • Another portion is in contact with the source oxide layer 61, and the lower surface of the drain transistor 40 of the thin film transistor One portion of the face is in contact with the drain footprint 13 and the other portion is in contact with the drain oxide layer 62.
  • the lower surface of the etch stop layer 20 is in contact with the etch stop layer footprint 12.
  • the etch stop layer 20 is only located in the etch stop layer coverage area. Above the 12, and other portions of the data line 50 (ie, removed from the source 30) A data line oxide layer 63 is disposed below the remaining area of the portion, in logarithm More comprehensive protection is provided according to line 50.
  • the number The line oxide layer 63 may be formed on the gate insulating layer and disposed in the same layer as the active layer 10, and The passivation layer 81 covers the data line 50, the source 30, and the drain 40. Easy to understand, the figure The pixel electrode and the common electrode in Fig. 5 are omitted in 4.
  • the etch stop layer 20 may be formed using an oxide of silicon (eg, SiO 2 ) and/or a nitride of silicon (SiNx).
  • the oxide thin film transistors each have a bottom gate structure, but the present invention is not limited thereto. root
  • the oxide in the array substrate according to an embodiment of the present invention may also have a top gate structure.
  • a method of manufacturing the above array substrate includes the steps of: forming a pattern including gate lines; forming including a thin film crystal a pattern of an active layer of the tube; forming a pattern comprising a metal oxide layer; and forming the data including a pattern of source and drain of the line and the thin film transistor, the oxide layer being disposed at least in the a portion of the data line that overlaps the gate line, and an upper surface of the oxide layer It is in contact with the lower surface of the data line.
  • the oxide layer may protect a portion of the data line overlapping the gate line
  • the lower end surface is not etched by the gap between the data line and the material around the data line Liquid corrosion.
  • the oxide layer prevents the data line from coming into contact with the source of the thin film transistor The portion is etched by the etching solution.
  • the oxide layer may correspond to the entire strip Said data line. That is, the entire lower end surface of the data line may be on the upper side of the oxide layer The surfaces are in contact, that is, the data lines may be formed on the upper surface of the oxide layer.
  • the oxide layer may be An active layer of the oxide thin film transistor is located in the same layer, and the oxide layer is oxidized
  • the active layer of the thin film transistor is made of the same material.
  • the manufacturer The method includes forming the oxide while forming an active layer of the oxide thin film transistor Floor. That is, the active layer including the oxide thin film transistor is formed by the same step patterning process A pattern of layers and the oxide layer.
  • the specific type of the patterning process is not limited.
  • the oxide thin film transistor can be simultaneously formed by a patterning process such as transfer, printing, or the like An active layer and the oxide layer.
  • the active layer and the forming layer may be formed as follows The oxide layer: first, an oxide film is deposited on the substrate; and then a photolithography process is utilized A pattern including the active layer and the oxide layer is formed.
  • the active layer of the oxide thin film transistor may be made of ZnO, Any one of InZnO, ZnSnO, GaInZnO, and ZrInZnO is used.
  • the oxidation The layer may be any one of ZnO, InZnO, ZnSnO, GaInZnO, and ZrInZnO. Made of species.
  • the step of forming the oxide layer 60 and the forming a step of forming a pattern of the data line 50 and the source 30 and the drain 40 of the thin film transistor may include the following steps performed in sequence: forming including an etch barrier a pattern of the layer 20, the etch stop layer 20 is located on the active layer 10 and the oxide Above the layer 60; and forming the first via 31, the second via 41, and the data line recess, The first via 31 and the second via 41 both pass through the etch stop layer 20 to reach the location An active layer 10 of an oxide thin film transistor, the data line groove passing through the etch stop The barrier layer 20 reaches the oxide layer 60.
  • the formation includes the source 30, the drain 40, and the data line 50.
  • the source 30 is in phase with the active layer 10 through the first via 31 Connecting (the material of the active layer fills the first via to form the first electrode in the first via, The first electrode connects the source and the active layer, and the drain 40 passes through the second via 41 is connected to the active layer 10 (the material of the active layer fills the second via, forming the first a second electrode in the second via, the second electrode connecting the drain and the active layer), the data line At least a portion of 50 is located in the data line recess and is formed in the oxide layer 60 On the upper surface.
  • a worker who forms a pattern including a source, a drain, and a data line Art is not specifically limited, and can be formed by processes such as printing and transfer, including source and drain.
  • the pattern of the pole and the data line can also be formed by a conventional lithography patterning process including the source, The pattern of the drain and data lines.
  • a gate electrode 90 including a gate line 92 and an oxide thin film transistor is formed on a glass substrate Graphic
  • a pattern including a source 30, a drain 40, and a data line 50 is formed, the source 31 Connected to the active layer 10 through a first via 31, the drain 40 passes through the second A via 41 is connected to the active layer 10, at least a portion of the data line 50 (at least the lower half) Partially located in the data line groove, and the lower surface of the data line 50 is oxidized Contact layer 60 is in contact;
  • a pattern including the pixel electrode 80 is formed, and a portion of the pixel electrode 80 covers the portion At least a portion of the drain 40;
  • a pattern including the common electrode 70 is formed.
  • the active layer of the thin film transistor includes a source cover a region 11, a drain footprint 13 and between the source footprint and the drain footprint An etch barrier covering region 12, the oxide layer comprising one side of the active layer and a source oxide layer 61 connected to the source footprint, on the other side of the active layer And a drain oxide layer 62 and a data line oxide layer 63 connected to the drain footprint.
  • the forming includes a source, a drain, and a step of patterning the data line, a portion of the lower surface of the source is covered with the source a region contact, another portion in contact with the source oxide layer, and a lower surface of the drain A portion is in contact with the drain footprint and another portion is in contact with the drain oxide layer.
  • the source 30 a portion of the lower surface is in contact with the source footprint 11 and another portion is opposite the source
  • the oxide layer 61 is in contact with a portion of the lower surface of the drain 40 and the drain footprint 13 contact, another portion is in contact with the drain oxide layer 62, and the data line 50 Formed on an upper surface of the data line oxide layer 63;
  • a pattern including a common electrode is formed.
  • a pixel electrode connected to the drain may be formed, and then a passivation layer covering the substrate is formed, Finally, a common electrode is formed on the passivation layer.
  • a display device the display device
  • the array substrate is included, wherein the array substrate is the above array substrate provided by the present invention.
  • the source and the drain of the tube are made of metal (for example, any one of aluminum, molybdenum, and copper).
  • the corrosion resistance of the oxide layer is stronger than that of the metal material, and therefore, by oxidation
  • the layer is disposed below a portion where the data line is connected to the source of the oxide thin film transistor, that is, Below the portion where the data line and the gate line overlap, the source and the drain may be formed by etching
  • the pattern of the data line prevents the data line from being connected to the source of the oxide thin film transistor a portion of the lower surface, that is, a lower surface of a portion where the data line and the gate line overlap are etched by the liquid etch eclipse.
  • the data line can be prevented from being caught by the steam drum between the metal layer and the etch barrier layer.
  • the gap is etched by the etching liquid, thereby improving the overall quality of the array substrate.
  • An oxide thin film transistor is used in the display device provided by the present invention, which has High mobility, therefore, the display device provided by the present invention can have a large area. Therefore, it can be applied to electronic devices such as computers and televisions.
  • the display device of the present invention may be a liquid crystal panel, a liquid crystal display, or a liquid crystal Vision, OLED display panel, OLED display, OLED TV, mobile phone, PDA Or an electronic book or other device.

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Abstract

　本发明提供一种阵列基板，该阵列基板包括多条数据线、多条栅线和多个氧化物薄膜晶体管，多条所述数据线与多条所述栅线互相交错并将所述阵列基板划分为多个像素单元，每个所述像素单元内均设置有所述氧化物薄膜晶体管，所述阵列基板还包括至少设置在所述数据线与所述栅线相交叠的部分的下方的金属氧化物层，该金属氧化物层的上表面与所述数据线的下表面相接触。本发明还提供了所述阵列基板的制造方法以及包括所述阵列基板的显示装置。

Description

阵列基板及其制造方法和显示装置 技术领域
本发明涉及显示技术领域，具体地，涉及一种阵列基板以及该 阵列基板的制造方法，以及一种包括所述阵列基板的显示装置。
背景技术
显示装置的显示面板包括阵列基板，该阵列基板包括互相交错 的多条栅线和多条数据线，所述栅线和数据线将阵列基板划分为多个 像素单元，每个像素单元内都设置有薄膜晶体管。传统的阵列基板中 的薄膜晶体管通常为非晶硅薄晶体管，而非晶硅薄膜晶体管的迁移率 一般在0.5cmW·S左右。
近年来随着平板显示器尺寸的不断增大，驱动电路的频率不断 提高，现有的非晶硅薄膜晶体管迁移率很难满足需求。例如，当液晶 显示器尺寸超过80英寸时，驱动频率应当为120Hz，在这种情况下 需要薄膜晶体管的迁移率在1cmW·S以上，因此，现在非晶硅薄膜晶 体管的迁移率显然很难满足上述要求。
氧化物薄膜晶体管具有迁移率高、均一性好、透明、制作工艺 简单等优点，可以更好地满足大尺寸显示器对薄膜晶体管迁移率的要 求。
图1中所示的是一种典型包括氧化物薄膜晶体管的阵列基板的 剖视图。由于氢键对由金属氧化物制成的有源层影响较大，因此，如 图1中所示，所述阵列基板包括位于氧化物薄膜晶体管的有源层10 上方的刻蚀阻挡层20，氧化物薄膜晶体管的源极30和漏极40通过 穿过刻蚀阻挡层20的过孔与氧化物薄膜晶体管的有源层10连接，从 而可以在刻蚀氧化物薄膜晶体管的源极和漏极时，防止刻蚀液渗透进 入有源层。
为了节约制造成本，通常采用二氧化硅制成刻蚀阻挡层20。但 是，由于二氧化硅的致密性较差，所以在薄膜晶体管的源漏金属层与 刻蚀阻挡层20之间存在汽包状间隙。在对源漏金属层进行刻蚀时， 刻蚀液会沿着这种气泡状间隙渗入到数据线50与刻蚀阻挡层20的接 触面，这样就会导致数据线50上与薄膜晶体管的源极30相连接的部 分被腐蚀，从而降低了阵列基板的总体质量。
因此，如何防止刻蚀液腐蚀数据线上与薄膜晶体管的源极相接 触的部分成为本领域亟待解决的技术问题。
发明内容
本发明的目的在于提供一种阵列基板及其制造方法和包括所述 阵列基板的显示装置。所述阵列基板中数据线上与薄膜晶体管的源极 相接触的部分不易被腐蚀。
为了实现上述目的，作为本发明的一个方面，提供一种阵列基 板，该阵列基板包括多条数据线、多条栅线和多个氧化物薄膜晶体管， 多条所述数据线与多条所述栅线互相交错并将所述阵列基板划分为 多个像素单元，每个所述像素单元内均设置有所述氧化物薄膜晶体 管，其中，所述阵列基板还包括至少设置在所述数据线与所述栅线相 交叠的部分的下方的金属氧化物层，该金属氧化物层的上表面与所述 数据线的下表面相接触。
可以在每个所述数据线与所述栅线的交叠处均设置有所述金属 氧化物层，所述金属氧化物层的宽度可以与所述数据线的宽度相同， 所述金属氧化物层的长度可以与所述栅线的宽度相同。
可替代地，所述金属氧化物层的大小可以对应于所述数据线的 大小。
所述金属氧化物层和所述氧化物薄膜晶体管的有源层可以由同 种材料制成。在所述氧化物薄膜晶体管的有源层上方可以设置有刻蚀 阻挡层。
所述金属氧化物层可以由ZnO、InZnO、ZnSnO、GaInZnO、 ZrInZnO中的任意一种材料制成。
在上述阵列基板中，所述氧化物薄膜晶体管的源极和漏极可以 位于所述氧化物薄膜晶体管的有源层的上方，且所述氧化物薄膜晶体 管的源极和漏极可以分别通过穿过所述刻蚀阻挡层的第一过孔和第 二过孔与所述有源层相连，所述数据线可以通过至少部分形成于穿过 所述刻蚀阻挡层的凹槽内而与所述金属氧化物层相接触。
在上述阵列基板中，可替代地，所述薄膜晶体管的有源层可以 包括源极覆盖区、漏极覆盖区和位于所述源极覆盖区和所述漏极覆盖 区之间的刻蚀阻挡层覆盖区，所述金属氧化物层包括位于所述有源层 一侧且与所述源极覆盖区连接的源极氧化物层、位于所述有源层另一 侧且与所述漏极覆盖区连接的漏极氧化物层、以及位于所述数据线下 方且与所述数据线的下表面接触的数据线氧化物层。所述薄膜晶体管 的源极的下表面的一部分可以与所述源极覆盖区接触，另一部分可以 与所述源极氧化物层接触，所述薄膜晶体管的漏极的下表面的一部分 可以与所述漏极覆盖区接触，另一部分可以与所述漏极氧化物层接 触，所述刻蚀阻挡层的下表面可以仅与所述刻蚀阻挡层覆盖区接触。
作为本发明的另一个方面，提供一种阵列基板的制造方法，所 述制造方法包括以下步骤：形成包括栅线的图形；形成包括薄膜晶体 管的有源层的图形；形成包括金属氧化物层的图形；以及形成包括数 据线和薄膜晶体管的源极、漏极的图形，其中，所述金属氧化物层至 少设置在所述数据线与所述栅线相交叠的部分的下方，并且所述金属 氧化物层的上表面与所述数据线的下表面相接触。
所述金属氧化物层可以与所述氧化物薄膜晶体管的有源层位于 同一层，所述金属氧化物层可以与所述氧化物薄膜晶体管的有源层由 同种材料制成，并且可以在同一步构图工艺中形成包括所述氧化物薄 膜晶体管有源层和所述金属氧化物层的图形。
在上述制造方法中，在所述形成包括所述金属氧化物层的图形 的步骤与所述形成包括数据线和薄膜晶体管的源极、漏极的图形的步 骤之间，所述制造方法还可以包括以下步骤：形成包括刻蚀阻挡层的 图形，所述刻蚀阻挡层位于所述有源层上方；以及形成第一过孔、第 二过孔和数据线凹槽，所述第一过孔和所述第二过孔均穿过所述刻蚀 阻挡层到达所述氧化物薄膜晶体管的有源层，所述数据线凹槽穿过所 述刻蚀阻挡层到达所述金属氧化物层。在所述形成包括数据线和薄膜 晶体管的源极、漏极的图形的步骤中，所述源极可以通过第一过孔与 所述有源层相连，所述漏极可以通过所述第二过孔与所述有源层相 连，所述数据线位于所述数据线凹槽中，且所述数据线的下表面与所 述金属氧化物层接触。
在上述制造方法中，可替代地，所述薄膜晶体管的有源层可以 包括源极覆盖区、漏极覆盖区和位于所述源极覆盖区和所述漏极覆盖 区之间的刻蚀阻挡层覆盖区，所述金属氧化物层包括位于所述有源层 一侧且与所述源极覆盖区连接的源极氧化物层、位于所述有源层另一 侧且与所述漏极覆盖区连接的漏极氧化物层、以及位于所述数据线下 方且与所述数据线的下表面接触的数据线氧化物层。所述源极的下表 面的一部分可以与所述源极覆盖区接触，另一部分可以与所述源极氧 化物层接触，所述漏极的下表面的一部分可以与所述漏极覆盖区接 触，另一部分可以与所述漏极氧化物层接触。在所述形成包括所述金 属氧化物层的步骤和所述形成包括数据线和薄膜晶体管的源极、漏极 的图形的步骤之间，所述制造方法还包括步骤：形成包括刻蚀阻挡层 的图形，所述刻蚀阻挡层位于所述有源层上方，且所述刻蚀阻挡层仅 覆盖所述刻蚀阻挡层覆盖区。
在上述制造方法中，所述金属氧化物层可以由ZnO、InZnO、 ZnSnO、GaInZnO、ZrInZnO中的任意一种材料制成。
作为本发明的再一个方面，提供一种显示装置，该显示装置包 括本发明实施例所提供的上述阵列基板。
在根据本发明实施例的阵列基板中，数据线、氧化物薄膜晶体 管的源极以及漏极均由金属(例如，铝、钼、铜中的任意一种)制成， 金属氧化物层的防腐蚀能力比金属材料防腐蚀能力强，因此，通过将 金属氧化物层设置在数据线与氧化物薄膜晶体管的源极相连的部分 下方，即，数据线与栅线相交叠的部分下方，可以在刻蚀形成包括源 极、漏极以及数据线的图形时，防止数据线与氧化物薄膜晶体管的源 极相连接的部分的下表面，即，数据线与栅线相交叠的部分的下表面 被刻蚀液腐蚀。进一步地，通过将数据线设置在不同于刻蚀阻挡层的 金属氧化物层的上表面上，可以防止数据线由于金属层与刻蚀阻挡层 之间存在的汽包状间隙而被刻蚀液腐蚀，从而提高了阵列基板的总体 质量。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一 部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本 发明的限制。在附图中：
图1是现有技术中的阵列基板的一部分的剖视图；
图2是本发明实施例所提供的阵列基板的第一实施例的俯视图；
图3是图2中所示的阵列基板的沿A-A折线截取的剖视图；
图4是本发明实施例所提供的阵列基板的第二实施例的俯视图；
图5是图4中所示的阵列基板的沿B-B折线截取的剖视图。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理 解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不 用于限制本发明。
作为本发明的一个方面，在根据本发明实施例的阵列基板的第 一实施例中，如图2至图5中所示，提供一种阵列基板，该阵列基板 包括多条数据线50、多条栅线92和多个氧化物薄膜晶体管，多条数 据线50与多条栅线92互相交错，将所述阵列基板划分为多个像素单 元，每个所述像素单元内均设置有所述氧化物薄膜晶体管。所述阵列 基板还包括至少设置在数据线50与栅线92相交叠的部分下方的氧化 物层60，且该氧化物层60的上表面与数据线50的下表面接触。
数据线50、氧化物薄膜晶体管的源极30以及漏极40均由金属 (例如，铝、钼、铜中的任意一种)制成，氧化物层60的防腐蚀能 力比金属材料防腐蚀能力强，因此，通过将氧化物层60设置在数据 线50与氧化物薄膜晶体管的源极30相连接的部分下方，即，数据线 50与栅线92相重叠的部分的下方，可以在刻蚀形成包括源极30、漏 极40以及数据线50的图形时，防止数据线50与源极30相连接的部 分，即，数据线50与栅线92相重叠的部分的下表面被刻蚀液腐蚀， 从而提高了阵列基板的总体质量。
应当理解的是，本发明中所用的方位词“上、下”均是指图3 和图5中的“上、下”方向。此外，在图2中，栅线92的图案包含 了栅极90的图案，但本发明不限于此。
在本发明实施例中，可以仅在数据线50与栅线92相重叠的部 分的下方设置氧化物层60。此外，可以在每个数据线与栅线的交叠 处都设置氧化物层，所述氧化物层的宽度与所述数据线的宽度相同， 所述氧化物层的长度与所述栅线的宽度相同。
可替代地，氧化物层60可以设置在整个数据线50的下方并且 氧化物层60的大小对应于数据线50的大小，如图2所示，从而可以 更好地保护数据线50的下表面不被腐蚀，提高阵列基板的总体质量。
在本发明实施例中，对氧化物层的具体材料也没有特殊的限制， 只要氧化物层比形成数据线50的金属耐腐蚀即可。为了简化制备工 艺，提高阵列基板的生产效率，可以利用与所述氧化物薄膜晶体管的 有源层10相同的材料来制成氧化物层60。例如，可以利用ZnO、 InZnO、ZnSnO、GaInZnO、ZrInZnO中的任意一种材料来制成有源 层10，与制成数据线50的金属材料相比，上述材料具有较好的耐腐 蚀性，而且上述材料还具有较好的柔韧性。
此外，可以在有源层10的上方设置刻蚀阻挡层20，以避免在刻 蚀氧化物薄膜晶体管的源极和漏极时，刻蚀液渗透进入有源层。
由于氧化物层60与有源层10采用相同的材料制成，因此，可 以在同一步构图工艺中同时形成氧化物层60和有源层10。
在本发明实施例中，对所述氧化物薄膜晶体管的具体结构也没 有特殊的限制。例如，如图2和图3中所示，所述氧化物薄膜晶体管 的源极30和漏极40位于所述氧化物薄膜晶体管的有源层10的上方， 且所述氧化物薄膜晶体管的源极30和漏极40分别通过穿透刻蚀阻挡 层20的第一过孔31和第二过孔41与有源层10相连，数据线50形 成在氧化物层60的上表面上，数据线50通过至少部分形成于穿过刻 蚀阻挡层20的凹槽内而与氧化物层60相接触。
需要指出的是，图3仅为示意图，适应性地表示出刻蚀阻挡层、 氧化物层有源层之间的位置关系，并非刻蚀阻挡层、氧化物层有源层 的实际尺寸关系。所示的阵列基板中，所述氧化物薄膜晶体管具有底 栅结构，因此，栅极90设置在有源层10下方，栅极90和有源层10 之间设置有栅绝缘层91，有源层10和氧化物层60设置在栅绝缘层 91的上表面上，且刻蚀阻挡层20覆盖整个基板。此外，数据线50 通过穿过刻蚀阻挡层20的凹槽来与氧化物层60接触并且形成在氧化 物层60的上表面上，数据线50与氧化物薄膜晶体管的源极30相连 接。当然，刻蚀阻挡层20也可以仅覆盖有源层10。
应当理解的是，图2中省略了图3中的公共电极70、像素电极 80和钝化层81。并且，在图3中所示的实施方式中，公共电极70 位于像素电极80的上方，像素电极80直接与氧化物薄膜晶体管的漏 极40相连。栅绝缘层91与刻蚀阻挡层20均可以采用二氧化硅材料 制成。
在根据本发明实施例的阵列基板的第二实施例中，主要对不同 于第一实施例的构造进行描述。如图4和图5所示，薄膜晶体管的有 源层10可以包括源极覆盖区11、漏极覆盖区13和位于源极覆盖区 11和漏极覆盖区13之间的刻蚀阻挡层覆盖区12，氧化物层包括位于 有源层10一侧且与源极覆盖区11连接的源极氧化物层61、位于有 源层10另一侧且与漏极覆盖区13连接的漏极氧化物层62和位于所 述数据线下方且与所述数据线的下表面接触的数据线氧化物层63， 所述薄膜晶体管的源极30的下表面的一部分与源极覆盖区11接触， 另一部分与源极氧化物层61接触，所述薄膜晶体管的漏极40的下表 面的一部分与漏极覆盖区13接触，另一部分与漏极氧化物层62接触， 刻蚀阻挡层20的下表面与刻蚀阻挡层覆盖区12接触。
如图4和图5中所示，刻蚀阻挡层20仅位于刻蚀阻挡层覆盖区 12的上方，并且数据线50上其他部分(即除去与源极30相连接的 部分之外剩下的区域)的下方均设置有数据线氧化物层63，以对数 据线50进行更加全面的保护。在此情况下，如图4和图5所示，数 据线氧化物层63可以形成在栅绝缘层上并与有源层10同层设置，并 且钝化层81覆盖数据线50、源极30和漏极40。容易理解的是，图 4中省去了图5中的像素电极和公共电极。
在本发明实施例中，可以利用硅的氧化物(如，SiO 2)和/或硅 的氮化物(SiNx)形成刻蚀阻挡层20。
容易理解的是，虽然在阵列基板的上述第一实施例和第二实施 例中，氧化物薄膜晶体管均具有底栅结构，但是本发明不限于此。根 据本发明实施例的阵列基板中的氧化物也可以具有顶栅结构。
作为本发明的另一个方面，提供一种上述阵列基板的制造方法， 该制造方法包括以下步骤：形成包括栅线的图形；形成包括薄膜晶体 管的有源层的图形；形成包括金属氧化物层的图形；和形成包括数据 线和薄膜晶体管的源极、漏极的图形，所述氧化物层至少设置在所述 数据线与所述栅线相交叠的部分的下方，并且所述氧化物层的上表面 与所述数据线的下表面相接触。
所述氧化物层可以保护所述数据线与所述栅线相交叠的部分的 下端面不被沿数据线与该数据线周围的材料之间的间隙渗入的刻蚀 液腐蚀。所述氧化物层可以防止数据线上与薄膜晶体管的源极相接触 的部分被刻蚀液腐蚀。
为了更好地保护所述数据线，所述氧化物层可以对应于整条所 述数据线。即，所述数据线的整个下端面可以均与所述氧化物层的上 表面相接触，即，所述数据线可以形成在所述氧化物层的上表面上。
为了简化制造方法，提高生产效率，所述氧化物层可以与所述 氧化物薄膜晶体管的有源层位于同一层，且所述氧化物层与所述氧化 物薄膜晶体管的有源层由同种材料制成。在这种情况中，所述制造方 法包括在形成所述氧化物薄膜晶体管有源层的同时形成所述氧化物 层。即，通过同一步构图工艺形成包括所述氧化物薄膜晶体管的有源 层和所述氧化物层的图形。
在本发明实施例中，对构图工艺的具体类型并不做限定。例如， 可以通过转印、打印等构图工艺，同时形成所述氧化物薄膜晶体管的 有源层和所述氧化物层。或者，可以按照如下步骤形成所述有源层和 所述氧化物层：首先，在基板上沉积氧化物薄膜；然后利用光刻工艺 形成包括所述有源层和所述氧化物层的图形。
如上文中所述，所述氧化物薄膜晶体管的有源层可以由ZnO、 InZnO、ZnSnO、GaInZnO、ZrInZnO中的任意一种制成。所述氧化 物层可以由ZnO、InZnO、ZnSnO、GaInZnO、ZrInZnO中的任意一 种制成。
为了形成本发明第一实施例的阵列基板(即，图2和图3中所 示的阵列基板)，在所述形成包括所述氧化物层60的步骤与所述形 成包括数据线50和薄膜晶体管的源极30、漏极40的图形的步骤之 间，所述制造方法可以包括依次进行的以下步骤：形成包括刻蚀阻挡 层20的图形，所述刻蚀阻挡层20位于所述有源层10和所述氧化物 层60上方；以及形成第一过孔31、第二过孔41和数据线凹槽，所 述第一过孔31和所述第二过孔41均穿过所述刻蚀阻挡层20到达所 述氧化物薄膜晶体管的有源层10，所述数据线凹槽穿过所述刻蚀阻 挡层20到达所述氧化物层60。
在这种情况中，在所述形成包括源极30、漏极40和数据线50 的图形的步骤中，所述源极30通过第一过孔31与所述有源层10相 连(有源层的材料填充第一过孔，形成位于第一过孔中的第一电极， 该第一电极将源极和有源层相连)，所述漏极40通过所述第二过孔 41与所述有源层10相连(有源层的材料填充第二过孔，形成位于第 二过孔中的第二电极，该第二电极将漏极和有源层相连)，数据线 50的至少一部分位于数据线凹槽中，并且形成在所述氧化物层60的 上表面上。
同样地，本发明中对形成包括源极、漏极和数据线的图形的工 艺并不做具体限定，既可以通过打印、转印等工艺形成包括源极、漏 极和数据线的图形，也可以通过传统的光刻构图工艺形成包括源极、 漏极和数据线的图形。
下面详细介绍图2和图3中所示的阵列基板的制造方法，其包 括以下步骤：
在玻璃基板上形成包括栅线92和氧化物薄膜晶体管的栅极90 的图形；
形成栅绝缘层91；
形成包括薄膜晶体管的有源层10和氧化物层60的图形；
形成刻蚀阻挡层20，该刻蚀阻挡层20覆盖进行了上述步骤的玻 璃基板，即，覆盖了所述有源层20和所述氧化物层60；
形成第一过孔31、第二过孔41和数据线凹槽，所述第一过孔 31和所述第二过孔41到达所述有源层10，所述数据线凹槽到达所述 氧化物层60；
形成包括源极30、漏极40和数据线50的图形，所述源极31 通过第一过孔31与所述有源层10相连，所述漏极40通过所述第二 过孔41与所述有源层10相连，数据线50的至少一部分(至少下半 部分)位于数据线凹槽中，并且所述数据线50的下表面与所述氧化 物层60接触；
形成包括像素电极80的图形，该像素电极80的一部分覆盖所 述漏极40的至少一部分；
形成钝化层81，该钝化层81覆盖进行了上述步骤的玻璃基板； 以及
形成包括公共电极70的图形。
在根据本发明第二实施例的阵列基板(即，图4和图5中所示 的阵列基板)的制造方法中，所述薄膜晶体管的有源层包括源极覆盖 区11、漏极覆盖区13和位于所述源极覆盖区和所述漏极覆盖区之间 的刻蚀阻挡层覆盖区12，所述氧化物层包括位于所述有源层一侧且 与所述源极覆盖区连接的源极氧化物层61、位于所述有源层另一侧 且与所述漏极覆盖区连接的漏极氧化物层62和数据线氧化物层63。
在上述阵列基板的制造方法中，在所述形成包括源极、漏极和 数据线的图形的步骤中，所述源极的下表面的一部分与所述源极覆盖 区接触，另一部分与所述源极氧化物层接触，所述漏极的下表面的一 部分与所述漏极覆盖区接触，另一部分与所述漏极氧化物层接触。
下面详细介绍图4和图5中所示的阵列基板的制造方法，其包 括以下步骤：
在玻璃基板上形成包括栅极90和栅线92的图形；
形成栅绝缘层91；
在栅绝缘层91上形成包括有源层和氧化物层的图形；
形成包括刻蚀阻挡层20的图形，该刻蚀阻挡层20仅覆盖所述 刻蚀阻挡层覆盖区12；
形成包括源极30、漏极40和数据线50的图形，所述源极30 的下表面的一部分与所述源极覆盖区11接触，另一部分与所述源极 氧化物层61接触，所述漏极40的下表面的一部分与所述漏极覆盖区 13接触，另一部分与所述漏极氧化物层62接触，并且所述数据线50 形成在所述数据线氧化物层63的上表面上；
形成包括像素电极的图形；
在进行了上述步骤的玻璃基板上形成钝化层81；以及
形成包括公共电极的图形。
与图2和图3中所示的实施例相比，图4和图5中所示的实施 例无需加工过孔。
容易理解的是，在形成了氧化物薄膜晶体管的源极和漏极之后， 可以形成与所述漏极相连的像素电极，随后形成覆盖基板的钝化层， 并最后在钝化层上形成公共电极。这些步骤都是本领域所公知的，因 此不再赘述。
作为本发明的另一个方面，还提供一种显示装置，该显示装置 包括阵列基板，其中，所述阵列基板为本发明所提供的上述阵列基板。
在根据本发明实施例的阵列基板中，数据线、氧化物薄膜晶体 管的源极以及漏极均由金属(例如，铝、钼、铜中的任意一种)制成， 氧化物层的防腐蚀能力比金属材料防腐蚀能力强，因此，通过将氧化 物层设置在数据线与氧化物薄膜晶体管的源极相连的部分下方，即， 数据线与栅线相交叠的部分下方，可以在刻蚀形成包括源极、漏极以 及数据线的图形时防止数据线与氧化物薄膜晶体管的源极相连接的 部分的下表面，即，数据线与栅线相交叠的部分的下表面被刻蚀液腐 蚀。进一步地，通过将数据线设置在不同于刻蚀阻挡层的氧化物层的 上表面上，可以防止数据线由于金属层与刻蚀阻挡层之间存在的汽包 状间隙而被刻蚀液腐蚀，从而提高了阵列基板的总体质量。
本发明所提供的显示装置中使用了氧化物薄膜晶体管，具有较 高的迁移率，因此，本发明所提供的显示装置可以具有较大的面积， 从而可以应用于电脑、电视等电子设备中。
本发明所述的显示装置可以为液晶面板、液晶显示器、液晶电 视、OLED显示面板、OLED显示器、OLED电视、手机、掌上电脑 或者电子书等装置。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用 的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术 人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和 改进，这些变型和改进也视为本发明的保护范围。

Claims (14)

  1. 一种阵列基板，该阵列基板包括多条数据线、多条栅线和多 个氧化物薄膜晶体管，多条所述数据线与多条所述栅线互相交错并将 所述阵列基板划分为多个像素单元，每个所述像素单元内均设置有所 述氧化物薄膜晶体管，其特征在于，
    所述阵列基板还包括至少设置在所述数据线与所述栅线相交叠 的部分的下方的金属氧化物层，该金属氧化物层的上表面与所述数据 线的下表面相接触。
  2. 根据权利要求1所述的阵列基板，其特征在于，在每个所述 数据线与所述栅线的交叠处均设置有所述金属氧化物层，所述金属氧 化物层的宽度与所述数据线的宽度相同，所述金属氧化物层的长度与 所述栅线的宽度相同。
  3. 根据权利要求1所述的阵列基板，其特征在于，所述金属氧 化物层的大小对应于所述数据线的大小。
  4. 根据权利要求1至3中任意一项所述的阵列基板，其特征在 于，所述金属氧化物层和所述氧化物薄膜晶体管的有源层由同种材料 制成。
  5. 根据权利要求4所述的阵列基板，其特征在于，在所述氧化 物薄膜晶体管的有源层上方设置有刻蚀阻挡层。
  6. 根据权利要求4所述的阵列基板，其特征在于，所述金属氧 化物层由ZnO、InZnO、ZnSnO、GaInZnO、ZrInZnO中的任意一种 材料制成。
  7. 根据权利要求5所述的阵列基板，其特征在于，所述氧化物 薄膜晶体管的源极和漏极位于所述氧化物薄膜晶体管的有源层的上 方，且所述氧化物薄膜晶体管的源极和漏极分别通过穿过所述刻蚀阻 挡层的第一过孔和第二过孔与所述有源层相连，所述数据线通过至少 部分形成于穿过所述刻蚀阻挡层的凹槽内而与所述金属氧化物层相 接触。
  8. 根据权利要求5所述的阵列基板，其特征在于，所述薄膜晶 体管的有源层包括源极覆盖区、漏极覆盖区和位于所述源极覆盖区和 所述漏极覆盖区之间的刻蚀阻挡层覆盖区，
    所述金属氧化物层包括位于所述有源层一侧且与所述源极覆盖 区连接的源极氧化物层、位于所述有源层另一侧且与所述漏极覆盖区 连接的漏极氧化物层、以及位于所述数据线下方且与所述数据线的下 表面接触的数据线氧化物层，
    所述薄膜晶体管的源极的下表面的一部分与所述源极覆盖区接 触，另一部分与所述源极氧化物层接触，所述薄膜晶体管的漏极的下 表面的一部分与所述漏极覆盖区接触，另一部分与所述漏极氧化物层 接触，所述刻蚀阻挡层的下表面仅与所述刻蚀阻挡层覆盖区接触。
  9. 一种阵列基板的制造方法，其特征在于，所述制造方法包括 以下步骤：
    形成包括栅线的图形；
    形成包括薄膜晶体管的有源层的图形；
    形成包括金属氧化物层的图形；以及
    形成包括数据线和薄膜晶体管的源极、漏极的图形，
    其中，所述金属氧化物层至少设置在所述数据线与所述栅线相 交叠的部分的下方，并且所述金属氧化物层的上表面与所述数据线的 下表面相接触。
  10. 根据权利要求9所述的制造方法，其特征在于，所述金属 氧化物层与所述氧化物薄膜晶体管的有源层位于同一层，所述金属氧 化物层与所述氧化物薄膜晶体管的有源层由同种材料制成，并且在同 一步构图工艺中形成包括所述氧化物薄膜晶体管有源层和所述金属 氧化物层的图形。
  11. 根据权利要求10所述的制造方法，其特征在于，
    在所述形成包括所述金属氧化物层的图形的步骤与所述形成包 括数据线和薄膜晶体管的源极、漏极的图形的步骤之间，所述制造方 法还包括以下步骤：
    形成包括刻蚀阻挡层的图形，所述刻蚀阻挡层位于所述有源层 上方；以及
    形成第一过孔、第二过孔和数据线凹槽，所述第一过孔和所述 第二过孔均穿过所述刻蚀阻挡层到达所述氧化物薄膜晶体管的有源 层，所述数据线凹槽穿过所述刻蚀阻挡层到达所述金属氧化物层，
    其中，在所述形成包括数据线和薄膜晶体管的源极、漏极的图 形的步骤中，所述源极通过所述第一过孔与所述有源层相连，所述漏 极通过所述第二过孔与所述有源层相连，所述数据线位于所述数据线 凹槽中，且所述数据线的下表面与所述金属氧化物层接触。
  12. 根据权利要求10所述的制造方法，其特征在于，
    所述薄膜晶体管的有源层包括源极覆盖区、漏极覆盖区和位于 所述源极覆盖区和所述漏极覆盖区之间的刻蚀阻挡层覆盖区，所述金 属氧化物层包括位于所述有源层一侧且与所述源极覆盖区连接的源 极氧化物层、位于所述有源层另一侧且与所述漏极覆盖区连接的漏极 氧化物层、以及位于所述数据线下方且与所述数据线的下表面接触的 数据线氧化物层，并且
    所述源极的下表面的一部分与所述源极覆盖区接触，另一部分 与所述源极氧化物层接触，所述漏极的下表面的一部分与所述漏极覆 盖区接触，另一部分与所述漏极氧化物层接触，
    在所述形成包括所述金属氧化物层的步骤和所述形成包括数据 线和薄膜晶体管的源极、漏极的图形的步骤之间，所述制造方法还包 括步骤：形成包括刻蚀阻挡层的图形，所述刻蚀阻挡层位于所述有源 层上方，且所述刻蚀阻挡层仅覆盖所述刻蚀阻挡层覆盖区。
  13. 根据权利要求9所述的制造方法，其特征在于，所述金属 氧化物层由ZnO、InZnO、ZnSnO、GaInZnO、ZrInZnO中的任意一 种材料制成。
  14. 一种显示装置，该显示装置包括阵列基板，其特征在于， 所述阵列基板为权利要求1至8中任意一项所述的阵列基板。
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CN105932024B (zh) * 2016-05-05 2019-05-24 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置
CN106252362B (zh) * 2016-08-31 2019-07-12 深圳市华星光电技术有限公司 一种阵列基板及其制备方法
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