CN107065361B - 阵列基板、显示面板和显示装置 - Google Patents

阵列基板、显示面板和显示装置 Download PDF

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CN107065361B
CN107065361B CN201710432950.5A CN201710432950A CN107065361B CN 107065361 B CN107065361 B CN 107065361B CN 201710432950 A CN201710432950 A CN 201710432950A CN 107065361 B CN107065361 B CN 107065361B
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array substrate
thin film
film transistor
electrode
pattern layer
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CN107065361A (zh
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田露
郝金刚
黄东升
张惠博
张鹏曲
严帅
孟国萃
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种阵列基板，所述阵列基板包括衬底基板、栅图形层、有源图形层和源漏图形层，所述栅图形层包括多条栅线，所述源漏图形层包括多条数据线，多条所述栅线和多条所述数据线交叉设置，以将所述阵列基板划分为多个像素单元，所述阵列基板还包括设置在所述像素单元中的薄膜晶体管，所述栅图形层还包括所述薄膜晶体管的栅极，所述源漏图形层还包括所述薄膜晶体管的源极和漏极，所述有源图形层包括所述薄膜晶体管的有源层，其中，所述薄膜晶体管的漏极在所述衬底基板上的正投影不超出该薄膜晶体管的栅极在所述衬底基板上的正投影。本发明还提供一种显示面板和一种显示装置。所述显示面板进行显示时不容易出现显示不良。

Description

阵列基板、显示面板和显示装置
技术领域
本发明涉及显示技术领域，具体地，涉及一种阵列基板、一种包括该阵列基板的显示面板和一种包括所述显示面板的显示装置。
背景技术
显示装置包括阵列基板。所述阵列基板包括衬底基板、栅图形层、有源图形层和源漏图形层，所述栅图形层包括多条栅线，所述源漏图形层包括多条数据线，多条所述栅线和多条所述数据线交叉设置，以将所述阵列基板划分为多个像素单元，所述阵列基板还包括设置在所述像素单元中的薄膜晶体管，所述栅图形层还包括所述薄膜晶体管的栅极，所述源漏图形层还包括所述薄膜晶体管的源极和漏极，所述有源图形层包括所述薄膜晶体管的有源层，为了确保具有足够的空间设置与像素电极电连接的过孔，因此，将漏极尺寸制造的比较大，但是，这种情况中，容易造成源极和漏极短路。
因此，如何防止显示装置中的源极和漏极发生短路成为本领域亟待解决的技术问题。
发明内容
本发明的目的在于提供一种阵列基板、包括该阵列基板的显示面板和一种显示装置，所述阵列基板的源极和漏极之间不容易发生短路。
为了实现上述目的，作为本发明的一个方面，提供一种阵列基板，所述阵列基板包括衬底基板、栅图形层、有源图形层和源漏图形层，所述栅图形层包括多条栅线，所述源漏图形层包括多条数据线，多条所述栅线和多条所述数据线交叉设置，以将所述阵列基板划分为多个像素单元，所述阵列基板还包括设置在所述像素单元中的薄膜晶体管，所述栅图形层还包括所述薄膜晶体管的栅极，所述源漏图形层还包括所述薄膜晶体管的源极和漏极，所述有源图形层包括所述薄膜晶体管的有源层，其中，所述薄膜晶体管的漏极在所述衬底基板上的正投影不超出该薄膜晶体管的栅极在所述衬底基板上的正投影。
优选地，所述漏极沿数据线方向的长度在7μm至12μm，所述栅极沿所述数据线方向的长度在10μm至15μm之间。
优选地，所述薄膜晶体管的源极为相应数据线的一部分。
优选地，所述薄膜晶体管为底栅型薄膜晶体管。
优选地，在至少一个所述薄膜晶体管中，所述有源层在所述衬底基板上的正投影为梯形，所述有源层上包括梯形的下底的部分与所述源极连接，所述有源层上包括梯形的上底的部分与所述漏极连接。
优选地，所述阵列基板包括覆盖所述源漏图形层的钝化绝缘层，所述阵列基板还包括像素电极层，所述像素电极层多个像素电极，每个所述像素单元中设置有一个所述像素电极，所述像素电极通过贯穿所述钝化绝缘层的过孔与相应的漏极电连接。
作为本发明的第二个方面，提供一种显示面板，所述显示面板包括阵列基板，其中，所述阵列基板为本发明所提供的上述阵列基板。
作为本发明的第三个方面，提供一种显示装置，所述显示装置包括显示面板，其中，所述显示面板为本发明所提供的上述显示面板。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是现有技术中的阵列基板的一部分的示意图；
图2是本发明所提供的阵列基板的一部分的示意图。
附图标记说明
100：栅线 110：栅极
210：数据线 220：源极
230：漏极 300：薄膜晶体管
400：有源层 410：残余材料
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
经本发明的发明人研究发现，现有技术中，阵列基板发生显示不良的原因如下：
在形成有源图形层后，阵列基板的栅线100的边缘处容易形成有源层材料的残余材料410，由于该残余材料410形成在栅线的边缘，因此过程内PI监控无法发现该残余。
为了确保足够的空间设置过孔(在图1中所示的实施方式中，将过孔设置在虚线圈A处)，将薄膜晶体管300的漏极230的尺寸设置的比较大，如图中所示，漏极230已经延伸至栅极110的外部。如图1所示，残余材料410连接在源极220和漏极230之间。当在包括所述阵列基板的显示装置进行显示时，栅线100边缘的残余材料410也能够将源极220和漏极230导通，从而造成显示不良。
为了解决上述问题，作为本发明的一个方面，提供一种阵列基板，所述阵列基板包括衬底基板、栅图形层、有源图形层和源漏图形层，如图2所示，所述栅图形层包括多条栅线100，所述源漏图形层包括多条数据线210，多条栅线100和多条所述数据线交叉设置，以将所述阵列基板划分为多个像素单元，所述阵列基板还包括设置在所述像素单元中的薄膜晶体管300，所述栅图形层还包括所述薄膜晶体管的栅极110，所述源漏图形层还包括所述薄膜晶体管的源极220和漏极230，所述有源图形层包括所述薄膜晶体管的有源层400，其中，所述薄膜晶体管的漏极230在所述衬底基板上的正投影不超出该薄膜晶体管的栅极110在所述衬底基板上的正投影。
如图2中所示，由于漏极230在栅极110的范围内，因此，即便栅线100的边缘处存在有源层材料的残余材料410，该残余材料410也不会将源极220和漏极230连接，因此，在包括所述阵列基板的显示装置进行显示时，不会出现因源极220和漏极230短路而造成的显示不良。进而可以提高包括所述阵列基板的显示面板的显示效果。
在本发明中，对栅极110、漏极230的尺寸并没有特殊的要求，为了确保漏极230上具有足够的空间形成与像素电极相连的过孔(如图2中所示，过孔形成在虚线框A处)，优选地，漏极230沿数据线210方向的长度L1在7μm至12μm之间，栅极110沿数据线210方向的长度L2在10μm至15μm之间。需要指出的是，L1＜L2。
当然，本发明并不限于此，在设置栅极110的尺寸以及漏极230的尺寸时，只要满足L1＜L2、且在临界尺寸(CD，critical dimension)管控范围内即可。
在本发明中，对源极220的具体结构没有特殊的规定，只要源极220能够接收来自数据线210的数据信号即可。例如，源极220可以从数据线上凸出。为了简化形成源漏图形层的掩膜板，优选地，如图2所示，薄膜晶体管的源极220为相应数据线210的一部分。
容易理解的是，同一列的薄膜晶体管300对应同一条数据线210。
本发明所提供的结构尤其适用于底栅型薄膜晶体管，即，所述薄膜晶体管为底栅型薄膜晶体管，即，栅图形层位于有源图形层和衬底基板之间。
本领域技术人员容易理解的是，在栅图形层和有源图形层之间设置有栅绝缘层。
为了提高阵列基板的开口率，优选地，如图2所示，在至少一个薄膜晶体管300中，有源层400在所述衬底基板上的正投影为梯形，有源层400上包括梯形的下底的部分与源极220连接，有源层400上包括梯形的上底的部分与漏极230连接。
形状为梯形的有源层可以在确保具有足够的沟道尺寸的同时减少栅极面积，从而可以提高开口率。
通常，所述阵列基板包括公共电极和像素电极。每个像素单元中均设置有一个所述像素电极。公共电极与公共电极线电连接，通过该公共电极线向公共电极提供公共电压。像素电极与薄膜晶体管的漏极电连接，通过漏极向薄膜晶体管提供数据电压。
为了形成存储电容，公共电极和像素电极绝缘间隔设置。在本发明中，对公共电极和像素电极的具体位置并没有特殊的要求，可以将公共电极设置在像素电极与衬底基板之间，也可以将像素电极设置在公共电极与衬底基板之间。
作为本发明的一种优选实施方式，可以将公共电极设置在像素电极与所述衬底基板之间。具体地，所述阵列基板包括覆盖所述源漏图形层的钝化绝缘层，所述阵列基板还包括像素电极层，所述像素电极层多个像素电极，每个所述像素单元中设置有一个所述像素电极，所述像素电极通过贯穿所述钝化绝缘层的过孔与相应的漏极电连接。
作为本发明的第二个方面，提供一种显示面板，所述显示面板包括阵列基板，其中，所述阵列基板为本发明所提供的上述阵列基板。
由于所述阵列基板的薄膜晶体管中，源极和漏极之间不存在残余的有源层材料，因此，在所述显示面板进行显示时，不会出现因源极和漏极短路而造成的显示不良。
作为一种实施方式，所述显示面板为液晶显示面板。因此，所述显示面板还包括阵列基板、与阵列基板对盒设置的对盒基板以及填充在阵列基板与对盒基板之间的液晶材料。
优选地，可以在对盒基板上设置彩膜层，以实现彩色显示。当然，也可以将彩膜层设置在阵列基板上。
当然，所述显示面板还可以是电致变色显示面板，在阵列基板和对盒基板之间设置电致变色材料。
作为本发明的第三个方面，提供一种显示装置，所述显示装置包括显示面板，其中，所述显示面板为本发明所提供的上述显示面板。
如上文中所述，所述显示装置中不会出现因有源层残余导致源漏极短路而形成的不良而造成的显示不良。
容易理解的是，所述显示装置可以为液晶显示装置。
优选地，所述显示装置还可以包括背光源，以为所述显示面板提供光源。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (5)

1.一种阵列基板，所述阵列基板包括衬底基板、栅图形层、有源图形层和源漏图形层，所述栅图形层包括多条栅线，所述源漏图形层包括多条数据线，多条所述栅线和多条所述数据线交叉设置，以将所述阵列基板划分为多个像素单元，所述阵列基板还包括设置在所述像素单元中的薄膜晶体管，所述栅图形层还包括所述薄膜晶体管的栅极，所述源漏图形层还包括所述薄膜晶体管的源极和漏极，所述有源图形层包括所述薄膜晶体管的有源层，其特征在于，所述薄膜晶体管的漏极在所述衬底基板上的正投影不超出该薄膜晶体管的栅极在所述衬底基板上的正投影，所述薄膜晶体管的源极为相应数据线的一部分，
所述薄膜晶体管为底栅型薄膜晶体管，在至少一个所述薄膜晶体管中，所述有源层在所述衬底基板上的正投影为梯形，所述有源层上包括梯形的下底的部分与所述源极连接，所述有源层上包括梯形的上底的部分与所述漏极连接。
2.根据权利要求1所述的阵列基板，其特征在于，所述漏极沿数据线方向的长度在7μm至12μm之间，所述栅极沿所述数据线方向的长度在10μm至15μm之间。
3.根据权利要求1或2所述的阵列基板，其特征在于，所述阵列基板包括覆盖所述源漏图形层的钝化绝缘层，所述阵列基板还包括像素电极层，所述像素电极层多个像素电极，每个所述像素单元中设置有一个所述像素电极，所述像素电极通过贯穿所述钝化绝缘层的过孔与相应的漏极电连接。
4.一种显示面板，所述显示面板包括阵列基板，其特征在于，所述阵列基板为权利要求1至3中任意一项所述的阵列基板。
5.一种显示装置，所述显示装置包括显示面板，其特征在于，所述显示面板为权利要求4所述的显示面板。
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