WO2015096360A1 - 一种阵列基板、其制备方法、以及包括该阵列基板的母板和显示装置 - Google Patents

一种阵列基板、其制备方法、以及包括该阵列基板的母板和显示装置 Download PDF

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Publication number
WO2015096360A1
WO2015096360A1 PCT/CN2014/077920 CN2014077920W WO2015096360A1 WO 2015096360 A1 WO2015096360 A1 WO 2015096360A1 CN 2014077920 W CN2014077920 W CN 2014077920W WO 2015096360 A1 WO2015096360 A1 WO 2015096360A1
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Prior art keywords
electrode
gate
layer
pixel
forming
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PCT/CN2014/077920
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English (en)
French (fr)
Inventor
刘旭
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/432,025 priority Critical patent/US9461074B2/en
Priority to EP14861100.7A priority patent/EP3088951B1/en
Publication of WO2015096360A1 publication Critical patent/WO2015096360A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate to a motherboard, an array substrate, a method of fabricating the same, and a display device.
  • LCD Liquid Crystal Display
  • a pixel is disposed on the array substrate of the liquid crystal display
  • the area, and the periphery of the pixel area for connecting to the driver IC, testing, preventing static electricity, etc. a surrounding wiring area; various metal wirings are disposed in the peripheral wiring area.
  • On the metal wiring because of gold
  • the need for wiring layout and the limitation of layout space often require connecting holes through via holes.
  • Metal wiring in different layers, however, perforated corrosion often occurs at the via location Elephant.
  • the gate line leads in the peripheral wiring area
  • the gate line leads and the pixel area
  • the gate is formed in the same layer and simultaneously, which is generally buried in the inner layer of the array substrate, but the gate line
  • the line needs to be connected to the driver IC.
  • the current practice is to set the corrosion resistance at the outermost layer. Strong metal oxide conductive electrode and forming a via on the underlying insulating layer It is electrically connected to the gate line directly under the via.
  • the metal oxide conductive electrode exposed to the air is resistant to corrosion
  • the etch ability is relatively strong, but the water vapor in the air will inevitably penetrate the electrode layer. And directly reach the gate line lead through the via hole, thereby causing the metal gate line lead to be corroded. The yield of the array substrate.
  • embodiments of the present invention provide an array substrate including a pixel region and peripheral wiring a peripheral conductive region including a transparent conductive contact electrode disposed on the base substrate,
  • the transparent conductive contact electrode passes through a via provided on a different insulating layer and a metal electrode disposed underneath
  • the wires are electrically connected, and the via holes located in different insulating layers do not overlap in the projection direction.
  • the pixel region includes a plurality of thin film transistors disposed on the base substrate, common An electrode and a pixel electrode electrically connected to a drain of the thin film transistor; the transparent conductive contact electrode It is disposed in the same layer as the upper of the pixel electrode and the common electrode.
  • the pixel region further includes a data line and a gate line disposed on the base substrate;
  • the metal electrode line includes an extension line of the gate line and/or an extension line of the data line.
  • the thin film transistor is a bottom gate type thin film transistor; an extension line of the gate line includes a gate a wire lead, and the gate wire lead is disposed in the same layer as the gate line and the gate of the thin film transistor;
  • the transparent conductive contact electrode is electrically connected to the source and drain retention patterns through the first via provided on the passivation layer And the source drain retention pattern passes through the second via provided on the gate insulating layer and the gate line lead Electrical connection.
  • the passivation layer is located in the pixel region and the peripheral wiring region, and in the pixel a region between the pixel electrode and the common electrode; the source drain retention pattern and the source a drain and a drain are disposed in the same layer; the gate insulating layer is located in the pixel region and the peripheral wiring region, and in the The pixel region is located between the gate and the source and the drain.
  • the thin film transistor is a bottom gate type thin film transistor; an extension line of the gate line includes a gate a wire lead, and the gate wire lead is disposed in the same layer as the gate line and the gate of the thin film transistor;
  • the transparent conductive contact electrode passes through the third via hole and the first transparent electrode retention pattern disposed on the passivation layer Electrically connecting, the first transparent electrode retaining pattern passes through a fourth via provided on the gate insulating layer
  • the gate line leads are electrically connected.
  • the passivation layer is located in the pixel region and the peripheral wiring region.
  • a pole-retaining pattern is disposed in the same layer as the electrode located below the pixel electrode and the common electrode; a gate insulating layer is located in the pixel region and the peripheral wiring region, and is located in the gate region in the pixel region Between the source and the drain.
  • the thin film transistor is a bottom gate type thin film transistor;
  • the extension line of the data line includes data a wire lead, and the data line lead is the same as the data line, the source and drain of the thin film transistor a layer disposed;
  • the transparent conductive contact electrode passes through a fifth via disposed on the passivation layer and a second transparent
  • the electrode retention pattern is electrically connected, and the second transparent electrode retention pattern is disposed on the protective layer
  • the six vias are electrically connected to the data line leads.
  • the passivation layer is located in the pixel area and outside Surrounding the wiring region, and located between the pixel electrode and the common electrode in the pixel region; a second transparent electrode retention pattern is the same as the lower electrode of the pixel electrode and the common electrode a layer setting; the protective layer is located in the pixel area and the peripheral wiring area, and is located in the pixel area The source and the drain are between the adjacent pixel electrode or the common electrode.
  • the thin film transistor is a top gate type thin film transistor;
  • the extension line of the data line includes data a wire lead, and the data line lead is the same as the data line, the source and drain of the thin film transistor Layer arrangement;
  • the transparent conductive contact electrode is retained by a seventh via and a gate disposed on the passivation layer a pattern electrically connected, the gate retention pattern passing through the eighth via provided on the gate insulating layer and the number According to the wire lead electrical connection.
  • the passivation layer is located in the pixel region and the peripheral wiring region, and The pixel region is located above the gate; the gate retention pattern is disposed in the same layer as the gate; The gate insulating layer is located in the pixel region and the peripheral wiring region, and is located in the gate region in the pixel region a pole between the source and the drain.
  • the transparent conductive contact electrode is disposed in the same layer as the common electrode, and the pixel electrode Provided between the common electrode and the substrate.
  • the transparent conductive contact electrode is disposed in the same layer as the pixel electrode, and the common electrode Provided between the pixel electrode and the substrate.
  • an embodiment of the present invention provides a display device, including any of the arrays described above.
  • Column substrate In another aspect, an embodiment of the present invention provides a display device, including any of the arrays described above.
  • an embodiment of the present invention provides a motherboard, including at least one array substrate,
  • the array substrate is any of the array substrates described above.
  • the motherboard further includes: parallel to the data lines of the array substrate, and transparent conductive a test gate line electrically connected to the contact electrodes; and/or parallel to the gate line of the array substrate, and A test data line in which the transparent conductive contact electrodes are electrically connected.
  • test gate line and/or the test data line are in the same layer as the transparent conductive contact electrode Settings.
  • test gate line and the test data line are electrically connected.
  • an embodiment of the present invention further provides a preparation for the array substrate described above.
  • the method includes: forming a metal electrode line in a peripheral wiring region around a pixel region of a base substrate, and a transparent conductive contact electrode located above the metal electrode line; wherein the transparent conductive contact is electrically
  • the poles are electrically connected to the metal electrode lines formed under the through holes formed on the different insulating layers, And the via holes located in different insulating layers do not overlap in the projection direction.
  • the preparation method further includes forming a plurality of thin portions in the pixel region of the base substrate a film transistor, a common electrode, and a pixel electrode electrically connected to a drain of the thin film transistor; wherein The transparent conductive contact electrode is located above the pixel electrode and the common electrode Floor.
  • the forming a metal electrode line in a peripheral wiring region of the base substrate includes:
  • the peripheral wiring region of the base substrate forms an extension line of the gate line and/or an extension line of the data line.
  • the preparation method includes:
  • the preparation method includes:
  • the preparation method includes:
  • the preparation method includes:
  • An active layer and a gate insulating layer located in the pixel region are sequentially formed on the substrate having the source/drain metal layer;
  • an eighth via located in the peripheral wiring region is formed on the gate insulating layer, and the eighth pass a hole exposing the data line lead;
  • FIG. 1 is a schematic top plan view of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a via hole in a peripheral wiring region of an array substrate according to an embodiment of the present invention
  • FIG. 3 is a pixel area and a corresponding peripheral wiring area in an array substrate according to an embodiment of the present invention. Schematic diagram of the cross-sectional structure at the via;
  • FIG. 4 is a pixel area and a corresponding peripheral wiring area in an array substrate according to an embodiment of the present invention. Schematic diagram of the cross-sectional structure at the via;
  • FIG. 5 is a schematic diagram of a pixel area and a corresponding peripheral wiring area in an array substrate according to an embodiment of the present invention. Schematic diagram of the cross-sectional structure at the via;
  • FIG. 6 is a diagram showing a pixel area and a corresponding peripheral wiring area in an array substrate according to an embodiment of the present invention. Schematic diagram of the cross-sectional structure at the via hole;
  • FIG. 7 is a diagram showing a pixel area and a corresponding peripheral wiring area in an array substrate according to an embodiment of the present invention. Schematic diagram of the cross-section of the via hole 5;
  • FIG. 8 is a schematic top plan view of a motherboard according to an embodiment of the present invention.
  • FIG. 9 is a second partial schematic structural view of a motherboard according to an embodiment of the present invention.
  • An embodiment of the present invention provides an array substrate 01, as shown in FIG. 1, including a pixel region 20 and a peripheral wiring region 30 including a transparent guide disposed on the base substrate 10 Electrically contacting the electrode 301, the transparent conductive contact electrode 301 is disposed on different insulating layers The hole is electrically connected to the metal electrode line disposed under the hole, and is projected between the via holes of different insulation layers There is no overlap in the direction.
  • the projection direction is along the array substrate 01.
  • the vertical direction ie, the normal direction of the array substrate 01.
  • the contact electrode 301 is to be disposed on a different insulating layer disposed under the transparent conductive contact electrode 301.
  • the via hole is electrically connected to the metal electrode line below, and therefore, may be disposed between different insulating layers
  • a conductive layer is disposed such that, for example, the transparent conductive contact electrode 301 can pass through a via hole on the first insulating layer in direct contact with the transparent conductive contact electrode 301 and the conductive layer Electrically connected, the conductive layer passes through the via hole on the lower second insulating layer and the metal underneath Polar line electrical connection.
  • the conductive layer is not limited, considering that the array base should be minimized
  • the number of patterning processes of the board 01, the conductive layer and the layer between the different insulating layers in the embodiment of the present invention The conductive patterns in the pixel region 20 are formed together.
  • the insulating layer located in the peripheral wiring region 30 is not limited, and It may be formed together with the insulating layer of the pixel region 20.
  • the embodiment of the present invention does not limit the specific configuration of the metal electrode line, for example, It may be an extension line 2031 and/or a data line of the gate line in the pixel region 20 as shown in FIG.
  • the line 2041 is extended.
  • An embodiment of the present invention provides an array substrate 01 including an image disposed on a substrate substrate 10. a region 20 and a peripheral wiring region 30; the peripheral wiring region 30 includes a substrate 10 disposed on the substrate Transparent conductive contact electrode 301 on the transparent conductive contact electrode 301 The via hole on the edge layer is electrically connected to the metal electrode line disposed under the hole, and the via hole is located in a different insulating layer There is no overlap between the projection directions.
  • a via hole on the layer is connected to the metal electrode line and is located between the via holes of different insulating layers
  • the direction does not overlap, when the water vapor permeates the transparent conductive contact electrode 301 exposed to the outside, as shown in the figure In the direction of the middle arrow, since the via has a small cross-sectional area, The water vapor molecules at the vias of the insulating conductive contact electrode 301 penetrating into the insulating layer in direct contact therewith are very Limited, and since the via located below does not overlap vertically with the via located above, In this way, the limited water vapor molecules that penetrate into the overlying holes are hard to reach below.
  • the via hole can prevent the metal electrode line disposed under the via hole from being corroded.
  • the pixel region 20 may further include a substrate base. a plurality of thin film transistors on the board 10, a common electrode 202, and a drain of the thin film transistor 2003 Electrically connected pixel electrode 201; the transparent conductive contact electrode 301 and the pixel electrode 201 and One of the upper electrodes of the common electrode 202 is disposed in the same layer.
  • the transparent conductive contact electrode 301 and the pixel electrode 201 and the common electrode One of the upper ones of the 202 is disposed in the same layer, and the pixel electrode 201 is disposed in the common In the case of the electrode 202, the transparent conductive contact electrode 301 is the same as the pixel electrode 201 Layer setting, of course, in order to avoid an increase in the number of patterning processes, the transparent conductive contact electrode 301 Formed with the pixel electrode 201 by one patterning process; the common electrode 202 is disposed at the In the case of the above pixel electrode 201, the transparent conductive contact electrode 301 and the common electrode 202 is set in the same layer, and in order to avoid an increase in the number of patterning processes, the transparent conductive contact electrode 301 and the common electrode 202 are formed by one patterning process.
  • FIG. 1 is only set with the common electrode 202.
  • the pixel electrode 201 is described as an example, but the pixel electrode is not applied to the embodiment of the present invention.
  • the relative position of 201 and the common electrode 202 is defined.
  • the pixel region 20 further includes a data line 204 disposed on the base substrate 10. And a gate line 203; the metal electrode line includes an extension line 2031 of the gate line and/or an extension line of the data line 2041.
  • the metal electrode line described above includes the extension line 2031 of the gate line and / Or the extension line 2041 of the data line means that different outer sides can be disposed on the periphery of the pixel area 20
  • the difference in function of 30, in the same array substrate 01 may include one of the above types
  • the peripheral wiring region 30 may also include the above-described two types of the peripheral wiring regions 30.
  • the range of the pixel region 20 is a plurality of the gate lines 203 and a plurality of roots
  • the data line 204 is defined; wherein two adjacent gate lines 203 intersect with two adjacent data lines 204
  • the fork defines one pixel unit, and each pixel unit includes the thin film transistor and the thin film crystal
  • the pixel electrode 201 electrically connected to the drain electrode 2003 of the body tube and the common electrode 202.
  • the thin film transistor is a bottom gate type thin film crystal a tube
  • an extension line of the gate line is a gate line lead 2031a
  • the gate line lead 2031a and the gate In the case where the line 203 and the gate electrode 2001 of the thin film transistor are disposed in the same layer:
  • the transparent conductive contact electrode 301 can be set to be passivated
  • the first via 3021 on the layer 302 is electrically connected to the source drain retention pattern 303, the source drain retention map 303 through the second via 2051 disposed on the gate insulating layer 205 and the gate line 2031a Electrical connection.
  • the passivation layer 302 is located in the pixel region 20 and the peripheral wiring region 30, and In the pixel region 20, the passivation layer 302 is located at the pixel electrode 201 and the common electrode 202.
  • the source drain retention pattern 303 is disposed in the same layer as the source and drain electrodes; the gate insulating layer 205 Located in the pixel region 20 and the peripheral wiring region 30, and located in the gate region 20 in the gate region 2001 is between the source 2002 and the drain 2003.
  • the transparent conductive contact electrode 301 passes through the first via hole on the passivation layer 302 described above 3021 is electrically connected to the source drain retention pattern 303, and the source drain retention pattern 303 passes through the gate a second via 2051 on the edge layer 205 is electrically connected to the gate line lead 2031a, and the first via hole 3021 and the second via hole 2051 do not overlap in the vertical direction, so as to prevent moisture from penetrating
  • the gate line lead 2031a is directly etched.
  • the material of the gate line lead 2031a may be A metal alloy having a strong corrosion resistance such as aluminum-bismuth may be used, and a weak resistance such as molybdenum may also be used.
  • Corrosive metal element; and the source drain retention pattern 303 is directly passed through a via
  • the transparent conductive contact electrode 301 is connected, and the water vapor infiltrated from the transparent conductive contact electrode 301 can be
  • the source drain retention pattern 303 causes corrosion, and thus the source drain retention pattern 303 is herein
  • the material may be a metal alloy having a strong corrosion resistance such as aluminum-bismuth.
  • the transparent conductive contact electrode 301 is disposed on the passivation layer 302.
  • the upper via hole 3022 is electrically connected to the first transparent electrode retention pattern 304, the first transparent electrode
  • the retention pattern 304 passes through the fourth via 2052 disposed on the gate insulating layer 205 and the gate line lead 2031a is electrically connected.
  • the passivation layer 302 is located in the pixel region 20 and the peripheral wiring region 30, and In the pixel region 20, the passivation layer 302 is located at the pixel electrode 201 and the common electrode 202. Between the first transparent electrode retention pattern 304 and the pixel electrode 201 and the common electrode The lower electrode is disposed in the same layer as 202; the gate insulating layer 205 is located in the pixel region 20 and outside Surrounding the wiring area 30, and in the pixel area 20, the gate 2001 and the source 2002 and Between the drains 2003.
  • the hole 3022 is electrically connected to the first transparent electrode retention pattern 304, and the first transparent electrode retention pattern
  • the case 304 is electrically connected to the gate line lead 2031a through a fourth via 2052 on the gate insulating layer 205.
  • the third via hole 3022 and the fourth via hole 2052 do not overlap in the vertical direction, and can be avoided.
  • the material of the gate line lead 2031a may be highly resistant to corrosion by using aluminum-bismuth or the like. Metal alloy, it is also possible to use a metal element with weak corrosion resistance such as molybdenum; and a transparent electrode Currently, materials such as ITO (Indium Tin Oxide) are generally used as materials. Corrosiveness is relatively high, therefore, the material of the first transparent electrode retention pattern 304 is not limited However, in order to reduce the number of patterning processes, the material of the first transparent electrode retention pattern 304 and the same layer The material of the pixel electrode 201 or the common electrode 202 is the same, so that it can be processed by one patterning process. Forming the first transparent electrode retention pattern 304 to form a pixel electrode 201 or the same layer in the same layer Electrode 202.
  • the extension line of the data line is a data line lead 2041a, and the data line lead 2041a and the data line 204, the source of the thin film transistor In the case of 2002 and drain 2003 with the same layer settings:
  • the transparent conductive contact electrode 301 is disposed on the passivation layer 302.
  • the upper via 3023 is electrically connected to the second transparent electrode retention pattern 305, the second transparent electrode
  • the retention pattern 305 passes through the sixth via 3061 disposed on the protective layer 306 and the data line lead 2041a is electrically connected.
  • the passivation layer 302 is located in the pixel region 20 and the peripheral wiring region 30, and In the pixel region 20, the passivation layer 302 is located at the pixel electrode 201 and the common electrode 202. Between the second transparent electrode retention pattern 305 and the pixel electrode 201 and the common electrode The lower electrode is disposed in the same layer in 202; the protective layer 306 is located in the pixel region 20 and the periphery a wiring region 30, and the image in the pixel region 20 at the source and the drain and the proximity Between the element electrode 201 or the common electrode 202.
  • the common electrode 202 is disposed on the pixel electrode 201.
  • the transparent conductive contact electrode 301 is disposed in the same layer as the common electrode 202, and the second transparent electricity
  • the pole retention pattern 305 is disposed in the same layer as the pixel electrode 201; and, in the pixel region 20,
  • the protective layer 306 is located at the source electrode 2002 and the drain electrode 2003 and the pixel electrode adjacent thereto Between 201.
  • the hole 3023 is electrically connected to the second transparent electrode retention pattern 305, and the second transparent electrode retains a pattern 305 is electrically connected to the data line lead 2041a through a sixth via 3061 on the protective layer 306, and
  • the fifth via hole 3023 and the sixth via hole 3061 do not overlap in the vertical direction, which can be avoided.
  • an extension line of the data line is a data line lead 2041a, and the data line lead 2041a and the data line 204, the thin film crystal
  • the source tube 2002 and the drain 2003 are set in the same layer:
  • the transparent conductive contact electrode 301 is disposed on the passivation layer 302 .
  • the upper via 3024 is electrically connected to the gate retention pattern 307, and the gate retention pattern 307 is passed
  • An eighth via 2053 disposed on the gate insulating layer 205 is electrically connected to the data line lead 2041a.
  • the passivation layer 302 is located in the pixel region 20 and the peripheral wiring region, and in the pixel region 20 is located above the gate 2001; the gate retention pattern 307 is disposed in the same layer as the gate; The gate insulating layer 205 is located in the pixel region 20 and the peripheral wiring region 30, and in the pixel region 20 The middle is located between the gate 2001 and the source 2002 and the drain 2003.
  • the passivation layer 302 is in the pixel area. 20 is located above the gate electrode 2001, and refers to a shape in the preparation process of the array substrate 01. The gate electrode 2001 is formed, and the passivation layer 302 is further formed.
  • the transparent conductive contact electrode 301 passes through the seventh via provided on the passivation layer 302 3024 is electrically connected to the gate retention pattern 307, and the gate retention pattern 307 is disposed through the gate insulation
  • An eighth via 2053 on the layer 205 is electrically connected to the data line lead 2041a, and the seventh via 3024 and the eighth via 2053 do not overlap in the vertical direction, so as to prevent moisture from penetrating.
  • the data line lead 2041a is directly etched.
  • the transparent conductive contact electrode 301 and The common electrode 202 is disposed in the same layer, and the pixel electrode 201 is disposed on the common electrode 201 and Between the substrate substrates 10.
  • the position of the pixel electrode 201 can be based on the class of the thin film transistor The type is adjusted accordingly to minimize the complexity of the process.
  • the transparent conductive connection The contact electrode 301 may also be disposed in the same layer as the pixel electrode 201, and the common electrode 202 is disposed on The pixel electrode 201 and the base substrate 10 are not described herein again.
  • An embodiment of the present invention provides an array substrate 01, as shown in FIG. 7, including a pixel region 20 and a peripheral wiring region 30 including a plurality of bottom gate type thin films disposed on the base substrate 10.
  • the peripheral wiring region 30 includes a substrate 10 disposed on the substrate Transparent conductive contact electrode 301 and gate line lead 2031a, wherein the transparent conductive contact
  • the pole 301 is in the same layer as the common electrode 202 and is formed by one patterning process
  • the gate line lead 2031a is formed in the same layer as the gate line 203 and the gate electrode 2001 and is formed by one patterning process.
  • the transparent conductive contact electrode 301 passes through the first via 3021 disposed on the passivation layer 302 Electrically connected to the source drain retention pattern 303, the source drain retention pattern 303 is then placed through the gate
  • the second via 2051 on the edge layer 205 is electrically connected to the gate line 2031a, and along the array substrate In the vertical direction of 01, the two vias are not overlapped; wherein the source and drain retention patterns 303 are The source and drain are in the same layer and are formed by a single patterning process.
  • the passivation layer 302 and the gate insulating layer 205 are located both in the pixel region 20 and at the periphery.
  • the material may be a metal alloy having a strong corrosion resistance such as aluminum-bismuth, or a molybdenum or the like. a metal element having a weaker corrosion resistance; and the source drain retention pattern 303 is directly passed through
  • the via holes are connected to the transparent conductive contact electrode 301 and penetrate from the transparent conductive contact electrode 301 Water vapor can cause corrosion to the source drain retention pattern 303, so the source and drain retention maps are described herein.
  • the material of the case 303 may be a metal alloy having a strong corrosion resistance such as aluminum-bismuth.
  • a data line lead 2041a disposed on the base substrate 10, wherein the data line lead 2041a is included The same as the data line 204, the source 2002 and the drain 2003 of the thin film transistor and pass through a layer The sub-patterning process is formed.
  • the transparent conductive contact electrode 301 passes through the first layer disposed on the passivation layer 302.
  • the five vias 3023 are electrically connected to the second transparent electrode retention pattern 305, and the second transparent electrode remains as a pattern Case 305 through the sixth via 3061 disposed on the protective layer 306 and the data line lead 2041a Electrical connection.
  • the second transparent electrode retention pattern 305 is in the same layer as the pixel electrode 201 and passes through A patterning process is formed; the protective layer 306 is located in both the pixel region 20 and the peripheral wiring region 30. And in the pixel region 20, the source electrode 2002 and the drain electrode 2003 and the pixel electrode Between 201.
  • the embodiment of the invention provides a display device comprising the array substrate according to any one of the preceding claims.
  • the liquid crystal display device may be a liquid crystal display, a liquid crystal television, a digital photo frame, or a mobile phone.
  • An embodiment of the present invention further provides a motherboard, including at least one array substrate 01, the array
  • the substrate 01 is the array substrate 01 described in any one of the above.
  • the mother board refers to a relatively large lining in the whole process of the preparation of the array substrate 01.
  • a plurality of array substrates 01 are formed on the base substrate, and a plurality of arrays having a specific size are formed by a process such as cutting.
  • the column substrate 01, therefore, the array substrate 01 included in the motherboard is of the same type as described above The array substrate 01.
  • the motherboard further includes: a data line with the array substrate 01 a test gate line 308 that is parallel and electrically connected to the transparent conductive contact electrode 301; and/or, The gate lines 203 of the array substrate are parallel and electrically connected to the transparent conductive contact electrodes 301 Test data line 309; wherein the test gate line 308 and/or the test data line 309 are The transparent conductive contact electrode 301 is disposed in the same layer. Further, for example, the test gate line 308 and/or the The test data line 309 and the transparent conductive contact electrode 301 are formed by one patterning process.
  • the test gate line 308 will electrically connect the transparent conductive contact electrode to the gate line lead 2031a 301 is electrically connected together, and the gate line 203 can be detected under the Determining whether it is conducting; likewise, passing the test data line 309 with the data lead 2041a
  • the transparent conductive contact electrodes 301 electrically connected are electrically connected together, and can be disposed on the lower side
  • the data line 204 is detected to determine whether it is turned on.
  • test gate line 308 and/or the test data line 309 can be The transparent conductive contact electrode 301 is cut or formed to form a single array substrate 01.
  • test gate line 308 and the test data line 309 Electrically connected such that the test plate 308 and the test number can be maintained in the motherboard
  • the potentials of the gate line 203 and the data line 204 electrically connected according to the line 309 are identical, thereby avoiding An electrostatic potential difference is generated in the mother board to cause electrostatic breakdown to the mother board.
  • the embodiment of the present invention further provides a preparation method for the array substrate 01 described above, and a package include:
  • Metal wiring lines are formed in the peripheral wiring region 30 around the pixel region 20 of the base substrate 10, and a transparent conductive contact electrode 301 located above the metal electrode line; wherein the transparent conductive connection
  • the contact electrode 301 passes through a via provided on a different insulating layer and the metal electrode line disposed under Electrically connected, and the vias located in different insulating layers do not overlap in the projection direction.
  • the preparation method further includes forming in the pixel region 20 of the base substrate 10 a plurality of thin film transistors, a common electrode 202, and an image electrically connected to the drain 2003 of the thin film transistor a cathode electrode 201; wherein the transparent conductive contact electrode 301 and the pixel electrode 201 and the The upper side of the common electrode 202 is disposed in the same layer.
  • the forming the metal electrode line in the peripheral wiring region 30 of the base substrate 10 includes: An extension line 2031 and/or data of the gate line is formed in the peripheral wiring region 30 of the base substrate 10.
  • the extension line 2041 of the line is formed in the peripheral wiring region 30 of the base substrate 10.
  • the preparation method further comprises: on the substrate Forming a second transparent electrode located in the pixel region 20 on the substrate 10, that is, relative to the substrate 10, the first transparent electrode is located above the second transparent electrode; wherein the first transparent One of the electrode and the second transparent electrode is the pixel electrode 201, and the other is the common electrode 202.
  • the second transparent electrode is a pixel
  • the pixel electrode 201 located in the pixel region 20 is formed.
  • the common electrode 202 located in the pixel region 20 is formed.
  • the second transparent electrode is the common electrode 202
  • the first transparent electricity In the case of an extremely pixel electrode, the common electrode 202 and the source 2002 and the drain 2003 are required to be secured. Etc. no electrical connection, therefore, if the second transparent electrode is formed at the source 2002, the drain 2003 Then, before the passivation layer 302, the source electrode 2002 and the drain electrode are required to be formed by forming an insulating layer. Is insulated from the second transparent electrode.
  • the transparent conductive contact electrode 301 passes the first pass
  • the hole 3021 is electrically connected to the source drain retention pattern 303, and the source drain retention pattern 303 is passed
  • the second via 2051 is electrically connected to the gate line 2031a, and the first via 3021 is
  • the second via holes 2051 do not overlap in the vertical direction, and the water vapor can be prevented from penetrating the transparent conductive
  • the gate line lead 2031a is directly etched.
  • the gate line lead 2031a may be made of a metal alloy material having a strong corrosion resistance such as aluminum-bismuth. It is also possible to use a metal elemental material having a weak corrosion resistance such as molybdenum; and the source and drain retention map
  • the case 303 is connected to the transparent conductive contact electrode 301 directly through the second via 2051. Water vapor permeating from the transparent conductive contact electrode 301 may cause the source drain retention pattern 303 Corrosion, therefore, the source and drain metal layers may be made of a metal having strong corrosion resistance such as aluminum-bismuth. alloy.
  • one of the first transparent electrode and the second transparent electrode is a pixel electrode 201,
  • the other is the common electrode 202.
  • the first transparent electrode is a pixel
  • the formation may be located.
  • the transparent electrode retention pattern 304 is formed in the step S26 in the pixel area 20
  • the insulating layer needs to be formed before the step S24 is performed.
  • the source 2002 and the drain 2003 are insulated from the first transparent electrode.
  • the transparent conductive contact electrode 301 passes the third pass
  • the hole 3022 is electrically connected to the first transparent electrode retention pattern 304, and the first transparent electrode remains
  • the pattern 304 is electrically connected to the gate line lead 2031a through the fourth via 2052, and the third The via hole 3022 and the fourth via hole 2052 do not overlap in the vertical direction to avoid water vapor permeation.
  • the gate line lead 2031a is directly etched.
  • the first transparent electrode is formed, ITO (Indium Tin Oxide, oxygen) is generally used.
  • a transparent conductive material such as indium tin oxide, which is relatively high in corrosion resistance, and therefore, the embodiment of the present invention
  • the material used for the first transparent electrode is not limited.
  • the second transparent electrode and the second transparent electrode retention pattern 305 are formed Forming a passivation layer 302 on the substrate; wherein the peripheral layer is formed on the passivation layer 302 a fifth via 3023 of the line region 30, the fifth via 3023 exposing the second transparent electrode retention map Case 305.
  • one of the first transparent electrode and the second transparent electrode is a pixel electrode 201,
  • the other is the common electrode 202.
  • the protection may be performed in the step S34.
  • step S35 the pixel electrode 201 located in the pixel region 20 is formed and located at the periphery
  • the second transparent electrode of the wiring region 30 retains a pattern 305, wherein the pixel electrode 201 passes the The via is electrically connected to the drain 2003; in this case, the location is formed in the step S37
  • the common electrode 202 of the pixel region 20 and the transparent guide at the peripheral wiring region 30 Electrically contacting electrode 301.
  • the protective layer 306 on the pixel region 20 and the passivation layer 302 are required. Via holes for connecting the pixel electrode 201 and the drain electrode 2003 are formed on the upper side, and are not described herein again.
  • the transparent conductive contact electrode 301 passes the fifth pass
  • the hole 3023 is electrically connected to the second transparent electrode retention pattern 305, and the second transparent electrode remains
  • the pattern 305 is electrically connected to the data line lead 2041a through the sixth via 3061, and the The five via holes 3023 and the sixth via hole 3061 do not overlap in the vertical direction, thereby avoiding water vapor permeation.
  • the transparent conductive contact electrode 301 is passed through, the data line lead 2041a is directly etched.
  • the preparation method further comprises: on the substrate Forming a second transparent electrode located in the pixel region 20 on the substrate 10; the first transparent electrode and the One of the second transparent electrodes is the pixel electrode 201 and the other is the common electrode 202.
  • the first transparent electrode is common In the case of the electrode 202, as shown in FIG. 6, for example, after the completion of the step S41, Before the step S42 is performed, the pixel electrode 201 located in the pixel region 20 is formed; In the step S45, the common electrode 202 located in the pixel region 20 is formed.
  • the second transparent electrode is the common electrode 202
  • the step S44 may be formed. a rim layer and the common electrode 202 located in the pixel region 20; in this case, at the step Forming the pixel electrode 201 located in the pixel region 20 in S45 and located in the peripheral wiring area The transparent conductive contact electrode 301 of 30.
  • the transparent conductive contact electrode 301 is provided by passivation
  • the seventh via 3024 on the layer 302 is electrically connected to the gate retention pattern 307, the gate protection
  • the leaving pattern 307 passes through the eighth via 2053 disposed on the gate insulating layer 205 and the data
  • the wire lead 2041a is electrically connected, and the seventh via 3024 is perpendicular to the eighth via 2053 There is no overlap upward, and direct corrosion can be avoided when water vapor permeates the transparent conductive contact electrode 301
  • the data line lead 2041a is no overlap upward, and direct corrosion can be avoided when water vapor permeates the transparent conductive contact electrode 301.
  • the seventh via 3024 and the eighth via 2053 arrive at the data line lead 2041a, and thus,
  • the material of the data line lead 2041a can be made of aluminum-bismuth or the like with strong corrosion resistance.
  • a metal alloy which may also be a metal element having a weak corrosion resistance such as molybdenum;
  • the leaving pattern 307 passes through the seventh via 3024 and the transparent conductive contact electrode 301 Connected, water vapor permeating from the transparent conductive contact electrode 301 can cause the gate retention pattern 307 Corrosion, therefore, the material of the gate retention pattern 307 described herein may be strongly resistant to aluminum-germanium or the like. Corrosive metal alloy.
  • the peripheral wiring area is provided with two insulating layers. And the case of two vias. However, depending on the actual needs, the peripheral wiring area may or may be provided with multiple layers of insulation. Layer, in this case, correspondingly also set a plurality of vias and multiple locations that do not overlap in the projection direction Conductive layers between the insulating layers are all within the scope of the present invention.

Abstract

一种阵列基板、其制备方法、以及包括该阵列基板的母板和显示装置。该阵列基板包括像素区（20）和外围布线区（30）。外围布线区（30）包括设置在衬底基板（10）上的透明导电接触电极（301）。透明导电接触电极（301）通过设置于不同绝缘层上的过孔（3021, 3022, 3023, 3024, 2051, 2052, 3061, 2053）与设置于下方的金属电极线（2031, 2041）电连接，且位于不同绝缘层的过孔（3021, 3022, 3023, 3024, 2051, 2052, 3061, 2053）之间在投影方向无交叠。

Description

母板、阵列基板及制备方法、显示装置 技术领域
本发明的实施例涉及一种母板、阵列基板及制备方法、显示装置。
背景技术
目前，液晶显示器(Liquid Crystal Display，简称LCD)已经成为 了显示器领域发展的主流趋势。液晶显示器的阵列基板上设置有像素 区，以及在像素区周边的用于与驱动IC连接、测试、防止静电等的外 围布线区；外围布线区中设置有各种金属布线。在金属布线上因为金 属布线排布的需要以及排布空间的限制，往往需要通过过孔来连接位 于不同层的金属布线，然而在该过孔位置处经常会发生过孔腐蚀的现 象。
例如，对于外围布线区中的栅线引线，由于栅线引线与像素区中 的栅极同层且同时形成，其一般是埋在阵列基板的里层，然而栅线引 线需要与驱动IC连接，目前的做法是在最外层设置抗腐蚀能力相对较 强的金属氧化物导电电极，并通过在其下方的绝缘层上形成一个过孔 来与该过孔正下方的栅线引线电连接。
在上述方法中，虽然暴露在空气中的金属氧化物导电电极的抗腐 蚀能力相对较强，但是空气中的水汽不可避免的还是会渗透该电极层， 并通过过孔直接到达栅线引线，从而导致金属的栅线引线被腐蚀，影 响阵列基板的良率。
发明内容
一方面，本发明的实施例提供了一种阵列基板，包括像素区和外围布线 区；所述外围布线区包括设置在所述衬底基板上的透明导电接触电极，所述 透明导电接触电极通过设置于不同绝缘层上的过孔与设置于下方的金属电极 线电连接，且位于不同绝缘层的过孔之间在投影方向无交叠。
例如，所述像素区包括设置在所述衬底基板上的多个薄膜晶体管、公共 电极和与所述薄膜晶体管的漏极电连接的像素电极；所述透明导电接触电极 与所述像素电极和所述公共电极二者中位于上方的同层设置。
例如，所述像素区还包括设置在所述衬底基板上的数据线和栅线；所述 金属电极线包括栅线的延伸线和/或数据线的延伸线。
例如，所述薄膜晶体管为底栅型薄膜晶体管；所述栅线的延伸线包括栅 线引线，且所述栅线引线与所述栅线、所述薄膜晶体管的栅极同层设置；所 述透明导电接触电极通过设置于钝化层上的第一过孔与源漏极保留图案电连 接，所述源漏极保留图案通过设置于栅绝缘层上的第二过孔与所述栅线引线 电连接。在此情况下，所述钝化层位于像素区和外围布线区，且在所述像素 区中位于所述像素电极和所述公共电极之间；所述源漏极保留图案与所述源 极和漏极同层设置；所述栅绝缘层位于所述像素区和外围布线区，且在所述 像素区中位于所述栅极与所述源极和所述漏极之间。
例如，所述薄膜晶体管为底栅型薄膜晶体管；所述栅线的延伸线包括栅 线引线，且所述栅线引线与所述栅线、所述薄膜晶体管的栅极同层设置；所 述透明导电接触电极通过设置于钝化层上的第三过孔与第一透明电极保留图 案电连接，所述第一透明电极保留图案通过设置于栅绝缘层上的第四过孔与 所述栅线引线电连接。在此情况下，所述钝化层位于像素区和外围布线区， 且在所述像素区中位于所述像素电极和所述公共电极之间；所述第一透明电 极保留图案与所述像素电极和所述公共电极中位于下方的电极同层设置；所 述栅绝缘层位于所述像素区和外围布线区，且在所述像素区中位于所述栅极 与所述源极和所述漏极之间。
例如，薄膜晶体管为底栅型薄膜晶体管；所述数据线的延伸线包括数据 线引线，且所述数据线引线与所述数据线、所述薄膜晶体管的源极和漏极同 层设置；所述透明导电接触电极通过设置于钝化层上的第五过孔与第二透明 电极保留图案电连接，所述第二透明电极保留图案通过设置于保护层上的第 六过孔与所述数据线引线电连接。在此情况下，所述钝化层位于像素区和外 围布线区，且在所述像素区中位于所述像素电极和所述公共电极之间；所述 第二透明电极保留图案与所述像素电极和所述公共电极中位于下方的电极同 层设置；所述保护层位于所述像素区和外围布线区，且在所述像素区中位于 所述源极和所述漏极与靠近的所述像素电极或所述公共电极之间。
例如，薄膜晶体管为顶栅型薄膜晶体管；所述数据线的延伸线包括数据 线引线，且所述数据线引线与所述数据线、所述薄膜晶体管的源极和漏极同 层设置；所述透明导电接触电极通过设置于钝化层上的第七过孔与栅极保留 图案电连接，所述栅极保留图案通过设置于栅绝缘层上的第八过孔与所述数 据线引线电连接。在此情况下，所述钝化层位于像素区和外围布线区，且在 所述像素区中位于所述栅极上方；所述栅极保留图案与所述栅极同层设置； 所述栅绝缘层位于所述像素区和外围布线区，且在所述像素区中位于所述栅 极与所述源极和所述漏极之间。
例如，所述透明导电接触电极与所述公共电极同层设置，所述像素电极 设置于所述公共电极和所述衬底基板之间。
例如，所述透明导电接触电极与所述像素电极同层设置，所述公共电极 设置于所述像素电极和所述衬底基板之间。
另一方面，本发明实施例提供了一种显示装置，包括任一如上所述的阵 列基板。
再一方面，本发明实施例提供了一种母板，包括至少一个阵列基板，所 述阵列基板为任一如上所述的阵列基板。
例如，所述母板还包括：与所述阵列基板的数据线平行，且与透明导电 接触电极均电连接的测试栅线；和/或，与所述阵列基板的栅线平行，且与所 述透明导电接触电极均电连接的测试数据线。
例如，所述测试栅线和/或所述测试数据线与所述透明导电接触电极同层 设置。
例如，所述测试栅线和测试数据线电连接。
又一方面，本发明实施例还提供了一种针对上述的所述阵列基板的制备 方法，包括：在衬底基板的像素区周边的外围布线区形成金属电极线、以及 位于所述金属电极线上方的透明导电接触电极；其中，所述透明导电接触电 极通过形成于不同绝缘层上的过孔与形成于下方的所述金属电极线电连接， 且位于不同绝缘层的过孔之间在投影方向无交叠。
例如，所述制备方法还包括：在所述衬底基板的所述像素区形成多个薄 膜晶体管、公共电极和与所述薄膜晶体管的漏极电连接的像素电极；其中， 所述透明导电接触电极与所述像素电极和所述公共电极二者中位于上方的同 层。
例如，所述在衬底基板的外围布线区形成金属电极线，包括：在所述衬 底基板的所述外围布线区形成栅线的延伸线和/或数据线的延伸线。
例如，所述制备方法包括：
在所述衬底基板上形成包括位于所述像素区的栅极、栅线以及位于所述 外围布线区的栅线引线的栅金属层；在形成有所述栅金属层的基板上依次形 成栅绝缘层和位于所述像素区的有源层；其中，在所述栅绝缘层上形成位于 所述外围布线区的第二过孔，所述第二过孔露出所述栅线引线；在形成有所 述栅绝缘层和所述有源层的基板上形成包括位于所述像素区的源极、漏极、 与所述源极电连接的数据线以及位于所述外围布线区的源漏极保留图案的源 漏金属层；所述源漏极保留图案通过所述第二过孔与所述栅线引线电连接； 在形成有所述源漏金属层的基板上形成钝化层；其中，在所述钝化层上形成 位于所述外围布线区的第一过孔，所述第一过孔露出所述源漏极保留图案； 在形成有所述钝化层的基板上形成位于所述像素区的第一透明电极和位于所 述外围布线区的透明导电接触电极，所述透明导电接触电极通过所述第一过 孔与所述源漏极保留图案电连接；其中，在形成所述钝化层之前，所述制备 方法还包括：在所述衬底基板上形成位于所述像素区的第二透明电极；所述 第一透明电极和所述第二透明电极其中之一为像素电极，另一个为公共电极。
例如，所述制备方法包括：
在所述衬底基板上形成包括位于所述像素区的栅极、栅线以及位于所述 外围布线区的栅线引线的栅金属层；在形成有所述栅金属层的基板上依次形 成栅绝缘层和位于所述像素区的有源层；其中，在所述栅绝缘层上形成位于 所述外围布线区的第四过孔，所述第四过孔露出所述栅线引线；在形成有所 述栅绝缘层和所述有源层的基板上形成包括位于所述像素区的源极、漏极、 与所述源极电连接的数据线的源漏金属层；在形成有所述源漏金属层的基板 上形成位于所述像素区的第一透明电极以及位于所述外围布线区的第一透明 电极保留图案；其中，所述第一透明电极保留图案通过所述第四过孔与所述 栅线引线电连接；在形成有所述第一透明电极以及所述第一透明电极保留图 案的基板上形成钝化层；其中，在所述钝化层上形成位于所述外围布线区的 第三过孔，所述第三过孔露出所述第一透明电极保留图案；在形成有钝化层 的基板上形成位于所述像素区的第二透明电极以及位于所述外围布线区的透 明导电接触电极；其中，所述透明导电接触电极通过所述第三过孔与所述第 一透明电极保留图案电连接；其中，所述第一透明电极和所述第二透明电极 其中之一为像素电极，另一个为公共电极。
例如，所述制备方法包括：
在所述衬底基板上形成包括位于所述像素区的栅极、栅线的栅金属层； 在形成有所述栅金属层的基板上依次形成栅绝缘层和位于所述像素区的有源 层；在形成有所述栅绝缘层和所述有源层的基板上形成包括位于所述像素区 的源极、漏极、与所述源极电连接的数据线、以及位于所述外围布线区的数 据线引线的源漏金属层；在形成有所述源漏金属层的基板上形成保护层；其 中，在所述保护层上形成位于所述外围布线区的第六过孔，所述第六过孔露 出所述数据线引线；在形成有所述保护层的基板上形成位于所述像素区的第 二透明电极以及位于所述外围布线区的第二透明电极保留图案；在形成有所 述第二透明电极以及所述第二透明电极保留图案的基板上形成钝化层；其中， 在所述钝化层上形成位于所述外围布线区的第五过孔，所述第五过孔露出所 述第二透明电极保留图案；在形成有所述钝化层的基板上形成位于所述像素 区的第一透明电极以及位于所述外围布线区的透明导电接触电极，所述透明 导电接触电极通过所述第五过孔与所述第二透明电极保留图案电连接；其中， 所述第一透明电极和所述第二透明电极其中之一为像素电极，另一个为公共 电极。
例如，所述制备方法包括：
在所述衬底基板上形成包括位于所述像素区的源极、漏极、与所述源极 连接的数据线以及位于所述外围布线区的数据线引线的源漏金属层；在形成 有所述源漏金属层的基板上依次形成位于所述像素区的有源层和栅绝缘层； 其中，在所述栅绝缘层上形成位于所述外围布线区的第八过孔，所述第八过 孔露出所述数据线引线；在形成有所述栅绝缘层的基板上形成包括位于所述 像素区的栅极、栅线以及位于所述外围布线区的栅极保留图案的栅金属层； 在形成有所述栅金属层的基板上形成钝化层；其中，在所述钝化层上形成位 于所述外围布线区的第七过孔，所述第七过孔露出所述栅极保留图案；在形 成有所述钝化层的基板上形成位于所述像素区的第一透明电极和位于所述外 围布线区的透明导电接触电极，所述透明导电接触电极通过所述第七过孔与 所述栅极保留图案电连接；其中，在形成所述钝化层之前，所述制备方法还 包括：在所述衬底基板上形成位于所述像素区的第二透明电极；所述第一透 明电极和所述第二透明电极其中之一为像素电极，另一个为公共电极。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图1为本发明实施例提供的一种阵列基板的俯视结构示意图；
图2为本发明实施例提供的一种阵列基板中外围布线区过孔处的剖面结 构示意图；
图3为本发明实施例提供的一种阵列基板中像素区和对应的外围布线区 过孔处的剖面结构示意图一；
图4为本发明实施例提供的一种阵列基板中像素区和对应的外围布线区 过孔处的剖面结构示意图二；
图5为本发明实施例提供的一种阵列基板中像素区和对应的外围布线区 过孔处的剖面结构示意图三；
图6为本发明实施例提供的一种阵列基板中像素区和对应的外围布线区 过孔处的剖面结构示意图四；
图7为本发明实施例提供的一种阵列基板中像素区和对应的外围布线区 过孔处的剖面结构示意图五；
图8为本发明实施例提供的一种母板的局部俯视结构示意图一；以及
图9为本发明实施例提供的一种母板的局部俯视结构示意图二。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图， 对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例 是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实 施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实 施例，都属于本发明保护的范围。
本发明实施例提供了一种阵列基板01，如图1所示，包括像素区20和 外围布线区30，所述外围布线区30包括设置在所述衬底基板10上的透明导 电接触电极301，所述透明导电接触电极301通过设置于不同绝缘层上的过 孔与设置于下方的金属电极线电连接，且位于不同绝缘层的过孔之间在投影 方向无交叠。
需要说明的是，本发明实施例中，所述投影方向即为沿所述阵列基板01 的垂直方向(即，所述阵列基板01的法线方向)。此外，由于所述透明导电 接触电极301要通过设置在所述透明导电接触电极301下方的不同绝缘层上 的过孔与下方的所述金属电极线电连接，因此，在不同绝缘层之间还可以设 置有导电层，这样一来，例如所述透明导电接触电极301可通过与其下方的 与所述透明导电接触电极301直接接触的第一层绝缘层上的过孔与该导电层 电连接，该导电层再通过下方的第二层绝缘层上的过孔与下方的所述金属电 极线电连接。
这里，不对所述导电层进行限制，考虑到应最大程度地减小所述阵列基 板01的构图工艺次数，在本发明实施例中所述不同绝缘层之间的导电层与所 述像素区20中的导电图案一起形成。
需要说明的是，不对位于所述外围布线区30的所述绝缘层进行限定，其 可以与像素区20的绝缘层一起形成。
需要说明的是，本发明实施例不限定所述金属电极线的具体构成，例如 可以为如图2中所示的所述像素区20中的栅线的延伸线2031和/或数据线的 延伸线2041。
本发明实施例提供了一种阵列基板01，包括设置在衬底基板10上的像 素区20和外围布线区30；所述外围布线区30包括设置在所述衬底基板10 上的透明导电接触电极301，所述透明导电接触电极301通过设置于不同绝 缘层上的过孔与设置于下方的金属电极线电连接，且位于不同绝缘层的过孔 之间在投影方向无交叠。
这样，参考图2所示，由于所述透明导电接触电极301是通过不同绝缘 层上的过孔与所述金属电极线相连的，且位于不同绝缘层的过孔之间在投影 方向无交叠，当水汽渗透暴露在外面的所述透明导电接触电极301时，如图 中箭头方向所示，由于所述过孔通常具有很小的横截面积，能够通过所述透 明导电接触电极301渗透到与其直接接触的绝缘层上的过孔处的水汽分子很 有限，而且由于位于下方的过孔与位于上方的过孔在垂直方向上没有交叠， 这样以来，渗透到位于上方的过孔处的有限的水汽分子很难再到达位于下方 的过孔，从而可以避免设置在下方过孔下方的所述金属电极线被腐蚀。
在上述基础上，参考图1所示，所述像素区20还可以包括设置在衬底基 板10上的多个薄膜晶体管、公共电极202、与所述薄膜晶体管的漏极2003 电连接的像素电极201；所述透明导电接触电极301与所述像素电极201和 所述公共电极202二者中位于上方的一方同层设置。
这里，所述透明导电接触电极301与所述像素电极201和所述公共电极 202中位于上方的一方同层设置，是指在所述像素电极201设置在所述公共 电极202之上的情况下，所述透明导电接触电极301与所述像素电极201同 层设置，当然，为了避免构图工艺次数的增加，所述透明导电接触电极301 与所述像素电极201通过一次构图工艺形成；在所述公共电极202设置在所 述像素电极201之上的情况下，所述透明导电接触电极301与所述公共电极 202同层设置，同样为了避免构图工艺次数的增加，所述透明导电接触电极 301与所述公共电极202通过一次构图工艺形成。
此外，本领域相关技术人员应当理解，图1仅以所述公共电极202设置 在所述像素电极201之上为例进行说明，但本发明实施例不对所述像素电极 201与所述公共电极202的相对位置做限定。
进一步的，所述像素区20还包括设置在所述衬底基板10上的数据线204 和栅线203；所述金属电极线包括栅线的延伸线2031和/或数据线的延伸线 2041。
需要说明的是，上述描述的所述金属电极线包括栅线的延伸线2031和/ 或数据线的延伸线2041是指，在所述像素区20的外围可以设置有不同的外 围布线区30，即：在一种类型的外围布线区30中，所述透明导电接触电极 301与栅线的延伸线2031电连接，在另一种类型的外围布线区30中，所述 透明导电接触电极301与数据线的延伸线2041电连接。根据所述外围布线区 30作用的不同，在同一个所述阵列基板01中，可以包括上述的一种类型的 所述外围布线区30，也可以包括上述的两种类型的所述外围布线区30。
这样，所述像素区20的范围即由横纵交叉的多根所述栅线203和多根所 述数据线204限定；其中，相邻的两根栅线203与相邻的两根数据线204交 叉限定一个像素单元，而每个像素单元包括所述薄膜晶体管、与所述薄膜晶 体管的漏极2003电连接的所述像素电极201以及所述公共电极202。
基于上述的描述，参考图3所示，在所述薄膜晶体管为底栅型薄膜晶体 管，所述栅线的延伸线为栅线引线2031a，且所述栅线引线2031a与所述栅 线203、所述薄膜晶体管的栅极2001同层设置的情况下：
可选的，如图3所示，所述透明导电接触电极301可以通过设置于钝化 层302上的第一过孔3021与源漏极保留图案303电连接，所述源漏极保留图 案303通过设置于栅绝缘层205上的第二过孔2051与所述栅线引线2031a 电连接。
其中，所述钝化层302位于像素区20和外围布线区30，并且，在所述 像素区20中,所述钝化层302位于所述像素电极201和所述公共电极202之 间；所述源漏极保留图案303与所述源极和漏极同层设置；所述栅绝缘层205 位于所述像素区20和外围布线区30，且在所述像素区20中位于所述栅极 2001与所述源极2002和所述漏极2003之间。
由于所述透明导电接触电极301通过上述的钝化层302上的第一过孔 3021与所述源漏极保留图案303电连接，所述源漏极保留图案303通过栅绝 缘层205上的第二过孔2051与所述栅线引线2031a电连接，且所述第一过孔 3021与所述第二过孔2051在垂直方向上没有交叠，可以避免水汽渗透所述 透明导电接触电极301时，直接腐蚀所述栅线引线2031a。
此处，由于从透明导电接触电极301渗透的水汽不易通过错位排列的两 个过孔到达所述栅线引线2031a，因此，这里所述栅线引线2031a的材料可 以采用铝-钕等具有较强抗腐蚀能力的金属合金，也可以采用钼等具有较弱抗 腐蚀能力的金属单质；而所述源漏极保留图案303由于直接通过一个过孔与 所述透明导电接触电极301连接，从透明导电接触电极301渗透的水汽可对 所述源漏极保留图案303造成腐蚀，因此，这里所述源漏极保留图案303的 材料可以采用铝-钕等具有较强抗腐蚀能力的金属合金。
可选的，如图4所示，所述透明导电接触电极301通过设置于钝化层302 上的第三过孔3022与第一透明电极保留图案304电连接，所述第一透明电极 保留图案304通过设置于栅绝缘层205上的第四过孔2052与所述栅线引线 2031a电连接。
其中，所述钝化层302位于像素区20和外围布线区30，并且，在所述 像素区20中，所述钝化层302位于所述像素电极201和所述公共电极202 之间；所述第一透明电极保留图案304与所述像素电极201和所述公共电极 202中位于下方的电极同层设置；所述栅绝缘层205位于所述像素区20和外 围布线区30，且在所述像素区20中位于所述栅极2001与所述源极2002和 所述漏极2003之间。
需要说明的是，图4中仅以所述公共电极202设置在所述像素电极201 之上的情况进行说明，即：当所述公共电极202在上，像素电极201在下时， 所述透明导电接触电极301与所述公共电极202同层设置，所述第一透明电 极保留图案304与所述像素电极201同层设置。
由于所述透明导电接触电极301可以通过上述的钝化层302上的第三过 孔3022与所述第一透明电极保留图案304电连接，所述第一透明电极保留图 案304通过栅绝缘层205上的第四过孔2052与所述栅线引线2031a电连接， 且所述第三过孔3022与所述第四过孔2052在垂直方向上没有交叠，可以避 免水汽渗透所述透明导电接触电极301时，直接腐蚀所述栅线引线2031a。
此处，所述栅线引线2031a的材料可以采用铝-钕等具有较强抗腐蚀能力 的金属合金，也可以采用钼等具有较弱抗腐蚀能力的金属单质；而透明电极 的材料目前一般采用ITO(Indium Tin Oxide，氧化铟锡)等材料，其本身抗 腐蚀性相对较高，因此，不对所述第一透明电极保留图案304的材料进行限 定，但是为了减少构图工艺次数，第一透明电极保留图案304的材料与同层 的像素电极201或公共电极202的材料相同，这样可以通过一次构图工艺既 形成所述第一透明电极保留图案304又形成与之同层的像素电极201或公共 电极202。
在薄膜晶体管为底栅型薄膜晶体管，所述数据线的延伸线为数据线引线 2041a，且所述数据线引线2041a与所述数据线204、所述薄膜晶体管的源极 2002和漏极2003同层设置的情况下：
可选的，如图5所示，所述透明导电接触电极301通过设置于钝化层302 上的第五过孔3023与第二透明电极保留图案305电连接，所述第二透明电极 保留图案305通过设置于保护层306上的第六过孔3061与所述数据线引线 2041a电连接。
其中，所述钝化层302位于像素区20和外围布线区30，并且，在所述 像素区20中，所述钝化层302位于所述像素电极201和所述公共电极202 之间；所述第二透明电极保留图案305与所述像素电极201和所述公共电极 202中位于下方的电极同层设置；所述保护层306位于所述像素区20和外围 布线区30，且在所述像素区20中位于所述源极和所述漏极与靠近的所述像 素电极201或所述公共电极202之间。
需要说明的是，图5中仅以所述公共电极202设置在所述像素电极201 之上的情况进行说明，即：当所述公共电极202在上，像素电极201在下时， 所述透明导电接触电极301与所述公共电极202同层设置，所述第二透明电 极保留图案305与所述像素电极201同层设置；并且，在所述像素区20中， 所述保护层306位于所述源极2002和所述漏极2003与靠近的所述像素电极 201之间。
由于所述透明导电接触电极301可以通过上述的钝化层302上的第五过 孔3023与第二透明电极保留图案305电连接，所述第二透明电极保留图案 305通过保护层306上的第六过孔3061与所述数据线引线2041a电连接，且 所述第五过孔3023与所述第六过孔3061在垂直方向上没有交叠，可以避免 水汽渗透所述透明导电接触电极301时，直接腐蚀所述数据线引线2041a。
此外，在所述薄膜晶体管为顶栅型薄膜晶体管，所述数据线的延伸线为 数据线引线2041a，且所述数据线引线2041a与所述数据线204、所述薄膜晶 体管的源极2002和漏极2003同层设置的情况下：
可选的，如图6所示，所述透明导电接触电极301通过设置于钝化层302 上的第七过孔3024与栅极保留图案307电连接，所述栅极保留图案307通过 设置于栅绝缘层205上的第八过孔2053与所述数据线引线2041a电连接。
其中，所述钝化层302位于像素区20和外围布线区，且在所述像素区 20中位于所述栅极2001上方；所述栅极保留图案307与所述栅极同层设置； 所述栅绝缘层205位于所述像素区20和外围布线区30，且在所述像素区20 中位于所述栅极2001与所述源极2002和所述漏极2003之间。
需要说明的是，在本发明所有实施例中，所述钝化层302在所述像素区 20中位于所述栅极2001上方，是指在所述阵列基板01的制备过程中，先形 成的所述栅极2001，再形成所述钝化层302。
由于所述透明导电接触电极301通过设置于钝化层302上的第七过孔 3024与栅极保留图案307电连接，所述栅极保留图案307通过设置于栅绝缘 层205上的第八过孔2053与所述数据线引线2041a电连接，且所述第七过孔 3024与所述第八过孔2053在垂直方向上没有交叠，可以避免水汽渗透所述 透明导电接触电极301时，直接腐蚀数据线引线2041a。
基于上述的描述，由于像素电极201与所述漏极2003需电连接，考虑到 工艺制备过程的复杂度，参考图3～图6所示，所述透明导电接触电极301与 所述公共电极202同层设置，所述像素电极201设置于所述公共电极201和 所述衬底基板10之间。其中，像素电极201的位置可以根据薄膜晶体管的类 型进行相应的调整，以最大可能的简化工艺复杂度。当然，所述透明导电接 触电极301也可以与所述像素电极201同层设置，所述公共电极202设置于 所述像素电极201和所述衬底基板10之间，此处不再赘述。
下面提供一个具体实施例，用来详细描述上述的阵列基板。
本发明实施例提供了一种阵列基板01，如图7所示，包括像素区20和 外围布线区30，所述像素区20包括设置在衬底基板10上的多个底栅型薄膜 晶体管、与所述底栅型薄膜晶体管的漏极2003电连接的像素电极201、设置 在所述像素电极之上的公共电极202、以及多根栅线203和多根数据线204 (图7中未标识出)。
进一步的，参考图7所示，所述外围布线区30包括设置在衬底基板10 上的透明导电接触电极301以及栅线引线2031a，其中所述透明导电接触电 极301与所述公共电极202同层且通过一次构图工艺形成；所述栅线引线 2031a与所述栅线203、所述栅极2001同层且通过一次构图工艺形成。
所述透明导电接触电极301通过设置于钝化层302上的第一过孔3021 与源漏极保留图案303电连接，所述源漏极保留图案303再通过设置在栅绝 缘层205上的第二过孔2051与栅线引线2031a电连接，且沿所述阵列基板 01的垂直方向，所述两个过孔无交叠；其中所述源漏极保留图案303与所述 源极和漏极同层且通过一次构图工艺形成。
此处，所述钝化层302和所述栅绝缘层205既位于像素区20也位于外围 布线区30；在所述像素区20中,所述钝化层302位于所述像素电极201和所 述公共电极202之间，所述栅绝缘层205位于所述栅极2001与所述源极2002 和所述漏极2003之间。
此外，由于从透明导电接触电极301渗透的水汽不易通过的错位排列的 两个过孔到达下方的所述栅线引线2031a，因此，这里所述栅线引线2031a 的材料可以采用铝-钕等具有较强抗腐蚀能力的金属合金，也可以采用钼等具 有较弱抗腐蚀能力的金属单质；而所述源漏极保留图案303由于直接通过一 个过孔与所述透明导电接触电极301连接，从透明导电接触电极301渗透的 水汽可对所述源漏极保留图案303造成腐蚀，所以，这里所述源漏极保留图 案303的材料可以采用铝-钕等具有较强抗腐蚀能力的金属合金。
这样，当水汽渗透暴露在外面的所述透明导电接触电极301，并通过第 一过孔3021向下渗透时，由于第一过孔3021本身的尺寸较小，能够通过所 述透明导电接触电极301渗透到第一过孔3021的水汽分子很有限，而且由于 第二过孔2051与第一过孔3021在垂直方向上没有交叠，这样以来，渗透到 第一过孔3021处的有限的水汽分子很难再到达位于下方的第二过孔2051， 从而可以避免使设置在第二过孔2051下方的所述栅线引线2031a被腐蚀。
在上述实施例的基础上，参考图5所示，在所述外围布线区30，还可以 包括设置在衬底基板10上的数据线引线2041a，其中，所述数据线引线2041a 与所述数据线204、所述薄膜晶体管的源极2002和漏极2003同层且通过一 次构图工艺形成。
在此情况下，所述透明导电接触电极301通过设置于钝化层302上的第 五过孔3023与第二透明电极保留图案305电连接，所述第二透明电极保留图 案305通过设置于保护层306上的第六过孔3061与所述数据线引线2041a 电连接。
其中，所述第二透明电极保留图案305与所述像素电极201同层且通过 一次构图工艺形成；所述保护层306既位于像素区20也位于外围布线区30， 且在所述像素区20中位于所述源极2002和所述漏极2003与所述像素电极 201之间。
这样，当水汽渗透暴露在外面的所述透明导电接触电极301时，也可以 避免使设置在第六过孔3061下方的所述数据线引线2041a被腐蚀。
本发明实施例提供一种显示装置，包括上述任一项所述的阵列基板。
上述液晶显示装置具体可以为液晶显示器、液晶电视、数码相框、手机、 平板电脑等具有任何显示功能的产品或者部件。
本发明实施例还提供了一种母板，包括至少一个阵列基板01，所述阵列 基板01为上述任一项所述的阵列基板01。
此处，所述母板是指在阵列基板01的制备过程中在一整块相对较大的衬 底基板上形成多个阵列基板01，通过切割等工艺形成多个具有特定尺寸的阵 列基板01，因此，所述母板中包括的阵列基板01为多个上述的同一种类型 的所述阵列基板01。
可选的，如图8所示，所述母板还包括：与所述阵列基板01的数据线 204平行，且与透明导电接触电极301均电连接的测试栅线308；和/或，与 所述阵列基板的栅线203平行，且与所述透明导电接触电极301均电连接的 测试数据线309；其中，所述测试栅线308和/或所述测试数据线309与所述 透明导电接触电极301同层设置。此外，例如，所述测试栅线308和/或所述 测试数据线309与所述透明导电接触电极301通过一次构图工艺形成。
由于所述透明导电接触电极301通过不同绝缘层上的两个过孔与所述栅 线引线2031a，和/或所述数据线引线2041a电连接，而所述栅线引线2031a、 所述数据引线2041a又分别与所述栅线203、所述数据线204电连接，通过 所述测试栅线308将与所述栅线引线2031a电连接的所述透明导电接触电极 301电连接在一起，可以对设置于下方的即对所述栅线203进行检测，从而 判断其是否导通；同样的，通过所述测试数据线309将与所述数据引线2041a 电连接的所述透明导电接触电极301电连接在一起，可以对设置于下方的所 述数据线204进行检测，从而判断其是否导通。
测试完毕后，可以通过将所述测试栅线308和/或所述测试数据线309与 所述透明导电接触电极301切割开来等方式形成单个的所述阵列基板01。
进一步可选的，如图9所示，所述测试栅线308和所述测试数据线309 电连接，这样，可以保持所述母板中分别与所述测试栅线308和所述测试数 据线309电连接的所述栅线203和所述数据线204的电位均一致，避免了由 于在所述母板中产生静电电位差，而对所述母板产生的静电破坏。
本发明实施例还提供了一种针对上述所述阵列基板01的制备方法，包 括：
在衬底基板10的像素区20周边的外围布线区30形成金属电极线、以及 位于所述金属电极线上方的透明导电接触电极301；其中，所述透明导电接 触电极301通过设置于不同绝缘层上的过孔与设置于下方的所述金属电极线 电连接，且位于不同绝缘层的过孔之间在投影方向无交叠。
这里，所述制备方法还包括：在所述衬底基板10的所述像素区20形成 多个薄膜晶体管、公共电极202和与所述薄膜晶体管的漏极2003电连接的像 素电极201；其中，所述透明导电接触电极301与所述像素电极201和所述 公共电极202二者中位于上方的一方同层设置。
进一步的，所述在衬底基板10的外围布线区30形成金属电极线，包括： 在所述衬底基板10的所述外围布线区30形成栅线的延伸线2031和/或数据 线的延伸线2041。
在上述基础上，针对上述所述阵列基板01的可选的制备方法一，参考图 3所示，具体可包括：
S11、在所述衬底基板10上形成包括位于所述像素区20的栅极2001、 栅线203(图中未标识出)以及位于所述外围布线区的栅线引线2031a的栅 金属层。
S12、在形成有所述栅金属层的基板上依次形成栅绝缘层205和位于所 述像素区20的有源层；其中，在所述栅绝缘层205上形成位于所述外围布线 区30的第二过孔2051，所述第二过孔2051露出所述栅线引线2031a。
S13、在形成有所述栅绝缘层205和所述有源层的基板上形成包括位于 所述像素区20的源极2002、漏极2003、与所述源极2002电连接的数据线 204(图中未标识出)以及位于所述外围布线区30的源漏极保留图案303的 源漏金属层；所述源漏极保留图案303通过所述第二过孔2051与所述栅线引 线2031a电连接。
S14、在形成有所述源漏金属层的基板上形成钝化层302；其中，在所述 钝化层302上形成位于所述外围布线区30的第一过孔3021，所述第一过孔 3021露出所述源漏极保留图案303。
S15、在形成有所述钝化层302的基板上形成位于所述像素区20的第一 透明电极和位于所述外围布线区30的透明导电接触电极301，所述透明导电 接触电极301通过所述第一过孔3021与所述源漏极保留图案303电连接。
其中，在形成所述钝化层302之前，所述制备方法还包括：在所述衬底 基板10上形成位于所述像素区20的第二透明电极，即相对于所述衬底基板 10，所述第一透明电极位于所述第二透明电极的上方；其中，所述第一透明 电极和所述第二透明电极其中之一为像素电极201，另一个为公共电极202。
这里，当所述第一透明电极为公共电极202，所述第二透明电极为像素 电极201的情况下，参考图3所示，例如可以在完成所述步骤S13之后，进 行所述步骤S14之前，形成位于所述像素区20的所述像素电极201。在此情 况下，在所述步骤S15中，形成位于所述像素区20的所述公共电极202和 位于所述外围布线区30的所述透明导电接触电极301。
需要说明的是，当所述第二透明电极为公共电极202，所述第一透明电 极为像素电极的情况下，需保证所述公共电极202与所述源极2002、漏极2003 等无电连接，因此，若所述第二透明电极形成在所述源极2002、漏极2003 之后且钝化层302之前时，需通过形成绝缘层来使所述源极2002、漏极2003 与所述第二透明电极绝缘。
这样，参考图3所示，由于所述透明导电接触电极301通过所述第一过 孔3021与所述源漏极保留图案303电连接，而所述源漏极保留图案303通过 所述第二过孔2051与所述栅线引线2031a电连接，且所述第一过孔3021与 所述第二过孔2051在垂直方向上没有交叠，可以避免水汽渗透所述透明导电 接触电极301时，直接腐蚀所述栅线引线2031a。
由于从透明导电接触电极301渗透的水汽不易通过相互的错位排列的所 述第一过孔3021以及所述第二过孔2051到达所述栅线引线2031a，因此， 所述栅线引线2031a可以采用铝-钕等具有较强抗腐蚀能力的金属合金材料， 也可以采用钼等具有较弱抗腐蚀能力的金属单质材料；而所述源漏极保留图 案303由于直接通过所述第二过孔2051与所述透明导电接触电极301连接， 从所述透明导电接触电极301渗透的水汽可对所述源漏极保留图案303造成 腐蚀，因此，所述源漏极金属层可以采用铝-钕等具有较强抗腐蚀能力的金属 合金材料。
针对上述所述阵列基板01的可选的制备方法二，参考图4所示，具体可 包括：
S21、在所述衬底基板10上形成包括位于所述像素区20的栅极2001、 栅线203(图中未标识出)以及位于所述外围布线区30的栅线引线2031的 栅金属层。
S22、在形成有所述栅金属层的基板上依次形成栅绝缘层205和位于所 述像素区20的有源层；其中，在所述栅绝缘层205上形成位于所述外围布线 区30的第四过孔2052，所述第四过孔2052露出所述栅线引线2031a。
S23、在形成有所述栅绝缘层205和所述有源层的基板上形成包括位于 所述像素区20的源极2002、漏极2003、与所述源极2002电连接的数据线 204(图中未标识出)的源漏金属层。
S24、在形成有所述源漏金属层的基板上形成位于所述像素区20的第一 透明电极以及位于所述外围布线区30的第一透明电极保留图案304；其中， 所述第一透明电极保留图案304通过所述第四过孔2052与所述栅线引线 2031a电连接。
S25、在形成有所述第一透明电极以及所述第一透明电极保留图案304 的基板上形成钝化层302；其中，在所述钝化层302上形成位于所述外围布 线区30的第三过孔3022，所述第三过孔3022露出所述第一透明电极保留图 案304。
S26、在形成有钝化层302的基板上形成位于所述像素区20的第二透明 电极以及位于所述外围布线区30的透明导电接触电极301；其中，所述透明 导电接触电极301通过所述第三过孔3022与所述第一透明电极保留图案304 电连接。
其中，所述第一透明电极和所述第二透明电极其中之一为像素电极201， 另一个为公共电极202。
这里，当所述第二透明电极为公共电极202，所述第一透明电极为像素 电极201的情况下，参考图4所示，例如可以在所述步骤S24中，形成位于 所述像素区20的所述像素电极201以及位于所述外围布线区30的所述第一 透明电极保留图案304，在所述步骤S26中形成位于所述像素区20的所述公 共电极202以及位于所述外围布线区30的所述透明导电接触电极301。
当所述第一透明电极为公共电极202，第二透明电极为像素电极201的 情况下，在完成所述步骤S23之后、进行所述步骤S24之前需形成绝缘层， 以使源极2002、漏极2003与所述第一透明电极绝缘。
这样，参考图4所示，由于所述透明导电接触电极301通过所述第三过 孔3022与所述第一透明电极保留图案304电连接，而所述第一透明电极保留 图案304通过所述第四过孔2052与所述栅线引线2031a电连接，且所述第三 过孔3022与所述第四过孔2052在垂直方向上没有交叠，可以避免水汽渗透 所述透明导电接触电极301时，直接腐蚀所述栅线引线2031a。
这里，由于制作所述第一透明电极一般采用ITO(Indium Tin Oxide，氧 化铟锡)等透明导电材料，其本身抗腐蚀性相对较高，因此，本发明实施例 不限定所述第一透明电极所采用的材料。
针对上述所述阵列基板01的可选的制备方法三，参考图5所示，具体可 包括：
S31、在所述衬底基板10上形成包括位于所述像素区20的栅极2001、 栅线203(图中未标识出)的栅金属层。
S32、在形成有所述栅金属层的基板上依次形成栅绝缘层205和位于所 述像素区20的有源层。
S33、在形成有所述栅绝缘层205和所述有源层的基板上形成包括位于 所述像素区20的源极2002、漏极2003、与所述源极2002电连接的数据线 204(图中未标识出)、以及位于所述外围布线区30的数据线引线2041a的 源漏金属层。
S34、在形成有所述源漏金属层的基板上形成保护层306；其中，在所述 保护层306上形成位于所述外围布线区30的第六过孔3061，所述第六过孔 3061露出所述数据线引线2041a。
S35、在形成有所述保护层306的基板上形成位于所述像素区20的第二 透明电极以及位于所述外围布线区30的第二透明电极保留图案305。
S36、在形成有所述第二透明电极以及所述第二透明电极保留图案305 的基板上形成钝化层302；其中，在所述钝化层302上形成位于所述外围布 线区30的第五过孔3023，所述第五过孔3023露出所述第二透明电极保留图 案305。
S37、在形成有所述钝化层302的基板上形成位于所述像素区20的第一 透明电极以及位于所述外围布线区30的透明导电接触电极301，所述透明导 电接触电极301通过所述第五过孔3023与所述第二透明电极保留图案305 电连接。
其中，所述第一透明电极和所述第二透明电极其中之一为像素电极201， 另一个为公共电极202。
这里，当所述第二透明电极为像素电极201，所述第一透明电极为公共 电极202的情况下，参考图5所示，例如可以在所述步骤S34中在所述保护 层306上形成位于像素区20的过孔，该过孔露出所述漏极2003；在所述步 骤S35中，形成位于所述像素区20的所述像素电极201以及位于所述外围 布线区30的所述第二透明电极保留图案305，其中所述像素电极201通过该 过孔与所述漏极2003电连接；在此情况下，在所述步骤S37中形成位于所 述像素区20的所述公共电极202以及位于所述外围布线区30的所述透明导 电接触电极301。
当所述第一透明电极为像素电极201，第二透明电极为公共电极202的 情况下，则需在位于所述像素区20的所述保护层306上和所述钝化层302 上均形成用于连接所述像素电极201和所述漏极2003的过孔，在此不再赘述。
这样，参考图5所示，由于所述透明导电接触电极301通过所述第五过 孔3023与所述第二透明电极保留图案305电连接，而所述第二透明电极保留 图案305通过所述第六过孔3061与所述数据线引线2041a电连接，且所述第 五过孔3023与所述第六过孔3061在垂直方向上没有交叠，可以避免水汽渗 透所述透明导电接触电极301时，直接腐蚀所述数据线引线2041a。
针对上述所述阵列基板01的可选的制备方法四，参考图6所示，具体可 包括：
S41、在所述衬底基板10上形成包括位于所述像素区20的源极2002、 漏极2003、与所述源极2002连接的数据线204(图中未标识出)以及位于所 述外围布线区30的数据线引线2041a的源漏金属层。
S42、在形成有所述源漏金属层的基板上依次形成位于所述像素区20的 有源层和栅绝缘层205；其中，在所述栅绝缘层205上形成位于所述外围布 线区30的第八过孔2053，所述第八过孔2053露出所述数据线引线2041a。
S43、在形成有所述栅绝缘层205的基板上形成包括位于所述像素区20 的栅极2001、栅线203(图中未标识出)以及位于所述外围布线区30的栅极 保留图案307的栅金属层。
S44、在形成有所述栅金属层的基板上形成钝化层302；其中，在所述钝 化层302上形成位于所述外围布线区30的第七过孔3024，所述第七过孔3024 露出所述栅极保留图案307。
S45、在形成有所述钝化层302的基板上形成位于所述像素区20的第一 透明电极和位于所述外围布线区30的透明导电接触电极301，所述透明导电 接触电极301通过所述第七过孔3024与所述栅极保留图案307电连接。
其中，在形成所述钝化层302之前，所述制备方法还包括：在所述衬底 基板10上形成位于所述像素区20的第二透明电极；所述第一透明电极和所 述第二透明电极其中之一为像素电极201，另一个为公共电极202。
这里，当所述第二透明电极为像素电极201，所述第一透明电极为公共 电极202的情况下，参考图6所示，例如可以在完成所述步骤S41之后、进 行所述步骤S42之前，形成位于所述像素区20的所述像素电极201；在此情 况下，在所述步骤S45中形成位于所述像素区20的所述公共电极202以及 位于所述外围布线区30的所述透明导电接触电极301。
当所述第一透明电极为像素电极201，所述第二透明电极为公共电极202 的情况下，可以在完成所述步骤S43之后，进行所述步骤S44之前，形成绝 缘层和位于所述像素区20的所述公共电极202；在此情况下，在所述步骤 S45中形成位于所述像素区20的所述像素电极201以及位于所述外围布线区 30的所述透明导电接触电极301。
这样，参考图6所示，由于所述透明导电接触电极301通过设置于钝化 层302上的所述第七过孔3024与所述栅极保留图案307电连接，所述栅极保 留图案307通过设置于所述栅绝缘层205上的所述第八过孔2053与所述数据 线引线2041a电连接，且所述第七过孔3024与所述第八过孔2053在垂直方 向上没有交叠，可以避免水汽渗透所述透明导电接触电极301时，直接腐蚀 所述数据线引线2041a。
这里，由于从透明导电接触电极301渗透的水汽不易通过错位排列的所 述第七过孔3024以及所述第八过孔2053到达所述数据线引线2041a，因此， 这里所述数据线引线2041a的材料可以采用铝-钕等具有较强抗腐蚀能力的 金属合金，也可以采用钼等具有较弱抗腐蚀能力的金属单质；而所述栅极保 留图案307由于直接通过所述第七过孔3024与所述透明导电接触电极301 连接，从透明导电接触电极301渗透的水汽可对所述栅极保留图案307造成 腐蚀，因此，这里所述栅极保留图案307的材料可以采用铝-钕等具有较强抗 腐蚀能力的金属合金。
需要说明的是，本技术领域技术人员还应该明白，本发明所有附图是阵 列基板的简略的示意图，只为清楚描述本方案体现了与发明点相关的结构， 对于其他的与发明点无关的结构是现有结构，在附图中并未体现或只体现部 分。
需要说明的是，在上述实施例中均描述了外围布线区设置有两层绝缘层 和两个过孔的情况。但是，根据实际需要，外围布线区可能或设置多层绝缘 层，在此情况下，相应地也要设置多个在投影方向无交叠的过孔和多个位于 绝缘层之间的导电层，这均属于本发明的保护范围。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范 围，本发明的保护范围由所附的权利要求确定。
相关申请的交叉引用
本申请要求于2013年12月27日递交的第201310741386.7号中国专利 申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的 一部分。

Claims (20)

  1. 一种阵列基板，包括像素区和外围布线区，其中
    所述外围布线区包括设置在衬底基板上的透明导电接触电极，所述透明 导电接触电极通过设置于不同绝缘层上的过孔与设置于下方的金属电极线电 连接，且位于不同绝缘层的过孔之间在投影方向无交叠。
  2. 根据权利要求1所述的阵列基板，其中所述像素区包括设置在所述衬 底基板上的多个薄膜晶体管、公共电极和与所述薄膜晶体管的漏极电连接的 像素电极；
    所述透明导电接触电极与所述像素电极和所述公共电极二者中位于上方 的一方同层设置。
  3. 根据权利要求2所述的阵列基板，其中所述像素区还包括设置在所述 衬底基板上的数据线和栅线；
    所述金属电极线包括栅线的延伸线和/或数据线的延伸线。
  4. 根据权利要求3所述的阵列基板，其中所述薄膜晶体管为底栅型薄膜 晶体管；所述栅线的延伸线包括栅线引线，且所述栅线引线与所述栅线、所 述薄膜晶体管的栅极同层设置；
    所述透明导电接触电极通过设置于钝化层上的第一过孔与源漏极保留图 案电连接，所述源漏极保留图案通过设置于栅绝缘层上的第二过孔与所述栅 线引线电连接；
    所述钝化层位于像素区和外围布线区，且在所述像素区中位于所述像素 电极和所述公共电极之间；所述源漏极保留图案与所述源极和漏极同层设置；
    所述栅绝缘层位于所述像素区和外围布线区，且在所述像素区中位于所 述栅极与所述源极和所述漏极之间。
  5. 根据权利要求3所述的阵列基板，其中所述薄膜晶体管为底栅型薄膜 晶体管；所述栅线的延伸线包括栅线引线，且所述栅线引线与所述栅线、所 述薄膜晶体管的栅极同层设置；
    所述透明导电接触电极通过设置于钝化层上的第三过孔与第一透明电极 保留图案电连接，所述第一透明电极保留图案通过设置于栅绝缘层上的第四 过孔与所述栅线引线电连接；
    所述钝化层位于像素区和外围布线区，且在所述像素区中位于所述像素 电极和所述公共电极之间；所述第一透明电极保留图案与所述像素电极和所 述公共电极中位于下方的电极同层设置；
    所述栅绝缘层位于所述像素区和外围布线区，且在所述像素区中位于所 述栅极与所述源极和所述漏极之间。
  6. 根据权利要求3所述的阵列基板，其中薄膜晶体管为底栅型薄膜晶体 管；所述数据线的延伸线包括数据线引线，且所述数据线引线与所述数据线、 所述薄膜晶体管的源极和漏极同层设置；
    所述透明导电接触电极通过设置于钝化层上的第五过孔与第二透明电极 保留图案电连接，所述第二透明电极保留图案通过设置于保护层上的第六过 孔与所述数据线引线电连接；
    所述钝化层位于像素区和外围布线区，且在所述像素区中位于所述像素 电极和所述公共电极之间；所述第二透明电极保留图案与所述像素电极和所 述公共电极中位于下方的电极同层设置；
    所述保护层位于所述像素区和外围布线区，且在所述像素区中位于所述 源极和所述漏极与靠近的所述像素电极或所述公共电极之间。
  7. 根据权利要求3所述的阵列基板，其中薄膜晶体管为顶栅型薄膜晶体 管；所述数据线的延伸线包括数据线引线，且所述数据线引线与所述数据线、 所述薄膜晶体管的源极和漏极同层设置；
    所述透明导电接触电极通过设置于钝化层上的第七过孔与栅极保留图案 电连接，所述栅极保留图案通过设置于栅绝缘层上的第八过孔与所述数据线 引线电连接；
    所述钝化层位于像素区和外围布线区，且在所述像素区中位于所述栅极 上方；所述栅极保留图案与所述栅极同层设置；
    所述栅绝缘层位于所述像素区和外围布线区，且在所述像素区中位于所 述栅极与所述源极和所述漏极之间。
  8. 根据权利要求2所述的阵列基板，其中
    所述透明导电接触电极与所述公共电极同层设置；
    所述像素电极设置于所述公共电极和所述衬底基板之间。
  9. 根据权利要求2所述的阵列基板，其中
    所述透明导电接触电极与所述像素电极同层设置；
    所述公共电极设置于所述像素电极和所述衬底基板之间。
  10. 一种如权利要求1至9任一项所述阵列基板的制备方法，包括：
    在衬底基板的像素区周边的外围布线区形成金属电极线、以及位于所述 金属电极线上方的透明导电接触电极；
    其中，所述透明导电接触电极通过形成于不同绝缘层上的过孔与形成于 下方的所述金属电极线电连接，且位于不同绝缘层的过孔之间在投影方向无 交叠。
  11. 根据权利要求10所述的制备方法，其中所述制备方法还包括：
    在所述衬底基板的所述像素区形成多个薄膜晶体管、公共电极和与所述 薄膜晶体管的漏极电连接的像素电极；
    其中所述透明导电接触电极与所述像素电极和所述公共电极二者中位于 上方的一方同层形成。
  12. 根据权利要求11所述的制备方法，其中
    所述在衬底基板的外围布线区形成金属电极线包括：在所述衬底基板的 所述外围布线区形成栅线的延伸线和/或数据线的延伸线。
  13. 根据权利要求12所述的制备方法，其中所述制备方法包括：
    在所述衬底基板上形成包括位于所述像素区的栅极、栅线以及位于所述 外围布线区的栅线引线的栅金属层；
    在形成有所述栅金属层的基板上依次形成栅绝缘层和位于所述像素区的 有源层；其中，在所述栅绝缘层上形成位于所述外围布线区的第二过孔，所 述第二过孔露出所述栅线引线；
    在形成有所述栅绝缘层和所述有源层的基板上形成包括位于所述像素区 的源极、漏极、与所述源极电连接的数据线以及位于所述外围布线区的源漏 极保留图案的源漏金属层；所述源漏极保留图案通过所述第二过孔与所述栅 线引线电连接；
    在形成有所述源漏金属层的基板上形成钝化层；其中，在所述钝化层上 形成位于所述外围布线区的第一过孔，所述第一过孔露出所述源漏极保留图 案；
    在形成有所述钝化层的基板上形成位于所述像素区的第一透明电极和位 于所述外围布线区的透明导电接触电极，所述透明导电接触电极通过所述第 一过孔与所述源漏极保留图案电连接；
    其中，在形成所述钝化层之前，所述制备方法还包括：在所述衬底基板 上形成位于所述像素区的第二透明电极；
    所述第一透明电极和所述第二透明电极其中之一为像素电极，另一个为 公共电极。
  14. 根据权利要求12所述的制备方法，其中所述制备方法包括：
    在所述衬底基板上形成包括位于所述像素区的栅极、栅线以及位于所述 外围布线区的栅线引线的栅金属层；
    在形成有所述栅金属层的基板上依次形成栅绝缘层和位于所述像素区的 有源层；其中，在所述栅绝缘层上形成位于所述外围布线区的第四过孔，所 述第四过孔露出所述栅线引线；
    在形成有所述栅绝缘层和所述有源层的基板上形成包括位于所述像素区 的源极、漏极、与所述源极电连接的数据线的源漏金属层；
    在形成有所述源漏金属层的基板上形成位于所述像素区的第一透明电极 以及位于所述外围布线区的第一透明电极保留图案；其中，所述第一透明电 极保留图案通过所述第四过孔与所述栅线引线电连接；
    在形成有所述第一透明电极以及所述第一透明电极保留图案的基板上形 成钝化层；其中，在所述钝化层上形成位于所述外围布线区的第三过孔，所 述第三过孔露出所述第一透明电极保留图案；
    在形成有钝化层的基板上形成位于所述像素区的第二透明电极以及位于 所述外围布线区的透明导电接触电极；其中，所述透明导电接触电极通过所 述第三过孔与所述第一透明电极保留图案电连接；
    其中，所述第一透明电极和所述第二透明电极其中之一为像素电极，另 一个为公共电极。
  15. 根据权利要求12所述的制备方法，其中所述制备方法包括：
    在所述衬底基板上形成包括位于所述像素区的栅极、栅线的栅金属层；
    在形成有所述栅金属层的基板上依次形成栅绝缘层和位于所述像素区的 有源层；
    在形成有所述栅绝缘层和所述有源层的基板上形成包括位于所述像素区 的源极、漏极、与所述源极电连接的数据线、以及位于所述外围布线区的数 据线引线的源漏金属层；
    在形成有所述源漏金属层的基板上形成保护层；其中，在所述保护层上 形成位于所述外围布线区的第六过孔，所述第六过孔露出所述数据线引线；
    在形成有所述保护层的基板上形成位于所述像素区的第二透明电极以及 位于所述外围布线区的第二透明电极保留图案；
    在形成有所述第二透明电极以及所述第二透明电极保留图案的基板上形 成钝化层；其中，在所述钝化层上形成位于所述外围布线区的第五过孔，所 述第五过孔露出所述第二透明电极保留图案；
    在形成有所述钝化层的基板上形成位于所述像素区的第一透明电极以及 位于所述外围布线区的透明导电接触电极，所述透明导电接触电极通过所述 第五过孔与所述第二透明电极保留图案电连接；
    其中，所述第一透明电极和所述第二透明电极其中之一为像素电极，另 一个为公共电极。
  16. 根据权利要求12所述的制备方法，其中所述制备方法包括：
    在所述衬底基板上形成包括位于所述像素区的源极、漏极、与所述源极 连接的数据线以及位于所述外围布线区的数据线引线的源漏金属层；
    在形成有所述源漏金属层的基板上依次形成位于所述像素区的有源层和 栅绝缘层；其中，在所述栅绝缘层上形成位于所述外围布线区的第八过孔， 所述第八过孔露出所述数据线引线；
    在形成有所述栅绝缘层的基板上形成包括位于所述像素区的栅极、栅线 以及位于所述外围布线区的栅极保留图案的栅金属层；
    在形成有所述栅金属层的基板上形成钝化层；其中，在所述钝化层上形 成位于所述外围布线区的第七过孔，所述第七过孔露出所述栅极保留图案；
    在形成有包括所述钝化层的基板上形成位于所述像素区的第一透明电极 和位于所述外围布线区的透明导电接触电极，所述透明导电接触电极通过所 述第七过孔与所述栅极保留图案电连接；
    其中，在形成所述钝化层之前，所述制备方法还包括：在所述衬底基板 上形成位于所述像素区的第二透明电极；
    所述第一透明电极和所述第二透明电极其中之一为像素电极，另一个为 公共电极。
  17. 一种显示装置，包括权利要求1至9任一项所述的阵列基板。
  18. 一种母板，包括至少一个阵列基板，所述阵列基板为权利要求1至 9任一项所述的阵列基板。
  19. 根据权利要求18所述的母板，其中所述母板还包括：
    与所述阵列基板的数据线平行，且与透明导电接触电极均电连接的测试 栅线；和/或，
    与所述阵列基板的栅线平行，且与所述透明导电接触电极均电连接的测 试数据线；
    其中，所述测试栅线和/或所述测试数据线与所述透明导电接触电极同层 设置。
  20. 根据权利要求19所述的母板，其中所述测试栅线和所述测试数据线 电连接。
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