WO2019227963A1 - 显示面板及其制造方法、显示装置 - Google Patents

显示面板及其制造方法、显示装置 Download PDF

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Publication number
WO2019227963A1
WO2019227963A1 PCT/CN2019/074197 CN2019074197W WO2019227963A1 WO 2019227963 A1 WO2019227963 A1 WO 2019227963A1 CN 2019074197 W CN2019074197 W CN 2019074197W WO 2019227963 A1 WO2019227963 A1 WO 2019227963A1
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Prior art keywords
layer
segment
lead
display area
insulating layer
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PCT/CN2019/074197
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English (en)
French (fr)
Inventor
廖文骏
张陶然
冯巧
李林宣
尚延阳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/471,696 priority Critical patent/US11594557B2/en
Publication of WO2019227963A1 publication Critical patent/WO2019227963A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • Embodiments of the present disclosure relate to a display panel, a manufacturing method thereof, and a display device.
  • the non-display area of the display panel is prone to cracks when it is bumped.
  • the display panel cannot be used normally.
  • a detection line is provided in a non-display area of a display panel to detect a crack in the non-display area.
  • the detection line may be electrically connected to the data line in the display area.
  • a detection signal may be applied to the data line through the detection line, and whether the display panel displays a vertical orientation. Bright line. It should be noted that if the non-display area of the display panel is cracked when it is bumped, the detection line will also be broken when it is bumped, and the detection signal cannot be transmitted to the data line. At this time, the locations of these data lines are Bright vertical lines are displayed. Therefore, it is possible to determine whether a crack occurs in the non-display area by detecting whether the display panel can display a vertical bright line.
  • At least one embodiment of the present disclosure provides a display panel including a base substrate, a display area and a non-display area provided on the base substrate, and a data line is provided in the display area; the non-display A detection line is provided in the area; wherein the detection line is electrically connected to the data line and is formed by overlapping a plurality of wire segments.
  • the plurality of lead segments include: a first lead segment, and other lead segments other than the first lead segment, and the first lead segment and the base substrate Septa are provided in the rooms.
  • the other lead segments include: a second lead segment, the first lead segment and the second lead segment are alternately arranged, and the first lead segment overlaps the first lead segment On the second wire segment.
  • the spacer includes a first insulation layer, the first insulation layer is located on the second wire segment and covers the non-display area, and the first insulation layer is disposed on the first insulation layer.
  • a first target conductive layer, a first target insulating layer, and a second target conductive layer that are sequentially formed are further disposed in a display area on the base substrate.
  • the first target conductive layer is disposed on the same layer
  • the first insulating layer is disposed on the same layer as the first target insulating layer
  • the first wire segment is disposed on the same layer as the second target conductive layer.
  • a thin-film transistor having a top-gate structure and a storage capacitor are further provided in a display region on the base substrate.
  • the thin-film transistor includes: an active layer sequentially disposed on the base substrate, A first gate insulating layer, a gate, a second gate insulating layer, a source-drain insulating layer, and a source-drain pattern;
  • the storage capacitor includes a first electrode, a capacitor insulating layer, and A second electrode;
  • the first target conductive layer includes the gate, the first target insulating layer includes the second gate insulating layer, and the second target conductive layer includes the second electrode.
  • the other wire segments include: a third wire segment and a fourth wire segment, the first wire segment and the third wire segment are alternately and spaced one by one, and the fourth The lead segments are overlapped on the adjacent first lead segments and the third lead segments.
  • the spacer includes a second insulating layer located on the third wire segment and covering the non-display area, and the first wire segment is disposed on the second insulation.
  • a third insulating layer on the first lead segment and covering the non-display area is further provided on the base substrate;
  • the second insulating layer and the third insulating layer are provided with a second via hole penetrating through the second insulating layer and the third insulating layer, and the second via hole and an adjacent first wire segment It is in communication with a third wire segment, and the fourth wire segment is disposed on the third insulation layer, and is overlapped on the third wire segment and the first wire segment through the second via hole.
  • a third target conductive layer a second target insulating layer, a fourth target conductive layer, a third target insulating layer, and Five target conductive layers,
  • the third wire segment is disposed on the same layer as the third target conductive layer
  • the second insulation layer is disposed on the same layer as the second target insulation layer
  • the first wire segment is disposed on the fourth target conductive layer
  • the third insulating layer is disposed on the same layer as the second target insulating layer
  • the fourth wire segment is disposed on the same layer as the fifth target conductive layer.
  • a thin-film transistor with a top-gate structure and a storage capacitor are further disposed in a display area on the substrate, wherein:
  • the thin film transistor includes: an active layer, a first gate insulating layer, a gate, a second gate insulating layer, a source-drain insulating layer, and a source-drain pattern disposed in this order on a substrate;
  • the storage capacitor includes: A first electrode, a capacitor insulation layer, and a second electrode sequentially disposed on the base substrate;
  • the third target conductive layer includes the gate
  • the second target insulating layer includes the second gate insulating layer
  • the fourth target conductive layer includes the second electrode
  • the third target insulating layer The source-drain insulating layer is included, and the fifth target conductive layer includes the source-drain pattern.
  • At least one embodiment of the present disclosure provides a method for manufacturing a display panel, including:
  • the detection line is formed by overlapping a plurality of wire segments and is electrically connected to the data line.
  • the manufacturing method further includes: forming a spacer on a non-display area on the base substrate;
  • the plurality of lead segments includes a first lead segment and other lead segments except the first lead segment, and the spacer is provided between the first lead segment and the base substrate. Thing.
  • the other lead segment includes a second lead segment, and forming a detection line in a non-display area of the base substrate includes:
  • the first lead segments overlapped with the second lead segments are formed in the non-display area of the base substrate, and the first lead segments and the second lead segments are alternately arranged one by one.
  • the other lead segments include a third lead segment and a fourth lead segment, and forming a detection line in a non-display area of the base substrate includes:
  • first lead segments Forming the first lead segments in a non-display area of the base substrate, and the first lead segments and the third lead segments are alternately and spaced apart;
  • the fourth wire segment is formed in the non-display area of the base substrate to overlap the adjacent first wire segment and the third wire segment.
  • At least one embodiment of the present disclosure provides a display device including the above display panel.
  • FIG. 1 is a schematic diagram of a detection line known to the inventor
  • FIG. 2 is a schematic diagram of a partial structure of a display panel according to an embodiment of the present disclosure
  • Figure 3 is a top view of Figure 2;
  • FIG. 4 is a partial structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 5 is a partial structural diagram of a display panel according to another embodiment of the present disclosure.
  • Figure 6 is a top view of Figure 5;
  • FIG. 7 is a flowchart of a manufacturing method of a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a manufacturing method of a display panel according to another embodiment of the present disclosure.
  • FIG. 9 to 11 are schematic structural diagrams formed according to each process step of the manufacturing method of the display panel shown in FIG. 8;
  • FIG. 12 is a flowchart of another method for manufacturing a display panel according to an embodiment of the present invention.
  • FIG. 13-17 are schematic diagrams of structures formed according to each process step of at least the method of the display panel shown in FIG. 12.
  • FIG. 1 shows the structure of a detection line in the prior art of the inventor.
  • the detection line is disposed in a non-display area 0001 of the display panel, and the detection line 0002 and several data lines 0004 in the display area 0003 in the display panel are electrically connected. Connected, when the non-display area 0001 of the display panel is broken, the detection line 0002 is also broken accordingly. At this time, a detection signal cannot be applied to the data line 0004 through the detection line 0002. At this time, the positions where these data lines 0004 are displayed are vertical.
  • the bright line indicates that the non-display area of the display panel has broken.
  • This detection line can also be called a panel crack detector (English: Panel Crack Detector; PCD for short) signal line.
  • the detection line can often transmit a signal after a slight break, so that when a detection signal is applied to the data line through the detection line, the display panel still does not display a vertical bright line. Therefore, the accuracy of detecting cracks in related technologies is relatively high. low.
  • FIG. 2 is a schematic partial structural diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 3 is a top view of FIG. 2.
  • the display panel 0 includes: a base substrate 01, a display area (not shown in FIG. 2) and a non-display area (shown in FIG. 2) provided on the base substrate 01. Area), the non-display area is located around the display area.
  • Data lines (not shown in FIG. 2) are provided in the display area on the base substrate 01; detection lines 03 are provided in the non-display area on the base substrate 01.
  • the detection line 03 is formed by overlapping a plurality of wire segments, and is electrically connected to the data line.
  • the detection lines located in the non-display area are overlapped by a plurality of wire segments. Therefore, when a slight break occurs in the non-display area, the The stress is large, and the overlap is prone to severe fractures, which leads to the disconnection between the various wire segments of the test line. It is impossible to input a test signal to the data line through the test line. At this time, the positions of these data lines will show vertical Bright lines, so it can effectively detect slight fractures in non-display areas, improving the accuracy of crack detection.
  • the detection line when detecting cracks, it can be achieved not only by detecting whether the display panel can display a vertical bright line, but also by detecting the resistance on the detection line. For example, when the detection line is broken, the resistance on the detection line will increase. Once the resistance is detected to be higher than the preset resistance, it can be determined that the current detection line is broken, and then the non-display area of the display panel is broken.
  • the detection line is a single-layer signal line, when the display panel is subjected to an external force, the signal line is not easily broken due to its good ductility, or the signal line only occurs Slight breakage. At this time, the resistance change in the detection wire is small, and cracks cannot be detected.
  • a detection line is formed by overlapping the multi-layered wire segments.
  • the overlap of the multi-layered wire segments will be severely broken. The resistance changes greatly, and cracks can be detected.
  • the plurality of lead segments overlapped into the detection line 03 may include at least one first lead segment 031, and other lead segments except the at least one first lead segment 031.
  • a spacer 04 is disposed between each of the first lead segments 031 and the base substrate 01.
  • step difference refers to the height difference between the two film layers, usually the height difference between the bottom of one film layer and the bottom of the other film layer. In this way, a slight break in the non-display area can be detected more effectively, thereby further improving the accuracy of crack detection.
  • the multiple wire segments may have multiple bonding modes.
  • the following two bonding modes are used for description.
  • the first overlap mode of the plurality of wire segments may be as shown in FIG. 2 and FIG. 3.
  • the other wire segments may include: a plurality of second wire segments 032, the first The lead segments 031 and the second lead segments 032 are alternately arranged one by one, and the first lead segment 031 is overlapped on the second lead segment 032.
  • the spacer 04 may include a first insulating layer 041 located on a plurality of second lead segments 032 and covering a non-display area.
  • the first insulating layer 041 is provided through the first insulating layer 041 and communicates with a plurality of second The plurality of first via holes G1 of the lead segment 032; the plurality of first lead segments 031 are disposed on the first insulating layer 041, and the plurality of first via holes G1 are overlapped with the plurality of second lead segments 032 to realize electricity connection.
  • a plurality of film layers may be provided in a display area on the base substrate, and the plurality of film layers may include a first target conductive layer, a first target insulation layer, and a second layer formed in this order.
  • the target conductive layer that is, among the first target conductive layer, the first target insulating layer, and the second target conductive layer, the first target conductive layer is formed first, the first target insulating layer is formed second, and the second target is formed.
  • a third conductive layer is formed.
  • the second wire segment may be formed in the same layer as the first target conductive layer, the first insulation layer may be arranged in the same layer as the first target insulation layer, and the first wire segment is arranged in the same layer as the second target conductive layer. That is, the first lead segment, the second lead segment, and the first insulating layer that need to be formed in the non-display area can be disposed on the same layer as the film layer of the display area, which can improve the manufacturing efficiency of the display panel.
  • the so-called layer arrangement means that multiple parts are made of the same material and formed through the same patterning process.
  • One patterning process includes: photoresist coating, exposure, development, etching, and photoresist stripping. Therefore, using one patterning process to process the material includes: coating a layer of photoresist on the wire layer, and then using a mask The film plate exposes the photoresist, so that the photoresist forms a fully exposed area and a non-exposed area, and then is processed by a developing process, so that the photoresist in the fully exposed area is removed, and the photoresist in the non-exposed area is retained. The corresponding area of the fully exposed area on the material layer is etched. After the etching is completed, the photoresist in the non-exposed area can be peeled to obtain a component provided in the same layer.
  • FIG. 4 is a schematic diagram of a partial structure of a display panel according to another embodiment of the present disclosure.
  • a thin-film transistor (English: Thin Film Transistor) with a top-gate structure may also be disposed in the display area on the substrate 01. ; Abbreviation: TFT) 05 and storage capacitor 06.
  • the thin film transistor 05 may include: an active layer 051, a first gate insulating layer 052, a gate 053, a second gate insulating layer 054, a source-drain insulating layer 055, and a source-drain disposed on the base substrate 01 in this order.
  • the pattern 056; the storage capacitor 06 may include a first electrode D1, a capacitor insulating layer D3, and a second electrode D2 that are sequentially disposed on the base substrate 01.
  • the first target conductive layer may include a gate
  • the first target insulating layer may include a second gate insulating layer
  • the second target conductive layer may include a second electrode.
  • the first lead segment 031 may be disposed on the same layer as the second electrode D2 in the storage capacitor 06
  • the second lead segment 032 may be disposed on the same layer as the gate 053 in the thin film transistor 05.
  • the first insulating layer 041 may be disposed in the same layer as the second gate insulating layer 054.
  • the film layer in the non-display area may be formed on the same layer as other film layers in the display area.
  • the second wire segment may also be disposed on the same layer as the source and drain patterns.
  • the target conductive layer may include a source-drain pattern; the thin-film transistor in the display area may not be a thin-film transistor with a top-gate structure, for example, the thin-film transistor in the display area may also be a thin-gate transistor with a bottom-gate structure; There are no restrictions.
  • the length of the first wire segment may be 10 micrometers, and the length of the second wire segment may be 10 micrometers.
  • FIG. 5 is a schematic view showing a partial structure of a display panel according to another embodiment of the present disclosure
  • FIG. 6 is a top view of FIG. 5.
  • Figure 5 shows a second way of overlapping a plurality of conductor segments.
  • the other wire segments may include a plurality of third wire segments 033 and a plurality of fourth wire segments 034.
  • the first lead segments 031 and the third lead segments 033 are alternately and spaced one by one, and the fourth lead segment 034 overlaps the adjacent first lead segment 031 and the third lead segment 033.
  • the spacer 04 includes: a second insulating layer 042 located on the plurality of third lead segments 033 and covering the non-display area, and a plurality of first lead segments 031 disposed on the second insulating layer 042
  • a third insulating layer 043 located on the plurality of first lead segments 031 and covering the non-display area is provided on the base substrate 01;
  • a second insulating layer is provided in the second insulating layer 042 and the third insulating layer 043 042 and a plurality of second via holes G2 of the third insulating layer 043, each of the second via holes G2 is in communication with the adjacent first lead segment 031 and the third lead segment 033, and the plurality of fourth lead segments 034 are disposed at the first
  • the three insulating layers 043 are overlapped on the plurality of third lead segments 033 and the plurality of first lead segments 031 through a plurality of second via holes G2 to realize electrical connection.
  • a plurality of film layers may be provided in the display area on the substrate, and the plurality of film layers may include a third target conductive layer, a second target insulating layer, a fourth target conductive layer, and a third target insulating layer which are sequentially formed. And a fifth target conductive layer.
  • the third conductive line segment is disposed on the same layer as the third target conductive layer
  • the second insulating layer is disposed on the same layer as the second target insulating layer
  • the first conductive line segment is disposed on the same layer as the fourth target conductive layer
  • the third The insulating layer is disposed on the same layer as the second target insulating layer
  • the fourth wire segment is disposed on the same layer as the fifth target conductive layer.
  • the first lead segment, the second lead segment, and the first insulating layer that need to be formed in the non-display area can be disposed on the same layer as the film layer of the display area, so that the film layers formed on the same layer can be simultaneously formed, thereby The manufacturing efficiency of a display panel can be improved.
  • a thin film transistor 05 and a storage capacitor 06 may be further provided in the display area on the base substrate 01.
  • the third target conductive layer may include a gate electrode 053, the second target insulating layer may include a second gate insulating layer 054, the fourth target conductive layer may include a second electrode D2, and the third target insulating layer may include a source-drain insulating layer 055.
  • the fifth target conductive layer may include a source-drain pattern 056.
  • the first lead segment 031 may be provided at the same layer as the second electrode D2
  • the third lead segment 033 may be provided at the same layer as the gate electrode 053 in the thin film transistor 05
  • the fourth lead segment 034 may be provided at the same layer as the source-drain pattern 056.
  • the second insulating layer 042 is disposed on the same layer as the second gate insulating layer 054, and the third insulating layer 043 may be disposed on the same layer as the source-drain insulating layer 055 in the thin film transistor 05.
  • the thin film transistor in the display region may not be a thin film transistor with a top-gate structure.
  • the thin film transistor in the display region may also be a thin-film transistor with a bottom-gate structure. limited.
  • the length of the first wire segment may be 10 micrometers
  • the length of the third wire segment may be 10 micrometers
  • the length of the fourth wire segment may be 3 micrometers.
  • the display panel may further be provided with a buffer layer 08 and a polyimide layer 09, and the first gate insulating layer 052 in the thin film transistor may extend to the non-display area.
  • the first gate insulating layer 052, the buffer layer 08, and the polyimide layer 09 are all located between the base substrate 01 and the plurality of third wire segments 033, and the polyimide
  • the amine layer is provided near the base substrate 01. As shown in FIG.
  • the first gate insulating layer 052, the buffer layer 08, and the polyimide layer 09 are all located between the base substrate 01 and the plurality of second lead segments 032, and the polyimide
  • the amine layer is provided near the base substrate 01.
  • the display panel according to the embodiment of the present disclosure may be an organic light emitting diode (English: Organic Light-Emitting Diode; OLED for short) display panel or a liquid crystal display panel.
  • OLED display panels include OLED materials. Since OLED materials are extremely sensitive to water and oxygen, a small amount of water and oxygen erosion will cause the display of the OLED display panel to fail. When the display panel is subjected to external forces such as bumps and bends, micro-cracks are easily generated on the edges of the display panel. When the cracks extend into the display area, it becomes a channel for water and oxygen to enter and erode the OLED material in the display area, eventually causing the display product to fail. In the embodiment of the present disclosure, it is possible to effectively detect whether the display panel is cracked through the signal line, thereby preventing the display panel from failing.
  • the detection lines located in the non-display area are overlapped by a plurality of wire segments. Therefore, when a slight break occurs in the non-display area, the plurality of wire segments The stress at the lap joint is greater, and the lap joint is prone to more severe fractures. At this time, the fracture portion is severely broken, so it is impossible to input a detection signal to the data line through the detection line. At this time, these Vertical bright lines are displayed at the location of the data line, so it can effectively detect slight fractures in non-display areas, which improves the accuracy of crack detection.
  • FIG. 7 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure.
  • the display panel may be the display panel shown in FIG. 2 or FIG. 5.
  • the method for manufacturing the display panel may include:
  • Step 701 Form a data line in a display area of the base substrate.
  • Step 702 Form a detection line in a non-display area of the base substrate; wherein the detection line is formed by overlapping a plurality of wire segments and is electrically connected to the data line.
  • the detection line located in the non-display area is formed by overlapping a plurality of wire segments. Therefore, when a slight break occurs in the non-display area, the The stress at the overlap of multiple wire segments is relatively large, and the overlap is prone to severe fractures. At this time, the fracture portion is severely broken, so it is impossible to input a detection signal to the data line through the detection line. At this time, vertical bright lines are displayed at the positions of these data lines, so it is possible to effectively detect slight fractures in non-display areas, and improve the accuracy of crack detection.
  • FIG. 8 is a flowchart of a method of manufacturing a display panel according to another embodiment of the present disclosure.
  • the display panel may be the display panel shown in FIG. 2.
  • the method of manufacturing the display panel may include:
  • Step 801 Form a data line in a display area of the base substrate.
  • a gate line, a thin-film transistor with a top-gate structure, and a storage capacitor may also be formed in a display area of the base substrate.
  • the thin film transistor in the display area may not be a thin film transistor with a top-gate structure.
  • the thin film transistor in the display area may also be a thin-film transistor with a bottom-gate structure, which is not limited in the embodiments of the present disclosure.
  • Step 802 Form a plurality of second wire segments in a non-display area of the base substrate.
  • a polyimide layer 09, a buffer layer 08, and a first gate insulating layer 052 may be sequentially formed in the non-display area of the base substrate 01.
  • a plurality of second wire segments 032 may be formed on the first gate insulating layer 052.
  • the process of forming the plurality of second wire segments 032 may include: depositing a wire layer by sputtering in a non-display area of the substrate substrate 01, such as forming the wire layer by coating or sputtering. ; Then, a patterning process may be performed on the conductive wire layer to obtain a plurality of second conductive wire segments 032.
  • a patterning process includes: photoresist coating, exposure, development, etching, and photoresist stripping. Therefore, using a patterning process to process the wire layer includes: coating a layer of photoresist on the wire layer, Then use a mask to expose the photoresist, so that the photoresist forms a fully exposed area and a non-exposed area, and then use a developing process to process the photoresist in the fully exposed area and remove the photoresist in the non-exposed area. Retain, and then etch the corresponding area of the fully exposed area on the wire layer. After the etching is completed, the photoresist in the non-exposed area can be stripped to obtain a plurality of second wire segments.
  • Step 803 Form a first insulating layer covering a non-display area on the plurality of second lead segments.
  • a first insulating layer 041 covering a non-display area may be formed on the plurality of second lead segments 032.
  • the step of forming the first insulating layer includes: depositing an insulating material layer by a plasma enhanced chemical vapor deposition method (English: Plasma Enhanced Chemical Deposition; PECVD for short) to obtain the first insulating layer 041.
  • a plasma enhanced chemical vapor deposition method English: Plasma Enhanced Chemical Deposition; PECVD for short
  • Step 804 Form a plurality of first vias on the first insulation layer to communicate with the plurality of second wire segments.
  • the first insulating layer 041 may be processed by a patterning process to form a plurality of first via holes G1 on the first insulating layer 041, and each of the first via holes G1 is The plurality of first vias G1 are electrically connected to the second lead segment 032, and the plurality of first vias G1 communicate with the plurality of second lead segments 032 formed in step 802.
  • the process of applying a patterning process to a certain film layer can be referred to the process of applying a patterning process to the wire layer in step 802, and details are not described herein.
  • Step 805 Form a plurality of first wire segments on the first insulation layer, and the plurality of first wire segments are overlapped with the plurality of second wire segments through the plurality of first via holes, and the first wire segment and the second wire are overlapped. Segments are set alternately.
  • a wire layer can be deposited on the first insulating layer 041 by sputtering, and the wire layer is processed by a patterning process to obtain a plurality of first The lead segment 031, and the plurality of first lead segments 031 overlap with the plurality of second lead segments 032 formed in step 802 through the plurality of first vias formed in step 804, and the first lead segment 031 and the second The lead segments 032 are alternately arranged one by one.
  • the detection line is formed by overlapping a plurality of first lead segments and a plurality of second lead segments, and is electrically connected to the data line.
  • a spacer that is, a first insulating layer is disposed between each first wire segment and the base substrate.
  • the detection lines located in the non-display area are formed by overlapping a plurality of wire segments. Therefore, when a slight break occurs in the non-display area, the multi- The stress at the overlapped portion of each wire segment is relatively large, and the overlapped portion is prone to severe fracture. At this time, the fractured portion is severely broken, so it is impossible to input a detection signal to the data line through the detection line.
  • the data lines are located, vertical bright lines are displayed, so it is possible to effectively detect slight fractures in non-display areas and improve the accuracy of crack detection.
  • FIG. 12 is a flowchart of a method for manufacturing a display panel according to another embodiment of the present disclosure.
  • the display panel may be the display panel shown in FIG. 5.
  • the method for manufacturing the display panel may include:
  • Step 1201 Form a data line in a display area of the base substrate.
  • a gate line, a thin-film transistor with a top-gate structure, and a storage capacitor may also be formed in a display area of the base substrate.
  • the thin film transistor in the display area may not be a thin film transistor with a top-gate structure.
  • the thin film transistor in the display area may also be a thin-film transistor with a bottom-gate structure, which is not limited in the embodiments of the present disclosure.
  • Step 1202 forming a plurality of third lead segments in a non-display area of the base substrate.
  • a polyimide layer 09, a buffer layer 08, and a first gate insulating layer 052 may be sequentially formed in the non-display area of the base substrate 01.
  • step 1202 a plurality of third wire segments 033 may be formed on the first gate insulating layer 052.
  • step 802 for the process of forming the third wire segment 033, reference may be made to step 802 in the embodiment shown in FIG. 8, and details are not described herein.
  • Step 1203 Form a second insulating layer covering the non-display area on the plurality of third wire segments.
  • a second insulating layer 042 covering a non-display area may be formed on the plurality of third wire segments 033.
  • a second insulating layer 042 covering a non-display area may be formed on the plurality of third wire segments 033.
  • Step 1204 Form a plurality of first lead segments in the non-display area of the base substrate, and the first lead segments and the third lead segments are alternately arranged at intervals.
  • a plurality of first lead segments 031 may be formed in a non-display area of the base substrate 01.
  • first wire segment 031 For the process of forming the first wire segment 031, reference may be made to step 802 in the embodiment shown in FIG. 8, and details are not described herein again. And the first lead segments 031 and the third lead segments 033 are alternately and spaced apart.
  • Step 1205 Form a third insulating layer covering the non-display area on the plurality of first wire segments.
  • a third insulating layer 043 covering a non-display area may be formed on the plurality of first lead segments 031.
  • a third insulating layer 043 covering a non-display area may be formed on the plurality of first lead segments 031.
  • Step 1206 Form a plurality of second vias in the second insulating layer and the third insulating layer, and each second via is in communication with the adjacent first conductive line segment and the third conductive line segment.
  • a plurality of second vias may be formed in the second insulating layer 042 and the third insulating layer 043.
  • step 804 in the embodiment shown in FIG. 8, and details are not described herein.
  • Each second via is in communication with adjacent first and third lead segments 031 and 033.
  • Step 1207 Form a plurality of fourth wire segments on the third insulation layer, and the plurality of fourth wire segments are overlapped on the plurality of third wire segments and the plurality of first wire segments through a plurality of second via holes to realize Electrical connection.
  • a plurality of fourth wire segments 034 may be formed on the third insulation layer 043.
  • fourth wire segment 044 reference may be made to step 802 in the embodiment shown in FIG. 8, and details are not described herein.
  • the detection line is formed by overlapping multiple first lead segments, multiple third lead segments, and multiple fourth lead segments, and is electrically connected to the data line.
  • a spacer that is, a second insulating layer is disposed between each first lead segment and the base substrate.
  • the detection lines located in the non-display area are formed by overlapping a plurality of wire segments. Therefore, when a slight break occurs in the non-display area, the multi- The stress at the overlapped portion of each wire segment is relatively large, and the overlapped portion is prone to severe fracture. At this time, the fractured portion is severely broken, so it is impossible to input a detection signal to the data line through the detection line.
  • the data lines are located, vertical bright lines are displayed, so it is possible to effectively detect slight fractures in non-display areas and improve the accuracy of crack detection.
  • At least one embodiment of the present disclosure provides a display device, which may include a display panel shown in FIG. 2 or FIG. 5.
  • the display device may be any liquid crystal display device, electronic paper, organic light emitting diode display device, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc., which have any display function or component.
  • the method embodiments according to the present disclosure can be cross-referenced with the corresponding display panel embodiments, which are not limited in the embodiments of the present disclosure.
  • the order of the steps in the method embodiments according to the embodiments of the present disclosure can be appropriately adjusted, and the steps can be increased or decreased according to the situation. Any person skilled in the art can easily think of it within the technical scope disclosed in this disclosure. The methods of change should all be covered by the protection scope of the present disclosure, so they will not be described again.

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Abstract

一种显示面板包括：衬底基板(01)，设置在所述衬底基板(01)上的显示区域和非显示区域，所述显示区域内设置有数据线；所述衬底基板上的非显示区域内设置有检测线；其中，所述检测线与所述数据线电连接，并由多个导线段搭接而成。还提供了一种显示面板的制造方法以及显示装置。

Description

显示面板及其制造方法、显示装置
本申请要求于2018年5月28日递交的中国专利申请第201810520493.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示面板及其制造方法、显示装置。
背景技术
在显示面板的制造过程中，显示面板的非显示区域较容易在受到磕碰时出现裂纹。当外界的水分和氧气通过该裂纹进入显示面板内部时，显示面板无法正常使用。
在发明人已知的技术中，通过在显示面板的非显示区域设置检测线，以对非显示区域的裂纹进行检测。示例的，该检测线可以与显示区域内的数据线电连接，在检测显示面板的非显示区域是否出现裂纹时，可以通过该检测线向数据线施加检测信号，并检测显示面板是否显示竖向亮线。需要说明的是，若显示面板的非显示区域在受到磕碰时出现裂纹，则该检测线也会在受到磕碰时发生断裂，该检测信号无法传输至数据线，此时，这些数据线所在的位置会显示竖向亮线。因此，可以通过检测显示面板是否能够显示竖向亮线，来判断非显示区域是否出现裂纹。
发明内容
本公开的至少一个实施例提供了一种显示面板，包括：衬底基板，设置在所述衬底基板上的显示区域和非显示区域，所述显示区域内设置有数据线；所述非显示区域内设置有检测线；其中，所述检测线与所述数据线电连接，并由多个导线段搭接而成。
在本公开的一个实施例中，所述多个导线段包括：第一导线段，以及除所述第一导线段之外的其他导线段，所述第一导线段与所述衬底基板之间均 设置有隔垫物。
在本公开的一个实施例中，所述其他导线段包括：第二导线段，所述第一导线段与所述第二导线段交替设置，且所述第一导线段搭接在所述第二导线段上。
在本公开的一个实施例中，所述隔垫物包括第一绝缘层，所述第一绝缘层位于所述第二导线段上且覆盖所述非显示区域，所述第一绝缘层上设置有连通所述第二导线段的第一过孔；以及所述第一导线段设置在所述第一绝缘层上，且通过所述第一过孔与所述第二导线段搭接。
在本公开的一个实施例中，所述衬底基板上的显示区域内还设置有依次形成的第一目标导电层、第一目标绝缘层和第二目标导电层，所述第二导线段与所述第一目标导电层同层设置，所述第一绝缘层与所述第一目标绝缘层同层设置，所述第一导线段与所述第二目标导电层同层设置。
在本公开的一个实施例中，所述衬底基板上的显示区域内还设置有顶栅结构的薄膜晶体管和存储电容，所述薄膜晶体管包括：在衬底基板上依次设置的有源层、第一栅绝缘层、栅极、第二栅绝缘层、源漏极绝缘层以及源漏极图案；所述存储电容包括：在所述衬底基板上依次设置的第一电极、电容绝缘层和第二电极；所述第一目标导电层包括所述栅极，所述第一目标绝缘层包括所述第二栅绝缘层，所述第二目标导电层包括所述第二电极。
在本公开的一个实施例中，所述其他导线段包括：第三导线段和第四导线段，所述第一导线段和所述第三导线段一一交替并间隔设置，所述第四导线段搭接在相邻的第一导线段和第三导线段上。
在本公开的一个实施例中，所述隔垫物包括：位于所述第三导线段上且覆盖所述非显示区域的第二绝缘层，所述第一导线段设置在所述第二绝缘层上；
所述衬底基板上还设置有位于所述第一导线段上且覆盖所述非显示区域的第三绝缘层；以及
所述第二绝缘层和所述第三绝缘层中设置有贯穿所述第二绝缘层和所述第三绝缘层的第二过孔，所述第二过孔与相邻的第一导线段和第三导线段连通，所述第四导线段设置在所述第三绝缘层上，且通过所述第二过孔搭接在所述第三导线段和所述第一导线段上。
在本公开的一个实施例中，所述衬底基板上的显示区域内还设置有依次形成的第三目标导电层、第二目标绝缘层、第四目标导电层、第三目标绝缘层以及第五目标导电层，
所述第三导线段与所述第三目标导电层同层设置，所述第二绝缘层与所述第二目标绝缘层同层设置，所述第一导线段与所述第四目标导电层同层设置，所述第三绝缘层与所述第二目标绝缘层同层设置，所述第四导线段与所述第五目标导电层同层设置。
在本公开的一个实施例中，所述衬底基板上的显示区域内还设置有顶栅结构的薄膜晶体管和存储电容，其中，
所述薄膜晶体管包括：在衬底基板上依次设置的有源层、第一栅绝缘层、栅极、第二栅绝缘层、源漏极绝缘层以及源漏极图案；所述存储电容包括：在所述衬底基板上依次设置的第一电极、电容绝缘层和第二电极；
所述第三目标导电层包括所述栅极，所述第二目标绝缘层包括所述第二栅绝缘层，所述第四目标导电层包括所述第二电极，所述第三目标绝缘层包括所述源漏极绝缘层，所述第五目标导电层包括所述源漏极图案。
本公开的至少一个实施例提供了一种显示面板的制造方法，其包括：
在所述衬底基板的显示区域内形成数据线；
在所述衬底基板的非显示区域内形成检测线；
其中，所述检测线由多个导线段搭接而成，且与所述数据线电连接。
在本公开的一个实施例中，所述制造方法还包括：在所述衬底基板上的非显示区域形成隔垫物；
其中，所述多个导线段包括第一导线段，以及除所述第一导线段之外的其他导线段，所述第一导线段与所述衬底基板之间均设置有所述隔垫物。
在本公开的一个实施例中，所述其他导线段包括第二导线段，在所述衬底基板的非显示区域内形成检测线包括：
在所述衬底基板的非显示区域内形成所述第二导线段；
在所述衬底基板的非显示区域内形成搭接在所述第二导线段上的所述第一导线段，且所述第一导线段与所述第二导线段一一交替设置。
在本公开的一个实施例中，所述其他导线段包括第三导线段和第四导线段，在所述衬底基板的非显示区域内形成检测线包括：
在所述衬底基板的非显示区域内形成所述第三导线段；
在所述衬底基板的非显示区域内形成所述第一导线段，且所述第一导线段和所述第三导线段交替并间隔设置；
在所述衬底基板的非显示区域内形成搭接在相邻的第一导线段和第三导线段上的所述第四导线段。
本公开的至少一个实施例提供了一种显示装置，包括上述显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为发明人已知的一种检测线的示意图；
图2为根据本公开的一个实施例的显示面板的局部结构示意图；
图3为图2的俯视图；
图4为根据本公开的另一个实施例的显示面板的局部结构图；
图5为根据本公开的又一个实施例的显示面板的局部结构图；
图6为图5的俯视图；
图7为根据本公开的一个实施例的显示面板的制造方法流程图；
图8为根据本公开的另一个实施例的显示面板的制造方法流程图；
图9至图11示出了根据图8所示的显示面板的制造方法的每个工艺步骤所形成的结构示意图；
图12为本发明实施例提供的又一种显示面板的制造方法流程图；以及
图13-17是根据图12所示的显示面板的至少方法的每个工艺步骤所形成的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例，都属于本公开保护的范围。
在显示面板的制造过程中，显示面板的非显示区域较容易在受到磕碰时出现裂纹，该裂纹会影响显示面板的正常使用。图1示出了发明人已知技术中的检测线的结构，检测线设置在显示面板的非显示区域0001内，并将检测线0002与显示面板中显示区域0003内的几根数据线0004电连接，当显示面板的非显示区域0001断裂后，检测线0002也相应发生断裂，此时无法通过检测线0002向数据线0004施加检测信号，此时，这些数据线0004所在的位置会显示竖向亮线，以此提示该显示面板的非显示区域已经发生断裂。该检测线也可以称为面板裂纹检测器(英文：Panel Crack Detector；简称：PCD)信号线。
但是，检测线在轻微的断裂后往往还可以传输信号，使得在通过该检测线向数据线施加检测信号时，显示面板仍然未显示竖向亮线，因此，相关技术中检测裂纹的准确度较低。
本公开的至少一个实施例提供了一种显示面板，该显示面板中设置有检测线，通过该检测线能够对显示面板的非显示区域的裂纹进行检测。图2为根据本公开一个实施例的显示面板的局部结构示意图，图3为图2的俯视图。如图2和图3所示，该显示面板0包括：衬底基板01，设置在该衬底基板01上的显示区域(图2中未示出)和非显示区域(如图2所示的区域)，该非显示区域位于显示区域周边。
该衬底基板01上的显示区域内设置有数据线(图2中未示出)；衬底基板01上的非显示区域内设置有检测线03。其中，检测线03由多个导线段搭接而成，且与数据线电连接。
在根据本公开实施例的显示面板中，位于非显示区域的检测线由多个导线段搭接而成，因此，在非显示区域出现轻微的断裂时，该多个导线段的搭接处的应力较大，该搭接处容易发生较为严重的断裂，导致检测线各个导线段之间断开，无法通过该检测线向数据线输入检测信号，此时，这些数据线所在的位置会显示竖向亮线，所以能够有效的检测到非显示区域的轻微断裂，提高了裂纹检测的准确度。
在本公开的一个实施例中，在检测裂纹时，不仅可以通过检测显示面板是否能够显示竖向亮线，还可以通过检测该检测线上的电阻来实现。示例的， 当检测线发生断裂后，检测线上的电阻会增高，一旦检测到电阻高于预设电阻，就可以确定当前检测线发生了断裂，进而确定显示面板的非显示区域发生了断裂。但是，在发明人已知的技术中，由于检测线为单层信号线，在显示面板受到外力的作用时，该信号线由于其良好的延展性而不容易断裂，或者该信号线只会发生轻微的断裂，此时，检测线中的电阻变化较小，无法检测出裂纹。例如，如下表1所示，在以下的12种情况中，第1、2、3、10、11和12种情况中，是否检测到裂纹的结果以及检测线的电阻均与显示面板中是否出现裂纹的结果一致，而在第4至第9种情况中，虽然显示面板出现了裂纹，但是却通过检测线并未检测到裂纹，且检测线的电阻变化也较小，因此，在这几种情况中并未能检出裂纹。
表1
情况 显示面板中是否出现裂纹 是否检测到裂纹 检测线的电阻
1 否 否 24.1千欧
2 否 否 25.1千欧
3 否 否 22.1千欧
4 是 否 22.2千欧
5 是 否 42.5千欧
6 是 否 30.7千欧
7 是 否 30.1千欧
8 是 否 22.8千欧
9 是 否 27.8千欧
10 是 是 1871兆欧
11 是 是 1035兆欧
12 是 是 239.3兆欧
在本公开实施例中，通过多层导线段搭接成检测线，在显示面板受到外力而发生轻微断裂时，多层导线段的搭接处会发生较严重的断裂，此时，检测线中的电阻变化较大，能够检测出裂纹。
在本公开的一个实施例中，搭接成该检测线03的多个导线段可以包括：至少一个第一导线段031，以及除该至少一个第一导线段031之外的其他导线段，每个第一导线段031与衬底基板01之间均设置有隔垫物04。
由于第一导线段031下方设置有隔垫物04，能够增高第一导线段031的高度，并增大第一导线段031与其搭接的导线段的段差，从而使得在显示面 板受到外力的作用时，该较大的段差所在处的应力较大，使得该段差所在处更加容易断裂。所谓段差，指的是两个膜层之间的高度差，通常是一个膜层的底部与另一个膜层的底部的高度差。这样一来，就能够更加有效的检测到非显示区域的轻微断裂，从而进一步的提高裂纹检测的准确度。
需要说明的是，该多个导线段可以具有多种搭接方式，本公开实施例中将以下述两种搭接方式进行说明。
一方面，多个导线段的第一种搭接方式可以如图2和图3所示，在第一种搭接方式中，该其他导线段可以包括：多个第二导线段032，第一导线段031与第二导线段032一一交替设置，且第一导线段031搭接在第二导线段032上。
该隔垫物04可以包括：位于多个第二导线段032上且覆盖非显示区域的第一绝缘层041，第一绝缘层041上设置有贯穿该第一绝缘层041且连通多个第二导线段032的多个第一过孔G1；多个第一导线段031设置在第一绝缘层041上，且通过多个第一过孔G1与多个第二导线段032搭接以实现电连接。
在本公开的一个实施例中，衬底基板上的显示区域内可以设置有多个膜层，该多个膜层可以包括：依次形成的第一目标导电层、第一目标绝缘层和第二目标导电层，也即，在第一目标导电层、第一目标绝缘层和第二目标导电层中，第一目标导电层第一个形成，第一目标绝缘层第二个形成，第二目标导电层第三个形成。本公开实施例中的第二导线段可以与第一目标导电层同层形成，第一绝缘层可以与第一目标绝缘层同层设置，第一导线段与第二目标导电层同层设置。也即，该非显示区域中需要形成的第一导线段、第二导线段以及第一绝缘层均可以与显示区域的膜层同层设置，能够提高显示面板的制造效率。
所谓同层设置，指的是多个部件由同一种材料制成，并通过同一构图工艺形成。一次构图工艺包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离，因此，采用一次构图工艺对材料进行处理包括：在导线层上涂覆一层光刻胶，然后采用掩膜版对光刻胶进行曝光，使光刻胶形成完全曝光区和非曝光区，之后采用显影工艺进行处理，使完全曝光区的光刻胶被去除，非曝光区的光刻胶保留，之后对完全曝光区在材料层上的对应区域进行刻蚀，刻蚀完毕后 剥离非曝光区的光刻胶即可得到同层设置的部件。
图4为根据本公开另一个实施例的显示面板的局部结构示意图，如图4所示，该衬底基板01上的显示区域内还可以设置有顶栅结构的薄膜晶体管(英文：Thin Film Transistor；简称：TFT)05和存储电容06。其中，薄膜晶体管05可以包括：在衬底基板01上依次设置的有源层051、第一栅绝缘层052、栅极053、第二栅绝缘层054、源漏极绝缘层055以及源漏极图案056；存储电容06可以包括：在衬底基板01上依次设置的第一电极D1、电容绝缘层D3和第二电极D2。
第一目标导电层可以包括栅极，第一目标绝缘层可以包括第二栅绝缘层，第二目标导电层可以包括第二电极。请结合图2、图3和图4，该第一导线段031可以与存储电容06中的第二电极D2同层设置，第二导线段032可以与薄膜晶体管05中的栅极053同层设置，第一绝缘层041可以与第二栅绝缘层054同层设置。
在本公开的一个实施例中，非显示区域内的膜层还可以与显示区域内的其他膜层同层形成，如第二导线段还可以与源漏极图案同层设置，此时第二目标导电层可以包括源漏极图案；显示区域内的薄膜晶体管可以不为顶栅结构的薄膜晶体管，如显示区域内的薄膜晶体管还可以为底栅结构的薄膜晶体管等；本公开实施例对此均不作限定。
在本公开的一个实施例中，该第一导线段的长度可以为10微米，该第二导线段的长度可以为10微米。
图5示出了根据本公开另一实施例的显示面板的局部结构示意图，图6为图5的俯视图。图5示出了多个导线段的第二种搭接方式。如图5所示，该其他导线段可以包括：多个第三导线段033和多个第四导线段034。第一导线段031和第三导线段033一一交替并间隔设置，第四导线段034搭接在相邻的第一导线段031和第三导线段033上。
在本公开的一个实施例中，隔垫物04包括：位于多个第三导线段033上且覆盖非显示区域的第二绝缘层042，多个第一导线段031设置在第二绝缘层042上；衬底基板01上还设置有位于多个第一导线段031上且覆盖非显示区域的第三绝缘层043；第二绝缘层042和第三绝缘层043中设置有贯穿第二绝缘层042和第三绝缘层043的多个第二过孔G2，每个第二过孔G2与 相邻的第一导线段031和第三导线段033连通，多个第四导线段034设置在第三绝缘层043上，且通过多个第二过孔G2搭接在多个第三导线段033和多个第一导线段031上以实现电连接。
衬底基板上的显示区域内可以设置有多个膜层，该多个膜层可以包括：依次形成的第三目标导电层、第二目标绝缘层、第四目标导电层、第三目标绝缘层以及第五目标导电层。本公开实施例中的第三导线段与第三目标导电层同层设置，第二绝缘层与第二目标绝缘层同层设置，第一导线段与第四目标导电层同层设置，第三绝缘层与第二目标绝缘层同层设置，第四导线段与第五目标导电层同层设置。也即，该非显示区域中需要形成的第一导线段、第二导线段以及第一绝缘层均可以与显示区域的膜层同层设置，这样一来能够同时同层形成的膜层，从而能够提高显示面板的制造效率。
例如，如图4、图5和图6所示，衬底基板01上的显示区域内还可以设置有薄膜晶体管05和存储电容06。第三目标导电层可以包括栅极053，第二目标绝缘层可以包括第二栅绝缘层054，第四目标导电层可以包括第二电极D2，第三目标绝缘层可以包括源漏极绝缘层055，第五目标导电层可以包括源漏极图案056。也即，第一导线段031可以与第二电极D2同层设置，第三导线段033与薄膜晶体管05中的栅极053同层设置，第四导线段034可以与源漏极图案056同层设置，第二绝缘层042与第二栅绝缘层054同层设置，第三绝缘层043可以与薄膜晶体管05中的源漏极绝缘层055同层设置。
在本公开的一个实施例中，显示区域内的薄膜晶体管可以不为顶栅结构的薄膜晶体管，如显示区域内的薄膜晶体管还可以为底栅结构的薄膜晶体管等，本公开实施例对此不作限定。
在本公开的一个实施例中，该第一导线段的长度可以为10微米，该第三导线段的长度可以为10微米，第四导线段的长度可以为3微米。
另外，请结合图2至图5，显示面板上还可以设置有：缓冲层08和聚酰亚胺层09，且薄膜晶体管中的第一栅绝缘层052可以延伸至非显示区域。如图5所示，在非显示区域内，第一栅绝缘层052、缓冲层08和聚酰亚胺层09均位于衬底基板01和多个第三导线段033之间，且聚酰亚胺层靠近衬底基板01设置。如图2所示，在非显示区域内，第一栅绝缘层052、缓冲层08和聚酰亚胺层09均位于衬底基板01和多个第二导线段032之间，且聚酰亚胺层 靠近衬底基板01设置。
根据本公开实施例的显示面板可以为有机发光二极管(英文：Organic Light-Emitting Diode；简称：OLED)显示面板或者液晶显示面板。并且，OLED显示面板包括OLED材料，由于OLED材料对水、氧极度敏感，微量的水、氧侵蚀都会导致OLED显示面板的显示失效。当显示面板受到磕碰、弯曲等外力作用时，显示面板的边缘容易产生微裂纹，当裂纹扩展至显示区域时，即成为水氧进入并侵蚀显示区域的OLED材料的通道，最终导致显示产品失效。本公开实施例中能够通过信号线有效的检测出显示面板是否发生了破裂，进而能够防止显示面板失效。
综上所述，在根据本公开实施例的显示面板中，位于非显示区域的检测线由多个导线段搭接而成，因此，在非显示区域出现轻微的断裂时，该多个导线段的搭接处的应力较大，该搭接处容易发生较为严重的断裂，此时，该断裂部由于断裂程度较严重，因此，无法通过该检测线向数据线输入检测信号，此时，这些数据线所在的位置会显示竖向亮线，所以能够有效的检测到非显示区域的轻微断裂，提高了裂纹检测的准确度。
图7为根据本公开一个实施例的显示面板的制造方法的流程图，该显示面板可以为图2或图5所示的显示面板，如图7所示，该显示面板的制造方法可以包括：
步骤701、在衬底基板的显示区域内形成数据线；
步骤702、在衬底基板的非显示区域内形成检测线；其中，检测线由多个导线段搭接而成，且与数据线电连接。
综上所述，在根据本公开实施例的方法所制造的显示面板中，位于非显示区域的检测线由多个导线段搭接而成，因此，在非显示区域出现轻微的断裂时，该多个导线段的搭接处的应力较大，该搭接处容易发生较为严重的断裂，此时，该断裂部由于断裂程度较严重，因此，无法通过该检测线向数据线输入检测信号，此时，这些数据线所在的位置会显示竖向亮线，所以能够有效的检测到非显示区域的轻微断裂，提高了裂纹检测的准确度。
图8为根据本公开另一个实施例的显示面板的制造方法的流程图，该显示面板可以为图2所示的显示面板，如图8所示，该显示面板的制造方法可以包括：
步骤801、在衬底基板的显示区域内形成数据线。
例如，还可以在衬底基板的显示区域内形成栅线、顶栅结构的薄膜晶体管以及存储电容。需要说明的是，制造显示面板中显示区域内的各个结构的过程可以参考相关技术，本公开实施例在此不做赘述。例如，显示区域内的薄膜晶体管可以不为顶栅结构的薄膜晶体管，如显示区域内的薄膜晶体管还可以为底栅结构的薄膜晶体管等，本公开实施例对此不作限定。
步骤802、在衬底基板的非显示区域内形成多个第二导线段。
如图9所示，在步骤802前，衬底基板01的非显示区域内还可以依次形成有聚酰亚胺层09、缓冲层08和第一栅绝缘层052。
在步骤802中，可以在第一栅绝缘层052上形成多个第二导线段032。示例的，形成该多个第二导线段032的过程可以包括：在衬底基板01的非显示区域内通过溅射的方式沉积一个导线层，如采用涂覆或溅射的方式形成该导线层；然后，可以采用一次构图工艺对该导线层进行图案化处理，以得到多个第二导线段032。
其中，一次构图工艺包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离，因此，采用一次构图工艺对导线层进行处理包括：在导线层上涂覆一层光刻胶，然后采用掩膜版对光刻胶进行曝光，使光刻胶形成完全曝光区和非曝光区，之后采用显影工艺进行处理，使完全曝光区的光刻胶被去除，非曝光区的光刻胶保留，之后对完全曝光区在导线层上的对应区域进行刻蚀，刻蚀完毕后剥离非曝光区的光刻胶即可得到多个第二导线段。
步骤803、在多个第二导线段上形成覆盖非显示区域的第一绝缘层。
如图10所示，在形成多个第二导线段032后，可以在多个第二导线段032上形成覆盖非显示区域的第一绝缘层041。且形成该第一绝缘层的步骤包括：通过等离子体增强化学的气相沉积法(英文：Plasma Enhanced Chemical Vapor Deposition；简称：PECVD)的方式沉积绝缘材质层，以得到该第一绝缘层041。
步骤804、在第一绝缘层上形成连通多个第二导线段的多个第一过孔。
如图11所示，在步骤804中可以对第一绝缘层041采用一次构图工艺进行处理，以在第一绝缘层041上形成多个第一过孔G1，且每个第一过孔G1均与第二导线段032电连接，该多个第一过孔G1连通步骤802中形成的多 个第二导线段032。
需要说明的是，本公开实施例中对某一膜层采用一次构图工艺进行处理的过程，均可以参考步骤802中对导线层采用一次构图工艺进行处理的过程，在此不做赘述。
步骤805、在第一绝缘层上形成多个第一导线段，且多个第一导线段通过多个第一过孔与多个第二导线段搭接，且第一导线段与第二导线段一一交替设置。
如图2所示，在形成第一过孔之后，可以在第一绝缘层041上通过溅射的方式沉积一个导线层，并对该导线层采用一次构图工艺进行处理，以得到多个第一导线段031，且该多个第一导线段031通过步骤804中形成的多个第一过孔与步骤802中形成的多个第二导线段032搭接，且第一导线段031与第二导线段032一一交替设置。
需要说明的是，检测线由多个第一导线段和多个第二导线段搭接而成，且与数据线电连接。每个第一导线段与衬底基板之间均设置有隔垫物(也即第一绝缘层)。
综上所述，根据本公开实施例的方法所制造的显示面板中，位于非显示区域的检测线由多个导线段搭接而成，因此，在非显示区域出现轻微的断裂时，该多个导线段的搭接处的应力较大，该搭接处容易发生较为严重的断裂，此时，该断裂部由于断裂程度较严重，因此，无法通过该检测线向数据线输入检测信号，此时，这些数据线所在的位置会显示竖向亮线，所以能够有效的检测到非显示区域的轻微断裂，提高了裂纹检测的准确度。
图12为根据本公开又一个实施例的显示面板的制造方法的流程图，该显示面板可以为图5所示的显示面板，如图12所示，该显示面板的制造方法可以包括：
步骤1201、在衬底基板的显示区域内形成数据线。
例如，还可以在衬底基板的显示区域内形成栅线、顶栅结构的薄膜晶体管以及存储电容。需要说明的是，制造显示面板中显示区域内的各个结构的过程可以参考相关技术，在此不做赘述。例如，显示区域内的薄膜晶体管可以不为顶栅结构的薄膜晶体管，如显示区域内的薄膜晶体管还可以为底栅结构的薄膜晶体管等，本公开实施例对此不作限定。
步骤1202、在衬底基板的非显示区域内形成多个第三导线段。
如图13所示，在步骤1202前，还可以在衬底基板01的非显示区域内依次形成聚酰亚胺层09、缓冲层08和第一栅绝缘层052。
在步骤1202中，可以在第一栅绝缘层052上形成多个第三导线段033。形成第三导线段033的过程可以参考图8所示的实施例中的步骤802，在此不做赘述。
步骤1203、在多个第三导线段上形成覆盖非显示区域的第二绝缘层。
如图14所示，在步骤1203中，可以在多个第三导线段033上形成覆盖非显示区域的第二绝缘层042。形成第二绝缘层042的过程可以参考图8所示的实施例中的步骤803，在此不做赘述。
步骤1204、在衬底基板的非显示区域内形成多个第一导线段，且第一导线段和第三导线段一一交替并间隔设置。
如图15所示，在步骤1204中，可以在衬底基板01的非显示区域内形成多个第一导线段031。形成第一导线段031的过程可以参考图8所示的实施例中的步骤802，在此不做赘述。且第一导线段031和第三导线段033一一交替并间隔设置。
步骤1205、在多个第一导线段上形成覆盖非显示区域的第三绝缘层。
如图16所示，在步骤1205中，可以在多个第一导线段031上形成覆盖非显示区域的第三绝缘层043。形成第三绝缘层043的过程可以参考图8所示的实施例中的步骤803，在此不做赘述。
步骤1206、在第二绝缘层和第三绝缘层中形成多个第二过孔，每个第二过孔与相邻的第一导线段和第三导线段连通。
如图17所示，在步骤1206中，可以在第二绝缘层042和第三绝缘层043中形成多个第二过孔。形成第二过孔的过程可以参考图8所示的实施例中的步骤804，在此不做赘述。每个第二过孔与相邻的第一导线段031和第三导线段033连通。
步骤1207、在第三绝缘层上形成多个第四导线段，且多个第四导线段通过多个第二过孔搭接在多个第三导线段和多个第一导线段上以实现电连接。
如图5所示，在步骤1207中，可以在第三绝缘层043上形成多个第四导线段034。形成第四导线段044的过程可以参考图8所示的实施例中的步骤 802，在此不做赘述。
需要说明的是，检测线由多个第一导线段、多个第三导线段和多个第四导线段搭接而成，且与数据线电连接。每个第一导线段与衬底基板之间均设置有隔垫物(也即第二绝缘层)。
综上所述，根据本公开实施例的方法所制造的显示面板中，位于非显示区域的检测线由多个导线段搭接而成，因此，在非显示区域出现轻微的断裂时，该多个导线段的搭接处的应力较大，该搭接处容易发生较为严重的断裂，此时，该断裂部由于断裂程度较严重，因此，无法通过该检测线向数据线输入检测信号，此时，这些数据线所在的位置会显示竖向亮线，所以能够有效的检测到非显示区域的轻微断裂，提高了裂纹检测的准确度。
本公开的至少一个实施例提供了一种显示装置，该显示装置可以包括图2或图5所示的显示面板。该显示装置可以为：液晶显示装置、电子纸、有机发光二极管显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是，根据本公开的方法实施例能够与相应的显示面板实施例相互参考，本公开实施例对此不做限定。根据本公开实施例的方法实施例中的步骤的先后顺序能够进行适当调整，步骤也能够根据情况进行相应增减，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本公开的保护范围之内，因此不再赘述。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (15)

  1. 一种显示面板，包括：衬底基板，设置在所述衬底基板上的显示区域和非显示区域，所述显示区域内设置有数据线；所述非显示区域内设置有检测线；
    其中，所述检测线与所述数据线电连接，并由多个导线段搭接而成。
  2. 根据权利要求1所述的显示面板，其中，所述多个导线段包括：第一导线段，以及除所述第一导线段之外的其他导线段，所述第一导线段与所述衬底基板之间设置有隔垫物。
  3. 根据权利要求2所述的显示面板，其中，所述其他导线段包括：第二导线段，所述第一导线段与所述第二导线段交替设置，且所述第一导线段搭接在所述第二导线段上。
  4. 根据权利要求3所述的显示面板，其中，
    所述隔垫物包括第一绝缘层，所述第一绝缘层位于所述第二导线段上且覆盖所述非显示区域，所述第一绝缘层上设置有连通所述第二导线段的第一过孔；以及
    所述第一导线段设置在所述第一绝缘层上，且通过所述第一过孔与所述第二导线段搭接。
  5. 根据权利要求3或4所述的显示面板，其中，所述衬底基板上的显示区域内还设置有依次形成的第一目标导电层、第一目标绝缘层和第二目标导电层，
    所述第二导线段与所述第一目标导电层同层设置，所述第一绝缘层与所述第一目标绝缘层同层设置，所述第一导线段与所述第二目标导电层同层设置。
  6. 根据权利要求5所述的显示面板，其中，所述衬底基板上的显示区域 内还设置有顶栅结构的薄膜晶体管和存储电容，
    所述薄膜晶体管包括：在衬底基板上依次设置的有源层、第一栅绝缘层、栅极、第二栅绝缘层、源漏极绝缘层以及源漏极图案；所述存储电容包括：在所述衬底基板上依次设置的第一电极、电容绝缘层和第二电极；
    所述第一目标导电层包括所述栅极，所述第一目标绝缘层包括所述第二栅绝缘层，所述第二目标导电层包括所述第二电极。
  7. 根据权利要求2所述的显示面板，其中，所述其他导线段包括：第三导线段和第四导线段，所述第一导线段和所述第三导线段一一交替并间隔设置，所述第四导线段搭接在相邻的第一导线段和第三导线段上。
  8. 根据权利要求7所述的显示面板，其中，
    所述隔垫物包括：位于所述第三导线段上且覆盖所述非显示区域的第二绝缘层，所述第一导线段设置在所述第二绝缘层上；
    所述衬底基板上还设置有位于所述第一导线段上且覆盖所述非显示区域的第三绝缘层；以及
    所述第二绝缘层和所述第三绝缘层中设置有贯穿所述第二绝缘层和所述第三绝缘层的第二过孔，所述第二过孔与相邻的第一导线段和第三导线段连通，所述第四导线段设置在所述第三绝缘层上，且通过所述第二过孔搭接在所述第三导线段和所述第一导线段上。
  9. 根据权利要求8所述的显示面板，其中，所述衬底基板上的显示区域内还设置有依次形成的第三目标导电层、第二目标绝缘层、第四目标导电层、第三目标绝缘层以及第五目标导电层，
    所述第三导线段与所述第三目标导电层同层设置，所述第二绝缘层与所述第二目标绝缘层同层设置，所述第一导线段与所述第四目标导电层同层设置，所述第三绝缘层与所述第二目标绝缘层同层设置，所述第四导线段与所述第五目标导电层同层设置。
  10. 根据权利要求9所述的显示面板，其中，所述衬底基板上的显示区 域内还设置有顶栅结构的薄膜晶体管和存储电容，
    所述薄膜晶体管包括：在衬底基板上依次设置的有源层、第一栅绝缘层、栅极、第二栅绝缘层、源漏极绝缘层以及源漏极图案；所述存储电容包括：在所述衬底基板上依次设置的第一电极、电容绝缘层和第二电极；
    所述第三目标导电层包括所述栅极，所述第二目标绝缘层包括所述第二栅绝缘层，所述第四目标导电层包括所述第二电极，所述第三目标绝缘层包括所述源漏极绝缘层，所述第五目标导电层包括所述源漏极图案。
  11. 一种显示面板的制造方法，其包括：
    在衬底基板的显示区域内形成数据线；
    在所述衬底基板的非显示区域内形成检测线；
    其中，所述检测线由多个导线段搭接而成，且与所述数据线电连接。
  12. 根据权利要求11所述的方法，其还包括：
    在所述衬底基板上的非显示区域形成隔垫物；
    其中，所述多个导线段包括第一导线段，以及除所述第一导线段之外的其他导线段，所述第一导线段与所述衬底基板之间均设置有所述隔垫物。
  13. 根据权利要求12所述的方法，其中，所述其他导线段包括第二导线段，在所述衬底基板的非显示区域内形成检测线包括：
    在所述衬底基板的非显示区域内形成所述第二导线段；
    在所述衬底基板的非显示区域内形成搭接在所述第二导线段上的所述第一导线段，且所述第一导线段与所述第二导线段一一交替设置。
  14. 根据权利要求12所述的方法，其中，所述其他导线段包括第三导线段和第四导线段，在所述衬底基板的非显示区域内形成检测线包括：
    在所述衬底基板的非显示区域内形成所述第三导线段；
    在所述衬底基板的非显示区域内形成所述第一导线段，且所述第一导线段和所述第三导线段交替并间隔设置；
    在所述衬底基板的非显示区域内形成搭接在相邻的第一导线段和第三导 线段上的所述第四导线段。
  15. 一种显示装置，其包括权利要求1至10任一所述的显示面板。
PCT/CN2019/074197 2018-05-28 2019-01-31 显示面板及其制造方法、显示装置 WO2019227963A1 (zh)

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