WO2015070461A1 - 像素结构及其制作方法 - Google Patents

像素结构及其制作方法 Download PDF

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Publication number
WO2015070461A1
WO2015070461A1 PCT/CN2013/087347 CN2013087347W WO2015070461A1 WO 2015070461 A1 WO2015070461 A1 WO 2015070461A1 CN 2013087347 W CN2013087347 W CN 2013087347W WO 2015070461 A1 WO2015070461 A1 WO 2015070461A1
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Prior art keywords
passivation layer
transparent substrate
pixel electrode
data line
layer
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PCT/CN2013/087347
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English (en)
French (fr)
Inventor
郝思坤
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to JP2016552653A priority Critical patent/JP6370003B2/ja
Priority to GB1604505.6A priority patent/GB2533512B/en
Priority to US14/349,281 priority patent/US9685470B2/en
Priority to KR1020167009428A priority patent/KR101823803B1/ko
Publication of WO2015070461A1 publication Critical patent/WO2015070461A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel structure and a method of fabricating the same. Background technique
  • Liquid crystal displays are currently the most widely used flat panel display with high resolution color screens and have been widely used in a variety of electronic devices, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens. Wait.
  • Liquid crystal displays which are currently in common use, are usually composed of upper and lower substrates and an intermediate liquid crystal layer, and the substrate is composed of glass and electrodes. If electrodes are provided on the upper and lower substrates, a vertical electric field mode liquid crystal display such as a TN (Twist Nematic) mode liquid crystal display, a VA (Vertical Alignment) mode liquid crystal display, and a solution can be formed.
  • TN Transmission Nematic
  • VA Very Alignment
  • MVA Microiidomain Verticai Aiignment
  • the electrode is located only on one side of the substrate to form a liquid crystal display in a transverse electric field mode, such as an IPS (In-plane switching) mode liquid crystal display, FFS (Fringe Field Switching, edge switching). Mode LCD display, etc.
  • FFS mode LCD displays are used in many mobile communication devices due to their high aperture, high resolution, and wide viewing angle.
  • the display screen of mobile communication devices is moving toward high resolution (Pixels per inch, ⁇ ), high color gamut value, high contrast, and low power consumption.
  • ⁇ Pixel per inch
  • the parasitic capacitance inside the screen becomes more and more serious.
  • the thickness of the insulating layer formed of the nitrogen silicon compound (SiNx) or silicon dioxide (Si0 2 ) between the electrodes is generally increased, or an organic insulating layer having a larger thickness is used.
  • the above method also reduces the beneficial capacitance, such as the storage capacitor C st , while reducing the harmful parasitic capacitance.
  • FIG. 1 is a pixel structure used in a mobile phone screen in the prior art
  • FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1.
  • TFT thin film transistor
  • the product of the resistance (R) and the capacitance (C) is left and right, which causes some pixels in the liquid crystal panel to be undercharged, and the wrong gray scale is displayed, which affects the picture quality.
  • the thickness of the insulating layer between the transparent conductive layer electrode 100 of the common electrode and the data line 200 is generally increased, but this also reduces the transparent conductive layer electrode 100 of the common electrode and the transparent conductive layer electrode of the pixel electrode. 300 storage capacitors 2 . According to the formula
  • C st is the storage capacity value, V gh
  • FIG. 3 is a flow chart of fabricating a pixel structure in a FFS mode liquid crystal display in the prior art.
  • the first method is: sequentially depositing a first metal layer (GE ) and a gate insulating layer (GI ) on a glass substrate.
  • a-Si pixel electrode
  • GI gate insulating layer
  • Pixel ITO pixel electrode
  • S/D passivation layer
  • Comp ⁇ common electrode
  • the second method is: sequentially depositing a first metal layer (GE), a gate insulating layer (GI), an amorphous silicon layer (a-si), a second metal layer (S./D), and a pixel on a glass substrate.
  • An object of the present invention is to provide a pixel structure, which increases the storage capacitance of a pixel structure by reducing the distance between the pixel electrode and the common electrode, and reduces the picture quality of the FFS mode liquid crystal display using the pixel structure by the feedthrough voltage and the leakage current. Impact.
  • Another object of the present invention is to provide a method for fabricating a pixel structure, which is simple in manufacturing method, and increases the storage capacitance of the pixel structure by the second etching, and reduces the feedthrough voltage and leakage to the FFS mode liquid crystal to which the pixel structure is applied. The effect of the picture quality of the display.
  • Another object of the present invention is to provide a method for fabricating a pixel structure, which is simple in manufacturing method, and increases a storage capacitor of a pixel structure by a passivation layer of a two-layer structure, and reduces a feedthrough voltage and a leakage current to apply the pixel structure.
  • the effect of the picture quality of the FFS mode LCD is to provide a method for fabricating a pixel structure, which is simple in manufacturing method, and increases a storage capacitor of a pixel structure by a passivation layer of a two-layer structure, and reduces a feedthrough voltage and a leakage current to apply the pixel structure.
  • the present invention provides a pixel structure including: a transparent substrate, a gate line formed on the transparent substrate, a thin film transistor formed on the transparent substrate, and formed in a transparent a data line on the substrate, a pixel electrode formed on the transparent substrate and the thin film transistor are formed on the pixel electrode, a passivation layer on the transparent substrate and the data line, and a common electrode on the passivation layer, the passivation layer includes : Located in the first part of the data line.
  • the thickness of the first portion of the passivation layer is greater than the thickness of the third portion, and the top end of the second portion of the passivation layer is flush with the top end of the third portion;
  • the pixel structure further includes a thin film transistor and a pixel electrode. Protective layer between.
  • the thin film transistor has a gate, a drain and a source, the gate is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode
  • the pixel electrode is a transparent conductive layer, and the common electrode is a transparent conductive layer.
  • the invention also provides a method for fabricating a pixel structure, comprising the following steps:
  • Step 1 Provide a transparent substrate
  • Step 12 depositing a gate line, a thin film transistor data line, and a pixel electrode on the transparent substrate;
  • Step 13 Depositing a passivation layer on the transparent substrate, the data line and the pixel electrode, the passivation layer comprising: a first portion on the data line, a second portion on the pixel electrode, and a transparent substrate The third part on both sides of the data line;
  • Step 14 etching the passivation layer on the peripheral line to complete the first etching, and then etching the second portion of the passivation layer to complete the second etching to reduce the second portion of the passivation layer. Thickness such that the thickness of the first portion of the passivation layer is greater than the thickness of the second portion;
  • Step 15 Depositing a common electrode on the passivation layer.
  • the step 12 further includes forming a protective layer on the transparent substrate, the protective layer being formed between the thin film transistor and the pixel electrode.
  • the second etching in the step 14 further includes etching the third portion of the passivation layer, after the second etching is completed, the thickness of the first portion of the passivation layer is greater than the thickness of the third portion, the passivation The top end of the second portion of the layer is flush with the top end of the third portion.
  • the pixel electrode is a transparent conductive layer
  • the common electrode is a transparent conductive layer
  • the invention also provides a method for fabricating a pixel structure, comprising the following steps:
  • Step 21 providing a transparent base plate
  • Step 22 Depositing a gate line, a thin film transistor, a data line, and a pixel electrode on the transparent substrate;
  • Step 23 depositing a first passivation on the transparent substrate, the data line and the pixel electrode a layer, etching the first passivation layer, leaving only the first passivation layer above the data line, and the other portions are etched away;
  • Step 24 depositing a second passivation layer on the transparent substrate, the pixel electrode and the first passivation layer, etching the second passivation layer, and etching the second passivation layer on the peripheral line , other parts are reserved;
  • Step 25 Depositing a common electrode on the second passivation layer.
  • the thickness of the first passivation layer is greater than the thickness of the second passivation layer.
  • the step 22 further includes forming a protective layer on the transparent substrate, the protective layer is formed between the thin film transistor and the pixel electrode; the pixel electrode is a transparent conductive layer, and the common electrode is transparent. Conductive layer.
  • the present invention provides a pixel structure and a method of fabricating the same, which reduces the distance between a common electrode and a pixel electrode by a second etching or a passivation layer of a two-layer structure to increase The storage capacitance of the pixel structure; also increases the distance between the data line and the common electrode to reduce harmful parasitic capacitance, thereby reducing the influence of the feedthrough voltage and leakage on the picture quality of the FFS mode liquid crystal display to which the pixel structure is applied, Moreover, the method of fabricating the pixel structure is relatively simple.
  • FIG. 1 is a schematic diagram of a pixel structure in the prior art
  • Figure 2 is a cross-sectional view taken along line A A of Figure i;
  • FIG. 4 is a schematic structural view of a pixel structure of the present invention.
  • FIG. 5 is a flow chart showing steps of an embodiment of a method for fabricating a pixel structure according to the present invention
  • FIG. 6 is a schematic structural view of the manufacturing process in FIG. 5;
  • FIG. 7 is a flow chart of steps of another embodiment of a method for fabricating a pixel structure of the present invention.
  • FIG. 8 is a schematic structural view of a manufacturing process of FIG. Concrete real way
  • the present invention provides a pixel structure, including:
  • a transparent substrate 60 a gate line formed on the transparent substrate 60 (not shown for convenience of viewing), a thin film transistor (not shown for convenience of observation) formed on the transparent substrate 60, and formed on the transparent substrate 60 a data line 68, a pixel electrode 62 formed on the transparent substrate 60 and the thin film transistor, a passivation layer 64 formed on the pixel electrode 62, the transparent substrate 60 and the data line 68, and a common electrode 66 formed on the passivation layer 64 .
  • the passivation layer 64 includes: a first portion 72 on the data line 68, a second portion 74 on the pixel electrode 62, and a third portion 76 on the transparent substrate 60 and on both sides of the data line 68.
  • the thickness of the first portion 72 of the passivation layer 64 is greater than the thickness of the second portion 74, and the pixel electrode 62 partially overlaps the common electrode 66 to form a storage capacitor Cst .
  • the present invention reduces the parasitic capacitance C parasitic by increasing the distance between the data line 68 and the common electrode 66, and increases the storage capacitance Cst by reducing the distance between the pixel electrode 62 and the common electrode 66. The effect of small feedthrough voltage and leakage on the picture quality of the FFS mode liquid crystal display to which the pixel structure is applied.
  • the transparent substrate is a glass substrate.
  • the pixel structure further includes a protective layer (not shown) formed between the thin film transistor and the pixel electrode 62.
  • the thickness of the first portion 72 of the passivation layer 64 is also greater than the thickness of the third portion 76.
  • the top end of the second portion 74 of the passivation layer 64 is flush with the top end of the third portion 76.
  • the thin film transistor is configured to charge a data signal on the data line 68 according to a scan signal on the gate line to a storage capacitor C st formed by partially overlapping the pixel electrode 62 and the common electrode 66, which has a
  • the gate, the drain and the source are electrically connected to the gate line, the source is electrically connected to the data line 68, and the drain is electrically connected to the pixel electrode 62.
  • the common electrode 66 includes a portion 82 above the data line 68 and another portion 84 on the pixel electrode 62.
  • the pixel electrode 62 is a transparent conductive layer
  • the common electrode 66 is also a transparent conductive layer.
  • the present invention further provides a method for fabricating a pixel structure, including the following steps:
  • Step i 1 A transparent substrate 60 is provided.
  • the transparent substrate. 60 is a glass substrate irritation
  • Step 12 A gate line, a thin film transistor, a data line 68, and a pixel electrode 62 are deposited on the transparent substrate 60.
  • the formation processes of the gate lines, the thin film transistors, the data lines 68, and the pixel electrodes 62 are all formed according to the prior art.
  • the step further includes forming a protective layer on the transparent substrate 60, the protective layer being formed between the thin film transistor and the pixel electrode 62.
  • the formation process of the protective layer is the same as that in the prior art.
  • the thin film transistor has a gate, a drain and a source, the gate is electrically connected to the gate line, and the source is electrically connected to the data line 68.
  • the drain of the thin film transistor is electrically connected to the pixel electrode 62 to charge the data signal on the data line 68 to the storage capacitor C st .
  • the pixel electrode 62 is a transparent conductive layer.
  • Step 13 Forming a passivation layer 64 on the transparent substrate 60.
  • the passivation layer 64 includes: a first portion 72 on the data line 68, a second portion 74 on the pixel electrode 62, and a transparent A third portion 76 on the substrate 60 and on either side of the data line 68.
  • Step 14 Etching the passivation layer 64 on the peripheral line to complete the first etching, and then etching the second portion 74 of the passivation layer 64 to complete the second etching to reduce the passivation layer 64.
  • the thickness of the second portion 74 is such that the thickness of the first portion 72 of the passivation layer 64 is greater than the thickness of the second portion 74.
  • the second etching in the step 14 further includes etching the third portion 76 of the passivation layer 64.
  • the thickness of the first portion 72 of the passivation layer 64 is greater than the thickness of the third portion 76.
  • the top end of the second portion 74 of the passivation layer 64 is flush with the top end of the third portion 76.
  • Step 15 Depositing a common electrode 66 on the passivation layer 64.
  • the common electrode 66 is a transparent conductive layer comprising a portion 82 above the data line 68 and another portion 84 on the pixel electrode 62.
  • the thickness of the first portion 72 of the salient layer 64 is greater than the thickness of the second portion 74, that is, by increasing the distance between the data line 68 and the common electrode 66 to reduce the parasitic capacitance C while reducing the pixel.
  • the distance between the electrode 62 and the common electrode 66 increases the storage capacitor C st to reduce the influence of the feedthrough voltage and leakage on the picture quality of the FFS mode liquid crystal display to which the pixel structure is applied.
  • the present invention further provides a method for fabricating a pixel structure, including the following steps:
  • Step 2 providing a transparent substrate 60.
  • the transparent substrate 60 is a glass substrate.
  • Step 22 forming a gate line, a thin film transistor, a data line 68, and a pixel electrode 62 on the transparent substrate 60.
  • the step further includes forming a protective layer on the transparent substrate 60, the protective layer being formed in the The thin film transistor is between the pixel electrode 62.
  • the formation process of the protective layer is the same as that in the prior art.
  • the thin film transistor has a gate, a drain and a source, the gate is electrically connected to the gate line, and the source is electrically connected to the data line 68.
  • the drain of the thin film transistor is electrically connected to the pixel electrode 62 to charge the data signal on the data line 68 to the storage capacitor Csi .
  • the pixel electrode 62 is a transparent conductive layer.
  • Step 23 depositing a first passivation layer 92 on the transparent substrate 60, the data line 68 and the pixel electrode 62, and performing the first passivation layer 92 on the first passivation layer 92, leaving only the first layer above the data line 68. Passivation layer 92, the other portions are etched away.
  • Step 24 depositing a second passivation layer 94 on the transparent substrate 60, the pixel electrode 62 and the first passivation layer 92, etching the second passivation layer 94, and placing a second on the peripheral line
  • the passivation layer 94 is etched away and the other portions are retained.
  • the thickness of the first passivation layer 92 is greater than the thickness of the second passivation layer 94.
  • Step 25 depositing a common electrode 66 on the second passivation layer 94.
  • the common electrode 66 is a transparent conductive layer including a portion 82 above the data line 68 and another portion 84 on the pixel electrode 62.
  • the first and second passivation layers 92, 94 are included between the data line 68 and the common electrode 66, and only the second passivation layer 94 is between the pixel electrode 62 and the common electrode 66.
  • the data line 68 is common to The distance between the electrodes 66 is greater than the distance between the pixel electrode 62 and the common electrode 66, and the parasitic capacitance C is reduced by increasing the distance between the data line 68 and the common electrode 66, while reducing the pixel electrode 62 and the common The distance between the electrodes 66 increases the storage capacitor Cst to reduce the effect of the feedthrough voltage and leakage on the picture quality of the FFS mode liquid crystal display to which the pixel structure is applied.
  • the present invention provides a pixel structure and a method of fabricating the same, which reduces the distance between the common electrode and the pixel electrode by a second etching or a passivation layer of a two-layer structure to increase the pixel structure.
  • the storage capacitor also increases the distance between the data line and the common electrode to reduce harmful parasitic capacitance, thereby reducing the influence of the feedthrough voltage and leakage on the picture quality of the FFS mode liquid crystal display to which the pixel structure is applied, and
  • the fabrication method of the pixel structure is relatively simple.

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Abstract

一种像素结构包括：一透明基板（60）、形成于透明基板（60）上的栅极线、形成于透明基板（60）上的薄膜晶体管、形成于透明基板（60）上的数据线（68）、形成于透明基板（60）及薄膜晶体管上的像素电极（62）、形成于像素电极（62）、透明基板（60）及数据线（68）上的钝化层（64）、以及形成钝化层（64）上的公共电极（66），该钝化层（64）包括：位于数据线（68）上的第一部分（72）、位于像素电极（62）上的第二部分（74）、及位于透明基板（60）上且位于数据线（68）的两侧的第三部分（76），钝化层（64）第一部分（72）的厚度大于第二部分（74）的厚度。还提供了一种像素结构的制作方法。

Description

技术领域
本发明涉及显示技术领域， 尤其涉及一种像素结构及其制作方法。 背景技术
近年来显示技术发展很快， 平板显示器以其完全不同的显示和制造技 术使之与传统的视频图像显示器有很大的差别。 传统的视频图像显示器主 要为阴极射线管 CRT(Cathode ray tubes); 而平板显示器与之的主要区别在 于重量和体积 (厚度） 方面的变化， 通常平板显示器的厚度不超过 I 0cm， 当然还有其它的不同， 如显示原理、 制造材料> 工艺以及视频图像显示驱 动方面的各项技.术等。
液晶显示器是目前使用最广泛的具有高分辨率彩色屏幕的一种平板显 示器， 已经广泛被各种电子设备所应用， 如移动电话、 个人数字助理 (PDA), 数码相机、 计算机屏幕或笔记本电脑屏幕等。
目前普遍釆用的液晶显示器， 通常由上下衬底和中间液晶层组成， 而 衬底由玻璃和电极等组成。 如果上下衬底上都设有电极， 可以形成纵向电 场模式的液晶显示器， 如 TN ( Twist Nematic， 扭曲向列）模式液晶显示 器、 VA ( Vertical Alignment, 垂直配向）模式液晶显示器、 以 .及为了解决 视角过窄问题而开发的 MVA ( Muliidomain Verticai Aiignment, 多域垂直 配向）模式液晶显示器。 另外一类与上述液晶显示器不同， 电极只位于衬 底的一侧， 形成横向电场模式的液晶显示器， 如 IPS ( In- plane switching， 平面切换）模式液晶显示器、 FFS ( Fringe Field Switching, 边缘切换）模 式液晶显示器等。 FFS 模式液晶显示器以其高开口、 高分辨率、 广视角等 特点为众多移动通讯设备采用。
目前移动通讯设备的显示屏向高分辨率 ( Pixels per inch, ΡΡΐ ) 、 高色 域值、 高对比度、 低功耗方向发展。 随着分辨率的提高， 屏幕内部的寄生 电容变得越来越严重。 为了减小屏幕内部的寄生电容， 通常增加电极间由 氮硅化合物 （SiNx )或二氧化硅（Si02 )形成的绝缘层的厚度， 或者使用 厚度更大的有机绝缘层。 上述方法在减小有害寄生电容的同时， 也导致有 益电容的减小， 如存储电容 Cst。
具体的， 请参阅图 〗 及图 2， 图 1 为现有技术中手机屏使用的像素结 构， 图 2为图 1中 A- A线的剖面图， 为了方便说明， 图 i及图 2中均省略 了薄膜晶体管 ( Thin Film Transistor ， TFT )部分的结构。 在该 FFS模式 液晶显示器像素结构中， 公共电极的透明导电层电极 100 与数据线 （Date line ) 200间的寄生电容①会增加数据线 200上的 RC delay (即数据线上信 号传递的快慢受到电阻（R ) 与电容（C ) 的乘积所左右） ， 这就会使液晶 面板中部分像素充电不足， 而显示错误的灰阶， 影响画面品质。 为了减小 寄生电容①， 通常会增加公共电极的透明导电层电极 100与数据线 200间 绝缘层的厚度， 但是这样也减小了公共电极的透明导电层电极 100与像素 电极的透明 导电层电极 300 间 的存储电容② 。 根据公式
， Cst为存储 容值， Vgh
Figure imgf000004_0001
( Feedthrough ) ， 使液晶面板的亮度下降， 降低穿透。
请参阅图 3 , 其为现有技术中 FFS模式液晶显示器中像素结构的制作 流程图， 第一种方法是： 在玻璃基板依次沉积形成第一金属层（GE ) 、 栅 极绝缘层（GI ) ' 非晶硅层 （a- Si ) 、 像素电极 （Pixel ITO ) 、 第二金属 层 （S/D ) 、 钝化层 ( PV )及公共电极（Com ΠΌ ) 。 第二种方法是： 在 玻璃基板依次沉积形成第一金属层（GE ) 、 柵极绝缘层 （GI ) 、 非晶硅层 ( a- si ) 、 第二金属层（S./D ) 、 像素电极（Pixel ITO ) 、 钝化层 （ PV )及 公共电极（Com lTO ) 。 发明内容
本发明的目的在于提供一种像素结构， 通过减小像素电极与公共电极 的距离来增大像素结构的存储电容， 減小馈通电压及漏电对应用该像素结 构的 FFS模式液晶显示器的画面品质的影响。
本发明的另一目的在于提供一种像素结构的制作方法， 制作方法简 单， 通过第二次蚀刻来增大像素结构的存储电容， 减小馈通电压及漏电对 应用该像素结构的 FFS模式液晶显示器的画面品质的影响。
本发明的又一目的在于提供一种像素结构的制作方法， 制作方法简 单， 通过两层结构的钝化层来增大像素结构的存储电容， 减小馈通电压及 漏电对应用该像素结构的 FFS模式液晶显示器的画面品质的影响。
为实现上述目的， 本发明提供一种像素结构， 包括： 一透明基板、 形 成于透明基板上的栅极线、 形成于透明基板上的薄膜晶体管、 形成于透明 基板上的数据线、 形成于透明基板及薄膜晶体管上的像素电极 形成于像 素电极.、 透明基板及数据线上的钝化层， 以及形成钝化层上的公共电极， 所述钝化层包括： 位于数据线上的第一部分。 位于像素电极上的第二部 分、 以及位于透明基板上且位于数据线的两侧的第三部分， 所述钝化层第 一部分的厚度大于第二部分的厚度， 所述像素电极与所述公共电极部分重 叠以形成存储电容。
所述钝化层第一部分的厚度大于第三部分的厚度， 所述钝化层第二部 分的顶端与第三部分的顶端平齐； 所述像素结构还包括一形成于薄膜晶体 管及像素电极之间的保护层。
所述薄膜晶体管具有一栅极、 一漏极及一源极， 所述栅极与栅极线电 性连接， 所述源极与数据线电性连接， 所述漏极与像素电极电性连接， 所 述像素电极为一透明导电层， 所述.公共电极为一透明导电层。
本发明还提供一种像素结构的制作方法， 包括以下步骤：
步驟 1 1、 提供一透明基板；
步骤 12、 在所述透明基板上沉积形成栅极线、 薄膜晶体管 数据线及 像素电极；
步骤 13、 在所述透明基板、 数据线及像素电极上沉积形成钝化层， 所 述钝化层包括： 位于所述数据线上的第一部分、 位于像素电极上的第二部 分以及位于透明基板上且位于数据线两侧的第三部分；
步骤 14、 对外围线路上的钝化层进行蚀刻， 以完成第一次蚀刻， 之后 对钝化层的第二部分进行蚀刻， 以完成第二次蚀刻， 以减小钝化层第二部 分的厚度， 使得钝化层第一部分的厚度大于第二部分的厚度；
步骤 15、 在所述钝化层上沉积形成公共电极。
所述步骤 12 还包括在所述透明基板上形成一保护层， 所述保护层形 成于所述薄膜晶体管与所述.像素电极之间。
所述步骤 14 中的第二次蚀刻还包括对钝化层的第三部分进行蚀刻， 第二次蚀刻完成后， 所述钝化层第一部分的厚度大于第三部分的厚度， 所 述钝化层第二部分的顶端与第三部分的顶端平齐。
所述像素电极为一透明导电层， 所述公共电极为一透明导电层。
本发明还提供一种像素结构的制作方法， 包括以下步骤：
步骤 21、 提供一透明基.板；
步骤 22。 在所述透明基板上沉积形成柵极线、 薄膜晶体管、 数据线及 像素电极；
步骤 23、 在所述透明基板、 数据线及像素电极上沉积形成一第一钝化 层， 对所述第一钝化层进行蚀刻， 仅保留数据线上方的第一钝化层， 其它 部分蚀刻掉；
步骤 24、 在所述透明基板、 像素电极及第一钝化层上沉积形成一第二 钝化层， 对所述第二钝化层进行蚀刻， 将外围线路上的第二钝化层蚀刻 掉， 其它部分保留；
步骤 25、 在所述第二钝化层上沉积形成公共电极。
所述第一钝化层的厚度大于所述第二钝化层的厚度。
所述步骤 22 还包括在透明基板上形成一保护层， 所述保护层形成于 所述薄膜晶体管与所述像素电极之间； 所述像素电极为一透明导电层， 所 述公共电极为一透明导电层。
本发明的有益效果： 本发明提供一种像素结构及其制作方法， 通过第 二次蚀刻或两层结构的钝化层来減 ' j、公共电极.与像素电极之间的距离， 以 增大像素结构的存储电容； 同时也增大了数据线与公共电极的距离， 以减 小有害寄生电容， 进而减小馈通电压及漏电对应用该像素结构的 FFS模式 液晶显示器的画面品质的影响， 并且， 该像素结构的制作方法较为简单。
为了能更进一步了解本发明的特征以及技术内容， 请参阅以下有关本 发明的详细说明与附图， 然而附图仅提供参考与说明用， 并非用来对本发 明加以限制。 附图说明
下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明 的技术方案及其它有益效果显¾易见。
附图中，
图 1为现有技术中像素结构示意图；
图 2为图 i中 A A线的剖面图；
图 3为现有技术中像素结构的制作流程图；
图 4本发明像素结构的结构示意图；
图 5为本发明像素结构的制作方法一实施例的步驟流程图；
图 6为图 5中制作流程的结构示意图；
图 7为本发明像素结构的制作方法的另一实施例的步骤流程图； 图 8为图 7中制作流程的结构示意图。 具体实族方式
为更进一步阐述本发明所采取的技术手段及其效果， 以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 4， 本发明提供一种像素结构， 包括：
一透明基板 60、 形成于透明基板 60上的柵极线 （为了便于观察， 未 图示） 、 形成于透明基板 60 上的薄膜晶体管 （为了便于观察， 未图 示） 、 形成于透明基板 60上的数据线 68、 形成于透明基板 60及薄膜晶体 管上的像素电极 62、 形成于像素电极 62、 透明基板 60及数据线 68上的 钝化层 64、 以及形成钝化层 64上的公共电极 66。
所述钝化层 64包括： 位于数据线 68上的第一部分 72、 位于像素电极 62上的第二部分 74、 以及位于透明基板 60上且位于数据线 68的两側的 第三部分 76, 所述钝化层 64第一部分 72 的厚度大于第二部分 74 的厚 度， 所述像素电极 62与所述公共电极 66部分重叠以形成存储电容 Cst。 本 发明通过增加数据线 68与公共电极. 66之间的距离来减小寄生电容 C 寄生的 同时， 通过减小像素电极 62 与公共电极 66之间的距离来增大存储电容 Cst, 以减小馈通电压及漏电对应用该像素结构的 FFS模式液晶显示器的画 面品质的影响。
所述透明基板为玻璃基板。 所述像素结构还包括一形成于薄膜晶体管 及像素电极 62之间的保护层（未图示 ) „
所述钝化层 64第一部分 72的厚度也同样大于第三部分 76的厚度， 优选的, 所述.钝化层 64第二部分 74的顶端与第三部分 76的顶端平齐。
所述薄膜晶体管用于根据柵极线上的扫描信号将数据线 68 上的数据 信号充至所述.像素电极 62与所述.公共电极 66部分重叠形成的存储电容 Cst 中， 其具有一栅极、 一漏极及一源极， 所述栅极与栅极线电性连接, 所述 源极与数据线 68电性连接， 所述漏极与像素电极 62电性连接。
所述公共电极 66 包括位于数据线 68上方的一部分 82及位于像素电 极 62 上的另一部分 84。 在本实施例中， 所述像素电极 62 为一 -透明导电 层， 所述公共电极 66同样也为一透明导电层。
请参阅图 4 至图 6， 本发明还提供一种像素结构的制作方法， 包括以 下步骤：
步骤 i 1、 提供一透明基板 60。
所述透明基板. 60为玻璃基板„
步骤 12。 在所述透明基板 60上沉积形成柵极线、 薄膜晶体管、 数据 线 68及像素电极 62。
所述柵极线、 薄膜晶体管、 数据线 68及像素电极 62的形成工艺均按 照现有技术形成 该步骤还包括在透明基板 60 上形成一保护层， 所述保护层形成于所 述薄膜晶体管与所述像素电极 62 之间。 所述保护层的形成工艺与现有技 术中的工艺相同。
所述薄膜晶体管具有一柵极、 一漏极及一源极， 所述柵极与柵极线电 性连接， 所述源极与数据线 68 电性连接。 所述薄膜晶体管的漏极与像素 电极 62电性连接， 以将数据线 68上的数据信号充至存储电容 Cst。 所述像 素电极 62为一透明导电层。
步骤 13、 在所述透明基板 60 上沉积形成钝化层 64, 所述钝化层 64 包括： 位于所述数据线 68上的第一部分 72、 位于像素电极 62上的第二部 分 74以及位于透明基板 60上且位于数据线 68两侧的第三部分 76。
步骤 14、 对外围线路上的钝化层 64进行蚀刻， 以完成第一次蚀刻， 之后对钝化层 64的第二部分 74进行蚀刻， 以完成第二次蚀刻， 以減小钝 化层 64第二部分 74的厚.度， 使得钝化层 64第一部分 72的厚度大于第二 部分 74的厚度。
所述步骤 14 中的第二次蚀刻还包括对钝化层 64的第三部分 76进行 蚀刻， 第二次蚀刻完成后， 所述钝化层 64第一部分 72的厚度大于第三部 分 76的厚度， 优选的， 所述钝化层 64第二部分 74的顶端与第三部分 76 的顶端平齐。
步骤 15、 在所述钝化层 64上沉积形成公共电极 66。
所述公共电极 66为一透明导电层， 其包括位于数据线 68上方的一部 分 82及位于像素电极 62上的另一部分 84。 本发明中所述徒化层 64第一 部分 72的厚度大于第二部分 74的厚度， 即通过增加数据线 68与公共电 极 66之间的距离来减小寄生电容 C 生的同时， 通过减小像素电极 62与公 共电极 66之间的距离来增大存储电容 Cst， 以减小馈通电压及漏电对应用 该像素结构的 FFS模式液晶显示器的画面品质的影响„
请参阅图 7及图 8， 同时参考图 4， 本发明还提供一种像素结构的制 作方法， 包括以下步骤：
步骤 2】、 提供一透明基板 60。
所述透明基板 60为玻璃基板。
步骤 22、 在所述透明基板 60 上沉积形成栅极线， 薄膜晶体管、 数据 线 68及像素电极 62。
所述柵极线、 薄膜晶体管、 数据线 68及像素电极 62的形成工艺均按 照现有技术形成。
该步骤还包括在透明基板 60 上形成一保护层， 所述保护层形成于所 述薄膜晶体管与所述像素电极 62 之间。 所述保护层的形成工艺与现有技 术中的工艺相同。
所述薄膜晶体管具有一栅极、 一漏极及一源极， 所述栅极与栅极线电 性连接， 所述源极与数据线 68 电性连接。 所述薄膜晶体管的漏极与像素 电极 62电性连接， 以将数据线 68上的数据信号充至存储电容 Csi。
所述像素电极 62为一透明导电层。
步骤 23、 在所述透明基板 60、 数据线 68及像素电极 62 上沉积形成 一第一钝化层 92， 对所述第一钝化层 92进行独刻， 仅保留数据线 68上方 的第一钝化层 92， 其它部分蚀刻掉。
步骤 24、 在所述透明基板 60、 像素电极 62及第一钝化层 92上沉积 形成一第二钝化层 94， 对所述第二钝化层 94进行蚀刻， 将外围线路上的 第二钝化层 94蚀刻掉， 其它部分保留。
在本实施例中， 所述第一钝化层 92的厚度大于所述第二钝化层 94的 厚度。 步驟 25、 在所述第二钝化层 94上沉积形成公共电极 66。
所述公共电极 66为一透明导电层， 其包括位于数据线 68上方的一部 分 82及^ i于像素电极 62上的另一部分 84。
所述.数据线 68与公共电极 66之间包括第一、 第二钝化层 92、 94， 而 像素电极 62与公共电极 66之间只有第二钝化层 94， 所述数据线 68与公 共电极 66之间的距离大于像素电极 62与公共电极 66之间的距离， 通过 增加数据线 68与公共电极 66之间的距离来减小寄生电容 C 生的同时， 通 过減小像素电极 62与公共电极 66之间的距离来增大存储电容 Cst， 以减小 馈通电压及漏电对应用该像素结构的 FFS模式液晶显示器的画面品质的影 响。
综上所述， 本发明提供一种像素结构及其制作方法， 通过第二次蚀刻 或两层结构的钝化层来减 d、公共电极与像素电极之间的距离， 以增大像素 结构的存储电容； 同时也增大了数据线与公共电极的距离， 以减小有害寄 生电容， 进而减小馈通电压及漏电对应用该像素结构的 FFS模式液晶显示 器的画面品质的影响， 并且， 该像素结构的制作方法较为筒单。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims

Figure imgf000010_0001
l , 一种像素结构， 包括： 一透明基板、 形成于透明基板上的柵极 线、 形成于透明基板上的薄膜晶体管、 形成于透明基板上的数据线、 形成 于透明基板及薄膜晶体管上的像素电极、 形成于像素电极、 透明基板及数 据线上的钝化层、 以及形成钝化层上的公共电极， 所述钝化层包括： 位于 数据线上的第一部分、 位于像素电极上的第二部分、 以及位于透明基板上 且位于数据线的两侧的第三部分， 所述钝化层第一部分的厚度大于第二部 分的厚度， 所述像素电极与所述公共电极部分重叠以形成存储电容。
2、 如权利要求 1 所述的像素结构， 其中， 所述钝化层第一部分的厚 度大于第三部分的厚度， 所述钝化层第二部分的顶端与第三部分的顶端平 齐； 所述像素结构还包括一形成于薄膜晶体管及像素电极之间的保护层。
3、 如权利要求 所述的像素结构， 其中， 所述薄膜晶体管具有一柵 极 一漏极及一源极， 所述棚极与柵极线电性连接， 所述源极与数据线电 性连接， 所述漏极与像素电极电性连接， 所述像素电极为一透明导电层， 所述公共电极为一透明导电层。
4、 一种像素结构的制作方法， 包括以下步骤：
步骤 提供一透明基板；
步骤 12、 在所述透明基板上沉积形成栅极线、 薄膜晶体管 数据线及 像素电极；
步骤 13。 在所述透明基板、 数据线及像素电极上沉积形成钝化层， 所 述钝化层包括： 位于所述数据线上的第一部分、 位于像素电极上的第二部 分以及位于透明基板上且位于数据线两侧的第三部分；
步骤 14、 对外围线路上的钝化层进行蚀刻， 以完成第一次蚀刻， 之后 对钝化层的第二部分进行蚀刻， 以完成第二次蚀刻， 以减小钝化层第二部 分的厚度， 使得钝化层第一部分的厚度大于第二部分的厚度；
步骤 15、 在所述钝化层上沉积形成公共电极。
5、 如权利要求 4所述的像素结构的制作方法， 其中， 所述步骤 12还 包括在所述透明基板上形成一保护层， 所述 护层形成于所述薄膜晶体管 与所述像素电极之间。
6、 如权利要求 4所述的像素结构的制作方法， 其中， 所述步驟 14中 的第二次蚀刻还包括对钝化层的第三部分进行蚀刻， 第二次蚀刻完成后， 所述钝化层第一部分的厚度大于第三部分的厚度， 所述钝化层第二部分的 顶端与第三部分的顶端平齐。
，、 如权利要求 4 所述的像素结构的制作方法， 其中， 所述像素电极 为一透明导电层， 所述公共电极为一透明导电层。
一种像素结构的制作方法， 包括以下步骤：
Figure imgf000011_0001
步骤 22、 在所述透明基板上沉积形成柵极线、 薄膜晶体管、 数据线及 像素电极；
步骤 23、 在所述透明基板、 数据线及像素电极上沉积形成一第一钝化 层， 对所述第一钝化层进行蚀刻， 仅保留数据线上方的第一钝化层， 其它 部分蚀刻掉；
步骤 24、 在所述透明基板、 像素电极及第一钝化层上沉积形成一第二 钝化层， 对所述第二钝化层进行蚀刻， 将外围线路上的第二钝化层蚀刻 掉， 其它部分保留；
步驟 25、 在所述第二魏化层上沉积形成公共电极。
9 , 如权利要求 8 所述的像素结构的制作方法， 其中， 所述第一钝化 层的厚度大于所述第二钝化层的厚度。
10、 如权利要求 8 所述的像素结构的制作方法， 其中， 所述步骤 22 还包括在透明基板上形成一保护层， 所述保护层形成于所述薄膜晶体管与 所述像素电极之间； 所述像素电极为一透明导电层， 所述公共电极为一透 明导电层。
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