WO2018120431A1 - 像素电路结构及显示面板 - Google Patents

像素电路结构及显示面板 Download PDF

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Publication number
WO2018120431A1
WO2018120431A1 PCT/CN2017/076541 CN2017076541W WO2018120431A1 WO 2018120431 A1 WO2018120431 A1 WO 2018120431A1 CN 2017076541 W CN2017076541 W CN 2017076541W WO 2018120431 A1 WO2018120431 A1 WO 2018120431A1
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Prior art keywords
conductive layer
coupled
storage capacitor
line
voltage
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PCT/CN2017/076541
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English (en)
French (fr)
Inventor
陈猷仁
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US15/744,839 priority Critical patent/US20190012975A1/en
Publication of WO2018120431A1 publication Critical patent/WO2018120431A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • the present disclosure relates to the field of display technologies, and more particularly to a pixel circuit structure and a display panel that can improve the coupling effect.
  • a liquid crystal display is mostly a backlight type liquid crystal display, which is composed of a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel is composed of two transparent substrates and a liquid crystal sealed between the substrates.
  • a data signal is generally supplied through a plurality of pixel electrodes according to image information, and light transmittance of a plurality of pixel units is controlled to display a desired image.
  • each of the pixel electrodes is coupled with a data line and a scan line, and the scan line is coupled to the pixel electrode through a TFT (Thin Film Transistor).
  • the TFT is turned on by the scan line, and the data line charges the pixel electrode.
  • the data line generates a plurality of parasitic capacitances during the charging process, and the plurality of parasitic capacitances cause the voltage of the pixel electrodes to be shared (divided) due to the coupling effect (Crosstalk), resulting in insufficient voltage of the pixel electrodes to cause display color abnormality. And as the resolution gets higher and higher, the coupling effect is more pronounced.
  • the technical problem to be solved by the present disclosure is to provide a pixel circuit structure capable of improving the coupling effect.
  • One of the objectives of the present disclosure is to provide a pixel circuit structure, the pixel circuit structure including:
  • An active switch coupled to the data line and the scan line
  • the second storage capacitor is coupled to the first storage capacitor and coupled to the DC voltage.
  • the number of the second storage capacitors is two or more.
  • one end of the first storage capacitor is coupled to the active switch, and the other end of the first storage capacitor is coupled to a common line.
  • one end of the first storage capacitor is coupled to the active switch, and the other end of the first storage capacitor is coupled to one of the scan lines.
  • the first storage capacitor and the second storage capacitor are formed by a first conductive layer, a second conductive layer, and a third conductive layer, and the first conductive layer is coupled to a drain of the active switch;
  • the second conductive layer is coupled to the first voltage line;
  • the third conductive layer and the second voltage line are coupled;
  • the first conductive layer, the second conductive layer, and the third conductive layer are stacked and spaced apart.
  • the first conductive layer, the second conductive layer and the third conductive layer cover each other in a vertical space.
  • the first voltage line comprises a common line.
  • the second voltage line and the common line are overlapped in a first conductive layer coverage area.
  • the first voltage line comprises a previous scan line.
  • At least one of the first conductive layer, the second conductive layer, and the third conductive layer is made of a transparent conductive material.
  • An active switch coupled to the data line and the scan line
  • the first storage capacitor is coupled to the active switch, wherein one end of the first storage capacitor is coupled to the active switch, and the other end of the first storage capacitor is coupled to a common line or the Scan One of the lines;
  • a second storage capacitor coupled to the first storage capacitor and coupled to the DC voltage
  • the first storage capacitor and the second storage capacitor are formed by a first conductive layer, a second conductive layer, and a third conductive layer, and the first conductive layer is coupled to a drain of the active switch;
  • the first conductive layer, the second conductive layer and the third conductive layer are stacked and spaced apart, the first conductive The layer, the second conductive layer and the third conductive layer cover each other in a vertical space.
  • a display panel of the present disclosure includes an array substrate, wherein the array substrate includes a pixel circuit structure, and the pixel circuit structure includes:
  • An active switch coupled to the data line and the scan line
  • the second storage capacitor is coupled to the first storage capacitor and coupled to the DC voltage.
  • the two storage capacitors simultaneously maintain the pixel voltage level of the pixel structure to reduce the influence of parasitic capacitance, thereby improving the influence of the coupling effect, so that the display panel can be normally displayed.
  • FIG. 1 is a schematic structural view of a pixel structure of the present disclosure
  • FIG. 2 is a schematic structural view of a pixel structure of the present disclosure
  • FIG. 3 is a schematic structural view of a pixel structure of the present disclosure.
  • FIG. 4 is a schematic structural view of a pixel structure of the present disclosure.
  • FIG. 5 is a circuit diagram of a pixel structure of the present disclosure.
  • FIG. 6 is a circuit diagram of a pixel structure of the present disclosure.
  • FIG. 7 is a circuit diagram of a pixel structure of the present disclosure.
  • FIG. 8 is a circuit diagram of a pixel structure of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a pixel structure according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a pixel structure according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a pixel structure according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a pixel structure according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a pixel circuit structure according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram showing the structure of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of a first conductive layer, a second conductive layer, and a third conductive layer in combination with one embodiment of the present disclosure
  • 16 is a schematic diagram of a first conductive layer, a second conductive layer, and a third conductive layer in combination with one embodiment of the present disclosure
  • Figure 17 is an equivalent circuit diagram of a storage capacitor in accordance with one embodiment of the present disclosure.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality of means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection or integral connection; may be mechanical connection or electrical connection; may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two components.
  • the pixel structure is respectively coupled with the current data line Data n and the current scanning line Gate n, the current scanning.
  • the line actively couples the TFT and pixel structure coupling through an active switch (such as, but not limited to, a thin film transistor).
  • the active switching TFT is controlled to be turned on by the current scan line, and the current data line Data n is charged for the pixel structure.
  • the current data line Data n charges the liquid crystal capacitor Clc and the storage capacitor Cst during charging of the pixel structure by the voltage (Vdata) of its charging, and the pixel structure maintains the voltage (Vpixel) of the pixel structure through the storage capacitor Cst to make the display
  • the panel can be displayed normally.
  • the voltage of the current data line Data n for charging the pixel structure will constantly change, so that the voltage of the pixel structure also changes, due to the charging voltage and the pixel of the current data line.
  • the capacitance between the dotted lines is a plurality of parasitic capacitances, and multiple parasitic charges.
  • the capacitance (Cpd-L, Cgd, and Cpd-R) causes the voltage of the pixel structure to be divided due to the coupling effect (Crosstalk), resulting in insufficient voltage of the pixel structure to cause display color abnormality.
  • One is to set the data line away from the pixel structure, thereby reducing the generation of parasitic capacitance, thereby making the influence of the coupling effect smaller, but this increases the planar space of the display panel, and is not easily used in a display panel with higher resolution. .
  • the second is to increase the storage capacitor Cst, which is much larger than the parasitic capacitance (Cpd-L, Cgd, and Cpd-R), which makes the influence of the coupling effect smaller, but it is necessary to increase the size of the conductive layer in the storage capacitor.
  • the planar space of the pixel structure is increased. As the resolution becomes higher and higher, the pixel electrode space becomes smaller and smaller, and the storage capacitor setting is also smaller, so that the storage capacitor is also less likely to be used in the display panel with higher resolution, due to the storage capacitor plane space.
  • the size limit, and thus the effect of improving the coupling effect by increasing the storage capacitance, is also reduced.
  • an embodiment of the present disclosure discloses a pixel structure and a pixel circuit structure.
  • the pixel structure and the pixel circuit structure of the embodiment may be various, and multiple pixel structures may be respectively applied to different displays.
  • the pixel structure of the present disclosure is applied to the following display devices: Twisted Nematic (TN) or Super Twisted Nematic (STN) type, plane conversion (In-Plane Switching) , IPS) type, Vertical Alignment (VA) type, and High Vertical Alignment (HVA) type, curved type panel.
  • TN Twisted Nematic
  • STN Super Twisted Nematic
  • IPS plane conversion
  • VA Vertical Alignment
  • HVA High Vertical Alignment
  • the pixel structure of the embodiment of the present disclosure includes a first conductive layer 11, a second conductive layer 12, and a third conductive layer 13, as shown in FIGS. 15 and 16, the first conductive layer 11 and an active switch (for example, But not limited to the thin film transistor) drain coupling of the TFT, the second conductive layer 12 is coupled to the first voltage line, the third conductive layer 13 and the second voltage line are coupled; the first conductive layer 11 and the second The conductive layer 12 and the third conductive layer 13 are stacked and spaced apart, the first conductive layer 11, the second conductive layer 12 and the third conductive The electrical layer 13 covers each other in vertical space.
  • an active switch for example, But not limited to the thin film transistor
  • the three conductive layers of the pixel structure of the embodiments of the present disclosure can be energized, and the three can form two storage capacitors, and the two storage capacitors simultaneously maintain the pixel voltage of the pixel structure to reduce multiple The effect of parasitic capacitance, thereby improving the effects of the coupling effect, so that the display panel can be displayed normally.
  • the embodiment of the present disclosure maintains the voltage level of the pixel structure by two storage capacitors. Compared with the pixel structure in FIG. 1 to FIG. 8, the voltage level of the pixel structure is maintained by a storage capacitor, and the voltage level of the pixel structure is maintained. The effect is better, making the voltage structure of the pixel structure more stable.
  • the embodiment of the present disclosure directly stacks the first conductive layer, the second conductive layer and the third conductive layer, so that it is not necessary to increase the planar size of each conductive layer, so that the embodiments of the present disclosure do not increase the respective conductive layers. In the case of the plane size, the capacitance of the pixel structure is greatly improved, and the voltage level of the pixel structure is better maintained, so that the present disclosure is more suitable for a display panel with high resolution.
  • more stacked conductive layers may also be formed in the pixel structure to form more storage capacitors (fourth storage capacitor, fifth storage capacitor, etc.) in the pixel structure.
  • FIG. 16 is a specific manner of stacking a first conductive layer, a second conductive layer, and a third conductive layer according to an embodiment of the present disclosure.
  • the first conductive layer 11 is disposed between the second conductive layer 12 and the third conductive layer 13 such that a first storage capacitor 14 is formed between the first conductive layer 11 and the second conductive layer 12.
  • the first storage capacitor 14 is a storage capacitor Cst.
  • the storage capacitor Cst is defined as the first storage capacitor 14.
  • a second storage capacitor 16 is formed between the first conductive layer and the third conductive layer 13, and the second storage capacitor 16 is a storage capacitor Cnew, and the storage capacitor Cnew is defined as the second storage capacitor 16. Therefore, the two storage capacitors (the first storage capacitor 11 and the second storage capacitor 16) jointly maintain the potential of the pixel structure voltage without affecting the voltage of the pixel structure due to the change of the charging voltage of the current data line during charging. In turn, the coupling effect phenomenon is improved.
  • FIG. 16 is only a distribution of a specific conductive layer structure according to an embodiment of the present disclosure, and may also be other structural distributions, for example, as shown in FIG. 15 , FIG. 16 is an implementation of the present disclosure.
  • Another specific way of stacking the first conductive layer, the second conductive layer and the third conductive layer is, in particular, the second conductive layer 12 is disposed on the first conductive layer 11 and the third conductive layer.
  • the same storage capacitor as that of FIG. 16 is formed between the first conductive layer 11 and the second conductive layer 12, that is, the first storage capacitor 14, as shown in FIG. 13 and FIG. 14, the first storage capacitor 14 is the storage capacitor Cst.
  • the storage capacitor Cst is defined herein as the first storage capacitor 14.
  • a third storage capacitor 15 is formed between the second conductive layer 12 and the third conductive layer 13. As shown in FIG. 13 and FIG. 14, the third storage capacitor 15 is also illustrated as a storage capacitor Cnew (however, it should be noted that Since only one new storage capacitor, that is, the second storage capacitor or the third storage capacitor, can be illustrated in FIGS. 13 and 14, Cnew in FIGS. 13 and 14 is merely for explaining the second storage capacitor or the first Three storage capacitors, where the second storage capacitor and the third storage capacitor are not the same one.), when the pixel structure adopts the structure in FIG. 15, the storage capacitor Cnew is defined as the third storage capacitor. 15.
  • the two storage capacitors (the first storage capacitor and the third storage capacitor) together maintain the potential of the pixel structure voltage, and do not affect the voltage of the pixel structure due to the change of the charging voltage of the current data line during charging, and thus Improved coupling effects.
  • this embodiment replaces the second storage capacitor or the third storage capacitor with Cnew.
  • the first conductive layer 11 is coupled to the drain of the active switching TFT, one end of the capacitor Clc is coupled to the common line Vcom, and the capacitor Clc is coupled to the active switching TFT.
  • the thin film transistors are respectively coupled with the current data line Data n and the current scan line Gate n. When the current scan line controls the thin film transistor to be turned on, the current data line charges the pixel structure through the thin film transistor, specifically, the liquid crystal capacitor Clc is charged, and two memories are stored.
  • Capacitors (Cst and Cnew, specifically in FIG. 16, are the first storage capacitor and the second storage capacitor; or specifically in FIG. 15, which are the first storage capacitor and the third storage capacitor).
  • the first voltage line includes a previous scan line Gate n-1, as shown in FIG. 14, that is, the second conductive layer 12 is coupled with the previous scan line, and the charging process of the pixel structure is through the current scan.
  • the line Gate n controls the active switching TFT to be turned on, so that the current data line Data n is charged for the pixel structure, and the previous scan line is in the upper row of the current scan line, and the second conductive layer 12 is precharged by the previous scan line.
  • the second conductive layer 12 has a voltage, which can reduce the charging time when the current data line is charged, and will quickly The second conductive layer 12 reaches a predetermined potential. This is a specific manner in which the second conductive layer is coupled to the first voltage line.
  • the second conductive layer may also be coupled to other first voltage lines, for example, as shown in FIG.
  • the first voltage line includes a common line Vcom, that is, the second conductive layer 12 and the common line Vcom are coupled, and the common line Vcom charges the second conductive layer, which is simple in structure.
  • the third conductive layer 13 and the second voltage line are coupled.
  • the second voltage line Vdc of the embodiment of the present disclosure is coupled to the DC voltage and the second conductive.
  • the voltage of the common line of the layer connection is, for example, 7.5V or 0V; the voltage of the data line is -5 to 15V; the voltage of the scan line is -6 to 35V; due to the third conductive layer and the first conductive connected to the second voltage line.
  • the voltages of the layer and the second conductive layer are all different, so a storage capacitor can be formed between the third conductive layer and the first conductive layer or the second conductive layer.
  • the pixel circuit structure of the present disclosure includes:
  • a scan line Gate defining a pixel area with the data line Data
  • the active switching TFT is coupled to the data line Data and the scan line Gate;
  • the second storage capacitor Cnew is coupled to the first storage capacitor Cst and coupled to the DC voltage Vdc.
  • the pixel circuit structure of the present disclosure may include two or more second storage capacitors Cnew coupled between the first storage capacitor Cst and the DC voltage Vdc. To further improve the impact of the coupling effect.
  • one end of the first storage capacitor Cst is coupled to the active switching TFT, and the other end of the first storage capacitor Cst is coupled to a common line Vcom, as shown in FIG.
  • one end of the first storage capacitor Cst is coupled to the active switching TFT, and the other end of the first storage capacitor Cst is coupled to one of the scan lines Gate (on A scan line Gate n-1) is shown in FIG.
  • the first storage capacitor Cst and the second storage capacitor Cnew are formed by a first conductive layer, a second conductive layer, and a third conductive layer, the first conductive layer and the drain of the active switch Coupling; the second conductive layer and the first voltage line are coupled; the third conductive layer and the second voltage line are coupled; the first conductive layer, the second conductive layer and the third conductive layer are stacked and spaced apart The first conductive layer, the second conductive layer, and the third conductive layer cover each other in a vertical space.
  • the first voltage line comprises a common line Vcom.
  • the second voltage line and the common line Vcom are disposed to overlap within the first conductive layer coverage area.
  • the first voltage line includes a previous scan line Gate n-1.
  • the first conductive layer 11, the second conductive layer 12, and the third conductive layer 13 are respectively made of a conductive metal, which is a first conductive layer and a second conductive layer. And a specific structure of the third conductive layer, the three conductive layers (the first conductive layer 11, the second conductive layer 12 and the third conductive layer 13) are all made of a conductive metal, and the conductive metal has a good conductive effect.
  • the conductive metal of an embodiment of the present disclosure may be: Al, Mo, Cu, Ti, Ag or an alloy thereof.
  • the three conductive layers are all made of conductive metal or other conductive materials, which is a specific manner of the embodiments of the present disclosure.
  • Other embodiments may be employed in the disclosed embodiments:
  • the first conductive layer 11 and the second conductive layer 12 are respectively made of a conductive metal
  • the third conductive layer 13 is made of a transparent conductive material.
  • the first conductive layer 11 and the second conductive layer 12 are both made of conductive metal and are electrically conductive.
  • the metal conductive effect is good;
  • the third conductive layer 13 is made of a transparent conductive material, and the conductive material can also be electrically conductive.
  • ITO, IZO, AZO, ATO, GZO, TCO, ZnO or polyethylene dioxythiophene (PEDOT) polyethylene dioxythiophene
  • the first conductive layer 11 is made of a conductive metal
  • the second conductive layer 12 and the third conductive layer 13 are respectively made of a transparent conductive material.
  • the first conductive layer 11 is made of conductive gold.
  • the conductive metal has good electrical conductivity; the second conductive layer 12 and the third conductive layer 13 are made of a transparent conductive material, and the conductive effect can also be achieved.
  • the second voltage line Vdc and the common line Vcom partially overlap in space, specifically, the second voltage line and the common line are covered by the first conductive layer. Overlap settings in the area. If two or more wires are juxtaposed between each other, parasitic capacitances are generated between each other, and mutual interference occurs. However, in the embodiment of the present disclosure, the common line Vcom and the second voltage line Vdc are partially overlapped in space to prevent parasitic capacitance from being generated. Improve anti-interference ability.
  • the three conductive layers (the first conductive layer 11, the second conductive layer 12, and the third conductive layer 13) of one embodiment of the present disclosure are parallel to each other, so that the space occupied by the three in the plane space is further Small, the effect of applying the pixel structure of the embodiment of the present disclosure to the display panel is better.
  • an embodiment of the present disclosure further discloses an array substrate, wherein the array substrate is provided with a common line, a data line, and a scan line, and the array substrate further includes a pixel structure,
  • the pixel structures are coupled to the data lines and the scan lines, respectively.
  • the common line, the data line, the scan line, and the pixel structure on the array substrate of the embodiment refer to the common line, the data line, the scan line, and the pixel structure in the above embodiment, or the common line on the array substrate in this embodiment.
  • the data lines, the scan lines, and the pixel structure reference may be made to the common lines, the data lines, the scan lines, the pixel structures, and the mutual cooperation and connection relationship in FIG. 9 to FIG.
  • the array substrate of the present embodiment has a plurality of pixel structures. For each pixel structure, reference may be made to FIG. 9 to FIG. 16. The pixel structure, the common lines, the data lines, the scan lines, and the like are not described in detail herein.
  • an embodiment of the present disclosure further discloses a display panel including a color filter substrate and an array substrate, wherein the array substrate is provided with a common line, a data line, and a scan line.
  • the array substrate further includes a pixel structure, and the pixel structure is coupled to the data line and the scan line, respectively.
  • the common line, the data line, the scan line, and the pixel structure in the display panel of the present embodiment refer to the common line, the data line, the scan line, and the pixel structure in the above embodiment, or the common line in the display panel of this embodiment.
  • the array substrate of the example has a plurality of pixel structures.
  • the pixel structure, the common lines, the data lines, the scan lines, and the like are not described in detail herein.
  • an embodiment of the present disclosure further discloses a display device including a display panel and a backlight module, wherein the display panel includes a color film substrate and an array substrate, and the array substrate A common line, a data line and a scan line are disposed on the array substrate, and the array substrate further includes a pixel structure, and the pixel structure is coupled to the data line and the scan line, respectively.
  • the common line, the data line, the scan line, and the pixel structure in the display panel of the present embodiment refer to the common line, the data line, the scan line, and the pixel structure in the above embodiment, or the common line in the display panel of this embodiment.
  • the array substrate of the present embodiment has a plurality of pixel structures. For each pixel structure, reference may be made to FIG. 9 to FIG. 16.
  • the pixel structure, the common lines, the data lines, the scan lines, and the like are not described in detail herein.
  • the display device of the embodiment may be a liquid crystal display or other display device.
  • the backlight module can be used as a light source for supplying sufficient light source with uniform brightness and distribution.
  • the backlight module of this embodiment The group may be of the front light type or the backlight type. It should be noted that the backlight module of the embodiment is not limited thereto.

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Abstract

一种像素电路结构及显示面板，其中，像素电路结构包括数据线；扫描线，与数据线定义出一像素区；主动开关，耦接于数据线及扫描线；液晶电容，耦接于主动开关；第一存储电容（14），耦接于主动开关；以及第二存储电容（16），耦接于第一存储电容（14）。

Description

像素电路结构及显示面板 【技术领域】
本公开涉及显示技术领域，更具体的说，涉及一种可改善改善耦合效应的像素电路结构及显示面板。
【背景技术】
近年来，随着科技的进步，许多不同的显示设备，例如液晶显示器(Liquid Crystal Display，LCD)或电激发光(Electro Luminenscence，EL)显示设备已广泛地应用于平面显示器。以液晶显示器为例，液晶显示器大部分为背光型液晶显示器，其是由液晶显示面板及背光模块(backlight module)所组成。液晶显示面板是由两片透明基板以及被封于基板之间的液晶所构成。
现有的液晶显示器，通常是根据图像信息通过多个像素(pixel)电极分别提供数据信号，并且控制多个像素单元的透光率来显示所需图像。具体的是，每一个像素电极都分别耦合有数据线和扫描线，扫描线通过TFT(Thin Film Transistor，薄膜晶体管)和像素电极耦合。通过扫描线控制TFT打开，数据线为像素电极充电。但是，数据线在充电过程中产生多个寄生电容，多个寄生电容会因为耦合效应(Crosstalk)使像素电极的电压被share(分压)，导致像素电极的电压不足进而造成显示产色异常。而且随着分辨率越来越高，耦合效应更加明显。
【发明内容】
本公开所要解决的技术问题是提供一种能够改善耦合效应的像素电路结构。本公开的目的之一是提供一种像素电路结构，所述像素电路结构包括:
数据线；
扫描线，与所述数据线定义出一像素区；
主动开关，耦接于所述数据线及扫描线；
液晶电容，耦接于所述主动开关；
第一存储电容，耦接于所述主动开关；以及
第二存储电容，耦接于所述第一存储电容，且耦接于一直流电压。
在一些实施例中，所述第二存储电容的数量为二个或二个以上。
在一些实施例中，所述第一存储电容的一端是耦接于所述主动开关，所述第一存储电容的另一端是耦接于一共通线。
在一些实施例中，所述第一存储电容的一端是耦接于所述主动开关，所述第一存储电容的另一端是耦接于所述扫描线的其中之一。
在一些实施例中，所述第一存储电容及第二存储电容是由第一导电层、第二导电层及第三导电层所形成，所述第一导电层和主动开关的漏极耦合；所述第二导电层和第一电压线耦合；所述第三导电层和第二电压线耦合；述第一导电层、第二导电层和第三导电层三者叠放且间隔设置，所述第一导电层、第二导电层和第三导电层三者在垂直空间上相互覆盖。
在一些实施例中，所述第一电压线包括共通线。
在一些实施例中，所述第二电压线和共通线在第一导电层覆盖区域内重叠设置。
在一些实施例中，所述第一电压线包括上一扫描线。
在一些实施例中，所述第一导电层、第二导电层及第三导电层的其中至少一者是采用透明导电材料制成。
本公开的又一目的是提供一种像素电路结构，所述像素电路结构包括：
数据线；
扫描线，与所述数据线定义出一像素区；
主动开关，耦接于所述数据线及扫描线；
液晶电容，耦接于所述主动开关；
第一存储电容，耦接于所述主动开关，其中所述第一存储电容的一端是耦接于所述主动开关，所述第一存储电容的另一端是耦接于一共通线或所述扫描 线的其中之一；以及
第二存储电容，耦接于所述第一存储电容，且耦接于一直流电压；
其中，所述第一存储电容及第二存储电容是由第一导电层、第二导电层及第三导电层所形成，所述第一导电层和主动开关的漏极耦合；所述第二导电层和第一电压线耦合；所述第三导电层和第二电压线耦合；述第一导电层、第二导电层和第三导电层三者叠放且间隔设置，所述第一导电层、第二导电层和第三导电层三者在垂直空间上相互覆盖。
本公开的一种显示面板包括阵列基板，其中所述阵列基板包括像素电路结构，所述像素电路结构包括：
数据线；
扫描线，与所述数据线定义出一像素区；
主动开关，耦接于所述数据线及扫描线；
液晶电容，耦接于所述主动开关；
第一存储电容，耦接于所述主动开关；以及
第二存储电容，耦接于所述第一存储电容，且耦接于一直流电压。
两个存储电容同时保持像素结构的像素电压大小，以减小寄生电容的影响，从而改善耦合效应的影响，以使得显示面板能够正常显示。
【附图说明】
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本公开一种像素结构的结构示意图；
图2是本公开一种像素结构的结构示意图；
图3是本公开一种像素结构的结构示意图；
图4是本公开一种像素结构的结构示意图；
图5是本公开一种像素结构的电路示意图；
图6是本公开一种像素结构的电路示意图；
图7是本公开一种像素结构的电路示意图；
图8是本公开一种像素结构的电路示意图；
图9是本公开一个实施例像素结构的结构示意图；
图10是本公开一个实施例像素结构的结构示意图；
图11是本公开一个实施例像素结构的结构示意图；
图12是本公开一个实施例像素结构的结构示意图；
图13是本公开一个实施例像素电路结构的示意图；
图14是本公开一个实施例像素电路结构的示意图；
图15是本公开一个实施例第一导电层、第二导电层和第三导电层三者配合的示意图；
图16是本公开一个实施例第一导电层、第二导电层和第三导电层三者配合的示意图；
图17是本公开一个实施例存储电容的等效电路图。
【具体实施方式】
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本公开的示例性实施例的目的。但是本公开可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本公开的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或组件必须具有特定的方位、以特定的方位构造和操作， 因此不能理解为对本公开的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本公开的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个组件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
由于单个充电时间内的充电时间较短，为了保持像素结构的电压Vpixel，如图1至图8所示，具体的，像素结构分别耦合有当前数据线Data n和当前扫描线Gate n，当前扫描线通过主动开关(例如，但不限于薄膜晶体管)主动开关TFT和像素结构耦合。通过当前扫描线控制主动开关TFT打开，当前数据线Data n为像素结构充电。当前数据线Data n通过其充电的电压(Vdata)在为像素结构充电过程中为液晶电容Clc和存储电容Cst充电，像素结构通过存储电容Cst来保持像素结构的电压(Vpixel)大小，以使得显示面板能够正常显示。
但是，在显示面板显示过程中，会显示不同灰阶，当前数据线Data n为像素结构充电的电压会不断变化，从而使得像素结构的电压也随之变化，由于当前数据线的充电电压和像素结构存在多个寄生电容(Cpd-L、Cgd和Cpd-R)，如图7和8中的虚线部分，虚线部分之间的电容为多个寄生电容，多个寄生电 容(Cpd-L、Cgd和Cpd-R)会因为耦合效应(Crosstalk)使像素结构的电压被分压，导致像素结构的电压不足进而造成显示产色异常。
为减少多个寄生电容的影响，改善耦合效应的影响，申请人进一步采用以下两种方法：
其一是将数据线设置远离像素结构，从而减小寄生电容的产生，进而使得耦合效应的影响变小，但是这样就增加了显示面板的平面空间，不易用于分辨率较高的显示面板中。
其二是加大存储电容Cst，使其远大于寄生电容(Cpd-L、Cgd和Cpd-R)，进而使得耦合效应的影响变小，但是这样就需要加大了存储电容中导电层的大小，进而就增加了像素结构的平面空间。随着分辨率越来越高，像素电极空间越来越小，也会将存储电容设置变小，从而加大存储电容也不易用于分辨率较高的显示面板中，由于受到存储电容平面空间大小的限制，从而通过加大存储电容来改善耦合效应的效果也因此而降低。
为此，申请人又设计了另外的技术方案，以解决以上技术问题，具体如下：
下面结合附图9至16和较佳的实施例对本公开作进一步详细说明。
如图9至16所示，本公开一实施例公开了一种像素结构及像素电路结构，本实施例的像素结构及像素电路结构可以为多种，多种像素结构可以分别应用于不同的显示装置中，比如，将本公开的像素结构应用到以下几种显示装置中：扭曲向列(Twisted Nematic，TN)或超扭曲向列(Super Twisted Nematic，STN)型，平面转换(In-Plane Switching，IPS)型、垂直配向(Vertical Alignment，VA)型、及高垂直配向(High Vertical Alignment，HVA)型、曲面型面板。
其中，本公开实施例的像素结构包括有第一导电层11、第二导电层12和第三导电层13，如图15和16所示，所述第一导电层11和主动开关(例如，但不限于薄膜晶体管)TFT的漏极耦合，所述第二导电层12和第一电压线耦合，所述第三导电层13和第二电压线耦合；所述第一导电层11、第二导电层12和第三导电层13三者叠放且间隔设置，所述第一导电层11、第二导电层12和第三导 电层13三者在垂直空间上相互覆盖。
相比现有技术，本公开实施例的像素结构的三个导电层都可以通电，三者就可以形成两个存储电容，两个存储电容同时保持像素结构的像素电压大小，以减小多个寄生电容的影响，从而改善耦合效应的影响，以使得显示面板能够正常显示。
另外，本公开实施例通过两个存储电容来保持像素结构的电压大小，相比图1至图8中的像素结构，通过一个存储电容来保持像素结构的电压大小，对像素结构的电压大小保持效果更好，使得像素结构的电压大小更加稳定。同时，本公开实施例直接将第一导电层、第二导电层和第三导电层三者叠放设置，就不必增加各个导电层的平面大小，这样本公开实施例在不增大各个导电层平面大小的情况下就大大提高了像素结构的电容，更好的保持了像素结构的电压大小，从而本公开更加适用于分辨率高的显示面板中。
在一些实施例中，亦可在像素结构中形成更多堆栈的导电层，以形成更多的存储电容(第四存储电容、第五存储电容等)于像素结构中。
在本公开一本实施例中，如图16所示，图16为本公开一实施例第一导电、第二导电层和第三导电层三者叠放的一种具体方式，具体的是，第一导电层11设置在第二导电层12和第三导电层13之间，这样第一导电层11和第二导电层12之间形成第一存储电容14。结合图13和图14所示，第一存储电容14为存储电容Cst，当像素结构采用图16中的结构时，在此将存储电容Cst定义为第一存储电容14。第一导电层和第三导电层13之间形成第二存储电容16，第二存储电容16为存储电容Cnew，在此将存储电容Cnew定义为第二存储电容16。从而两个存储电容(第一存储电容11、第二存储电容16)共同保持像素结构电压的电位，而不会因为当前数据线在充电过程中的充电电压的变化而影响到像素结构的电压，进而就改善了耦合效应现象。
然而，需要说明的是，图16为仅为本公开一实施例的一种具体导电层结构的分布，也可以为其他结构分布，比如：如图15所示，图16为本公开一实施 例第一导电、第二导电层和第三导电层三者叠放的另一种具体方式，具体的是，所述第二导电层12设置在所述第一导电层11和第三导电层13之间。这样第一导电层11和第二导电层12之间形成与图16相同的存储电容，即第一存储电容14，同样结合图13和图14所示，第一存储电容14为存储电容Cst，在此将存储电容Cst定义为第一存储电容14。第二导电层12和第三导电层13之间形成一个第三存储电容15，同样结合图13和图14所示中，第三存储电容15也示意为存储电容Cnew(然而，需要说明的是，由于在图13及图14中仅能够示意出一个新的存储电容，即第二存储电容或第三存储电容，因此，图13和图14中的Cnew仅仅是为了说明第二存储电容或第三存储电容，在此，第二存储电容和第三存储电容并不是同一个。)，在此当像素结构采用图15中的结构时，此时就将将存储电容Cnew定义为第三存储电容15。这样两个存储电容(第一存储电容、第三存储电容)共同保持像素结构电压的电位，而不会因为当前数据线在充电过程中的充电电压的变化而影响到像素结构的电压，进而就改善了耦合效应现象。
在以下叙述中，本实施例将第二存储电容或第三存储电容用Cnew代替。
如图13和图14所示，第一导电层11和主动开关TFT的漏极耦合，电容Clc一端和共通线Vcom耦合，电容Clc和主动开关TFT耦合。薄膜晶体管分别和当前数据线Data n耦合、当前扫描线Gate n耦合，当前扫描线控制薄膜晶体管打开时，当前数据线通过薄膜晶体管为像素结构充电，具体是为液晶电容Clc充电、以及两个存储电容(Cst和Cnew，具体在图16中，即是第一存储电容和第二存储电容；或者具体在图15中，即是第一存储电容和第三存储电容)。
进一步的，所述第一电压线包括上一扫描线Gate n-1，如图14所示，也就是说第二导电层12和上一扫描线耦合，像素结构的充电过程是，通过当前扫描线Gate n控制主动开关TFT导通，使得当前数据线Data n为像素结构充电，而上一扫描线是在当前扫描线的上一行，通过上一扫描线预先为第二导电层12充电，使第二导电层12具有电压，在当前数据线充电时可减少充电时间，快速将 第二导电层12达到预定的电位。这是第二导电层与第一电压线耦合的一种具体方式，当然，需要说明的是，第二导电层也可以耦合到其他的第一电压线，比如：如图13所示，所述第一电压线包括共通线Vcom，也就是说第二导电层12和共通线Vcom耦合，所述共通线Vcom为第二导电层充电，这种方式结构简单。
在本公开一实施例中，第三导电层13和第二电压线耦合，如图9至图14所示，本公开一实施例的第二电压线Vdc耦合到一直流电压，与第二导电层连接的共通线的电压范围例如7.5V或0V；数据线的电压为-5～15V；扫描线的电压为-6～35V；由于与第二电压线连接的第三导电层和第一导电层和、第二导电层的电压均不相同，所以第三导电层与第一导电层或第二导电层之间就可以形成存储电容。
在本公开实施例中，如图13及图14所示，本公开的像素电路结构包括:
数据线Data；
扫描线Gate，与所述数据线Data定义出一像素区；
主动开关TFT，耦接于所述数据线Data及扫描线Gate；
液晶电容Clc，耦接于所述主动开关TFT；
第一存储电容Cst，耦接于所述主动开关TFT；以及
第二存储电容Cnew，耦接于所述第一存储电容Cst，且耦接于一直流电压Vdc。
如图17所示，在一些实施例中，本公开的像素电路结构可包括二个或二个以上的第二存储电容Cnew，耦接于所述第一存储电容Cst及直流电压Vdc之间，以进一步改善耦合效应的影响。
在一些实施例中，所述第一存储电容Cst的一端是耦接于所述主动开关TFT，所述第一存储电容Cst的另一端是耦接于一共通线Vcom，如图13所示。
在一些实施例中，所述第一存储电容Cst的一端是耦接于所述主动开关TFT，所述第一存储电容Cst的另一端是耦接于所述扫描线Gate的其中之一(上一扫描线Gate n-1)，如图14所示。
在一些实施例中，所述第一存储电容Cst及第二存储电容Cnew是由第一导电层、第二导电层及第三导电层所形成，所述第一导电层和主动开关的漏极耦合；所述第二导电层和第一电压线耦合；所述第三导电层和第二电压线耦合；述第一导电层、第二导电层和第三导电层三者叠放且间隔设置，所述第一导电层、第二导电层和第三导电层三者在垂直空间上相互覆盖。
在一些实施例中，所述第一电压线包括共通线Vcom。
在一些实施例中，所述第二电压线和共通线Vcom在第一导电层覆盖区域内重叠设置。
在一些实施例中，所述第一电压线包括上一扫描线Gate n-1。
在本公开一实施例中，其中，所述第一导电层11、第二导电层12及第三导电层13分别采用导电金属制成，这是本公开设置第一导电层、第二导电层及第三导电层的一种具体结构，三个导电层(第一导电层11、第二导电层12及第三导电层13)都采用导电金属制成，导电金属导电效果好。其中，本公开一实施例的导电金属可以是：Al、Mo、Cu,Ti、Ag或其合金。
需要说明的是，三个导电层(第一导电层11、第二导电层12及第三导电层13)都采用导电金属或其他导电材料制成是本公开实施例的一种具体方式，本公开实施例还可以采用其他方式：
例如1：所述第一导电层11和第二导电层12分别采用导电金属制成，所述第三导电层13采用透明导电材料制成。这是本公开实施例设置第一导电层11、第二导电层12及第三导电层13的另一种具体结构，第一导电层11和第二导电层12都采用导电金属制成，导电金属导电效果好；第三导电层13采用透明导电材料制成同样可以实现导电的效果，透明导电材料例如：ITO、IZO、AZO、ATO、GZO、TCO、ZnO或聚乙撑二氧噻吩(PEDOT)。
例如2：所述第一导电层11采用导电金属制成，所述第二导电层12和第三导电层13分别采用透明导电材料制成。这是本公开实施例设置第一导电层11、第二导电层12及第三导电层13的又一种具体结构，第一导电层11采用导电金 属制成，导电金属导电效果好；第二导电层12和第三导电层13采用透明导电材料制成同样可以实现导电的效果。
在本公开一实施例中，如图9至图12所示，所述第二电压线Vdc和共通线Vcom在空间上部分重叠，具体的是第二电压线和共通线在第一导电层覆盖区域内重叠设置。若两个或多个导线之间并列设置，相互之间也会产生寄生电容，相互产生干扰，而本公开实施例共通线Vcom和第二电压线Vdc在空间上部分重叠就可以防止产生寄生电容，提高抗干扰能力。
更进一步的，本公开一实施例的三个导电层(第一导电层11、第二导电层12、第三导电层13)相互平行，从而就使得三者在平面空间上所占用的空间更小，使得本公开实施例的像素结构应用到显示面板中的效果更佳。
在本公开的另一个实施例中，本公开实施例还公开了一种阵列基板，所述阵列基板上设置有共通线、数据线和扫描线，所述阵列基板还包括有像素结构，所述像素结构分别与所述数据线、扫描线耦合。其中，本实施例阵列基板上的共通线、数据线、扫描线、像素结构可以参见以上实施例中的共通线、数据线、扫描线、像素结构，或者说本实施例阵列基板上的共通线、数据线、扫描线、像素结构可以参见图9至图16中的共通线、数据线、扫描线、像素结构，以及相互的配合、连接关系。本实施例的阵列基板上具有多个像素结构，每个像素结构可参见图9至图16，在此不再对像素结构、共通线、数据线、扫描线等进行一一详述。
在本公开的又一个实施例中，本公开实施例还公开了一种显示面板，所述显示面板包括彩膜基板和阵列基板，所述阵列基板上设置有共通线、数据线和扫描线，所述阵列基板还包括有像素结构，所述像素结构分别与所述数据线、扫描线耦合。其中，本实施例显示面板中的共通线、数据线、扫描线、像素结构可以参见以上实施例中的共通线、数据线、扫描线、像素结构，或者说本实施例显示面板中的共通线、数据线、扫描线、像素结构可以参见图9至图16中的共通线、数据线、扫描线、像素结构，以及相互的配合、连接关系。本实施 例的阵列基板上具有多个像素结构，每个像素结构可参见图9至图16，在此不再对像素结构、共通线、数据线、扫描线等进行一一详述。
在本公开的再一个实施例中，本公开实施例还公开了一种显示装置，显示装置包括显示面板和背光模组，其中，所述显示面板包括彩膜基板和阵列基板，所述阵列基板上设置有共通线、数据线和扫描线，所述阵列基板还包括有像素结构，所述像素结构分别与所述数据线、扫描线耦合。其中，本实施例显示面板中的共通线、数据线、扫描线、像素结构可以参见以上实施例中的共通线、数据线、扫描线、像素结构，或者说本实施例显示面板中的共通线、数据线、扫描线、像素结构可以参见图9至图16中的共通线、数据线、扫描线、像素结构，以及相互的配合、连接关系。本实施例的阵列基板上具有多个像素结构，每个像素结构可参见图9至图16，在此不再对像素结构、共通线、数据线、扫描线等进行一一详述。其中，本实施例的显示装置可以为液晶显示器或其他显示装置，当显示装置为液晶显示器时，背光模组可作为光源，用于供应充足的亮度与分布均匀的光源，本实施例的背光模组可以为前光式，也可以为背光式，需要说明的是，本实施例的背光模组并不限于此。
以上内容是结合具体的优选实施方式对本公开所作的进一步详细说明，不能认定本公开的具体实施只局限于这些说明。对于本公开所属技术领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本公开的保护范围。

Claims (19)

  1. 一种像素电路结构，包括：
    数据线；
    扫描线，与所述数据线定义出一像素区；
    主动开关，耦接于所述数据线及扫描线；
    液晶电容，耦接于所述主动开关；
    第一存储电容，耦接于所述主动开关；以及
    第二存储电容，耦接于所述第一存储电容，且耦接于一直流电压。
  2. 如权利要求1所述的像素电路结构，其中所述第一存储电容的一端是耦接于所述主动开关，所述第一存储电容的另一端是耦接于一共通线。
  3. 如权利要求1所述的像素电路结构，其中所述第一存储电容的一端是耦接于所述主动开关，所述第一存储电容的另一端是耦接于所述扫描线的其中之一。
  4. 如权利要求1所述的像素电路结构，其中所述第一存储电容及第二存储电容是由第一导电层、第二导电层及第三导电层所形成，所述第一导电层和主动开关的漏极耦合；所述第二导电层和第一电压线耦合；所述第三导电层和第二电压线耦合；述第一导电层、第二导电层和第三导电层三者叠放且间隔设置，所述第一导电层、第二导电层和第三导电层三者在垂直空间上相互覆盖。
  5. 如权利要求4所述的像素电路结构，其中所述第一电压线包括共通线。
  6. 如权利要求4所述的像素电路结构，其中所述第二电压线和共通线在第一导电层覆盖区域内重叠设置。
  7. 如权利要求4所述的像素电路结构，其中所述第一电压线包括上一扫描线。
  8. 如权利要求4所述的像素电路结构，其中所述第一导电层、第二导电层及第三导电层的其中至少一者是采用透明导电材料制成。
  9. 如权利要求1所述的像素电路结构，其中所述第二存储电容的数量为二个或二个以上。
  10. 一种像素电路结构，包括：
    数据线；
    扫描线，与所述数据线定义出一像素区；
    主动开关，耦接于所述数据线及扫描线；
    液晶电容，耦接于所述主动开关；
    第一存储电容，耦接于所述主动开关，其中所述第一存储电容的一端是耦接于所述主动开关，所述第一存储电容的另一端是耦接于一共通线或所述扫描线的其中之一；以及
    第二存储电容，耦接于所述第一存储电容，且耦接于一直流电压；
    其中，所述第一存储电容及第二存储电容是由第一导电层、第二导电层及第三导电层所形成，所述第一导电层和主动开关的漏极耦合；所述第二导电层和第一电压线耦合；所述第三导电层和第二电压线耦合；述第一导电层、第二导电层和第三导电层三者叠放且间隔设置，所述第一导电层、第二导电层和第三导电层三者在垂直空间上相互覆盖；
    其中，所述第二存储电容的数量为二个或二个以上。
  11. 一种显示面板，包括阵列基板，其中所述阵列基板包括像素电路结构，所述像素电路结构包括：
    数据线；
    扫描线，与所述数据线定义出一像素区；
    主动开关，耦接于所述数据线及扫描线；
    液晶电容，耦接于所述主动开关；
    第一存储电容，耦接于所述主动开关；以及
    第二存储电容，耦接于所述第一存储电容，且耦接于一直流电压。
  12. 如权利要求11所述的显示面板，其中所述第一存储电容的一端是耦接 于所述主动开关，所述第一存储电容的另一端是耦接于一共通线。
  13. 如权利要求11所述的显示面板，其中所述第一存储电容的一端是耦接于所述主动开关，所述第一存储电容的另一端是耦接于所述扫描线的其中之一。
  14. 如权利要求11所述的显示面板，其中所述第一存储电容及第二存储电容是由第一导电层、第二导电层及第三导电层所形成，所述第一导电层和主动开关的漏极耦合；所述第二导电层和第一电压线耦合；所述第三导电层和第二电压线耦合；述第一导电层、第二导电层和第三导电层三者叠放且间隔设置，所述第一导电层、第二导电层和第三导电层三者在垂直空间上相互覆盖。
  15. 如权利要求14所述的显示面板，其中所述第一电压线包括共通线。
  16. 如权利要求14所述的显示面板，其中所述第二电压线和共通线在第一导电层覆盖区域内重叠设置。
  17. 如权利要求14所述的显示面板，其中所述第一电压线包括上一扫描线。
  18. 如权利要求14所述的显示面板，其中所述第一导电层、第二导电层及第三导电层的其中至少一者是采用透明导电材料制成。
  19. 如权利要求11所述的显示面板，其中所述第二存储电容的数量为二个或二个以上。
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