WO2015032149A1 - 阵列基板及其制备方法与显示装置 - Google Patents

阵列基板及其制备方法与显示装置 Download PDF

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Publication number
WO2015032149A1
WO2015032149A1 PCT/CN2013/089316 CN2013089316W WO2015032149A1 WO 2015032149 A1 WO2015032149 A1 WO 2015032149A1 CN 2013089316 W CN2013089316 W CN 2013089316W WO 2015032149 A1 WO2015032149 A1 WO 2015032149A1
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Prior art keywords
layer
source
array substrate
drain
via hole
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Ceased
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PCT/CN2013/089316
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English (en)
French (fr)
Inventor
李付强
王学路
李成
安星俊
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US14/361,577 priority Critical patent/US9647001B2/en
Publication of WO2015032149A1 publication Critical patent/WO2015032149A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes

Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device. Background technique
  • TFT Thin Film Transistor
  • LTPS Low Temperature Poly-silicon
  • Embodiments of the present invention provide an array substrate, a preparation method thereof, and a display device.
  • an array substrate comprising a substrate substrate, a metal shield layer sequentially formed on the substrate substrate, a semiconductor layer, a gate insulating layer, a gate metal layer, and an interlayer dielectric a layer, a source/drain metal layer, and a pixel electrode layer; wherein, the interlayer dielectric layer and the gate insulating layer are formed with at least one first via hole penetrating to the metal shield layer; and the source/drain metal layer is formed In the at least one first via and on the interlayer dielectric layer having the at least one first via.
  • the source/drain metal layer covers an inner wall of the at least one first via and is electrically connected to the metal shield.
  • the at least one first via has a cross-sectional shape of any one or more of a circle, a square, a triangle, and a trapezoid.
  • the array substrate further includes:
  • a buffer layer is formed between the metal shield layer and the semiconductor layer, and the at least one first via hole is formed in the interlayer dielectric layer, the gate insulating layer, and the buffer layer.
  • the source/drain metal layer includes a pattern of source, drain, and data lines.
  • source vias and drain vias for respectively electrically connecting the semiconductor layer to the source and drain are formed in the interlayer dielectric layer and the gate insulating layer.
  • the array substrate further includes:
  • the second via and the third via that are respectively connected to the source/drain metal layer are respectively formed in the flat layer and the passivation layer;
  • the pixel electrode layer is formed in the third via hole and on the passivation layer having the third via hole.
  • the semiconductor layer is a polysilicon layer.
  • the gate metal layer includes a pattern of gates, gate lines, and common electrode lines.
  • a display device comprising the above array substrate.
  • a method for fabricating an array substrate comprising: sequentially forming a metal shielding layer, a semiconductor layer, a gate insulating layer, a gate metal layer, and an interlayer dielectric layer on a substrate of the substrate;
  • a source/drain metal layer is formed in the first via hole and on the interlayer dielectric layer having the first via hole.
  • the method of fabricating further includes forming a pixel electrode layer over the source and drain metal layers.
  • the semiconductor layer is a polysilicon layer; after forming the metal shield layer, And before forming the semiconductor layer, the method further includes:
  • a buffer layer is formed on the metal shield layer, wherein the first via hole is formed in the interlayer dielectric layer, the gate insulating layer, and the buffer layer.
  • the source/drain metal layer includes a pattern of a source, a drain, and a data line; after forming the interlayer dielectric layer, and before forming the source/drain metal layer, the method further includes : source vias and drain vias for electrically connecting the semiconductor layer to the source and the drain, respectively, are formed in the interlayer dielectric layer and the gate insulating layer.
  • the method further includes:
  • Forming a pixel electrode layer over the source/drain metal layer includes:
  • the pixel electrode layer is formed in the third via hole and on the passivation layer having the third via hole.
  • the pixel electrode layer on the source/drain metal layer is electrically connected to the metal shielding layer by providing a via hole directly in the interlayer dielectric layer.
  • the common electrode line in the gate metal layer can form a storage capacitor with the source/drain metal layer, and can form a storage capacitor with the metal shield layer, thereby increasing the storage capacitor provided with the array substrate and improving the array substrate.
  • the pixel voltage retention ratio and the effect of reducing the occurrence of defects such as flicker of the display device improve the quality of the array substrate and the display device.
  • FIG. 1 is a schematic cross-sectional structural view of an array substrate according to Embodiment 1 of the present invention
  • FIG. 2(a) is a schematic plan view showing a planar structure of the metal shielding layer according to Embodiment 1 of the present invention
  • 2(b) is a plan view showing the planar structure of the semiconductor layer according to the first embodiment of the present invention
  • FIG. 2(c) is a schematic plan view showing the planar structure of the gate metal layer according to the first embodiment of the present invention
  • d) is a schematic plan view of the first via hole according to the first embodiment of the present invention
  • FIG. 2(a) is a schematic plan view showing a planar structure of the metal shielding layer according to Embodiment 1 of the present invention
  • 2(b) is a plan view showing the planar structure of the semiconductor layer according to the first embodiment of the present invention
  • FIG. 2(c) is a schematic plan view showing the planar structure of the gate metal layer according to the first embodiment of the present invention
  • FIG. 2(e) is a schematic plan view showing the planar structure of the source/drain metal layer according to the first embodiment of the present invention
  • f) is a schematic plan view showing the planar structure of the flat layer via hole in the first embodiment of the present invention
  • FIG. 2(g) is a plan view showing the planar structure of the common electrode layer in the first embodiment of the present invention
  • FIG. 2(i) is a schematic plan view showing the planar structure of the pixel electrode layer according to the first embodiment of the present invention
  • FIG. FIG. 4 is a cross-sectional structural view of the array substrate according to the second embodiment of the present invention
  • FIG. 4 is a second embodiment of the present invention
  • the cross-sectional structure of the array substrate is shown in FIG. detailed description
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 1 it is a cross-sectional structural diagram of an array substrate according to the first embodiment of the present invention.
  • the array substrate includes: a substrate substrate 11 and a metal shielding layer 12 sequentially formed on the substrate substrate 11 .
  • At least one first via 151 penetrating to the metal shield layer 12 is formed in the interlayer dielectric layer 15 and the gate insulating layer 14; the source/drain metal layer 16 is formed in the first via 151
  • the inside for example, the inner wall of the via hole and the bottom portion are electrically connected to the metal shield layer 12
  • the interlayer dielectric layer 15 having the first via hole 151 is formed in the interlayer dielectric layer 15 and the gate insulating layer 14; the source/drain metal layer 16 is formed in the first via 151
  • the inside for example, the inner wall of the via hole and the bottom portion are electrically connected to the metal shield layer 12
  • the gate metal layer may include a pattern of a gate line, a gate, and a common electrode line.
  • the source/drain metal layer 16 may include a pattern of a source, a drain, and a data line, which are not described in detail in the embodiments of the present invention.
  • the semiconductor layer 13 may be a polysilicon layer or a non-polysilicon layer; for example, in the implementation of the present invention In the example, the semiconductor layer 13 may be a polysilicon layer.
  • the array substrate may further include: a buffer layer 18 formed between the metal shield layer 12 and the semiconductor layer 13, wherein the first via hole 151 is formed in the interlayer dielectric layer 15 and the gate
  • the first via 151 may sequentially penetrate the interlayer dielectric layer 15, the gate insulating layer 14, and the buffer layer 18, for convenience of description, in the three layers.
  • the via holes are collectively referred to as a first via 151.
  • the array substrate may generally further include: a flat layer 19, a common electrode layer (not shown in Fig. 1), and a passivation layer 20 which are sequentially formed between the source/drain metal layer 16 and the pixel electrode layer 17.
  • the second via 191 and the third via 201 respectively penetrating to the source/drain metal layer 16 are respectively formed on the flat layer 19 and the passivation layer 20; the pixel electrode layer 17 is formed on The third via 201 is inside the passivation layer 20 having the third via 201.
  • the third via 201 and the second via 191 correspond to each other, and the third via 201 is formed at the second via.
  • the passivation layer 20 in the 191, that is, the horizontal projection area of the third via 201 on the substrate substrate 11 and the horizontal projection area of the second via 191 on the substrate 11 The third via 201 is generally smaller than the second via 191, as shown in FIG. 1 .
  • the pixel electrode layer 17 is generally electrically connected to the source/drain metal layer 16 through the third via 201, and due to the presence of the first via 151
  • the source/drain metal layer 16 can be electrically connected to the metal shield layer 12, and therefore, in the embodiment of the present invention, the pixel electrode layer 17 can be electrically connected to the metal shield layer 12, thereby causing the gate
  • the common electrode line in the metal layer can form a storage capacitor with the source/drain metal layer 16 and a storage capacitor with the metal shield layer 12, thereby increasing the storage capacitance of the array substrate and increasing the pixel voltage of the array substrate.
  • the rate and the effect of reducing the occurrence of defects such as flicker of the display device improve the quality of the array substrate and the display device.
  • each layer in each plan view of FIG. 2( a ) to FIG. 2 ( i ) is a transparent or translucent pattern.
  • FIG. 2( a ) it is a planar structure of the metal shielding layer 12 in the embodiment of the present invention.
  • the metal shield layer 12 is formed on the substrate substrate 11 and is mainly used for shielding the TFT channel to reduce the influence of the backlight on the TFT.
  • the metal shield layer 12 may be an aluminum layer.
  • the tungsten layer, the chrome layer or other metal, or the conductive layer of the metal compound, etc., are not limited in this embodiment of the present invention.
  • a buffer layer 18 is formed on the metal shielding layer 12, and the buffer layer 18 can be used to prevent substances in the substrate substrate 11 from diffusing to various layers on the substrate of the village substrate in a subsequent process (such as high-temperature crystallization).
  • a subsequent process such as high-temperature crystallization
  • the quality of the array substrate or the LTPS TFT to be fabricated is affected; of course, in some structures, such as the base substrate is an alkali-free glass or other specially processed substrate, the buffer layer may not be provided.
  • the first via hole only needs to penetrate through the interlayer dielectric layer 15 and the gate insulating layer 14 to penetrate the metal shield layer 12.
  • the buffer layer 18 may be a double-layer insulating layer structure composed of a silicon nitride film layer and a silicon oxide film layer, or may be a single-layer insulating layer structure such as a silicon nitride film layer or a silicon oxide film layer. This example does not limit this. Further, since the buffer layer 18 can generally cover the entire substrate substrate 11, the planar structure of the buffer layer 18 is not specifically illustrated in the embodiment of the present invention.
  • the semiconductor layer 13 may be formed on the buffer layer 18, and the semiconductor layer 13 is in the
  • the horizontal projection area of the substrate substrate 11 and the metal shield layer 12 may overlap at a plurality of locations in the horizontal projection area of the substrate substrate 11, for example, the TFT gates in the semiconductor layer 13 are on the substrate substrate 11.
  • the horizontal projection area may overlap with the metal shield layer 12 at a horizontal projection area of the substrate substrate 11.
  • a gate insulating layer 14 is formed on the semiconductor layer 13.
  • the gate insulating layer 14 may be a silicon oxide layer, a silicon nitride layer, or a composite insulating layer composed of a silicon oxide layer and a silicon nitride layer.
  • the embodiment of the invention does not limit this. Further, since the gate insulating layer 14 can generally cover the entire substrate substrate 11, via holes are formed only in some regions such as the peripheral wiring regions, similar to the prior art, and thus, in the embodiment of the present invention The planar structure of the gate insulating layer 14 is not specifically illustrated.
  • FIG. 2(c) it is a schematic diagram of a planar structure of the gate metal layer in the embodiment of the present invention (the gate metal layer is identified by reference numeral 21 in FIG. 2(c)), and the gate metal layer is formed on
  • the gate insulating layer 14 may be composed of two parts, a part of which is a gate and a gate line (Gate, reference numeral 211). A part is a common electrode line (Gate Metal Vcom, reference numeral 212); in Fig. 2 (c), there are three overlapping areas ⁇ , B, C in the horizontal projection area on the grid substrate 11, wherein the A and B areas are gates The location of the pole.
  • the pattern of the gate, the gate line and the common electrode line of the gate metal layer may be simultaneously formed by one patterning process, and the material used for the gate metal layer For example, it may be aluminum, tungsten, chromium or other metal and metal compound, etc., which is not limited in the embodiment of the present invention.
  • the common electrode line may be formed with the semiconductor layer 13 or the pixel electrode layer 17. Storage capacitors for the purpose of increasing the storage capacitance of the array substrate.
  • An interlayer dielectric layer 15 is formed on the gate metal layer to serve as a pattern for protecting the gate metal layer and to isolate the gate metal layer 21 and the subsequently formed source/drain metal layer 16;
  • the interlayer dielectric layer 15 may generally cover the entire substrate substrate 11, or may only form a pattern separating the gate metal layer 21 and the subsequently formed source/drain metal layer 16, similar to the prior art, and thus, the implementation of the present invention In the example, the planar structure of the interlayer dielectric layer 15 is not specifically illustrated.
  • At least one first via 151 penetrating to the metal shield layer 12 may be formed in the interlayer dielectric layer 15 , the gate insulating layer 14 , and the buffer layer 18 .
  • the cross-sectional shape of a via 151 may be, for example, one or more of a circular, a square, a triangular, a trapezoidal or other polygonal structure, which is not limited in the embodiment of the present invention.
  • the size of the first via hole 151 is adjustable, and the embodiment of the present invention does not limit this in order to achieve the purpose of adapting to different process conditions, improving flexibility and practicability of process preparation.
  • the cross-sectional shape of the first via 151 is square, and the horizontal projection area of the first via 151 on the substrate substrate 11 and the semiconductor layer 13 The horizontal projection areas of the gate metal layer 21 on the substrate substrate 11 are not overlapped.
  • interlayer dielectric layer 15 and the gate insulating layer 14 may also be formed with source vias and drains for electrically connecting the semiconductor layer 13 and the source and drain of the TFT, respectively.
  • a very large via (identified by the reference numeral 152), which is not described in detail in the embodiment of the present invention.
  • FIG. 2(e) it is a schematic diagram of a planar structure of the source/drain metal layer 16 in the embodiment of the present invention.
  • the source/drain metal layer 16 is formed on the interlayer dielectric layer 15, which may include Two parts, one is a metal layer in a strip structure, which may be generally referred to as a data line (Data); a metal layer having a square structure, which may be generally referred to as a source drain plate (SD Pad), wherein the source and drain are Flat plate in the base of the village
  • a horizontal projection area on the board 11 overlaps with a horizontal projection area of the first via 151 on the substrate substrate 11, that is, the first via 151 is generally formed between layers under the source drain plate
  • the dielectric layer 15, the gate insulating layer 14, and the buffer layer 18 are provided. It should be noted that the drawings of the embodiments of the present invention are only for the purpose of illustrating the embodiments, and the shapes, sizes, and positional relationships are not limited to the embodiments of the present invention.
  • a flat layer 19 is formed on the source/drain metal layer 16, and the flat layer 19 serves to protect the source/drain metal layer 16 and planarize the surface of the array substrate; for example, the planar layer 19 It may be an insulating layer formed of an inorganic material or an insulating layer formed of an organic material, which is not limited in the embodiment of the present invention.
  • the flat layer 19 is generally made of an organic resin material, and the organic resin may be benzocyclobutene (BCB) or other organic photosensitive material, which is not limited in the embodiment of the present invention. . Since the organic resin has a smaller hardness than the inorganic material, it is more advantageous to play a flat role on the surface of the array substrate, facilitating the formation of the subsequent common electrode layer and the pixel electrode layer 17, and the like, and the liquid crystal between the color filter substrate and the array substrate. The ideal arrangement of molecules.
  • BCB benzocyclobutene
  • a flat layer via 191 penetrating through the source/drain metal layer 16 may be formed in the flat layer 19.
  • the planar structure of the formed planar via 191 can be as shown in Fig. 2(f).
  • the cross-sectional shape of the flat layer via 191 may be, for example, one or more of a circular, square, triangular, trapezoidal or other polygonal structure, which is not limited in the embodiment of the present invention; in FIG. 2 (f)
  • the flat layer via 191 is, for example, a square structure.
  • a common electrode layer is formed on the flat layer 19.
  • the planar structure of the common electrode layer can be as shown in FIG. 2(g) (in FIG. 2(g), the common electrode layer is identified by reference numeral 22)
  • the common electrode layer may be formed by a single patterning process, and the material of the common electrode layer may be a transparent conductive film material such as ITO or ruthenium, which is not limited in the embodiment of the present invention.
  • a passivation layer 20 may be formed on the common electrode layer, and a passivation layer penetrating to the source/drain metal layer 17 corresponding to the flat layer via 191 may be formed in the passivation layer 20 .
  • Via 201 (third via); the planar structure of the passivation layer via 201 formed may be as shown in Fig. 2(h).
  • the size of the passivation layer via 201 is generally smaller than the flat layer via 191.
  • the cross-sectional shape of the passivation layer via 201 may also be circular, square, triangular, or trapezoidal. Or one or more of the other polygonal structures, the embodiment of the present invention does not limit this; in FIG. 2 (h), the passivation layer via 201 is, for example, a square structure.
  • the passivation layer 20 may be an insulating layer formed of an inorganic material or an insulating layer formed of an organic material, which is not limited in the embodiment of the present invention.
  • FIG. 2(i) it is a schematic diagram of a planar structure of the pixel electrode layer 17 in the embodiment of the present invention.
  • the pixel electrode layer 17 may be formed in the third via 201 and provided with the third
  • the passivation layer 20 of the via 201 is electrically connected to the metal shield layer 12 through the source/drain metal layer 16 located in the first via 151 such that the common electrode line in the gate metal layer can be sandwiched
  • a storage capacitor can be formed with the source/drain metal layer 16 and a storage capacitor can be formed with the metal shield layer 12, thereby realizing
  • the purpose of increasing the storage capacitance of the array substrate, increasing the pixel voltage retention ratio of the array substrate, and reducing the occurrence of flicker in the display device improves the quality of the array substrate and the display device.
  • each layer in FIG. 2( a ) to FIG. 2 ( i ) is only a schematic illustration of an embodiment of the present invention, and may be adjusted according to actual conditions. No restrictions are imposed.
  • Embodiment 1 of the present invention further provides a display device including the above array substrate.
  • the display device may be, for example, a liquid crystal display panel, an electronic paper, an OLED (Organic Light-Emitting Diode) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, or the like.
  • the functional product or component is not limited in this embodiment of the present invention.
  • the display device described in the embodiment of the present invention may be TN (Twisted).
  • the display device described in the embodiment of the present invention is particularly suitable for the IPS mode and the ADS mode.
  • the first embodiment of the present invention provides an array substrate and a display device, wherein a pixel electrode located on the source/drain metal layer is disposed by providing a via hole directly to the metal shielding layer in the interlayer dielectric layer and the gate insulating layer.
  • the layer may be electrically connected to the metal shielding layer, so that a common electrode line in the gate metal layer may be sandwiched between the source/drain metal layer and the metal shielding layer to form a metal layer with the source and drain layers.
  • the storage capacitor can also form a storage capacitor with the metal shielding layer, thereby increasing the storage capacitance of the array substrate, increasing the pixel voltage retention ratio of the array substrate, and reducing
  • the purpose of the display device such as flickering is improved, and the quality of the array substrate and the display device is improved.
  • the second embodiment of the present invention provides a method for preparing the array substrate according to the first embodiment of the present invention.
  • the preparation of the array substrate according to the second embodiment of the present invention is described below with reference to FIGS. 2( a ) to 2 ( i ).
  • the method is to be described.
  • the method for preparing the array substrate may include the following steps:
  • Step 101 Form a metal shield layer 12 on the substrate 11; for example, the pattern of the metal shield layer 12 can be as shown in Fig. 2(a).
  • the substrate of the substrate 11 may be a glass substrate or a plastic substrate, and the present invention is not limited thereto.
  • the substrate substrate 11 Before the metal shield layer 12 is formed on the substrate substrate 11, the substrate substrate 11 may be pre-cleaned. Thereafter, a metal shield layer 12 is formed over the substrate substrate 11, and the metal shield layer 12 is formed. It is mainly used to shield the TFT channel to reduce the influence of the backlight on the TFT.
  • the metal shielding layer 12 may be, for example, an aluminum layer, a tungsten layer, a chrome layer or other metal, or a metal compound conductive layer or the like, which is not limited in the embodiment of the present invention.
  • forming the metal shield layer 12 over the substrate substrate 11 may include:
  • metal shield layer 12 Forming a metal layer on the substrate 11 by deposition, sputtering, or the like, and forming a pattern by a patterning process including photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • the metal shield layer 12 is not described in detail in the embodiment of the present invention.
  • Step 102 Form a buffer layer 18 on the metal shield layer 12.
  • a buffer layer 18 may be deposited on the metal shield layer 12 by a method such as CVD (Chemical Vapor Deposition); the buffer layer 18 may be, for example, a silicon nitride film layer and The double-layered insulating layer structure of the silicon oxide film layer may be a single-layer insulating layer structure such as a silicon nitride film layer or a silicon oxide film layer, which is not limited in the embodiment of the present invention.
  • the buffer layer may not be provided. In this case, step 102 may be omitted.
  • Step 103 forming a semiconductor layer 13 on the buffer layer 18; the pattern of the semiconductor layer 13 can be as shown in Fig. 2(b).
  • an amorphous silicon layer may be deposited on the buffer layer 18 by CVD or the like, and an excimer laser annealing (ELA) or a solid phase may be used.
  • ELA excimer laser annealing
  • Crystallization (SPC) or the like crystallizes the amorphous silicon into polycrystalline silicon, and then forms a desired polysilicon pattern by a patterning process including photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • Step 104 Forming a gate insulating layer 14 on the semiconductor layer 13.
  • the gate insulating layer 14 may be deposited on the semiconductor layer 13 by a method such as CVD; wherein the gate insulating layer 14 may be a silicon oxide layer, a silicon nitride layer or a silicon oxide layer and a silicon nitride layer.
  • the composite insulating layer or the like is not limited in this embodiment of the present invention.
  • Step 105 forming a gate metal layer 21 on the gate insulating layer 14; the pattern of the gate metal layer 21 may be as shown in FIG. 2(c), including a gate, a gate line, and a common electrode line, wherein 211 corresponds to a gate and a gate, and reference numeral 212 corresponds to a common electrode line (Gate Metal Vcom).
  • a metal layer may be formed on the gate insulating layer 14 by a method such as PVD (Physical Vapor Deposition), and may include coating, exposing, developing, etching, and the like.
  • PVD Physical Vapor Deposition
  • a patterning process of a process such as photoresist stripping simultaneously forms patterns of gate lines, gate lines, and common electrode lines.
  • the metal layer may be an aluminum layer, a tungsten layer, a chromium layer or other metal and metal compound conductive layer, and the like, which is not limited in the embodiment of the present invention.
  • Step 106 Form an interlayer dielectric layer 15 on the gate metal layer 21.
  • An interlayer dielectric layer 15 may be deposited on the gate metal layer 21 by a method such as CVD to protect the gate metal layer 21 and isolate the gate metal layer 21 and the subsequent source/drain metal layer 16;
  • the interlayer dielectric layer 15 may be made of a material such as silicon oxide or silicon nitride, which is not limited in the embodiment of the present invention.
  • Step 107 forming at least one first via 151 penetrating into the metal shield layer 12 in the interlayer dielectric layer 15, the gate insulating layer 14, and the buffer layer 18; the first via 151 formed
  • the pattern can be as shown in Figure 2 (d).
  • a source via hole and a drain penetrating to the semiconductor layer 13 may be formed in the interlayer dielectric layer 15 and the gate insulating layer 14.
  • a very via (wherein the source via or drain via can be seen in Figure 2(d), specifically identified by reference numeral 152).
  • the first via 151, the source via, and the drain via may be formed by one or more patterning processes, which is not limited by the embodiment of the present invention; When the process forms the above-mentioned via holes, the formation of different depth via holes can be realized by the control of the etching parameters.
  • a conductive material is usually deposited on the surface of the interlayer dielectric layer 15 having the source via, the drain via, and the first via 151, and is coated, exposed, and developed by including photoresist. a patterning process of etching, photoresist stripping, etc. to form a source/drain metal layer 16 having a pattern; wherein the conductive material may be aluminum, tungsten, chromium or other metals and metal compounds, etc., This example does not limit this.
  • the source/drain metal layer 16 may specifically include two parts, a metal layer in a strip structure, which may be generally referred to as a data line, and a metal layer in a square structure, usually It may be referred to as a source drain plate, wherein a horizontal projection area of the source drain plate on the substrate substrate 11 overlaps with a horizontal projection area of the first via hole 161 on the substrate substrate 11, that is,
  • the first via 161 is typically formed in the interlayer dielectric layer 16, the gate insulating layer 14, and the buffer layer 18 under the source and drain plates.
  • Step 109 Forming a flat layer 19 on the source/drain metal layer 16.
  • the planarization layer 19 may be deposited on the source/drain metal layer 16 by a method such as CVD; wherein the planarization layer 19 may be an insulating layer formed of an inorganic material or an insulating layer formed of an organic material, and the embodiment of the present invention does not do any limited.
  • Step 110 forming a planar layer via 191 (second via) directly in the planar layer 19 to the source/drain metal layer 16; the pattern of the formed planar via 191 may be as shown in FIG. 2(f) Show.
  • planar layer via 191 having a set shape can be formed by a patterning process including photoresist coating, exposure, development, etching, photoresist stripping, and the like. 191;
  • the cross-sectional shape of the flat layer via 191 may be one or more of a circular, square, triangular, trapezoidal or other polygonal structure, which is not limited in this embodiment; FIG. 2(f)
  • the flat layer via 191 has a square structure.
  • Step 111 forming a common electrode layer 22 on the flat layer 19; a pattern of the formed common electrode layer 22 may be as shown in Fig. 2(g).
  • a transparent conductive film layer may be deposited on the flat layer 19 by CVD or the like, and formed by a patterning process including photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • a common electrode layer 22 having a pattern is provided.
  • the common electrode layer 22 may be made of a transparent conductive film material, and the transparent conductive film material may be ITO, ruthenium or the like, which is not limited in the embodiment of the present invention.
  • Step 112 forming a passivation layer 20 on the common electrode layer 22, and a via 201 (third via) in the passivation layer 20; the pattern of the passivation layer via 201 formed may be as shown in FIG. 2 ( h ).
  • a passivation layer 20 may be deposited over the common electrode layer 22 by a method such as CVD, and patterned by a patterning process including photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • a passivation layer via 201 having a set shape is formed in the layer 20.
  • the size of the passivation layer via 201 is generally smaller than that of the flat layer via.
  • the cross-sectional shape of the passivation layer via 201 may be one or more of a circular, square, triangular, trapezoidal or other polygonal structure, which is not limited in the embodiment of the present invention; In 2 ( h ), the passivation layer via 201 has a square structure.
  • the passivation layer 20 may be an insulating layer formed of an inorganic material or an insulating layer formed of an organic material, which is not limited in the embodiment of the present invention.
  • Step 113 forming a pixel electrode layer 17 on the passivation layer 20; forming the pixel electrode layer
  • the pattern of 17 can be as shown in Figure 2 (i).
  • the conductive material layer is subjected to a patterning process including a photoresist coating, exposure, development, etching, photoresist stripping, etc. to obtain a pixel electrode layer 17 having a pattern.
  • the obtained pixel electrode layer 17 is generally located in the passivation layer via 201 and over the passivation layer 20, and passes through the source/drain metal layer located in the first via 151.
  • the array substrate according to the first embodiment of the present invention can be obtained.
  • the cross-sectional structure of the obtained array substrate can be as shown in FIG. 1 and FIG. 3 to FIG. 1 corresponds to AA in Fig. 2(i), cross section, Fig. 3 corresponds to BB in 2(i), cross section, Fig. 4 corresponds to CC cross section in Fig. 2(i), and Fig. 5 corresponds to 2 ( DD in i), cross section.
  • a via hole penetrating into the metal shield layer is formed in the interlayer dielectric layer, the gate insulating layer, and the buffer layer, so that the pixel electrode is formed.
  • the layer may be electrically connected to the metal shielding layer through the source/drain metal layer, so that the common electrode line can form a storage capacitor with the source/drain metal layer, and can form a storage capacitor with the metal shielding layer, thereby The effect of increasing the storage capacitance of the array substrate, increasing the pixel voltage retention ratio of the array substrate, and reducing the flicker of the display device, and improving the product port of the array substrate and the display device
  • the embodiment of the present invention is described by taking a top-gate TFT in which a semiconductor layer is a polysilicon layer as an example.
  • the TFTs in which the semiconductor layer is an amorphous silicon layer or the like are equally applicable to the TFTs of the bottom gate type. Or other structurally deformed TFTs, as long as it is required to increase the storage capacitance by increasing the facing area, also belong to the protection range of the embodiment of the present invention.

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Abstract

一种阵列基板包括衬底基板（11）、依次形成在衬底基板（11）上的金属屏蔽层（12）、半导体层（13）、栅极绝缘层（14）、栅金属层、层间介电层（15）、源漏金属层（16）以及像素电极层（17），其中，层间介电层（15）和栅极绝缘层（14）内形成有至少一个贯通至金属屏蔽层（12）的第一过孔（151）；源漏金属层（16）形成在第一过孔（151）内以及具备第一过孔（151）的层间介电层（15）上。还提供一种阵列基板的制备方法和包括该阵列基板的显示装置。

Description

阵列基板及其制备方法与显示装置 技术领域
本发明实施例涉及显示技术领域， 尤其涉及一种阵列基板及其制备方法 与显示装置。 背景技术
随着 TFT ( Thin Film Transistor,薄膜晶体管 )液晶显示技术的不断发展， 具备功耗低、 分辨率高、反应速度快以及开口率高等特点的基于 LTPS ( Low Temperature Poly-silicon, 低温多晶硅 )技术的 TFT显示装置逐渐成为主流， 已被广泛应用于各种电子设备， 如液晶电视、 智能手机、 平板电脑以及数码 相机等数字电子设备中。
但是， 在基于 LTPS技术的 TFT显示装置等高分辨率产品中， 随着产品 分辨率以及开口率的越来越高， 会导致 LTPS TFT显示装置的阵列基板的像 素间距（pixel pitch )越来越小， 进而导致阵列基板的存储电容越来越小。 由 于对于 LTPS TFT阵列基板来说， 在同样大小漏电流情况下， 存储电容越小 会导致像素电压的保持率越低， 进而会导致闪烁 （Flicker )等不良现象的产 生， 极大地降低了阵列基板或 TFT显示装置等高分辨率产品的品质， 因此， 如何在不影响阵列基板开口率的同时提高其存储电容， 已成为业界亟需解决 的问题。 发明内容
本发明实施例提供了一种阵列基板及其制备方法与显示装置。
根据本发明的第一方面， 提供了一种阵列基板， 包括村底基板、 依次形 成在所述村底基板上的金属屏蔽层、 半导体层、 栅极绝缘层、 栅金属层、 层 间介电层、 源漏金属层以及像素电极层； 其中， 所述层间介电层和栅极绝缘 层内形成有至少一个贯通至所述金属屏蔽层的第一过孔； 所述源漏金属层形 成在所述至少一个第一过孔内以及具备所述至少一个第一过孔的层间介电层 上。 在一个示例中， 所述源漏金属层覆盖于至少一个第一过孔的内壁并且与 所述金属屏蔽层电连接。
在一个示例中， 所述至少一个第一过孔的截面形状为圓形、 方形、 三角 形以及梯形中的任意一种或多种。
在一个示例中， 所述阵列基板还包括：
形成在所述金属屏蔽层和所述半导体层之间的緩沖层， 所述至少一个第 一过孔形成在所述层间介电层、 栅极绝缘层以及緩沖层内。
在一个示例中， 所述源漏金属层包括源极、 漏极和数据线的图案。
在一个示例中， 所述层间介电层以及栅极绝缘层内还形成有分别用于将 所述半导体层与源极和漏极电连接的源极过孔以及漏极过孔。
在一个示例中， 所述阵列基板还包括：
依次形成在所述源漏金属层与所述像素电极层之间的平坦层、 公共电极 层以及钝化层；
其中， 所述平坦层以及钝化层内分别形成有相互对应的、 贯通至所述源 漏金属层的第二过孔、 第三过孔；
所述像素电极层形成在所述第三过孔内以及具备所述第三过孔的钝化层 上。
在一个示例中， 所述半导体层为多晶硅层。
在一个示例中， 所述栅金属层包括栅极、 栅线和公共电极线的图案。 根据本发明的第二方面， 还提供了一种显示装置， 包括上述阵列基板。 根据本发明的第三方面， 还提供了一种阵列基板的制备方法， 包括： 在村底基板上依次形成金属屏蔽层、半导体层、栅极绝缘层、栅金属层、 层间介电层；
在所述层间介电层和栅极绝缘层内形成至少一个贯通至所述金属屏蔽层 的第一过孔；
在所述第一过孔内以及具备所述第一过孔的层间介电层上形成源漏金属 层。
在一个示例中， 所述制备方法还包括在所述源漏金属层上方形成像素电 极层。
在一个示例中，所述半导体层为多晶硅层；在形成所述金属屏蔽层之后， 且在形成所述半导体层之前， 所述方法还包括：
在所述金属屏蔽层上形成緩沖层， 其中， 所述第一过孔形成在所述层间 介电层、 栅极绝缘层以及緩沖层内。
在一个示例中， 所述源漏金属层包括源极、 漏极和数据线的图案； 在形 成所述层间介电层之后， 且在形成所述源漏金属层之前， 所述方法还包括： 在所述层间介电层以及栅极绝缘层内形成分别用于将所述半导体层与源 极和漏极电连接的源极过孔以及漏极过孔。
在一个示例中， 在所述第一过孔内以及具备所述第一过孔的层间介电层 上形成源漏金属层之后， 且在所述源漏金属层上方形成像素电极层之前， 所 述方法还包括：
依次在所述源漏金属层上形成平坦层、 公共电极层以及钝化层； 漏金属层的第二过孔、 第三过孔；
在所述源漏金属层上方形成像素电极层， 包括：
在所述第三过孔内以及具备所述第三过孔的钝化层上形成所述像素电极 层。
在本发明实施例所述技术方案中， 通过在所述层间介电层内设置直达金 属屏蔽层的过孔， 使得位于源漏金属层上的像素电极层可与所述金属屏蔽层 电相连， 进而使得栅金属层中的公共电极线既能与所述源漏金属层形成存储 电容， 又能与所述金属屏蔽层形成存储电容， 从而起到了增加具备阵列基板 的存储电容、 提高阵列基板的像素电压保持率以及降低显示装置的闪烁等不 良现象的效果， 提高了阵列基板及显示装置的品质。 附图说明
为了更清楚地说明本发明实施例中的技术方案， 下面将对实施例描述中 所需要使用的附图作筒要介绍， 显而易见地， 下面描述中的附图仅仅是本发 明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动性的 前提下， 还可以根据这些附图获得其他的附图。
图 1所示为本发明实施例一中所述阵列基板的横截面结构示意图； 图 2 ( a )所示为本发明实施例一中所述金属屏蔽层的平面结构示意图； 图 2 ( b )所示为本发明实施例一中所述半导体层的平面结构示意图； 图 2 ( c )所示为本发明实施例一中所述栅金属层的平面结构示意图； 图 2 ( d )所示为本发明实施例一中所述第一过孔的平面结构示意图； 图 2 ( e )所示为本发明实施例一中所述源漏金属层的平面结构示意图； 图 2 ( f )所示为本发明实施例一中所述平坦层过孔的平面结构示意图； 图 2 ( g )所示为本发明实施例一中所述公共电极层的平面结构示意图； 图 2 ( h )所示为本发明实施例一中所述钝化层过孔的平面结构示意图； 图 2 ( i )所示为本发明实施例一中所述像素电极层的平面结构示意图； 图 3所示为本发明实施例二中所述阵列基板的横截面结构示意图一； 图 4所示为本发明实施例二中所述阵列基板的横截面结构示意图二； 图 5所示为本发明实施例二中所述阵列基板的横截面结构示意图三。 具体实施方式
为了使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本 发明作进一步地详细描述， 显然， 所描述的实施例仅仅是本发明一部分实施 例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在 没有做出创造性劳动前提下所获得的所有其它实施例， 都属于本发明保护的 范围。
实施例一：
如图 1所示，其为本发明实施例一中所述阵列基板的横截面结构示意图， 所述阵列基板包括： 村底基板 11、 依次形成在所述村底基板 11上的金属屏 蔽层 12、 半导体层 13、 栅极绝缘层 14、 栅金属层（图 1中未示出）、 层间介 电层 15、 源漏金属层 16以及像素电极层 17, 其中：
所述层间介电层 15以及栅极绝缘层 14内形成有至少一个贯通至所述金 属屏蔽层 12的第一过孔 151 ; 所述源漏金属层 16形成在所述第一过孔 151 内（例如过孔的内壁上并且底部与金属屏蔽层 12电连接 )以及具备所述第一 过孔 151的层间介电层 15上。
所述栅金属层通常可包括栅线、 栅极和公共电极线的图案， 所述源漏金 属层 16通常可包括源极、漏极和数据线的图案，本发明实施例对此不作赘述。
所述半导体层 13可为多晶硅层或非多晶硅层；例如，在本发明所述实施 例中， 所述半导体层 13通常可为多晶硅层。
所述阵列基板还可以包括： 形成在所述金属屏蔽层 12和所述半导体层 13之间的緩沖层 18, 其中， 所述第一过孔 151形成在所述层间介电层 15、 栅极绝缘层 14以及緩沖层 18内， 即所述第一过孔 151可依次贯穿层间介电 层 15、 栅极绝缘层 14以及緩沖层 18三层， 为方便描述， 这三层中的该过孔 统一称为第一过孔 151。
所述阵列基板通常还可以包括:依次形成在所述源漏金属层 16与所述像 素电极层 17之间的平坦层 19、公共电极层（图 1中未示出）以及钝化层 20。
其中， 所述平坦层 19以及钝化层 20上分别形成有相互对应的、 贯通至 所述源漏金属层 16的第二过孔 191、第三过孔 201;所述像素电极层 17形成 在所述第三过孔 201内以及具备所述第三过孔 201的钝化层 20上。
需要说明的是， 在本发明所述实施例中， 所述第三过孔 201与所述第二 过孔 191相互对应是指， 所述第三过孔 201形成在位于所述第二过孔 191内 的钝化层 20上， 即所述第三过孔 201在所述村底基板 11上的水平投影区域 与所述第二过孔 191在所述村底基板 11上的水平投影区域存在重叠；相应地， 所述第三过孔 201通常比所述第二过孔 191尺寸要小， 具体可如图 1所示。
也就是说，在本发明所述实施例中，所述像素电极层 17通常可通过所述 第三过孔 201与所述源漏金属层 16电相连，并且，由于第一过孔 151的存在， 所述源漏金属层 16可与所述金属屏蔽层 12电相连， 因此， 在本发明所述实 施例中， 所述像素电极层 17可与所述金属屏蔽层 12电相连， 从而使得栅金 属层中的公共电极线既能与所述源漏金属层 16形成存储电容，又能与所述金 属屏蔽层 12形成存储电容，起到了增加阵列基板的存储电容、提高阵列基板 的像素电压保持率以及降低显示装置的闪烁等不良现象的效果， 提高了阵列 基板及显示装置的品质。
下面结合图 2 ( a ) ~图 2 ( i )对适用于双栅 LTPS TFT中的所述阵列基 板的结构进行详细说明， 需要说明的是， 本发明实施例所述阵列基板还可适 用于单栅 LTPS TFT中， 本发明实施例对此不作任何限定。 另外需要说明的 是， 为了示意清楚， 图 2 ( a ) ~图 2 ( i )各平面图中的各层结构均是透明或 半透明的样式示意。
如图 2 ( a )所示， 其为本发明实施例中所述金属屏蔽层 12的平面结构 示意图， 所述金属屏蔽层 12形成在所述村底基板 11上， 主要用于对 TFT沟 道进行遮挡， 以减小背光源对 TFT的影响； 例如， 所述金属屏蔽层 12可以 为铝层、 钨层、 铬层或其他金属， 或者金属化合物导电层等， 本发明实施例 对此不作任何限定。
所述金属屏蔽层 12上形成有緩沖层 18,所述緩沖层 18可用于防止村底 基板 11内的物质在后续工艺中（如高温晶化过程中 )扩散到村底基板上的各 层结构中而影响所制作的阵列基板或 LTPS TFT的品质； 当然， 在有些结构 中， 如村底基板为无碱玻璃或者其他经过特殊加工后的基板时， 可以不设置 緩沖层， 此时， 所述第一过孔仅需贯穿层间介电层 15和栅极绝缘层 14即可 以贯通至金属屏蔽层 12。
所述緩沖层 18 例如可以为氮化硅薄膜层和氧化硅薄膜层所组成的双层 绝缘层结构， 也可以为氮化硅薄膜层或氧化硅薄膜层等单层绝缘层结构， 本 发明实施例对此不作任何限定。再有， 由于所述緩沖层 18通常可以覆盖整个 村底基板 11 , 因此， 在本发明所述实施例中， 未对所述緩沖层 18的平面结 构进行具体示意说明。
如图 2 ( b )所示， 其为本发明实施例中所述半导体层 13的平面结构示 意图，所述半导体层 13可形成在所述緩沖层 18上，且所述半导体层 13在所 述村底基板 11的水平投影区域与所述金属屏蔽层 12在所述村底基板 11的水 平投影区域可存在多处重叠， 例如， 半导体层 13中的 TFT栅极在所述村底 基板 11的水平投影区域可与所述金属屏蔽层 12在所述村底基板 11的水平投 影区域存在重叠。
所述半导体层 13上形成有栅极绝缘层 14,所述栅极绝缘层 14可为氧化 硅层、 氮化硅层或由氧化硅层和氮化硅层所组成的复合绝缘层等， 本发明实 施例对此不作任何限定。再有， 由于所述栅极绝缘层 14通常可以覆盖整个村 底基板 11 ,只在有些区域如周边走线区形成有过孔，与现有技术类似， 因此， 在本发明所述实施例中，未对所述栅极绝缘层 14的平面结构进行具体示意说 明。
如图 2 ( c )所示， 其为本发明实施例中所述栅金属层的平面结构示意图 (图 2 ( c )中以标号 21标识所述栅金属层）， 所述栅金属层形成在所述栅极 绝缘层 14上， 可由两部分组成， 一部分为栅极和栅线（Gate, 标号 211 ), 一部分为公共电极线（Gate Metal Vcom, 标号 212 ); 在图 2 ( c ) 中， 栅金 基板 11上的水平投影区域存在三处交叠区域八、 B、 C, 其中 A和 B区域为 栅极所在的位置。
需要说明的是， 在本发明所述实施例中， 可通过一次构图工艺来同时形 成所述栅金属层的栅极、 栅线和公共电极线的图案， 且所述栅金属层所采用 的材料例如可以为铝、 钨、 铬或其他金属及金属化合物等， 本发明实施例对 此不作任何限定； 另外需要说明的是， 所述公共电极线可与所述半导体层 13 或像素电极层 17形成存储电容， 以达到增大阵列基板存储电容的目的。
所述栅金属层上形成有层间介电层 15, 以起到保护栅金属层形成的图 案、 并隔离所述栅金属层 21和后续形成的源漏金属层 16的目的； 由于所述 层间介电层 15通常可以覆盖整个村底基板 11 , 或者仅形成隔离所述栅金属 层 21和后续形成的源漏金属层 16的图案， 与现有技术类似， 因此， 在本发 明所述实施例中， 未对所述层间介电层 15的平面结构进行具体示意说明。
如图 2 ( d )所示， 所述层间介电层 15、 栅极绝缘层 14 以及緩沖层 18 内可形成至少一个贯通至所述金属屏蔽层 12的第一过孔 151 ,所述第一过孔 151 的截面形状例如可以为圓形、 方形、 三角形、 梯形或其他多边形结构中 的一种或多种， 本发明实施例对此不作任何限定。 再有， 所述第一过孔 151 的大小可调， 本发明实施例对此也不作任何限定， 以便达到适应不同的工艺 条件、 提高工艺制备的灵活性和实用性的目的。
例如在图 2 ( d )中， 所述第一过孔 151的截面形状为方形， 且所述第一 过孔 151在所述村底基板 11上的水平投影区域与所述半导体层 13、 所述栅 金属层 21在所述村底基板 11上的水平投影区域均未重叠。
另外需要说明的是， 所述层间介电层 15以及栅极绝缘层 14内还可形成 有分别用于将所述半导体层 13与 TFT源极和漏极电连接的源极过孔以及漏 极过孔（可用标号 152来标识）， 本发明实施例对此不作赘述。
如图 2 ( e )所示， 其为本发明实施例中所述源漏金属层 16的平面结构 示意图，所述源漏金属层 16形成在所述层间介电层 15上，其可包括两部分， 一为呈条形结构的金属层， 通常可称为数据线（Data ); —为呈方形结构的金 属层， 通常可称为源漏平板（SD Pad ), 其中， 所述源漏平板在所述村底基 板 11上的水平投影区域与所述第一过孔 151在所述村底基板 11上的水平投 影区域重叠， 即所述第一过孔 151通常形成在位于所述源漏平板下的层间介 电层 15、 栅极绝缘层 14以及緩沖层 18内。 需要说明的是， 本发明实施例的 附图只是为了说明实施例， 其形状、 大小和位置关系并不是对本发明实施例 的限定。
所述源漏金属层 16上形成有平坦层 19,所述平坦层 19可起到保护所述 源漏金属层 16 以及对所述阵列基板的表面进行平坦化的目的； 所述平坦层 19例如可以是无机材料形成的绝缘层或有机材料形成的绝缘层，本发明实施 例对此不作任何限定。
较佳地，所述平坦层 19通常可由有机树脂材料制作而成，所述有机树脂 可以是苯并环丁烯（BCB ), 也可以是其他有机感光材料， 本发明实施例对 此不作任何限定。 由于有机树脂相比较无机材料硬度较小， 因而更有利于对 阵列基板表面起到平坦作用，有利于后续公共电极层和像素电极层 17等的形 成， 以及彩膜基板和阵列基板之间的液晶分子的理想排列。
所述平坦层 19内可形成有贯穿至所述源漏金属层 16的平坦层过孔 191
(第二过孔）； 所形成的平坦层过孔 191 的平面结构可如图 2 ( f )所示。 所 述平坦层过孔 191的截面形状例如可以为圓形、 方形、 三角形、 梯形或其他 多边形结构中的一种或多种， 本发明实施例对此不作任何限定； 在图 2 ( f ) 中， 所述平坦层过孔 191例如为方形结构。
所述平坦层 19上形成有公共电极层，其中，所述公共电极层的平面结构 示意图可如图 2 ( g )所示（图 2 ( g ) 中， 以标号 22标识所述公共电极层 ); 所述公共电极层例如可采用一次构图工艺形成， 且所述公共电极层的材料通 常可为 ITO、 ΑΖΟ等透明导电薄膜材料， 本发明实施例对此不作任何限定。
所述公共电极层上可形成有钝化层 20, 且所述钝化层 20内还形成有与 所述平坦层过孔 191相互对应的、 贯通至所述源漏金属层 17的钝化层过孔 201 (第三过孔）； 所形成的钝化层过孔 201的平面结构可如图 2 ( h )所示。
需要说明的是， 所述钝化层过孔 201 的大小通常小于所述平坦层过孔 191; 再有， 所述钝化层过孔 201的截面形状也可以为圓形、 方形、 三角形、 梯形或其他多边形结构中的一种或多种， 本发明实施例对此不作任何限定； 在图 2 ( h ) 中， 所述钝化层过孔 201例如为方形结构。 再有需要说明的是， 与所述平坦层 19类似， 所述钝化层 20可以是无机 材料形成的绝缘层或有机材料形成的绝缘层， 本发明实施例对此不作任何限 定。
如图 2 ( i )所示， 其为本发明实施例中所述像素电极层 17的平面结构 示意图，所述像素电极层 17可形成在所述第三过孔 201内以及具备所述第三 过孔 201的钝化层 20上， 并可通过位于所述第一过孔 151 内的源漏金属层 16与所述金属屏蔽层 12电相连， 使得栅金属层中的公共电极线可以夹在所 述源漏金属层 16以及所述金属屏蔽层 12之间， 达到既能与所述源漏金属层 16形成存储电容， 又能与所述金属屏蔽层 12形成存储电容的效果， 从而实 现了增加阵列基板的存储电容、 提高阵列基板的像素电压保持率以及降低显 示装置的闪烁等不良现象的目的， 提高了阵列基板以及显示装置的品质。
最后需要说明的是， 图 2 ( a ) ~图 2 ( i ) 中各层的图案结构只是示意性 的说明本发明的实施例， 还可根据实际情况进行调整设定， 本发明实施例对 此不作任何限定。
本发明实施例一还提供了一种显示装置， 包括上述的阵列基板。 所述显 示装置例如可以为液晶显示面板、 电子纸、 OLED ( Organic Light-Emitting Diode, 有机发光二极管）面板、 手机、 平板电脑、 电视机、 显示器、 笔记本 电脑、 数码相框、 导航仪等任何具备显示功能的产品或部件， 本发明实施例 对此不作任何限定。
需要说明的是， 本发明实施例中所述的显示装置可以为 TN ( Twisted
Nematic, 扭曲向列 )模式、 VA ( Vertical Alignment, 垂直取向 )模式、 IPS ( In-Plane Switching,平面转换技术 )模式或 ADS( Advanced Super Dimension Switch, 高级超维场转换技术）模式， 本发明实施例对此不作任何限定； 较 优地， 本发明实施例中所述的显示装置尤其适用于 IPS模式和 ADS模式。
上述本发明实施例一提供了一种阵列基板及显示装置， 通过在层间介电 层以及栅极绝缘层内设置直达所述金属屏蔽层的过孔， 使得位于源漏金属层 上的像素电极层可与所述金属屏蔽层电相连， 进而使得栅金属层中的公共电 极线可以夹在所述源漏金属层以及所述金属屏蔽层之间， 达到既能与所述源 漏金属层形成存储电容， 又能与所述金属屏蔽层形成存储电容的效果， 从而 实现了增加阵列基板的存储电容、 提高阵列基板的像素电压保持率以及降低 显示装置的闪烁等不良现象的目的， 提高了阵列基板及显示装置的品质。 实施例二：
本发明实施例二提供了一种可用于制备本发明实施例一中所述阵列基板 的方法， 下面结合图 2 ( a ) ~图 2 ( i )对本发明实施例二中所述阵列基板的 制备方法进行筒要说明。 以阵列基板中所述半导体层为多晶硅层为例， 所述 阵列基板的制备方法可以包括以下步骤：
步骤 101: 在村底基板 11上形成金属屏蔽层 12; 例如所述金属屏蔽层 12的图案可如图 2 ( a )所示。
所述村底基板 11可以为玻璃基板或塑料基板等，本发明实施例对此不作 任何限定。
在所述村底基板 11上形成金属屏蔽层 12之前， 可对所述村底基板 11 进行预清洗操作， 之后， 在所述村底基板 11上方形成金属屏蔽层 12, 所述 金属屏蔽层 12主要用于对 TFT沟道进行遮挡，以减小背光源对 TFT的影响。 所述金属屏蔽层 12例如可以为铝层、钨层、铬层或其他金属， 或者金属化合 物导电层等， 本发明实施例对此不作任何限定。
例如， 在所述村底基板 11上方形成金属屏蔽层 12可以包括：
采用沉积、溅射等方式在所述村底基板 11上形成一金属层，并通过包括 光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺的构图工艺形成具备设 定图案的金属屏蔽层 12, 本发明实施例对此不作赘述。
步骤 102: 在所述金属屏蔽层 12上形成緩沖层 18。
在本发明所述实施例中， 可采用 CVD ( Chemical Vapor Deposition, 化学 气相沉积 )等方法在所述金属屏蔽层 12上沉积緩沖层 18; 所述緩沖层 18例 如可以为氮化硅薄膜层和氧化硅薄膜层所组成的双层绝缘层结构， 也可以为 氮化硅薄膜层或氧化硅薄膜层等单层绝缘层结构， 本发明实施例对此不作任 何限定。 当然， 在有些结构中， 如村底基板为无碱玻璃或者其他经过特殊加 工后的基板时， 可以不设置緩沖层， 此时， 则可以省略步骤 102。
步骤 103: 在所述緩沖层 18上形成半导体层 13; 所述半导体层 13的图 案可如图 2 ( b )所示。
在本步骤 103中， 当所述半导体层 13为多晶硅层时， 可采用 CVD等方 法在所述緩沖层 18上沉积非晶硅层， 并采用准分子激光退火（ ELA )或固相 结晶 （SPC )等方法将所述非晶硅晶化为多晶硅， 之后， 再通过包括光刻胶 涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺的构图工艺形成所需的多晶硅 图案。
步骤 104: 在所述半导体层 13上形成栅极绝缘层 14。
可采用 CVD等方法在所述半导体层 13上沉积栅极绝缘层 14; 其中， 所 述栅极绝缘层 14可为氧化硅层、氮化硅层或由氧化硅层和氮化硅层所组成的 复合绝缘层等， 本发明实施例对此不作任何限定。
步骤 105: 在所述栅极绝缘层 14上形成栅金属层 21 ; 所述栅金属层 21 的图案可如图 2 ( c )所示， 包括栅极、 栅线和公共电极线， 其中， 标号 211 对应栅极和栅线（ Gate ), 标号 212对应公共电极线（ Gate Metal Vcom )。
在本步骤 105中， 可采用 PVD ( Physical Vapor Deposition, 物理气相沉 积）等方法在所述栅极绝缘层 14上形成一金属层， 并通过包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺的构图工艺同时形成栅极、 栅线与公 共电极线的图案。
例如所述金属层可以为铝层、 钨层、 铬层或其他金属及金属化合物导电 层等， 本发明实施例对此不作任何限定。
步骤 106: 在所述栅金属层 21上形成层间介电层 15。
可采用 CVD等方法在所述栅金属层 21上沉积层间介电层 15 ,以起到保 护栅金属层 21、并隔离所述栅金属层 21和后续源漏金属层 16的目的；其中， 所述层间介电层 15可由氧化硅、氮化硅等材料制备而成，本发明实施例对此 不作任何限定。
步骤 107: 在所述层间介电层 15、 栅极绝缘层 14以及緩沖层 18内形成 至少一个贯通至所述金属屏蔽层 12的第一过孔 151; 所形成的第一过孔 151 的图案可如图 2 ( d )所示。
需要说明的是， 在形成所述第一过孔 151的同时， 还可在所述层间介电 层 15以及栅极绝缘层 14内形成贯通至所述半导体层 13的源极过孔以及漏极 过孔（其中， 所述源极过孔或漏极过孔的示意图可参见图 2 ( d )所示， 具体 可以标号 152来标识）。
在本步骤 107中， 可采用一次或多次构图工艺形成所述第一过孔 151、 源极过孔以及漏极过孔， 本发明实施例对此不作任何限定； 在通过一次构图 工艺形成上述各过孔时，可通过刻蚀参数的控制来实现不同深度过孔的形成。 步骤 108: 在所述第一过孔 151内以及具备所述第一过孔 151的层间介 电层 15上形成源漏金属层 16; 所形成的源漏金属层 16的图案可如图 2 ( e ) 所示。
在本步骤 108中， 通常可在具备源极过孔、 漏极过孔以及第一过孔 151 的层间介电层 15表面沉积一导电材料，并通过包括光刻胶涂敷、曝光、显影、 刻蚀、 光刻胶剥离等工艺的构图工艺来形成具备设定图案的源漏金属层 16; 其中， 所述导电材料可以为铝、 钨、 铬或其他金属及金属化合物等， 本发明 实施例对此不作任何限定。
例如在本发明所述实施例中，所述源漏金属层 16具体可包括两部分，一 为呈条形结构的金属层， 通常可称为数据线； 一为呈方形结构的金属层， 通 常可称为源漏平板，其中，所述源漏平板在所述村底基板 11上的水平投影区 域与所述第一过孔 161在所述村底基板 11上的水平投影区域重叠，即所述第 一过孔 161通常形成在位于所述源漏平板下的层间介电层 16、栅极绝缘层 14 以及緩沖层 18内。
步骤 109: 在所述源漏金属层 16上形成平坦层 19。
可采用 CVD等方法在所述源漏金属层 16上沉积平坦层 19; 其中， 所述 平坦层 19可以是无机材料形成的绝缘层或有机材料形成的绝缘层，本发明实 施例对此不作任何限定。
步骤 110: 在所述平坦层 19内形成直达所述源漏金属层 16的平坦层过 孔 191 (第二过孔）； 所形成的平坦层过孔 191的图案可如图 2 ( f )所示。
在所述源漏金属层 16上沉积平坦层 19之后， 可通过包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺的构图工艺形成具备设定形状的平坦 层过孔 191; 所述平坦层过孔 191的截面形状可以为圓形、 方形、 三角形、 梯形或其他多边形结构中的一种或多种， 本发明实施例对此不作任何限定； 在图 2 ( f ) 中， 所述平坦层过孔 191为方形结构。
步骤 111: 在所述平坦层 19上形成公共电极层 22; 所形成的公共电极层 22的图案可如图 2 ( g )所示。
可采用 CVD等方法在所述平坦层 19上方沉积一透明导电薄膜层， 并通 过包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺的构图工艺形成 具备设定图案的公共电极层 22。
例如所述公共电极层 22通常可由透明导电薄膜材料制备而成，所述透明 导电薄膜材料通常可为 ITO、 ΑΖΟ等材料，本发明实施例对此不作任何限定。
步骤 112: 在所述公共电极层 22上形成钝化层 20, 并在所述钝化层 20 层过孔 201 (第三过孔）；所形成的钝化层过孔 201的图案可如图 2 ( h )所示。
可采用 CVD等方法在所述公共电极层 22之上沉积钝化层 20,并通过包 括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺的构图工艺在所述钝 化层 20之内形成具备设定形状的钝化层过孔 201。
需要说明的是， 所述钝化层过孔 201 的大小通常小于所述平坦层过孔
191; 再有， 所述钝化层过孔 201的截面形状可以为圓形、 方形、 三角形、 梯 形或其他多边形结构中的一种或多种， 本发明实施例对此不作任何限定； 在 图 2 ( h ) 中， 所述钝化层过孔 201为方形结构。
例如所述钝化层 20可以是无机材料形成的绝缘层或有机材料形成的绝 缘层， 本发明实施例对此不作任何限定。
步骤 113:在所述钝化层 20上形成像素电极层 17; 所形成的像素电极层
17的图案可如图 2 ( i )所示。 导电材料层， 并通过包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工 艺的构图工艺来得到具备设定图案的像素电极层 17。
需要说明的是， 所得到的像素电极层 17通常位于所述钝化层过孔 201 内以及所述钝化层 20之上， 并通过位于所述第一过孔 151 内的源漏金属层
16与所述金属屏蔽层 12电连接。
也就是说， 经过上述步骤 101~步骤 113之后， 可得到本发明实施例一中 所述的阵列基板，所得到的阵列基板的横截面结构示意图可如图 1以及图 3~ 图 5所示， 其中， 图 1对应图 2 ( i ) 中的 A-A， 横截面， 图 3对应 2 ( i ) 中 的 B-B， 横截面， 图 4对应图 2 ( i ) 中的 C-C 横截面， 图 5对应 2 ( i ) 中 的 D-D， 横截面。
在本发明实施例二所述的阵列基板制备方法中，通过在所述层间介电层、 栅极绝缘层以及緩沖层内形成贯通至所述金属屏蔽层的过孔， 使得像素电极 层可通过所述源漏金属层与所述金属屏蔽层电相连， 进而使得公共电极线既 能与所述源漏金属层形成存储电容， 又能与所述金属屏蔽层形成存储电容， 从而起到了增加阵列基板的存储电容、 提高阵列基板的像素电压保持率以及 降低显示装置的闪烁等不良现象的效果， 提高了阵列基板及显示装置的产品 口口 臾
需要说明的是，本发明实施例以半导体层为多晶硅层的顶栅型 TFT为例 进行说明， 对于半导体层为非晶硅层等的 TFT, 本发明实施例同样适用， 且 对于底栅型 TFT或者其他结构变形的 TFT,只要是需要通过增加正对面积而 增大存储电容的方案， 也都属于本发明实施例的保护范围。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板， 包括村底基板、依次形成在所述村底基板上的金属屏 蔽层、 半导体层、 栅极绝缘层、 栅金属层、 层间介电层、 源漏金属层以及像 素电极层， 其中
所述层间介电层和栅极绝缘层内形成有至少一个贯通至所述金属屏蔽层 的第一过孔；
所述源漏金属层形成在所述至少一个第一过孔内以及具备所述至少一个 第一过孔的层间介电层上。
2、如权利要求 1所述的阵列基板，其中所述源漏金属层覆盖于至少一个 第一过孔的内壁并且与所述金属屏蔽层电连接。
3、如权利要求 1或 2所述的阵列基板，其中所述至少一个第一过孔的截 面形状为圓形、 方形、 三角形以及梯形中的任意一种或多种。
4、 如权利要求 1~3任一项所述的阵列基板， 其中所述阵列基板还包括： 形成在所述金属屏蔽层和所述半导体层之间的緩沖层， 所述至少一个第 一过孔形成在所述层间介电层、 栅极绝缘层以及緩沖层内。
5、 如权利要求 1~4任一项所述的阵列基板， 其中所述源漏金属层包括 源极、 漏极和数据线的图案。
6、如权利要求 5所述的阵列基板，其中所述层间介电层以及栅极绝缘层 内还形成有分别用于将所述半导体层与源极和漏极电连接的源极过孔以及漏 极过孔。
7、 如权利要求 1~6任一项所述的阵列基板， 其中所述阵列基板还包括： 依次形成在所述源漏金属层与所述像素电极层之间的平坦层、 公共电极 层以及钝化层；
其中， 所述平坦层以及钝化层内分别形成有相互对应的、 贯通至所述源 漏金属层的第二过孔、 第三过孔；
所述像素电极层形成在所述第三过孔内以及具备所述第三过孔的钝化层 上。
8、 如权利要求 1~7任一项所述的阵列基板， 其中所述半导体层为多晶 硅层。
9、 如权利要求 1~8任一项所述的阵列基板， 其中所述栅金属层包括栅 极、 栅线和公共电极线的图案。
10、 一种显示装置， 包括权利要求 1~9任一项所述的阵列基板。
11、 一种阵列基板制备方法， 包括：
在村底基板上依次形成金属屏蔽层、半导体层、栅极绝缘层、栅金属层、 层间介电层；
在所述层间介电层和栅极绝缘层内形成至少一个贯通至所述金属屏蔽层 的第一过孔；
在所述至少一个第一过孔内以及具备所述至少一个第一过孔的层间介电 层上形成源漏金属层。
12、如权利要求 11所述的阵列基板制备方法，还包括在所述源漏金属层 上方形成像素电极层。
13、 如权利要求 11或 12所述的阵列基板制备方法， 其中所述半导体层 为多晶硅层； 在形成所述金属屏蔽层之后， 且在形成所述半导体层之前， 所 述方法还包括：
在所述金属屏蔽层上形成緩沖层， 其中， 所述第一过孔形成在所述层间 介电层、 栅极绝缘层以及緩沖层内。
14、 如权利要求 11~13任一项所述的阵列基板制备方法， 其中所述源漏 金属层包括源极、 漏极和数据线的图案； 在形成所述层间介电层之后， 且在 形成所述源漏金属层之前， 所述方法还包括：
在所述层间介电层以及栅极绝缘层内形成分别用于将所述半导体层与源 极和漏极电连接的源极过孔以及漏极过孔。
15、如权利要求 12所述的阵列基板制备方法，其中在所述第一过孔内以 及具备所述第一过孔的层间介电层上形成源漏金属层之后， 且在所述源漏金 属层上方形成像素电极层之前， 所述方法还包括：
依次在所述源漏金属层上形成平坦层、 公共电极层以及钝化层； 漏金属层的第二过孔、 第三过孔；
在所述源漏金属层上方形成像素电极层， 包括：
在所述第三过孔内以及具备所述第三过孔的钝化层上形成所述像素电极 层。
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