WO2016065851A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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WO2016065851A1
WO2016065851A1 PCT/CN2015/076293 CN2015076293W WO2016065851A1 WO 2016065851 A1 WO2016065851 A1 WO 2016065851A1 CN 2015076293 W CN2015076293 W CN 2015076293W WO 2016065851 A1 WO2016065851 A1 WO 2016065851A1
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Prior art keywords
array substrate
grooves
groove
gate
pixel electrode
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PCT/CN2015/076293
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English (en)
French (fr)
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李文波
李盼
先建波
程鸿飞
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京东方科技集团股份有限公司
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Priority to US14/769,303 priority Critical patent/US9897863B2/en
Publication of WO2016065851A1 publication Critical patent/WO2016065851A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy

Definitions

  • Embodiments of the present invention relate to an array substrate, a display panel, and a display device.
  • liquid crystal display technology is widely used in television, mobile phone and public information display, and is a widely used display technology.
  • the liquid crystal display panel of the liquid crystal display includes oppositely disposed opposite substrates and an array substrate, and a liquid crystal layer between the two substrates.
  • a column spacer (PS) which plays a supporting role is generally disposed between the two substrates, and the PS is usually fixed on the array substrate, and the design of the PS affects the liquid crystal.
  • the uniformity of the layer thickness which in turn affects the quality of the liquid crystal display.
  • Embodiments of the present invention provide an array substrate, a display panel, and a display device.
  • a groove is formed on a gate line and/or a data line of an array substrate
  • the opposite substrate and the array substrate are paired with the groove, the spacer and the spacer.
  • the substrate is prevented from being bent and deformed by external pressure while ensuring the uniformity and stability of the thickness of the liquid crystal layer, and the movement of the spacer affects the display area.
  • An array substrate provided by at least one embodiment of the present invention includes: a plurality of gate lines and a plurality of data lines, pixel units arranged in an array on the array substrate, each pixel unit including a pixel electrode and a film a transistor, the data line serves as a source of the thin film transistor, the gate line serves as a gate of the thin film transistor, and a drain of the thin film transistor is electrically connected to the pixel electrode, and the gate line and the gate At least one of the data lines is provided with a recess for fixed alignment with the spacer.
  • a display panel provided by an embodiment of the present invention includes the array substrate described in the above embodiments of the present invention.
  • a display device includes the display panel described in the above embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view along the line A-A' of the array substrate structure of FIG. 1 according to an embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional view along the B-B' structure of the array substrate structure of FIG. 1 according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a planar structure of an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a cross-sectional structural diagram of a display panel according to an embodiment of the present invention.
  • PS is generally provided in a region corresponding to the black matrix on the opposite substrate, and in order to simplify the fabrication process, the heights of the PSs disposed on the opposite substrate are generally equal, so that the opposite After the substrate and the array substrate are paired with the box, the PS disposed between the two substrates is in contact with both the substrates to provide a supporting force to ensure uniformity and stability of the thickness of the liquid crystal layer; however, when the liquid crystal display panel is used When the external pressure is strong and the bending is deformed, the movement of the PS may affect the display area, thereby affecting the display of the liquid crystal display.
  • An array substrate provided by the embodiment of the invention includes: a plurality of gate lines and a plurality of data lines, wherein the pixel units are arranged in an array on the array substrate, and each pixel unit comprises a pixel electrode and a thin film transistor, and the data
  • the gate of the thin film transistor, the drain of the thin film transistor is electrically connected to the pixel electrode, and a groove for fixing the alignment with the spacer is disposed on the gate line and/or the data line.
  • the drain and the pixel electrode of the thin film transistor can be electrically connected through the via.
  • embodiments of the present invention are not limited thereto.
  • the pixel electrode may be directly overlapped on the drain of the thin film transistor.
  • the spacer in the embodiment of the present invention may be a column spacer or a spacer of other shapes, as long as a groove fixedly aligned with the array substrate can be disposed.
  • the following examples are described by taking a column spacer as an example.
  • the groove on the array substrate is not provided with the spacer fixed in position, the one end of the spacer is fixed on the opposite substrate, and the end of the spacer adjacent to the array substrate is not fixed.
  • the groove that is aligned with the spacer ie, the groove is opposite to the spacer and the groove is used for fixing the spacer
  • it can be realized at least parallel to the array substrate. In the direction of the plane, the position of the spacer adjacent to the array substrate is unchanged with respect to the position of the array substrate.
  • the groove and the column spacer are fixedly aligned, thereby The spacing between the opposing substrate and the array substrate is fixed up and down and fixed to the left and right.
  • the structure of an array substrate is as shown in FIG. 1 , the pixel unit including the pixel electrode 42 is the first pixel unit, and the pixel unit including the pixel electrode 41 is the second pixel unit.
  • a thin film transistor is provided at the intersection of the gate line 10 and the data line 30, and the gate 11 of the thin film transistor is shared with the gate line 10, and the source 31 and the data line 30 of the thin film transistor
  • the drain 32 is electrically connected to the pixel electrode 42 through the via 361.
  • a thin film transistor is disposed at the intersection of the gate line 10 and the data line 30, and the gate 11 and the gate line of the thin film transistor are provided.
  • the first pixel unit and the second pixel unit share the source 31, and the structure of the source 31 may have a structure as shown in FIG. 1.
  • the structure of another array substrate is as shown in FIG. 2, the pixel unit including the pixel electrode 42 is the first pixel unit, and the pixel unit including the pixel electrode 41 is the second pixel unit.
  • a thin film transistor is disposed at a point.
  • the gate 11 of the thin film transistor is shared with the gate line 10.
  • the source 31 of the thin film transistor is shared with the data line 30, and the drain 32 is electrically connected to the pixel electrode 42 through the via 361.
  • a thin film transistor is disposed at an intersection of the gate line 10 and the data line 30.
  • the gate electrode 11 of the thin film transistor is shared with the gate line 10.
  • the source 31 of the thin film transistor is shared with the data line 30, and the drain is passed.
  • the via 362 is electrically connected to the pixel electrode 41.
  • the first pixel unit and the second pixel unit share the source 31, and the structure of the source 31 may have a structure as shown in FIG. 2.
  • the structure of the source 31 may be the structure shown in FIG. 1 or the structure shown in FIG. 2. Of course, those skilled in the art should understand that the structure of the source 31 may also have Other structures are not specifically limited herein.
  • At least two grooves are disposed on the gate lines and/or the data lines, that is, at least two grooves are disposed on the gate lines or the data lines. Or the sum of the number of grooves set on the gate line and the data line is at least two.
  • At least two grooves are two grooves, and two grooves are disposed on the gate line.
  • At least two grooves are two grooves, and one of the two grooves is disposed on the grid line, and the other of the two grooves One is set on the data line.
  • the groove is disposed on the gate line, and similarly, the groove may be disposed on the data line.
  • At least two grooves are two grooves, that is, referring to FIG. 1 and FIG. 2, a circular concave is disposed on the gate line 10 between the first pixel unit and the second pixel unit.
  • a groove 363 and a groove 364 are provided on the gate line 10, and the groove 363 and the groove 364 are disposed directly above the gate line 10.
  • the two grooves may also be disposed on the data line 30 at the same time, or may be disposed on the gate line 10 and the other on the data line 30.
  • the grooves (the grooves 363 and the grooves 364) provided on the gate line 10 can be formed in synchronization with the via holes (the via holes 361 and the via holes 362), so that an additional mask is not required.
  • the original manufacturing process of the array substrate is used, and no additional equipment costs are added.
  • the groove comprises a circular and/or rectangular groove.
  • the shape of the groove includes, but is not limited to, a circle, a polygon (such as a rectangle), as long as it can be fixedly aligned with the PS.
  • the depths of the two grooves are different, so as to distinguish the primary and secondary PS when the groove is fixedly aligned with the PS, for example, for fixing the main
  • the depth of the groove of the PS is shallow, and the groove depth for fixing the secondary PS is deep.
  • the depth of the groove may be different by gray scale exposure, or the depth of the groove may be different by laying a pixel electrode in one of the two grooves, and the pixel electrode may be laid one or more layers. To change the depth of the groove.
  • the preparation process of the array substrate structure shown in FIG. 1 will be described in detail with reference to FIG. 3 and FIG. 4 , and the preparation process includes the following steps 1 to 6 , for example.
  • Step 1 performing sputtering on the array substrate 1 to deposit a metal layer, such as aluminum (Al), and separately coating the photoresist, exposing and developing, etching, forming a gate line, a gate 11 and The pattern of the common electrode line.
  • a metal layer such as aluminum (Al)
  • Step 2 depositing a gate insulating layer 21 by using Plasma Enhanced Chemical Vapor Deposition (PEVCD), for example, silicon nitride.
  • PEVCD Plasma Enhanced Chemical Vapor Deposition
  • Step 3 depositing a semiconductor layer, such as PECVD deposited amorphous silicon (a-Si) or sputter deposited indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO); coating photoresist, exposure development, etching, forming active The pattern of layer 22.
  • a semiconductor layer such as PECVD deposited amorphous silicon (a-Si) or sputter deposited indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO); coating photoresist, exposure development, etching, forming active The pattern of layer 22.
  • Step 4 sputter sputtering deposits a metal layer, such as aluminum (Al), coating photoresist, exposing and developing, etching, forming a pattern of data lines, source 311, drain 321 and drain 322;
  • the active layer 22 is located below the source 311, the drain 321 and the drain 322 and above the gate insulating layer 21.
  • Step 5 depositing a passivation layer 23, such as PECVD deposition of silicon nitride or a coating resin layer; coating a photoresist, exposing and developing, etching, forming vias 361 and vias 362; and vias 361 exposing the thin film transistors
  • a passivation layer 23 such as PECVD deposition of silicon nitride or a coating resin layer
  • coating a photoresist exposing and developing, etching, forming vias 361 and vias 362
  • vias 361 exposing the thin film transistors
  • the drain 321 , the via 362 exposes the drain 322 of the thin film transistor; while the via 361 and the via 362 are formed, the recess 363 and the recess 364 are formed, and the positions of the recess 363 and the recess 364 may be in the gate Line and / or data line.
  • Step 6 Sputter sputtering a transparent metal oxide conductive material layer, for example, an N-type oxide semiconductor indium tin oxide (ITO), coating a photoresist, exposing and developing, etching, Forming the pixel electrode 41 and the pixel electrode 42; wherein the pixel electrode 42 is electrically connected to the drain 321 of the thin film transistor through the via 361, and the pixel electrode 41 is electrically connected to the drain 322 of the thin film transistor through the via 362; A 363 or groove 364 may be covered with a layer of pixel electrodes 41. For example, as shown in FIG. 4, a layer of pixel electrodes 41 are laid in the recesses 364 to change the depth of the recesses, and the main and sub-PSs are distinguished when the recesses are fixedly aligned with the PS.
  • ITO N-type oxide semiconductor indium tin oxide
  • the gate line and the data line may be made of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), tungsten (W) and the like.
  • the material preparation can also be prepared by using an alloy of these materials.
  • the gate line can be a single layer structure or a multilayer structure such as Mo ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Ti ⁇ Cu.
  • the gate insulating layer 21 may be silicon nitride or silicon oxide; the gate insulating layer 21 may be a single layer structure, and the gate insulating layer 21 may also be a multilayer structure such as silicon oxide/silicon nitride.
  • the active layer 22 may be amorphous silicon or an oxide semiconductor.
  • the passivation layer 23 may be made of an inorganic substance such as silicon nitride or an organic substance such as a resin; the pixel electrode 41 and the pixel electrode 42 are prepared by using a transparent conductive oxide indium zinc oxide (IZO), ITO or other transparent metal oxide conductive material. .
  • IZO transparent conductive oxide indium zinc oxide
  • ITO transparent metal oxide conductive material
  • a plan view of the prepared array substrate is as shown in FIG. 5, and a black matrix (BM) resin is coated on the gate line 50 and the data line 51, and a groove 541 and a groove 542 are disposed on the gate line 50.
  • BM black matrix
  • a groove 543 and a groove 544 may be provided on the data line 51
  • red (R) green (G) blue (B) resin R resin 52, G resin 53, B resin 54
  • the array circuit is integrated and can also be fabricated on the opposite substrate.
  • a display panel according to an embodiment of the present invention includes the array substrate according to any one of the embodiments of the present invention.
  • the display panel includes, for example, a counter substrate 100 and an array substrate 200 which are sealed and sealed by a sealant, and a liquid crystal layer and a columnar shape for maintaining the thickness of the cartridge between the counter substrate 100 and the array substrate 200 .
  • Spacer 300 For example, a gate insulating layer 21 and a passivation layer 23 are sequentially disposed on the gate line 11 of the array substrate 200, and a recess 364 is provided at a position corresponding to the gate line 11 in the passivation layer 23, and the recess 364 is used for the column spacer
  • the pad 300 is fixed in place. It should be noted that FIG. 6 only shows a partial structure of the display panel.
  • the groove and the column spacer are fixedly aligned, thereby
  • the spacing between the opposing substrate and the array substrate is fixed up and down and fixed to the left and right to ensure liquid crystal
  • the uniformity and stability of the layer thickness prevent the substrate from being bent by external stress, and the movement of the column spacer affects the display area.
  • a display device includes the display panel described in the embodiment of the invention.
  • the groove and the column spacer are fixed.
  • the alignment is such that the spacing between the opposing substrate and the array substrate is fixed up and down and fixed to the left and right, and the uniformity and stability of the thickness of the liquid crystal layer are ensured, and the groove is not provided on the gate line and/or the data line.
  • the groove is fixed to the alignment by the column spacer to prevent the substrate from being bent and deformed by external pressure, and the movement of the column spacer affects the display area.
  • the display device is a liquid crystal display device.
  • the display device may be any product or component having a display function, such as an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Embodiments of the present invention provide an array substrate, a display panel, and a display device.
  • a recess is formed on a gate line and/or a data line of an array substrate
  • the opposite substrate and the array substrate are aligned, and the groove and the column spacer are separated.
  • the spacer is fixed in position, so that the spacing between the opposite substrate and the array substrate is fixed up and down and fixed to the left and right.
  • the uniformity and stability of the thickness of the liquid crystal layer are ensured, the substrate is prevented from being bent and deformed by external pressure, and the column spacer is The movement of the mat affects the display area.

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Abstract

一种阵列基板、显示面板及显示装置，所述阵列基板包括：多条栅线（10；50）和多条数据线（30；51），以及成阵列分布的像素单元，每一像素单元包括一个像素电极（41；42）与一个薄膜晶体管，所述数据线（30；51）作为所述薄膜晶体管的源极（31；311），所述栅线（10；50）作为所述薄膜晶体管的栅极（11），所述薄膜晶体管的漏极（32；321；322）与所述像素电极（41；42）电性连接，所述栅线（10；50）和所述数据线（30；51）中的至少一个上设置有用于与隔垫物固定对位的凹槽（363；364）。通过设置凹槽（363；364），可以防止显示面板受外部压力发生弯曲变形时，柱状隔垫物的移动对显示区域造成影响。

Description

阵列基板、显示面板及显示装置 技术领域
本发明实施例涉及一种阵列基板、显示面板及显示装置。
背景技术
目前，液晶显示技术广泛应用于电视、手机及公共信息显示，是一种使用广泛的显示技术。液晶显示器的液晶显示面板包括相对设置的对置基板和阵列基板、以及位于两基板之间的液晶层。另外，为了保证液晶层厚度的稳定性，在两基板之间一般还设置有起到支撑作用的柱状隔垫物(Post Spacer，PS)，该PS通常固定在阵列基板上，PS的设计影响液晶层厚度的均匀性，进而影响液晶显示品质。
发明内容
本发明实施例提供了一种阵列基板、显示面板及显示装置，通过在阵列基板的栅线和/或数据线上设置凹槽，使得对置基板和阵列基板对盒时，凹槽与隔垫物固定对位，在保证液晶层厚度的均匀性和稳定性的同时，防止基板受外部压力发生弯曲变形时，隔垫物的移动对显示区域造成影响。
本发明的至少一个实施例提供的一种阵列基板，包括：多条栅线和多条数据线，位于所述阵列基板上成阵列分布的像素单元，每一像素单元包括一个像素电极与一个薄膜晶体管，所述数据线作为所述薄膜晶体管的源极，所述栅线作为所述薄膜晶体管的栅极，所述薄膜晶体管的漏极与所述像素电极电性连接，所述栅线和所述数据线中的至少一个上设置有用于与隔垫物固定对位的凹槽。
本发明实施例提供的一种显示面板，包括本发明上述实施例中所述的阵列基板。
本发明实施例提供的一种显示装置，包括本发明上述实施例中所述的显示面板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例提供的一种阵列基板的结构示意图；
图2为本发明实施例提供的另一阵列基板的结构示意图；
图3为本发明实施例提供的图1所示阵列基板结构的沿A-A’剖面结构示意图；
图4为本发明实施例提供的图1所示阵列基板结构的沿B-B’剖面结构示意图；
图5为本发明实施例提供的阵列基板的平面结构示意图；
图6为本发明实施例提供的显示面板的剖面结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
附图中各膜层的厚度和区域的大小形状不反映阵列基板各部件的真实比例，目的只是示意说明本发明的内容。
在研究中，本申请的发明人注意到，一般在对置基板上与黑矩阵对应的区域设置PS，并且，为了简化制作工艺，设置在对置基板上的PS的高度一般相等，使得对置基板和阵列基板对盒后，设置在两基板之间的PS与所述两基板均接触，以提供支撑力，保证液晶层厚度的均匀性和稳定性；但是，采用此结构，当液晶显示面板因受到的外部压力较强而弯曲变形时，PS的移动可能对显示区域造成影响，进而影响液晶显示器的显示。
本发明实施例提供的一种阵列基板，包括：多条栅线和多条数据线，位于所述阵列基板上成阵列分布的像素单元，每一像素单元包括一个像素电极与一个薄膜晶体管，数据线直接作为该薄膜晶体管的源极，栅线直接作为该 薄膜晶体管的栅极，薄膜晶体管的漏极与像素电极电性连接，而且在栅线和/或数据线上设置有用于与隔垫物固定对位的凹槽。
在本发明实施例中，薄膜晶体管的漏极与像素电极可以通过过孔电性连接。但本发明实施例不限于此，例如，像素电极可以直接搭接在薄膜晶体管的漏极上。
此外，本发明实施例中的隔垫物可以是柱状隔垫物，也可以是其他形状的隔垫物，只要可以在阵列基板上设置与其固定对位的凹槽即可。以下实施例以柱状隔垫物为例进行说明。
在阵列基板上未设置与隔垫物固定对位的凹槽的情形中，隔垫物的一端固定在对置基板上，隔垫物的靠近阵列基板的一端则未固定。在本发明实施例中，通过设置与隔垫物固定对位的凹槽(即凹槽与隔垫物相对设置且凹槽用于固定隔垫物)，可以实现：至少沿平行于阵列基板所在平面的方向上，隔垫物的靠近阵列基板的一端相对于阵列基板的位置不变。
本发明实施例提供的阵列基板中，通过在阵列基板的栅线和/或数据线上设置凹槽，使得对置基板和阵列基板对盒时，凹槽与柱状隔垫物固定对位，从而使得对置基板和阵列基板之间的间距上下固定和左右固定，在保证液晶层厚度的均匀性和稳定性的同时，防止基板受外部压力发生弯曲变形时，柱状隔垫物的移动对显示区域造成影响。
在本发明实施例提供的阵列基板中，一种阵列基板的结构如图1所示，以包括像素电极42的像素单元为第一像素单元，包括像素电极41的像素单元为第二像素单元为例，在第一像素单元中，在栅线10和数据线30的交叉点处设置有薄膜晶体管，该薄膜晶体管的栅极11与栅线10共用，该薄膜晶体管的源极31与数据线30共用，漏极32通过过孔361与像素电极42电性连接；第二像素单元中，在栅线10和数据线30的交叉点处设置有薄膜晶体管，该薄膜晶体管的栅极11与栅线10共用，该薄膜晶体管的源极31与数据线30共用，漏极通过过孔362与像素电极41电性连接。第一像素单元和第二像素单元共用源极31，源极31的结构可以如图1中所示的结构。
在本发明实施例提供的阵列基板中，另一种阵列基板的结构如图2所示，以包括像素电极42的像素单元为第一像素单元，包括像素电极41的像素单元为第二像素单元为例，在第一像素单元中，在栅线10和数据线30的交叉 点处设置有薄膜晶体管，该薄膜晶体管的栅极11与栅线10共用，该薄膜晶体管的源极31与数据线30共用，漏极32通过过孔361与像素电极42电性连接；第二像素单元中，在栅线10和数据线30的交叉点处设置有薄膜晶体管，该薄膜晶体管的栅极11与栅线10共用，该薄膜晶体管的源极31与数据线30共用，漏极通过过孔362与像素电极41电性连接。第一像素单元和第二像素单元共用源极31，源极31的结构可以如图2中所示的结构。
值得注意的是，源极31的结构可以是图1中所示的结构，也可以是图2中所示的结构，当然，本领域技术人员应当理解的是，源极31的结构还可以有其它结构，此处并不用于具体限定。
在一种可能的实施方式中，本发明实施例提供的阵列基板中，栅线和/或数据线上设置有至少两个凹槽，即栅线或数据线上设置有至少两个凹槽，或者栅线和数据线上设置的凹槽数量之和至少为两个。
在一种可能的实施方式中，本发明实施例提供的阵列基板中，至少两个凹槽为两个凹槽，两个凹槽设置在栅线上。
在一种可能的实施方式中，本发明实施例提供的阵列基板中，至少两个凹槽为两个凹槽，两个凹槽中的一个设置在栅线上，两个凹槽中的另一个设置在数据线上。
本发明实施例提供的阵列基板中，将凹槽设置在栅线上，同样的，也可以在数据线上设置凹槽。
在本发明实施例中，至少两个凹槽为2个凹槽，即参见图1和图2，在第一像素单元和第二像素单元之间的栅线10上设置有一个圆形的凹槽363和一个矩形的凹槽364，但需要说明的是，可以根据PS位置的设置需求，设置凹槽的相应位置和个数。
具体实施时，如图1或图2所示，在栅线10上设置有凹槽363和凹槽364，凹槽363和凹槽364设置在栅线10的正上方。当然，两个凹槽也可以同时设置在数据线30上，也可以一个设置在栅线10上，另一个设置在数据线30上。
需要说明的是，栅线10上设置的凹槽(凹槽363和凹槽364)可以和过孔(过孔361和过孔362)同步形成，这样不需要额外的掩膜(mask)，可以使用阵列基板原有的制作工艺流程，无额外的设备成本增加。
在一种可能的实施方式中，本发明实施例提供的阵列基板中，所述凹槽包括圆形和/或矩形的凹槽。需要注意的是，凹槽的形状包括但不限于：圆形、多边形(如矩形)，只要满足能够与PS固定对位即可。
在一种可能的实施方式中，本发明实施例提供的阵列基板中，两个凹槽的深度不同，以便于在凹槽与PS固定对位时区分主、副PS，例如：用于固定主PS的凹槽深度较浅，用于固定副PS的凹槽深度较深。
具体实施时，可以通过灰阶曝光实现凹槽的深度不同，也可以通过在两个凹槽中的一个凹槽中铺设像素电极实现凹槽的深度不同，像素电极可铺设一层或多层，以改变凹槽的深度。
下面以图1所示的阵列基板结构为例，结合图3和图4对其制备过程进行详细说明，其制备过程例如包括以下步骤一至六。
步骤一、在阵列基板衬底1上进行溅射(sputter)沉积金属层，例如：铝(Al)，并分别进行涂覆光刻胶，曝光显影，刻蚀，形成栅线、栅极11和公共电极线的图形。
步骤二、采用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PEVCD)沉积栅极绝缘层21，所用材料例如是氮化硅。
步骤三、沉积半导体层，例如PECVD沉积非晶硅(a-Si)或sputter沉积铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)；涂覆光刻胶，曝光显影，刻蚀，形成有源层22的图形。
步骤四、sputter溅射沉积金属层，该金属层例如为铝(Al)，涂覆光刻胶，曝光显影，刻蚀，形成数据线、源极311、漏极321和漏极322的图形；其中，有源层22位于源极311、漏极321和漏极322的下方，位于栅极绝缘层21的上方。
步骤五、沉积钝化层23，例如PECVD沉积氮化硅或涂覆树脂层；涂覆光刻胶，曝光显影，刻蚀，形成过孔361和过孔362；过孔361暴露出薄膜晶体管的漏极321，过孔362暴露出薄膜晶体管的漏极322；在形成过孔361和过孔362的同时，形成凹槽363和凹槽364，并且凹槽363和凹槽364的位置可以在栅线和/或数据线上。
步骤六、Sputter溅射透明金属氧化物导电材料层，例如：N型氧化物半导体氧化铟锡(Indium Tin Oxides，ITO)，涂覆光刻胶，曝光显影，刻蚀， 形成像素电极41和像素电极42；其中，像素电极42通过过孔361与薄膜晶体管的漏极321电性连接，像素电极41通过过孔362与薄膜晶体管的漏极322电性连接；而且凹槽363或凹槽364可铺上一层像素电极41。例如，如图4所示，在凹槽364中铺设一层像素电极41，以改变凹槽的深度，用于凹槽与PS固定对位时区分主、副PS。
值得注意的是，本发明的实施例中，栅线、数据线可以采用铜(Cu)，铝(Al)，钼(Mo)，钛(Ti)，铬(Cr)，钨(W)等金属材料制备，也可以采用这些材料的合金制备，栅线可以是单层结构，也可以采用多层结构，例如Mo\Al\Mo，Ti\Cu\Ti，Mo\Ti\Cu。栅极绝缘层21可以采用氮化硅或氧化硅；栅极绝缘层21可以是单层结构，栅极绝缘层21也可以是多层结构，例如氧化硅\氮化硅。有源层22可以采用非晶硅，或氧化物半导体。钝化层23可以采用无机物例如氮化硅，也可以采用有机物例如树脂；像素电极41和像素电极42采用透明导电的氧化物氧化铟锌(IZO)、ITO或其他透明金属氧化物导电材料制备。
制备完成的阵列基板的平面图如图5所示，在栅线50和数据线51上涂覆有黑矩阵(Black Matrix，BM)树脂，在栅线50上设置有凹槽541和凹槽542，当然，也可以在数据线51上设置凹槽543和凹槽544，红(R)绿(G)蓝(B)树脂(R树脂52，G树脂53，B树脂54)可以在阵列基板上与阵列电路集成制作，也可以在对置基板上制作。
本发明实施例提供的一种显示面板，包括本发明实施例中任一所述的阵列基板。
如图6所示，该显示面板例如包括通过封框胶密封连接的对置基板100和阵列基板200，在对置基板100和阵列基板200之间设有液晶层以及用于维持盒厚的柱状隔垫物300。例如，阵列基板200中栅线11上依次设有栅极绝缘层21和钝化层23，钝化层23中对应栅线11的位置设有凹槽364，该凹槽364用于与柱状隔垫物300固定对位。需要说明的是，图6仅示出了显示面板的部分结构。
本发明实施例提供的显示面板中，通过在阵列基板的栅线和/或数据线上设置凹槽，使得对置基板和阵列基板对盒时，凹槽与柱状隔垫物固定对位，从而使得对置基板和阵列基板之间的间距上下固定和左右固定，在保证液晶 层厚度的均匀性和稳定性的同时，防止基板受外部压力发生弯曲变形时，柱状隔垫物的移动对显示区域造成影响。
本发明实施例提供的一种显示装置，包括本发明实施例中所述的显示面板。
本发明实施例提供的上述显示装置中，通过在显示面板中阵列基板的栅线和/或数据线上设置凹槽，使得对置基板和阵列基板对盒时，凹槽与柱状隔垫物固定对位，从而使得对置基板和阵列基板之间的间距上下固定和左右固定，在保证液晶层厚度的均匀性和稳定性的同时，与栅线和/或数据线上未设置凹槽相比，使用凹槽与柱状隔垫物固定对位，可以防止基板受外部压力发生弯曲变形时，柱状隔垫物的移动对显示区域造成影响。
在一种可能的实施方式中，本发明实施例提供的显示装置中，该显示装置为液晶显示装置。
本发明实施例提供的显示装置可以为：电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明实施例提供了一种阵列基板、显示面板及显示装置，通过在阵列基板的栅线和/或数据线上设置凹槽，使得对置基板和阵列基板对盒时，凹槽与柱状隔垫物固定对位，从而使得对置基板和阵列基板之间的间距上下固定和左右固定，在保证液晶层厚度的均匀性和稳定性的同时，防止基板受外部压力发生弯曲变形时，柱状隔垫物的移动对显示区域造成影响。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年10月27日递交的中国专利申请第201420628360.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (13)

  1. 一种阵列基板，包括：多条栅线和多条数据线，位于所述阵列基板上成阵列分布的像素单元，其中，
    每一像素单元包括一个像素电极与一个薄膜晶体管，所述数据线作为所述薄膜晶体管的源极，所述栅线作为所述薄膜晶体管的栅极，所述薄膜晶体管的漏极与所述像素电极电性连接，
    所述栅线和所述数据线中的至少一个上设置有用于与隔垫物固定对位的凹槽。
  2. 根据权利要求1所述的阵列基板，其中，所述栅线和所述数据线中的至少一个上设置有至少两个所述凹槽。
  3. 根据权利要求2所述的阵列基板，其中，至少两个所述凹槽为两个凹槽，所述两个凹槽设置在栅线或数据线上。
  4. 根据权利要求2所述的阵列基板，其中，至少两个所述凹槽为两个凹槽，所述两个凹槽中的一个设置在栅线上，所述两个凹槽中的另一个设置在数据线上。
  5. 根据权利要求2-4中任一项所述的阵列基板，其中，所述凹槽包括圆形和/或矩形的凹槽。
  6. 根据权利要求2-4中任一项所述的阵列基板，其中，所述凹槽包括多边形的凹槽。
  7. 根据权利要求3或4所述的阵列基板，其中，所述两个凹槽的深度不同。
  8. 根据权利要求3或4或7所述的阵列基板，其中，所述两个凹槽中的一个凹槽中铺设有像素电极。
  9. 根据权利要求1-8中任一项所述的阵列基板，其中，所述漏极通过过孔与所述像素电极电性连接，或者所述像素电极直接搭接在所述漏极上。
  10. 根据权利要求9所述的阵列基板，其中，所述凹槽与所述过孔位于同一层中。
  11. 一种显示面板，包括权利要求1-10中任一项所述的阵列基板。
  12. 一种显示装置，包括权利要求11所述的显示面板。
  13. 根据权利要求12所述的显示装置，其中，该显示装置为液晶显示装置。
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