WO2016065851A1 - 阵列基板、显示面板及显示装置 - Google Patents
阵列基板、显示面板及显示装置 Download PDFInfo
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- WO2016065851A1 WO2016065851A1 PCT/CN2015/076293 CN2015076293W WO2016065851A1 WO 2016065851 A1 WO2016065851 A1 WO 2016065851A1 CN 2015076293 W CN2015076293 W CN 2015076293W WO 2016065851 A1 WO2016065851 A1 WO 2016065851A1
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- array substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
Definitions
- Embodiments of the present invention relate to an array substrate, a display panel, and a display device.
- liquid crystal display technology is widely used in television, mobile phone and public information display, and is a widely used display technology.
- the liquid crystal display panel of the liquid crystal display includes oppositely disposed opposite substrates and an array substrate, and a liquid crystal layer between the two substrates.
- a column spacer (PS) which plays a supporting role is generally disposed between the two substrates, and the PS is usually fixed on the array substrate, and the design of the PS affects the liquid crystal.
- the uniformity of the layer thickness which in turn affects the quality of the liquid crystal display.
- Embodiments of the present invention provide an array substrate, a display panel, and a display device.
- a groove is formed on a gate line and/or a data line of an array substrate
- the opposite substrate and the array substrate are paired with the groove, the spacer and the spacer.
- the substrate is prevented from being bent and deformed by external pressure while ensuring the uniformity and stability of the thickness of the liquid crystal layer, and the movement of the spacer affects the display area.
- An array substrate provided by at least one embodiment of the present invention includes: a plurality of gate lines and a plurality of data lines, pixel units arranged in an array on the array substrate, each pixel unit including a pixel electrode and a film a transistor, the data line serves as a source of the thin film transistor, the gate line serves as a gate of the thin film transistor, and a drain of the thin film transistor is electrically connected to the pixel electrode, and the gate line and the gate At least one of the data lines is provided with a recess for fixed alignment with the spacer.
- a display panel provided by an embodiment of the present invention includes the array substrate described in the above embodiments of the present invention.
- a display device includes the display panel described in the above embodiment of the present invention.
- FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
- FIG. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
- FIG. 3 is a schematic cross-sectional view along the line A-A' of the array substrate structure of FIG. 1 according to an embodiment of the present invention
- FIG. 4 is a schematic cross-sectional view along the B-B' structure of the array substrate structure of FIG. 1 according to an embodiment of the present invention
- FIG. 5 is a schematic diagram of a planar structure of an array substrate according to an embodiment of the present invention.
- FIG. 6 is a cross-sectional structural diagram of a display panel according to an embodiment of the present invention.
- PS is generally provided in a region corresponding to the black matrix on the opposite substrate, and in order to simplify the fabrication process, the heights of the PSs disposed on the opposite substrate are generally equal, so that the opposite After the substrate and the array substrate are paired with the box, the PS disposed between the two substrates is in contact with both the substrates to provide a supporting force to ensure uniformity and stability of the thickness of the liquid crystal layer; however, when the liquid crystal display panel is used When the external pressure is strong and the bending is deformed, the movement of the PS may affect the display area, thereby affecting the display of the liquid crystal display.
- An array substrate provided by the embodiment of the invention includes: a plurality of gate lines and a plurality of data lines, wherein the pixel units are arranged in an array on the array substrate, and each pixel unit comprises a pixel electrode and a thin film transistor, and the data
- the gate of the thin film transistor, the drain of the thin film transistor is electrically connected to the pixel electrode, and a groove for fixing the alignment with the spacer is disposed on the gate line and/or the data line.
- the drain and the pixel electrode of the thin film transistor can be electrically connected through the via.
- embodiments of the present invention are not limited thereto.
- the pixel electrode may be directly overlapped on the drain of the thin film transistor.
- the spacer in the embodiment of the present invention may be a column spacer or a spacer of other shapes, as long as a groove fixedly aligned with the array substrate can be disposed.
- the following examples are described by taking a column spacer as an example.
- the groove on the array substrate is not provided with the spacer fixed in position, the one end of the spacer is fixed on the opposite substrate, and the end of the spacer adjacent to the array substrate is not fixed.
- the groove that is aligned with the spacer ie, the groove is opposite to the spacer and the groove is used for fixing the spacer
- it can be realized at least parallel to the array substrate. In the direction of the plane, the position of the spacer adjacent to the array substrate is unchanged with respect to the position of the array substrate.
- the groove and the column spacer are fixedly aligned, thereby The spacing between the opposing substrate and the array substrate is fixed up and down and fixed to the left and right.
- the structure of an array substrate is as shown in FIG. 1 , the pixel unit including the pixel electrode 42 is the first pixel unit, and the pixel unit including the pixel electrode 41 is the second pixel unit.
- a thin film transistor is provided at the intersection of the gate line 10 and the data line 30, and the gate 11 of the thin film transistor is shared with the gate line 10, and the source 31 and the data line 30 of the thin film transistor
- the drain 32 is electrically connected to the pixel electrode 42 through the via 361.
- a thin film transistor is disposed at the intersection of the gate line 10 and the data line 30, and the gate 11 and the gate line of the thin film transistor are provided.
- the first pixel unit and the second pixel unit share the source 31, and the structure of the source 31 may have a structure as shown in FIG. 1.
- the structure of another array substrate is as shown in FIG. 2, the pixel unit including the pixel electrode 42 is the first pixel unit, and the pixel unit including the pixel electrode 41 is the second pixel unit.
- a thin film transistor is disposed at a point.
- the gate 11 of the thin film transistor is shared with the gate line 10.
- the source 31 of the thin film transistor is shared with the data line 30, and the drain 32 is electrically connected to the pixel electrode 42 through the via 361.
- a thin film transistor is disposed at an intersection of the gate line 10 and the data line 30.
- the gate electrode 11 of the thin film transistor is shared with the gate line 10.
- the source 31 of the thin film transistor is shared with the data line 30, and the drain is passed.
- the via 362 is electrically connected to the pixel electrode 41.
- the first pixel unit and the second pixel unit share the source 31, and the structure of the source 31 may have a structure as shown in FIG. 2.
- the structure of the source 31 may be the structure shown in FIG. 1 or the structure shown in FIG. 2. Of course, those skilled in the art should understand that the structure of the source 31 may also have Other structures are not specifically limited herein.
- At least two grooves are disposed on the gate lines and/or the data lines, that is, at least two grooves are disposed on the gate lines or the data lines. Or the sum of the number of grooves set on the gate line and the data line is at least two.
- At least two grooves are two grooves, and two grooves are disposed on the gate line.
- At least two grooves are two grooves, and one of the two grooves is disposed on the grid line, and the other of the two grooves One is set on the data line.
- the groove is disposed on the gate line, and similarly, the groove may be disposed on the data line.
- At least two grooves are two grooves, that is, referring to FIG. 1 and FIG. 2, a circular concave is disposed on the gate line 10 between the first pixel unit and the second pixel unit.
- a groove 363 and a groove 364 are provided on the gate line 10, and the groove 363 and the groove 364 are disposed directly above the gate line 10.
- the two grooves may also be disposed on the data line 30 at the same time, or may be disposed on the gate line 10 and the other on the data line 30.
- the grooves (the grooves 363 and the grooves 364) provided on the gate line 10 can be formed in synchronization with the via holes (the via holes 361 and the via holes 362), so that an additional mask is not required.
- the original manufacturing process of the array substrate is used, and no additional equipment costs are added.
- the groove comprises a circular and/or rectangular groove.
- the shape of the groove includes, but is not limited to, a circle, a polygon (such as a rectangle), as long as it can be fixedly aligned with the PS.
- the depths of the two grooves are different, so as to distinguish the primary and secondary PS when the groove is fixedly aligned with the PS, for example, for fixing the main
- the depth of the groove of the PS is shallow, and the groove depth for fixing the secondary PS is deep.
- the depth of the groove may be different by gray scale exposure, or the depth of the groove may be different by laying a pixel electrode in one of the two grooves, and the pixel electrode may be laid one or more layers. To change the depth of the groove.
- the preparation process of the array substrate structure shown in FIG. 1 will be described in detail with reference to FIG. 3 and FIG. 4 , and the preparation process includes the following steps 1 to 6 , for example.
- Step 1 performing sputtering on the array substrate 1 to deposit a metal layer, such as aluminum (Al), and separately coating the photoresist, exposing and developing, etching, forming a gate line, a gate 11 and The pattern of the common electrode line.
- a metal layer such as aluminum (Al)
- Step 2 depositing a gate insulating layer 21 by using Plasma Enhanced Chemical Vapor Deposition (PEVCD), for example, silicon nitride.
- PEVCD Plasma Enhanced Chemical Vapor Deposition
- Step 3 depositing a semiconductor layer, such as PECVD deposited amorphous silicon (a-Si) or sputter deposited indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO); coating photoresist, exposure development, etching, forming active The pattern of layer 22.
- a semiconductor layer such as PECVD deposited amorphous silicon (a-Si) or sputter deposited indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO); coating photoresist, exposure development, etching, forming active The pattern of layer 22.
- Step 4 sputter sputtering deposits a metal layer, such as aluminum (Al), coating photoresist, exposing and developing, etching, forming a pattern of data lines, source 311, drain 321 and drain 322;
- the active layer 22 is located below the source 311, the drain 321 and the drain 322 and above the gate insulating layer 21.
- Step 5 depositing a passivation layer 23, such as PECVD deposition of silicon nitride or a coating resin layer; coating a photoresist, exposing and developing, etching, forming vias 361 and vias 362; and vias 361 exposing the thin film transistors
- a passivation layer 23 such as PECVD deposition of silicon nitride or a coating resin layer
- coating a photoresist exposing and developing, etching, forming vias 361 and vias 362
- vias 361 exposing the thin film transistors
- the drain 321 , the via 362 exposes the drain 322 of the thin film transistor; while the via 361 and the via 362 are formed, the recess 363 and the recess 364 are formed, and the positions of the recess 363 and the recess 364 may be in the gate Line and / or data line.
- Step 6 Sputter sputtering a transparent metal oxide conductive material layer, for example, an N-type oxide semiconductor indium tin oxide (ITO), coating a photoresist, exposing and developing, etching, Forming the pixel electrode 41 and the pixel electrode 42; wherein the pixel electrode 42 is electrically connected to the drain 321 of the thin film transistor through the via 361, and the pixel electrode 41 is electrically connected to the drain 322 of the thin film transistor through the via 362; A 363 or groove 364 may be covered with a layer of pixel electrodes 41. For example, as shown in FIG. 4, a layer of pixel electrodes 41 are laid in the recesses 364 to change the depth of the recesses, and the main and sub-PSs are distinguished when the recesses are fixedly aligned with the PS.
- ITO N-type oxide semiconductor indium tin oxide
- the gate line and the data line may be made of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), tungsten (W) and the like.
- the material preparation can also be prepared by using an alloy of these materials.
- the gate line can be a single layer structure or a multilayer structure such as Mo ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Ti ⁇ Cu.
- the gate insulating layer 21 may be silicon nitride or silicon oxide; the gate insulating layer 21 may be a single layer structure, and the gate insulating layer 21 may also be a multilayer structure such as silicon oxide/silicon nitride.
- the active layer 22 may be amorphous silicon or an oxide semiconductor.
- the passivation layer 23 may be made of an inorganic substance such as silicon nitride or an organic substance such as a resin; the pixel electrode 41 and the pixel electrode 42 are prepared by using a transparent conductive oxide indium zinc oxide (IZO), ITO or other transparent metal oxide conductive material. .
- IZO transparent conductive oxide indium zinc oxide
- ITO transparent metal oxide conductive material
- a plan view of the prepared array substrate is as shown in FIG. 5, and a black matrix (BM) resin is coated on the gate line 50 and the data line 51, and a groove 541 and a groove 542 are disposed on the gate line 50.
- BM black matrix
- a groove 543 and a groove 544 may be provided on the data line 51
- red (R) green (G) blue (B) resin R resin 52, G resin 53, B resin 54
- the array circuit is integrated and can also be fabricated on the opposite substrate.
- a display panel according to an embodiment of the present invention includes the array substrate according to any one of the embodiments of the present invention.
- the display panel includes, for example, a counter substrate 100 and an array substrate 200 which are sealed and sealed by a sealant, and a liquid crystal layer and a columnar shape for maintaining the thickness of the cartridge between the counter substrate 100 and the array substrate 200 .
- Spacer 300 For example, a gate insulating layer 21 and a passivation layer 23 are sequentially disposed on the gate line 11 of the array substrate 200, and a recess 364 is provided at a position corresponding to the gate line 11 in the passivation layer 23, and the recess 364 is used for the column spacer
- the pad 300 is fixed in place. It should be noted that FIG. 6 only shows a partial structure of the display panel.
- the groove and the column spacer are fixedly aligned, thereby
- the spacing between the opposing substrate and the array substrate is fixed up and down and fixed to the left and right to ensure liquid crystal
- the uniformity and stability of the layer thickness prevent the substrate from being bent by external stress, and the movement of the column spacer affects the display area.
- a display device includes the display panel described in the embodiment of the invention.
- the groove and the column spacer are fixed.
- the alignment is such that the spacing between the opposing substrate and the array substrate is fixed up and down and fixed to the left and right, and the uniformity and stability of the thickness of the liquid crystal layer are ensured, and the groove is not provided on the gate line and/or the data line.
- the groove is fixed to the alignment by the column spacer to prevent the substrate from being bent and deformed by external pressure, and the movement of the column spacer affects the display area.
- the display device is a liquid crystal display device.
- the display device may be any product or component having a display function, such as an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
- a display function such as an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
- Embodiments of the present invention provide an array substrate, a display panel, and a display device.
- a recess is formed on a gate line and/or a data line of an array substrate
- the opposite substrate and the array substrate are aligned, and the groove and the column spacer are separated.
- the spacer is fixed in position, so that the spacing between the opposite substrate and the array substrate is fixed up and down and fixed to the left and right.
- the uniformity and stability of the thickness of the liquid crystal layer are ensured, the substrate is prevented from being bent and deformed by external pressure, and the column spacer is The movement of the mat affects the display area.
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Abstract
Description
Claims (13)
- 一种阵列基板,包括:多条栅线和多条数据线,位于所述阵列基板上成阵列分布的像素单元,其中,每一像素单元包括一个像素电极与一个薄膜晶体管,所述数据线作为所述薄膜晶体管的源极,所述栅线作为所述薄膜晶体管的栅极,所述薄膜晶体管的漏极与所述像素电极电性连接,所述栅线和所述数据线中的至少一个上设置有用于与隔垫物固定对位的凹槽。
- 根据权利要求1所述的阵列基板,其中,所述栅线和所述数据线中的至少一个上设置有至少两个所述凹槽。
- 根据权利要求2所述的阵列基板,其中,至少两个所述凹槽为两个凹槽,所述两个凹槽设置在栅线或数据线上。
- 根据权利要求2所述的阵列基板,其中,至少两个所述凹槽为两个凹槽,所述两个凹槽中的一个设置在栅线上,所述两个凹槽中的另一个设置在数据线上。
- 根据权利要求2-4中任一项所述的阵列基板,其中,所述凹槽包括圆形和/或矩形的凹槽。
- 根据权利要求2-4中任一项所述的阵列基板,其中,所述凹槽包括多边形的凹槽。
- 根据权利要求3或4所述的阵列基板,其中,所述两个凹槽的深度不同。
- 根据权利要求3或4或7所述的阵列基板,其中,所述两个凹槽中的一个凹槽中铺设有像素电极。
- 根据权利要求1-8中任一项所述的阵列基板,其中,所述漏极通过过孔与所述像素电极电性连接,或者所述像素电极直接搭接在所述漏极上。
- 根据权利要求9所述的阵列基板,其中,所述凹槽与所述过孔位于同一层中。
- 一种显示面板,包括权利要求1-10中任一项所述的阵列基板。
- 一种显示装置,包括权利要求11所述的显示面板。
- 根据权利要求12所述的显示装置,其中,该显示装置为液晶显示装置。
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CN201420628360.1U CN204101855U (zh) | 2014-10-27 | 2014-10-27 | 阵列基板、显示面板及显示装置 |
CN201420628360.1 | 2014-10-27 |
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CN112086471A (zh) * | 2020-09-28 | 2020-12-15 | 成都中电熊猫显示科技有限公司 | 阵列基板的制造方法、阵列基板及显示面板 |
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CN204101855U (zh) * | 2014-10-27 | 2015-01-14 | 京东方科技集团股份有限公司 | 阵列基板、显示面板及显示装置 |
CN105445982B (zh) * | 2015-11-14 | 2019-11-29 | 合肥骇虫信息科技有限公司 | 一种防弯曲液晶板 |
CN110426904B (zh) * | 2019-06-27 | 2021-11-05 | 惠科股份有限公司 | 阵列基板和显示设备 |
CN113946074B (zh) | 2020-07-17 | 2023-04-07 | 合肥京东方显示技术有限公司 | 显示面板和显示装置 |
CN111769124A (zh) * | 2020-07-27 | 2020-10-13 | 成都中电熊猫显示科技有限公司 | 金属氧化物阵列基板的制造方法、阵列基板及显示面板 |
CN114236916A (zh) * | 2021-11-15 | 2022-03-25 | 滁州惠科光电科技有限公司 | 显示面板和显示装置 |
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CN203069938U (zh) * | 2013-02-21 | 2013-07-17 | 合肥京东方光电科技有限公司 | 显示面板及显示装置 |
CN104035239A (zh) * | 2014-05-08 | 2014-09-10 | 京东方科技集团股份有限公司 | 一种基板及显示器件 |
CN204101855U (zh) * | 2014-10-27 | 2015-01-14 | 京东方科技集团股份有限公司 | 阵列基板、显示面板及显示装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN112086471A (zh) * | 2020-09-28 | 2020-12-15 | 成都中电熊猫显示科技有限公司 | 阵列基板的制造方法、阵列基板及显示面板 |
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US20160266431A1 (en) | 2016-09-15 |
US9897863B2 (en) | 2018-02-20 |
CN204101855U (zh) | 2015-01-14 |
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