WO2015019677A1 - Procédé de fabrication de dispositif semi-conducteur - Google Patents

Procédé de fabrication de dispositif semi-conducteur Download PDF

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Publication number
WO2015019677A1
WO2015019677A1 PCT/JP2014/063565 JP2014063565W WO2015019677A1 WO 2015019677 A1 WO2015019677 A1 WO 2015019677A1 JP 2014063565 W JP2014063565 W JP 2014063565W WO 2015019677 A1 WO2015019677 A1 WO 2015019677A1
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Prior art keywords
metal
bonding
semiconductor chip
wiring
purity
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PCT/JP2014/063565
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English (en)
Japanese (ja)
Inventor
宮本　健二
中川　成幸
南部　俊和
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日産自動車株式会社
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Priority to JP2015530729A priority Critical patent/JP6260941B2/ja
Publication of WO2015019677A1 publication Critical patent/WO2015019677A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids

Definitions

  • the present invention relates to a semiconductor device in which a semiconductor chip and a wiring metal are joined, and further to a semiconductor device in which such a semiconductor device is disposed on a base plate such as a cooling body via an insulating ceramic substrate.
  • the present invention relates to a manufacturing method and a semiconductor device manufactured by such a method.
  • Recent semiconductor devices particularly semiconductor devices called high power modules having a large current density, are required to be usable even in a high temperature environment. Therefore, in a mounting structure of a semiconductor device, a joint having excellent high temperature durability when held at a high temperature or subjected to a high temperature thermal cycle is strongly desired. From the viewpoint of environmental protection, a Pb (lead) -free joining technique is essential.
  • solder is widely used for bonding for mounting such semiconductor devices, but the operating temperature is the melting point of the solder (for example, It is limited to about 200 ° C. or less. Also, for example, in a joint where the electrode is Cu, a Cu—Sn brittle intermetallic compound layer is formed at the interface, resulting in poor high-temperature durability. Therefore, various attempts have been made to ensure the high temperature durability of the joint.
  • a low-temperature bonding method has been proposed in which active surface energy of metal nanoparticles is used to agglomerate and bond at low temperatures. If this bonding method is used, the bonded interface after agglomeration becomes a bulk metal, and therefore has excellent high temperature durability.
  • a noble metal such as Au (gold) is used as the metal nanoparticle, and the surface of the metal nanoparticle is modified with an organic substance, resulting in a structure in which the particles are agglomerated, and the organic substance is a bonding process. Since the gas is sometimes gasified and remains, voids are present in the joint, resulting in large variations in joint strength.
  • an insert material containing a metal such as Zn (zinc) that causes a eutectic reaction with the base metal from the viewpoint of eliminating the influence on the bonding quality caused by the oxide film formed on the bonding surface and forming a sound bonded portion.
  • a metal such as Zn (zinc) that causes a eutectic reaction with the base metal
  • bonding is performed by causing a eutectic reaction at the bonding interface by pressurizing and heating in a state of interposing between the bonding surfaces. That is, by generating a eutectic reaction between the base metal and the insert material, the oxide film on the surface of the base material can be removed and discharged together with the generated eutectic reaction melt from the joint surface.
  • the yield point is lowered by increasing the purity of the wiring metal, and thermal stress is generated based on the difference in thermal expansion coefficient between the semiconductor chip and the wiring metal.
  • the concavo-convex structure remains on the joint surface, and the metal in the insert material contained in the solidified eutectic reaction liquid phase remaining on the concavo-convex bottom is on the wiring metal side. It has been found that it may spread. Then, it has been found that when such metal diffusion occurs, the purity of the wiring metal decreases, the thermal stress increases due to an increase in the yield point, and the elongation decreases, which may impair durability reliability.
  • the present invention has been made in view of the above problems in the conventional bonding technology applied to the mounting structure of a semiconductor device.
  • the present inventors have formed a metal atom diffusion prevention layer made of, for example, Ni or TiN on the surface of the bonding surface of the wiring metal made of high purity Al. As a result, the present inventors have found that the above problems can be solved, and have completed the present invention.
  • the bonding surface is mainly composed of at least one selected from the group consisting of Al, Cu, Ag, and Au.
  • the bonding surface is mainly composed of at least one selected from the group consisting of Al, Cu, Ag, and Au.
  • the bonding surface is mainly composed of at least one selected from the group consisting of Al, Cu, Ag, and Au.
  • the insert material is interposed, the semiconductor chip and the wiring metal are heated while being relatively pressurized, and the eutectic reaction melt generated at the bonding interface is discharged together with the oxide film, Without even wherein the bonding the metal A and a high-purity Al which constitutes the bonding surface of the semiconductor chip and the interconnect metal in some direct.
  • the semiconductor device of the present invention is formed by bonding a semiconductor chip and a wiring metal, and the semiconductor chip has at least one selected from the group consisting of Al, Cu, Ag and Au as a main component.
  • the wiring metal is made of high-purity Al and has a metal atom diffusion prevention layer on or inside the bonding surface, and constitutes the bonding surface of the semiconductor chip and the wiring metal.
  • Metal A and high-purity Al are directly bonded at at least a part of the bonding interface, Zn eutectic composition around the direct bonding part, and at least one metal other than Au contained in Al and metal A It is characterized by the presence of effluents containing the oxides.
  • the diffusion preventing layer for preventing the diffusion of metal atoms is formed on the surface or inside of the bonding surface of the wiring metal made of high purity Al. Therefore, even if the eutectic reaction liquid phase coagulum remains at the bottom of the concavo-convex structure of the joint surface, the metal atoms in the coagulum do not diffuse to the wiring metal side, and the yield is reduced due to the decrease in the purity of the wiring metal. It is possible to prevent an increase in point, a decrease in elongation, and an increase in thermal stress, and the durability reliability of the apparatus is improved.
  • (A)-(e) is process drawing which shows roughly the joining process of the semiconductor chip and wiring metal by the manufacturing method of the semiconductor device of this invention.
  • (A)-(c) is a perspective view which shows the example of the shape of the uneven structure formed in a junction part in the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor chip which comprises one side of the semiconductor device by the manufacturing method of this invention.
  • (A)-(d) is a schematic sectional drawing which shows the example which formed the diffusion prevention layer in the surface of a joining surface in the manufacturing method of the semiconductor device of this invention.
  • (A)-(d) is a schematic sectional drawing which shows the example which formed the diffusion prevention layer in the inside of a joining surface in the manufacturing method of the semiconductor device of this invention.
  • (A)-(d) is a schematic sectional drawing which respectively shows the embodiment of the semiconductor device by the manufacturing method of this invention. It is a schematic sectional drawing explaining the structure of the semiconductor device used for the Example of this invention.
  • % means mass percentage unless otherwise specified.
  • metal A mainly composed of at least one selected from the group consisting of Al, Cu, Ag and Au, and high-purity Al.
  • at least one of the joint surfaces is provided with unevenness for breaking the oxide film on the joint surface.
  • a metal atom diffusion preventing layer is formed on the surface or inside of the bonding surface of the wiring metal.
  • an insert material containing Zn as a metal that causes a eutectic reaction with at least one metal other than Au contained in Al and the metal A is interposed between both joint surfaces.
  • “high purity Al” means that containing 99.0% or more of Al.
  • the semiconductor chip and the wiring metal are relatively pressurized and heated, and the oxide film formed on the bonding surface is broken by the unevenness so that the metal A of the semiconductor chip and the wiring metal and the insert material are in contact with each other.
  • the eutectic reaction of the metal contained in the metal A and the Al contained in the wiring metal and the metal contained in the insert material is caused at the bonding interface.
  • the eutectic reaction melt is discharged together with the oxide film, and the metal A and the wiring metal of the semiconductor chip are directly bonded at at least a part of the bonding interface, so that the semiconductor chip and the wiring metal are firmly bonded.
  • the metal atoms in the solidified material are prevented by the diffusion preventing layer. Since diffusion to the wiring metal is prevented, the yield point of the wiring metal does not increase and the elongation does not decrease, and the durability reliability of the device can be improved.
  • Melting due to the eutectic reaction occurs when the composition of the interdiffusion region formed by mutual diffusion of two or more metals becomes the eutectic composition. A phase is formed.
  • the melting point of Al is 660 ° C.
  • the melting point of Zn is 419.5 ° C.
  • this eutectic metal melts at 382 ° C. which is lower than the respective melting points. Therefore, when the clean surfaces of both metals are brought into contact and heated to 382 ° C. or higher, a reaction (eutectic melting) occurs and Al-95% Zn has a eutectic composition, but the eutectic reaction itself is independent of the alloy components. It is a constant change, and the composition of the insert material only increases or decreases the amount of eutectic reaction.
  • the neighboring oxide film is crushed and decomposed by the formation of a liquid phase by the eutectic reaction, and further, eutectic melting spreads to the entire surface, thereby expanding and promoting the oxide film breakage, and lowering the oxide film on the joint surface at a low temperature. Since it is removed at (eutectic temperature), the metal A and the metal B can be directly joined without going through the brazing material layer. Therefore, the strength is ensured by the direct joining of the metal A and Al not containing Pb, so that even when kept at a high temperature, a brittle intermetallic compound layer and a Kirkendall void are not generated, and an excellent high temperature durability is achieved.
  • the semiconductor device provided with the provided Pb-free junction can be manufactured.
  • the eutectic composition is spontaneously achieved by interdiffusion, there is no need to control the composition, and the essential condition is that a low-melting eutectic reaction occurs between the base material (metal A, Al) and the metal contained in the insert material. Is to generate. At this time, it is necessary to cause eutectic reaction between the metal contained in the metal A of the semiconductor chip, Al of the wiring metal, and the metal contained in the insert material on the joint surface. It is necessary to heat to the higher eutectic temperature.
  • 1 (a) to 1 (e) are process diagrams for explaining a bonding process between a semiconductor chip and a wiring metal in a method of manufacturing a semiconductor device according to the present invention.
  • the formation of the diffusion preventing layer is omitted from this figure because it is not directly involved in the bonding process.
  • the insert material 4 is disposed between the wiring metal 2 and the semiconductor chip 3.
  • the wiring metal 2 is made of high-purity Al, and fine unevenness R is formed in advance on the joint surface, and a diffusion prevention layer (see FIG. (Not shown) is formed.
  • a metal layer 3c containing, for example, Al, Cu, or Ag as a main component is formed as a metal A on the bonding surface of the semiconductor chip 3 by plating, sputtering, or the like. Note that oxide films 2f and 3f are formed on the surfaces of the wiring metal 2 and the metal layer 3c.
  • the selection range of the metal A a pure metal selected from the group consisting of Al, Cu, Ag and Au, and various metals including an alloy between these metals can be adopted.
  • Joining that is, using an Al-based material eliminates the starting point of the degradation reaction at the interface, so that joining with higher durability reliability is possible.
  • the “same material” as used herein means a metal containing Al as a main component, and is not necessarily the same high-purity Al as the wiring metal 2.
  • the shape of the unevenness R formed on the joint surface of the wiring metal 2 is not limited as long as it has a function of concentrating stress and promoting the destruction of the oxide film.
  • FIG. ) To (c) can be employed. That is, as shown in FIG. 2 (a), if the convex-convex tip is made to be a substantially flat surface as a trapezoidal cross-sectional concavo-convex structure, the stress concentration means can be easily formed even if the stress concentration level is slightly reduced. Costs can be reduced.
  • FIG. 2B it is also possible to adopt a concavo-convex structure in which triangular prisms are arranged in parallel, whereby the convex tip of the concavo-convex structure becomes linear, and the stress concentration degree is increased. This can enhance the effect of breaking the oxide film.
  • FIG. 2 (c) it is possible to adopt a concavo-convex structure in which square pyramids are juxtaposed in the vertical and horizontal directions. Thus, the breaking performance of the oxide film can be improved.
  • the shape of the unevenness R is not particularly limited as long as it has a function of concentrating stress and promoting the destruction of the oxide film as described above. It is also possible to make the tip of the convex part such as a shape a curved surface. Needless to say, the smaller the radius of curvature of the curved surface, the more the stress concentration becomes more prominent, and the oxide film is easily broken.
  • Such unevenness R can be formed by, for example, cutting, grinding, plastic processing (roller processing), laser processing, electric discharge processing, etching processing, lithography, etc., and the formation method is particularly limited. It is not a thing. Of these processing methods, plastic processing enables formation at a very low cost.
  • the dimensions and shape of the fine irregularities are an aspect ratio (height / width): 0.001 or more, a pitch: 1 ⁇ m or more, and preferably an aspect ratio of 0.1 or more and a pitch: 10 ⁇ m or more.
  • the semiconductor chip 3 is provided with the metal layer 3c made of metal A on the joint surface side as described above.
  • the semiconductor chip body 3 made of SiC, Si, GaN, etc.
  • An adhesion layer 3a and a barrier layer 3b can be interposed between the layers 3c.
  • the barrier layer 3b has a function of preventing the components of the metal layer 3c from diffusing into the chip body, and Ni (nickel), Pt—Ir (platinum-iridium), or the like can be applied.
  • the adhesion layer 3a has a function of improving the adhesion between the barrier layer 3b and the chip body 3, and for example, Ti (titanium), Cr (chromium), or the like can be used.
  • the insert material 4 is made of Zn, which is a metal that causes a eutectic reaction with at least one metal element of Al, Cu, and Ag and Al contained in the wiring metal, other than Au contained in the metal A.
  • Zn is a metal that causes a eutectic reaction with at least one metal element of Al, Cu, and Ag and Al contained in the wiring metal, other than Au contained in the metal A.
  • a metal (pure zinc or zinc alloy) containing Zn as a main component is used.
  • an alloy containing Zn and Al, Mg, Cu, Ag, and Sn as a main component for example, an alloy containing Zn and Al as main components, Zn, Al, and Mg
  • An alloy containing a main component or an alloy containing Zn, Al, and Cu as main components can also be used. That is, the eutectic temperature of the alloy system containing Zn and Al is low (382 ° C. for the Zn—Al based alloy and 330 ° C. for the Zn—Al—Mg based alloy). Both members can be joined by removing the oxide film that hinders the joining from the joining interface without inducing.
  • the insert material 4 can contain metal contained in the metal A constituting the bonding surface of the semiconductor chip 3 and Al contained in the wiring metal, and the reactivity between the insert material and the member to be joined is improved. In addition, it is desirable for improving the affinity of the bonding interface.
  • the thickness of the insert material 4 is desirably 20 ⁇ m or more and 200 ⁇ m or less.
  • the thickness of the insert material 4 is less than 20 ⁇ m, the oxide film is not sufficiently discharged, the sealing performance of the joint portion is lowered, and oxidation progresses during joining and the strength characteristics of the joint portion are lowered.
  • it exceeds 200 ⁇ m a high pressurizing force may be required for discharging the surplus portion, or the residual pressure at the interface may increase and the joint performance may be deteriorated.
  • the “main component” in the metal A or the insert material means that the total content of these metal components is 80% or more.
  • the semiconductor chip 3 and the wiring metal 2 are relatively pressurized, brought into close contact via the insert material 4, and heating is started while further pressing.
  • the stress at the portion where the tip of the convex portion of the concavo-convex R contacts abruptly increases locally, and the oxide film 3f of the metal layer 3c is mechanically formed without increasing the applied pressure so much. Is destroyed and the new surface is exposed.
  • the oxide film 2f at the tip of the fine irregularities 2r is also destroyed, and the new surface of the wiring metal 2 is exposed.
  • a eutectic reaction occurs between the metal layer 3c and the metal element in the wiring metal 2, respectively.
  • a eutectic melt phase is generated.
  • the eutectic melting range extends to the entire bonding interface, so that the metal layer 3c and the oxide films 3f and 2f of the wiring metal 2 are removed from the surface. As shown in FIG. The 2f fragments are dispersed in the eutectic melt phase.
  • the eutectic reaction melt is discharged from the bonding interface, and most of the fragments of the oxide films 3f and 2f dispersed in the liquid phase are eutectic. It is extruded together with the melt from the bonding interface, and the new surfaces of the metal layer 3c and the wiring metal 2 are exposed, and the diffusion reaction of the component elements contained therein occurs at the bonding interface.
  • bonding between the wiring metal 2 and the metal layer 3c of the semiconductor chip 3 that is, direct bonding between the metal A and Al is achieved.
  • a small amount of mixture containing eutectic reaction product, oxide film, metal derived from insert material, etc. may remain at the bonding interface, but as long as the metal-to-metal direct bonding portion is formed, the strength It will not be a problem. Moreover, such a residue contributes to electric conduction and heat conduction.
  • FIG. 1 shows an example in which the unevenness R is formed on the wiring metal 2 side
  • the present invention is not limited to this, and the formation position of the fine unevenness is as described above.
  • it can be provided on both of the bonding surfaces. By forming it on both surfaces, it is possible to increase the breakdown starting point of the oxide film.
  • the form of foil It is desirable to sandwich between the two materials.
  • the bonding of the wiring metal 2 and the semiconductor chip 3 in the manufacturing method of the present invention can be performed in an inert gas atmosphere, but can be performed in the air without any trouble.
  • it is possible to carry out in vacuum but not only vacuum equipment is required, but also the vacuum gauge and gate valve may be damaged by melting of the insert material. Therefore, it is advantageous in terms of cost.
  • means for heating or maintaining the bonding portion within a predetermined temperature range is not particularly limited.
  • high-frequency heating, infrared heating, heater heating, or the like can be used.
  • a combined method can be employed.
  • the speed is high because the interface is oxidized and the discharge of the melt is lowered and the strength is lowered. This tendency occurs particularly in the case of bonding in the atmosphere.
  • the pressurizing force at the time of joining can be reduced by forming the unevenness R, and therefore the pressurizing force at the time of joining is preferably set to 1 MPa or more and 30 MPa or less. That is, when the pressure is less than 1 MPa, the oxide film cannot be destroyed or the eutectic reaction product or the oxide film fragments can be sufficiently discharged from the joint surface. If the pressure exceeds 30 MPa, the semiconductor chip 2 may be damaged. by.
  • FIG. 4 is a schematic cross-sectional view illustrating the function of the diffusion preventing layer in the method for manufacturing a semiconductor device of the present invention.
  • a wiring metal 2 and a semiconductor chip 3 are prepared, and an insert material 4 is disposed therebetween.
  • the wiring metal 2 is made of high-purity Al as described above, and fine irregularities R are formed in advance on the joint surface, and a metal atom diffusion prevention layer L is further formed on the surface.
  • a metal atom diffusion prevention layer L is further formed on the surface.
  • the diffusion preventing layer L any material of Ni, TiN, WN, TiWN, and PtIr can be used, and can be formed by vapor deposition or sputtering.
  • a metal layer 3c made of the above-described metal A (a metal mainly composed of at least one of Al, Cu, Ag, and Au) is formed by plating, sputtering, or the like. .
  • An oxide film 3f is formed on the surface of the metal layer 3c.
  • the oxide film 3f of the metal layer 3c is mechanically broken as described above, and this The eutectic reaction generated at the fracture portion expands to the bonding surface, and the oxide film 3f is broken and discharged from the bonding surface together with the eutectic melt.
  • the metal layer 3c and the wiring metal 2 are directly joined with the bottom of the unevenness R left, and a piece of the oxide film 3f is formed on the bottom of the unevenness R. It remains dispersed in the eutectic melt phase Em.
  • FIG. 4C shows the state of the bonding interface immediately after bonding, and the residue Es at the bottom of the unevenness R is solidified in a state in which the eutectic melt phase Em entrains the oxide film 3f.
  • metal atoms, typically Zn, contained in the residue Es diffuse into the metal layer 3c.
  • the diffusion preventing layer L becomes an obstacle, the diffusion of metal atoms is prevented. Therefore, a decrease in the elongation of the wiring metal 2 and an increase in thermal stress can be avoided, and the durability reliability of the semiconductor device can be improved.
  • FIG. 5 shows an example in which a metal atom diffusion preventing layer L is formed inside the joint surface of the wiring metal 2.
  • the diffusion preventing layer L is formed inside the bonding surface (position just below the surface) and the outermost surface of the bonding surface is high-purity Al
  • an oxide film (aluminum oxide) 2f is formed on the surface (FIG. 5 (a)), except that the diffusion of metal atoms after standing at high temperature extends to the range from the surface of the wiring metal 2 to the diffusion prevention layer L (see FIG. 5 (d)). There is no change.
  • the structure of the semiconductor device manufactured by the manufacturing method of the present invention is a semiconductor device in which a semiconductor chip and a wiring metal are joined, and the semiconductor chip is at least selected from the group consisting of Al, Cu, Ag, and Au.
  • a metal A mainly composed of one kind is provided on the bonding surface, the wiring metal is made of high-purity Al, and has a metal atom diffusion prevention layer on the surface or inside of the bonding surface.
  • the metal A and the high-purity Al constituting the bonding surface are directly bonded at least at a part of the bonding interface, and the eutectic composition of Zn around the direct bonding portion and Al and other than Au contained in the metal A Exhausts containing at least one metal oxide are present (see FIG. 1 (e)).
  • the “eutectic composition of Zn” is a composition obtained by eutectic reaction of Zn contained in the insert material, at least one metal other than Au contained in the metal A, and Al of the wiring metal.
  • the “oxide” is a fragment of the oxide film formed on the surfaces of the metal A and the wiring metal (high purity Al).
  • the wiring metal can be disposed on an insulating ceramic substrate, and the ceramic substrate is attached to a base plate (cooling body or the like) via a back metal provided on the surface of the ceramic substrate on the side opposite to the semiconductor chip.
  • a bonded structure can also be used.
  • the same manufacturing method and bonding structure as the above-described bonding of the semiconductor chip and the wiring metal can be employed for bonding the back metal and the base plate.
  • the back metal when joining the back metal provided on the anti-semiconductor chip side of the insulating ceramic substrate onto the base plate, the back metal is made of high-purity Al, and the joining surface of the base plate is made of Al, Cu, Ag and It is made of metal B mainly composed of at least one selected from the group consisting of Au, and at least one of the two joint surfaces is provided with unevenness for breaking the oxide film on the joint surface, As a metal that causes a eutectic reaction with Al and at least one metal other than Au contained in the metal B between the bonding surfaces after forming a diffusion preventing layer of metal atoms on the surface or inside of the bonding surface The back metal and the base plate are heated while relatively pressurizing the insert material containing And discharged together with oxide film, bonded directly to a high-purity Al metal B constituting the bonding surface of the back metal and the base plate in at least a part of the bonding interface.
  • the wiring metal is disposed on the insulating ceramic substrate, and the back metal provided on the side of the insulating ceramic substrate opposite to the semiconductor chip is bonded on the base plate.
  • the metal is made of high-purity Al and has a diffusion preventing layer for metal atoms on the surface or inside of the bonding surface, and the base plate is mainly composed of at least one selected from the group consisting of Al, Cu, Ag and Au.
  • the high-purity Al and metal B constituting the back surface metal and the base plate joint surface are directly joined at least at a part of the joint interface, and Zn is shared around the direct joint portion.
  • the crystal composition and the discharge containing at least one oxide of metal other than Au contained in Al and the metal A are interposed.
  • the metal B constituting the bonding surface of the base plate may be a material different from the metal A constituting the bonding surface of the semiconductor chip, but it is desirable to use the same kind of material.
  • FIGS. 6A to 6D are schematic cross-sectional views showing several examples of embodiments of a semiconductor device according to the manufacturing method of the present invention.
  • a semiconductor device 1 shown in FIG. 6A includes a bus bar in which a wiring metal 2 made of high-purity Al is arranged on one side of an insulating ceramic substrate 12 on a cooling body (heat sink) 11.
  • the semiconductor chip 3 is bonded to the wiring metal 2 and fixed.
  • the semiconductor chip 3 includes a metal layer 3c made of the metal A on the bonding surface, and the metal layer 3c of the semiconductor chip 3 and the wiring metal 2 are directly bonded by the method described above. Yes.
  • a semiconductor device 1 shown in FIG. 6B includes a wiring metal 2 made of high-purity Al on the upper surface side of the insulating ceramic substrate 12 in the drawing, and a back metal 5 also made of high-purity Al on the lower surface side in the drawing.
  • a cooling body 11 is provided on the back metal side of the ceramic substrate 12. Then, the wiring metal 2 (high purity Al) on the upper surface side and the semiconductor chip 3 having the metal layer 3c made of the metal A on the bonding surface are bonded by the above method, and the back surface metal 5 (high purity Al) on the lower surface side.
  • the cooling body 11 (metal B) is similarly joined.
  • the semiconductor device 1 shown in FIG. 6C shows an example of a double-sided mounting type semiconductor device, whereas FIGS. 6A and 6B are single-sided mountings.
  • a bus bar provided with a wiring metal 2 made of high-purity Al is disposed on one side of an insulating ceramic substrate 12 along with a cooling body 11 on the upper and lower sides of a semiconductor chip 3 provided with a metal layer 3c.
  • the metal layer 3c made of metal A provided on the upper and lower surfaces of the semiconductor chip 3 and the wiring metal 2 made of high-purity Al of the bus bar are directly bonded by the above-described method.
  • the semiconductor device 1 shown in FIG. 6D uses a ceramic substrate 12 having a wiring metal 2 and a back metal 5 both made of high-purity Al on both surfaces of an insulating ceramic substrate 12. It is a double-sided mounting type. That is, as shown in FIG. 6C, the back surface metal 5 (high-purity Al) and the cooling body 11 (metal B) disposed on the back surface side of the ceramic substrate 12 are joined by the method of the present invention.
  • the structure is substantially the same as the form.
  • FIG. 7 is a schematic cross-sectional view showing a state before bonding of the semiconductor device of the present invention (however, the insert material 4 is omitted).
  • the semiconductor chip 3 shown in the figure has a metal layer 3c made of metal A on the bonding surface. I have.
  • the metal layer 3c can also be formed via an adhesion layer 3a or a barrier layer 3b as shown in FIG.
  • the insulating ceramic substrate 12 includes a wiring metal 2 made of high-purity Al on the upper surface side in the drawing, and a back metal 5 also made of high-purity Al on the lower surface side in the drawing. Concavities and convexities R are formed on the surface of the metal 5 (bonding surface between the semiconductor chip 3 and a base plate 11 described later).
  • the base plate (cooling body) 11 is made of metal B, and unevenness R is similarly formed on the joint surface with the back surface metal 5. At this time, the unevenness R may be formed by only one of the back metal 5 and the base plate 11. A diffusion prevention layer L is formed on the uneven surface of the wiring metal 2 and the back metal 5.
  • the semiconductor device bonded in this way has the metal atom diffusion prevention layer L formed on the surfaces of the wiring metal 2 and the back surface metal 5, even if the unevenness R remains on the bonding surface, it is exposed to a high temperature environment. Even so, diffusion from the solidified portion of the uneven portion to the wiring metal 2 and the back metal 5 is prevented. Therefore, the original mechanical performance of the wiring metal 2 and the back surface metal 5 can be maintained, and the durability reliability of the semiconductor device can be improved.
  • Example 1 (A) Semiconductor chip After depositing Ti / Ni / Ag by vapor deposition on the back surface of an SiC diode (semiconductor chip 3) having a size of 1.66 ⁇ 1.52 ⁇ 0.36 mm, Al is deposited on the deposition surface. (Metal A) was sputtered to a thickness of 6 ⁇ m to form a metal layer 3c, which was used as a bonding surface.
  • Base plate A plate material having a thickness of 1.0 mm made of industrial pure aluminum (metal B) defined as A1070 in JIS H 4000 was used as the base plate 11. Then, a unidirectional groove having a height of 0.1 mm and a pitch of 0.1 mm was formed on the surface (bonding surface with the back surface metal 5) by using a diamond tool, thereby forming the unevenness R.
  • metal B industrial pure aluminum
  • Example 2 The same operation as in Example 1 above, except that a 0.1 mm thick foil strip made of a Zn-4.0% Al-2.0% Cu alloy produced by a rapid cooling single roll method was used as the insert material. By repeating the above, the respective joining surfaces were joined to obtain the semiconductor device of Example 2.
  • Example 3 By repeating the same operation as in Example 1 above, except that Ti / Ni / Ag is formed by vapor deposition on the back surface of the SiC diode of the above size (semiconductor chip 3) and the bonding surface is Ag. The respective joining surfaces were joined to obtain the semiconductor device of Example 3.
  • Example 4 Except for forming the diffusion prevention layer L by sputtering WN on the outermost surfaces of the wiring metal 2 and the back surface metal 5, the same operation as in Example 1 is repeated to join the respective bonding surfaces. A semiconductor device of Example 4 was obtained.
  • Comparative Example 1 By repeating the same operation as in Example 1 without forming a diffusion prevention layer on the bonding surface of the wiring metal 2 and the back surface metal 5, the respective bonding surfaces are bonded to obtain the semiconductor device of Comparative Example 1. It was.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Die Bonding (AREA)

Abstract

La présente invention concerne, au moment de la liaison d'un métal de câblage (2), qui est formé d'Al à pureté élevée et d'une puce à semi-conducteurs (3) en fournissant des renfoncements et des parties saillantes (R) sur une surface de liaison de la puce à semi-conducteurs (3), ladite surface de liaison étant formée d'un métal (A) (Al, Ag ou similaires) et/ou sur une surface de liaison du métal de câblage (2) et en générant une réaction eutectique entre un matériau d'insertion, qui est ménagé entre les surfaces de liaison et les matériaux de liaison à lier, une couche de prévention de diffusion d'atome métallique (L) formée de Ni, TiN, WN ou similaires est précédemment formée sur une surface de la surface de liaison du métal de câblage (2).
PCT/JP2014/063565 2013-08-09 2014-05-22 Procédé de fabrication de dispositif semi-conducteur WO2015019677A1 (fr)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5557388A (en) * 1978-10-20 1980-04-28 Hitachi Ltd Pressure welding method of aluminum member
JPH07169875A (ja) * 1993-03-11 1995-07-04 Toshiba Corp 電子回路装置及びその製造方法及び回路基板及び液晶表示装置及びサーマルヘッド及びプリンタ
JP2006324685A (ja) * 2002-07-08 2006-11-30 Nichia Chem Ind Ltd 窒化物半導体素子の製造方法及び窒化物半導体素子
JP2011200933A (ja) * 2010-03-26 2011-10-13 Panasonic Electric Works Co Ltd 接合方法
WO2012029789A1 (fr) * 2010-08-31 2012-03-08 日産自動車株式会社 Procédé de soudure par fusion de métaux à base d'aluminium
JP2013078793A (ja) * 2011-09-22 2013-05-02 Nissan Motor Co Ltd 接合方法及び接合部品
WO2013129229A1 (fr) * 2012-02-28 2013-09-06 日産自動車株式会社 Procédé de fabrication d'un dispositif semi-conducteur
JP2013176782A (ja) * 2012-02-28 2013-09-09 Nissan Motor Co Ltd 金属材料の接合方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5892306B2 (ja) * 2011-09-20 2016-03-23 日産自動車株式会社 接合方法及び接合部品
JP6016095B2 (ja) * 2011-09-22 2016-10-26 日産自動車株式会社 接合方法及び接合部品

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5557388A (en) * 1978-10-20 1980-04-28 Hitachi Ltd Pressure welding method of aluminum member
JPH07169875A (ja) * 1993-03-11 1995-07-04 Toshiba Corp 電子回路装置及びその製造方法及び回路基板及び液晶表示装置及びサーマルヘッド及びプリンタ
JP2006324685A (ja) * 2002-07-08 2006-11-30 Nichia Chem Ind Ltd 窒化物半導体素子の製造方法及び窒化物半導体素子
JP2011200933A (ja) * 2010-03-26 2011-10-13 Panasonic Electric Works Co Ltd 接合方法
WO2012029789A1 (fr) * 2010-08-31 2012-03-08 日産自動車株式会社 Procédé de soudure par fusion de métaux à base d'aluminium
JP2013078793A (ja) * 2011-09-22 2013-05-02 Nissan Motor Co Ltd 接合方法及び接合部品
WO2013129229A1 (fr) * 2012-02-28 2013-09-06 日産自動車株式会社 Procédé de fabrication d'un dispositif semi-conducteur
JP2013176782A (ja) * 2012-02-28 2013-09-09 Nissan Motor Co Ltd 金属材料の接合方法

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